1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */ 3 #include <linux/init.h> 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/slab.h> 7 #include <linux/pci.h> 8 #include <linux/interrupt.h> 9 #include <linux/delay.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/workqueue.h> 12 #include <linux/fs.h> 13 #include <linux/io-64-nonatomic-lo-hi.h> 14 #include <linux/device.h> 15 #include <linux/idr.h> 16 #include <linux/iommu.h> 17 #include <uapi/linux/idxd.h> 18 #include <linux/dmaengine.h> 19 #include "../dmaengine.h" 20 #include "registers.h" 21 #include "idxd.h" 22 #include "perfmon.h" 23 24 MODULE_VERSION(IDXD_DRIVER_VERSION); 25 MODULE_LICENSE("GPL v2"); 26 MODULE_AUTHOR("Intel Corporation"); 27 MODULE_IMPORT_NS(IDXD); 28 29 static bool sva = true; 30 module_param(sva, bool, 0644); 31 MODULE_PARM_DESC(sva, "Toggle SVA support on/off"); 32 33 bool tc_override; 34 module_param(tc_override, bool, 0644); 35 MODULE_PARM_DESC(tc_override, "Override traffic class defaults"); 36 37 #define DRV_NAME "idxd" 38 39 bool support_enqcmd; 40 DEFINE_IDA(idxd_ida); 41 42 static struct idxd_driver_data idxd_driver_data[] = { 43 [IDXD_TYPE_DSA] = { 44 .name_prefix = "dsa", 45 .type = IDXD_TYPE_DSA, 46 .compl_size = sizeof(struct dsa_completion_record), 47 .align = 32, 48 .dev_type = &dsa_device_type, 49 }, 50 [IDXD_TYPE_IAX] = { 51 .name_prefix = "iax", 52 .type = IDXD_TYPE_IAX, 53 .compl_size = sizeof(struct iax_completion_record), 54 .align = 64, 55 .dev_type = &iax_device_type, 56 }, 57 }; 58 59 static struct pci_device_id idxd_pci_tbl[] = { 60 /* DSA ver 1.0 platforms */ 61 { PCI_DEVICE_DATA(INTEL, DSA_SPR0, &idxd_driver_data[IDXD_TYPE_DSA]) }, 62 63 /* IAX ver 1.0 platforms */ 64 { PCI_DEVICE_DATA(INTEL, IAX_SPR0, &idxd_driver_data[IDXD_TYPE_IAX]) }, 65 { 0, } 66 }; 67 MODULE_DEVICE_TABLE(pci, idxd_pci_tbl); 68 69 static int idxd_setup_interrupts(struct idxd_device *idxd) 70 { 71 struct pci_dev *pdev = idxd->pdev; 72 struct device *dev = &pdev->dev; 73 struct idxd_irq_entry *ie; 74 int i, msixcnt; 75 int rc = 0; 76 77 msixcnt = pci_msix_vec_count(pdev); 78 if (msixcnt < 0) { 79 dev_err(dev, "Not MSI-X interrupt capable.\n"); 80 return -ENOSPC; 81 } 82 idxd->irq_cnt = msixcnt; 83 84 rc = pci_alloc_irq_vectors(pdev, msixcnt, msixcnt, PCI_IRQ_MSIX); 85 if (rc != msixcnt) { 86 dev_err(dev, "Failed enabling %d MSIX entries: %d\n", msixcnt, rc); 87 return -ENOSPC; 88 } 89 dev_dbg(dev, "Enabled %d msix vectors\n", msixcnt); 90 91 92 ie = idxd_get_ie(idxd, 0); 93 ie->vector = pci_irq_vector(pdev, 0); 94 rc = request_threaded_irq(ie->vector, NULL, idxd_misc_thread, 0, "idxd-misc", ie); 95 if (rc < 0) { 96 dev_err(dev, "Failed to allocate misc interrupt.\n"); 97 goto err_misc_irq; 98 } 99 dev_dbg(dev, "Requested idxd-misc handler on msix vector %d\n", ie->vector); 100 101 for (i = 0; i < idxd->max_wqs; i++) { 102 int msix_idx = i + 1; 103 104 ie = idxd_get_ie(idxd, msix_idx); 105 ie->id = msix_idx; 106 ie->int_handle = INVALID_INT_HANDLE; 107 ie->pasid = INVALID_IOASID; 108 109 spin_lock_init(&ie->list_lock); 110 init_llist_head(&ie->pending_llist); 111 INIT_LIST_HEAD(&ie->work_list); 112 } 113 114 idxd_unmask_error_interrupts(idxd); 115 return 0; 116 117 err_misc_irq: 118 idxd_mask_error_interrupts(idxd); 119 pci_free_irq_vectors(pdev); 120 dev_err(dev, "No usable interrupts\n"); 121 return rc; 122 } 123 124 static void idxd_cleanup_interrupts(struct idxd_device *idxd) 125 { 126 struct pci_dev *pdev = idxd->pdev; 127 struct idxd_irq_entry *ie; 128 int msixcnt; 129 130 msixcnt = pci_msix_vec_count(pdev); 131 if (msixcnt <= 0) 132 return; 133 134 ie = idxd_get_ie(idxd, 0); 135 idxd_mask_error_interrupts(idxd); 136 free_irq(ie->vector, ie); 137 pci_free_irq_vectors(pdev); 138 } 139 140 static int idxd_setup_wqs(struct idxd_device *idxd) 141 { 142 struct device *dev = &idxd->pdev->dev; 143 struct idxd_wq *wq; 144 struct device *conf_dev; 145 int i, rc; 146 147 idxd->wqs = kcalloc_node(idxd->max_wqs, sizeof(struct idxd_wq *), 148 GFP_KERNEL, dev_to_node(dev)); 149 if (!idxd->wqs) 150 return -ENOMEM; 151 152 idxd->wq_enable_map = bitmap_zalloc_node(idxd->max_wqs, GFP_KERNEL, dev_to_node(dev)); 153 if (!idxd->wq_enable_map) { 154 kfree(idxd->wqs); 155 return -ENOMEM; 156 } 157 158 for (i = 0; i < idxd->max_wqs; i++) { 159 wq = kzalloc_node(sizeof(*wq), GFP_KERNEL, dev_to_node(dev)); 160 if (!wq) { 161 rc = -ENOMEM; 162 goto err; 163 } 164 165 idxd_dev_set_type(&wq->idxd_dev, IDXD_DEV_WQ); 166 conf_dev = wq_confdev(wq); 167 wq->id = i; 168 wq->idxd = idxd; 169 device_initialize(wq_confdev(wq)); 170 conf_dev->parent = idxd_confdev(idxd); 171 conf_dev->bus = &dsa_bus_type; 172 conf_dev->type = &idxd_wq_device_type; 173 rc = dev_set_name(conf_dev, "wq%d.%d", idxd->id, wq->id); 174 if (rc < 0) { 175 put_device(conf_dev); 176 goto err; 177 } 178 179 mutex_init(&wq->wq_lock); 180 init_waitqueue_head(&wq->err_queue); 181 init_completion(&wq->wq_dead); 182 init_completion(&wq->wq_resurrect); 183 wq->max_xfer_bytes = WQ_DEFAULT_MAX_XFER; 184 idxd_wq_set_max_batch_size(idxd->data->type, wq, WQ_DEFAULT_MAX_BATCH); 185 wq->enqcmds_retries = IDXD_ENQCMDS_RETRIES; 186 wq->wqcfg = kzalloc_node(idxd->wqcfg_size, GFP_KERNEL, dev_to_node(dev)); 187 if (!wq->wqcfg) { 188 put_device(conf_dev); 189 rc = -ENOMEM; 190 goto err; 191 } 192 193 if (idxd->hw.wq_cap.op_config) { 194 wq->opcap_bmap = bitmap_zalloc(IDXD_MAX_OPCAP_BITS, GFP_KERNEL); 195 if (!wq->opcap_bmap) { 196 put_device(conf_dev); 197 rc = -ENOMEM; 198 goto err; 199 } 200 bitmap_copy(wq->opcap_bmap, idxd->opcap_bmap, IDXD_MAX_OPCAP_BITS); 201 } 202 idxd->wqs[i] = wq; 203 } 204 205 return 0; 206 207 err: 208 while (--i >= 0) { 209 wq = idxd->wqs[i]; 210 conf_dev = wq_confdev(wq); 211 put_device(conf_dev); 212 } 213 return rc; 214 } 215 216 static int idxd_setup_engines(struct idxd_device *idxd) 217 { 218 struct idxd_engine *engine; 219 struct device *dev = &idxd->pdev->dev; 220 struct device *conf_dev; 221 int i, rc; 222 223 idxd->engines = kcalloc_node(idxd->max_engines, sizeof(struct idxd_engine *), 224 GFP_KERNEL, dev_to_node(dev)); 225 if (!idxd->engines) 226 return -ENOMEM; 227 228 for (i = 0; i < idxd->max_engines; i++) { 229 engine = kzalloc_node(sizeof(*engine), GFP_KERNEL, dev_to_node(dev)); 230 if (!engine) { 231 rc = -ENOMEM; 232 goto err; 233 } 234 235 idxd_dev_set_type(&engine->idxd_dev, IDXD_DEV_ENGINE); 236 conf_dev = engine_confdev(engine); 237 engine->id = i; 238 engine->idxd = idxd; 239 device_initialize(conf_dev); 240 conf_dev->parent = idxd_confdev(idxd); 241 conf_dev->bus = &dsa_bus_type; 242 conf_dev->type = &idxd_engine_device_type; 243 rc = dev_set_name(conf_dev, "engine%d.%d", idxd->id, engine->id); 244 if (rc < 0) { 245 put_device(conf_dev); 246 goto err; 247 } 248 249 idxd->engines[i] = engine; 250 } 251 252 return 0; 253 254 err: 255 while (--i >= 0) { 256 engine = idxd->engines[i]; 257 conf_dev = engine_confdev(engine); 258 put_device(conf_dev); 259 } 260 return rc; 261 } 262 263 static int idxd_setup_groups(struct idxd_device *idxd) 264 { 265 struct device *dev = &idxd->pdev->dev; 266 struct device *conf_dev; 267 struct idxd_group *group; 268 int i, rc; 269 270 idxd->groups = kcalloc_node(idxd->max_groups, sizeof(struct idxd_group *), 271 GFP_KERNEL, dev_to_node(dev)); 272 if (!idxd->groups) 273 return -ENOMEM; 274 275 for (i = 0; i < idxd->max_groups; i++) { 276 group = kzalloc_node(sizeof(*group), GFP_KERNEL, dev_to_node(dev)); 277 if (!group) { 278 rc = -ENOMEM; 279 goto err; 280 } 281 282 idxd_dev_set_type(&group->idxd_dev, IDXD_DEV_GROUP); 283 conf_dev = group_confdev(group); 284 group->id = i; 285 group->idxd = idxd; 286 device_initialize(conf_dev); 287 conf_dev->parent = idxd_confdev(idxd); 288 conf_dev->bus = &dsa_bus_type; 289 conf_dev->type = &idxd_group_device_type; 290 rc = dev_set_name(conf_dev, "group%d.%d", idxd->id, group->id); 291 if (rc < 0) { 292 put_device(conf_dev); 293 goto err; 294 } 295 296 idxd->groups[i] = group; 297 if (idxd->hw.version <= DEVICE_VERSION_2 && !tc_override) { 298 group->tc_a = 1; 299 group->tc_b = 1; 300 } else { 301 group->tc_a = -1; 302 group->tc_b = -1; 303 } 304 /* 305 * The default value is the same as the value of 306 * total read buffers in GRPCAP. 307 */ 308 group->rdbufs_allowed = idxd->max_rdbufs; 309 } 310 311 return 0; 312 313 err: 314 while (--i >= 0) { 315 group = idxd->groups[i]; 316 put_device(group_confdev(group)); 317 } 318 return rc; 319 } 320 321 static void idxd_cleanup_internals(struct idxd_device *idxd) 322 { 323 int i; 324 325 for (i = 0; i < idxd->max_groups; i++) 326 put_device(group_confdev(idxd->groups[i])); 327 for (i = 0; i < idxd->max_engines; i++) 328 put_device(engine_confdev(idxd->engines[i])); 329 for (i = 0; i < idxd->max_wqs; i++) 330 put_device(wq_confdev(idxd->wqs[i])); 331 destroy_workqueue(idxd->wq); 332 } 333 334 static int idxd_init_evl(struct idxd_device *idxd) 335 { 336 struct device *dev = &idxd->pdev->dev; 337 struct idxd_evl *evl; 338 339 if (idxd->hw.gen_cap.evl_support == 0) 340 return 0; 341 342 evl = kzalloc_node(sizeof(*evl), GFP_KERNEL, dev_to_node(dev)); 343 if (!evl) 344 return -ENOMEM; 345 346 evl->size = IDXD_EVL_SIZE_MIN; 347 idxd->evl = evl; 348 return 0; 349 } 350 351 static int idxd_setup_internals(struct idxd_device *idxd) 352 { 353 struct device *dev = &idxd->pdev->dev; 354 int rc, i; 355 356 init_waitqueue_head(&idxd->cmd_waitq); 357 358 rc = idxd_setup_wqs(idxd); 359 if (rc < 0) 360 goto err_wqs; 361 362 rc = idxd_setup_engines(idxd); 363 if (rc < 0) 364 goto err_engine; 365 366 rc = idxd_setup_groups(idxd); 367 if (rc < 0) 368 goto err_group; 369 370 idxd->wq = create_workqueue(dev_name(dev)); 371 if (!idxd->wq) { 372 rc = -ENOMEM; 373 goto err_wkq_create; 374 } 375 376 rc = idxd_init_evl(idxd); 377 if (rc < 0) 378 goto err_evl; 379 380 return 0; 381 382 err_evl: 383 destroy_workqueue(idxd->wq); 384 err_wkq_create: 385 for (i = 0; i < idxd->max_groups; i++) 386 put_device(group_confdev(idxd->groups[i])); 387 err_group: 388 for (i = 0; i < idxd->max_engines; i++) 389 put_device(engine_confdev(idxd->engines[i])); 390 err_engine: 391 for (i = 0; i < idxd->max_wqs; i++) 392 put_device(wq_confdev(idxd->wqs[i])); 393 err_wqs: 394 return rc; 395 } 396 397 static void idxd_read_table_offsets(struct idxd_device *idxd) 398 { 399 union offsets_reg offsets; 400 struct device *dev = &idxd->pdev->dev; 401 402 offsets.bits[0] = ioread64(idxd->reg_base + IDXD_TABLE_OFFSET); 403 offsets.bits[1] = ioread64(idxd->reg_base + IDXD_TABLE_OFFSET + sizeof(u64)); 404 idxd->grpcfg_offset = offsets.grpcfg * IDXD_TABLE_MULT; 405 dev_dbg(dev, "IDXD Group Config Offset: %#x\n", idxd->grpcfg_offset); 406 idxd->wqcfg_offset = offsets.wqcfg * IDXD_TABLE_MULT; 407 dev_dbg(dev, "IDXD Work Queue Config Offset: %#x\n", idxd->wqcfg_offset); 408 idxd->msix_perm_offset = offsets.msix_perm * IDXD_TABLE_MULT; 409 dev_dbg(dev, "IDXD MSIX Permission Offset: %#x\n", idxd->msix_perm_offset); 410 idxd->perfmon_offset = offsets.perfmon * IDXD_TABLE_MULT; 411 dev_dbg(dev, "IDXD Perfmon Offset: %#x\n", idxd->perfmon_offset); 412 } 413 414 void multi_u64_to_bmap(unsigned long *bmap, u64 *val, int count) 415 { 416 int i, j, nr; 417 418 for (i = 0, nr = 0; i < count; i++) { 419 for (j = 0; j < BITS_PER_LONG_LONG; j++) { 420 if (val[i] & BIT(j)) 421 set_bit(nr, bmap); 422 nr++; 423 } 424 } 425 } 426 427 static void idxd_read_caps(struct idxd_device *idxd) 428 { 429 struct device *dev = &idxd->pdev->dev; 430 int i; 431 432 /* reading generic capabilities */ 433 idxd->hw.gen_cap.bits = ioread64(idxd->reg_base + IDXD_GENCAP_OFFSET); 434 dev_dbg(dev, "gen_cap: %#llx\n", idxd->hw.gen_cap.bits); 435 436 if (idxd->hw.gen_cap.cmd_cap) { 437 idxd->hw.cmd_cap = ioread32(idxd->reg_base + IDXD_CMDCAP_OFFSET); 438 dev_dbg(dev, "cmd_cap: %#x\n", idxd->hw.cmd_cap); 439 } 440 441 /* reading command capabilities */ 442 if (idxd->hw.cmd_cap & BIT(IDXD_CMD_REQUEST_INT_HANDLE)) 443 idxd->request_int_handles = true; 444 445 idxd->max_xfer_bytes = 1ULL << idxd->hw.gen_cap.max_xfer_shift; 446 dev_dbg(dev, "max xfer size: %llu bytes\n", idxd->max_xfer_bytes); 447 idxd_set_max_batch_size(idxd->data->type, idxd, 1U << idxd->hw.gen_cap.max_batch_shift); 448 dev_dbg(dev, "max batch size: %u\n", idxd->max_batch_size); 449 if (idxd->hw.gen_cap.config_en) 450 set_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags); 451 452 /* reading group capabilities */ 453 idxd->hw.group_cap.bits = 454 ioread64(idxd->reg_base + IDXD_GRPCAP_OFFSET); 455 dev_dbg(dev, "group_cap: %#llx\n", idxd->hw.group_cap.bits); 456 idxd->max_groups = idxd->hw.group_cap.num_groups; 457 dev_dbg(dev, "max groups: %u\n", idxd->max_groups); 458 idxd->max_rdbufs = idxd->hw.group_cap.total_rdbufs; 459 dev_dbg(dev, "max read buffers: %u\n", idxd->max_rdbufs); 460 idxd->nr_rdbufs = idxd->max_rdbufs; 461 462 /* read engine capabilities */ 463 idxd->hw.engine_cap.bits = 464 ioread64(idxd->reg_base + IDXD_ENGCAP_OFFSET); 465 dev_dbg(dev, "engine_cap: %#llx\n", idxd->hw.engine_cap.bits); 466 idxd->max_engines = idxd->hw.engine_cap.num_engines; 467 dev_dbg(dev, "max engines: %u\n", idxd->max_engines); 468 469 /* read workqueue capabilities */ 470 idxd->hw.wq_cap.bits = ioread64(idxd->reg_base + IDXD_WQCAP_OFFSET); 471 dev_dbg(dev, "wq_cap: %#llx\n", idxd->hw.wq_cap.bits); 472 idxd->max_wq_size = idxd->hw.wq_cap.total_wq_size; 473 dev_dbg(dev, "total workqueue size: %u\n", idxd->max_wq_size); 474 idxd->max_wqs = idxd->hw.wq_cap.num_wqs; 475 dev_dbg(dev, "max workqueues: %u\n", idxd->max_wqs); 476 idxd->wqcfg_size = 1 << (idxd->hw.wq_cap.wqcfg_size + IDXD_WQCFG_MIN); 477 dev_dbg(dev, "wqcfg size: %u\n", idxd->wqcfg_size); 478 479 /* reading operation capabilities */ 480 for (i = 0; i < 4; i++) { 481 idxd->hw.opcap.bits[i] = ioread64(idxd->reg_base + 482 IDXD_OPCAP_OFFSET + i * sizeof(u64)); 483 dev_dbg(dev, "opcap[%d]: %#llx\n", i, idxd->hw.opcap.bits[i]); 484 } 485 multi_u64_to_bmap(idxd->opcap_bmap, &idxd->hw.opcap.bits[0], 4); 486 487 /* read iaa cap */ 488 if (idxd->data->type == IDXD_TYPE_IAX && idxd->hw.version >= DEVICE_VERSION_2) 489 idxd->hw.iaa_cap.bits = ioread64(idxd->reg_base + IDXD_IAACAP_OFFSET); 490 } 491 492 static struct idxd_device *idxd_alloc(struct pci_dev *pdev, struct idxd_driver_data *data) 493 { 494 struct device *dev = &pdev->dev; 495 struct device *conf_dev; 496 struct idxd_device *idxd; 497 int rc; 498 499 idxd = kzalloc_node(sizeof(*idxd), GFP_KERNEL, dev_to_node(dev)); 500 if (!idxd) 501 return NULL; 502 503 conf_dev = idxd_confdev(idxd); 504 idxd->pdev = pdev; 505 idxd->data = data; 506 idxd_dev_set_type(&idxd->idxd_dev, idxd->data->type); 507 idxd->id = ida_alloc(&idxd_ida, GFP_KERNEL); 508 if (idxd->id < 0) 509 return NULL; 510 511 idxd->opcap_bmap = bitmap_zalloc_node(IDXD_MAX_OPCAP_BITS, GFP_KERNEL, dev_to_node(dev)); 512 if (!idxd->opcap_bmap) { 513 ida_free(&idxd_ida, idxd->id); 514 return NULL; 515 } 516 517 device_initialize(conf_dev); 518 conf_dev->parent = dev; 519 conf_dev->bus = &dsa_bus_type; 520 conf_dev->type = idxd->data->dev_type; 521 rc = dev_set_name(conf_dev, "%s%d", idxd->data->name_prefix, idxd->id); 522 if (rc < 0) { 523 put_device(conf_dev); 524 return NULL; 525 } 526 527 spin_lock_init(&idxd->dev_lock); 528 spin_lock_init(&idxd->cmd_lock); 529 530 return idxd; 531 } 532 533 static int idxd_enable_system_pasid(struct idxd_device *idxd) 534 { 535 return -EOPNOTSUPP; 536 } 537 538 static void idxd_disable_system_pasid(struct idxd_device *idxd) 539 { 540 541 iommu_sva_unbind_device(idxd->sva); 542 idxd->sva = NULL; 543 } 544 545 static int idxd_probe(struct idxd_device *idxd) 546 { 547 struct pci_dev *pdev = idxd->pdev; 548 struct device *dev = &pdev->dev; 549 int rc; 550 551 dev_dbg(dev, "%s entered and resetting device\n", __func__); 552 rc = idxd_device_init_reset(idxd); 553 if (rc < 0) 554 return rc; 555 556 dev_dbg(dev, "IDXD reset complete\n"); 557 558 if (IS_ENABLED(CONFIG_INTEL_IDXD_SVM) && sva) { 559 if (iommu_dev_enable_feature(dev, IOMMU_DEV_FEAT_SVA)) { 560 dev_warn(dev, "Unable to turn on user SVA feature.\n"); 561 } else { 562 set_bit(IDXD_FLAG_USER_PASID_ENABLED, &idxd->flags); 563 564 if (idxd_enable_system_pasid(idxd)) 565 dev_warn(dev, "No in-kernel DMA with PASID.\n"); 566 else 567 set_bit(IDXD_FLAG_PASID_ENABLED, &idxd->flags); 568 } 569 } else if (!sva) { 570 dev_warn(dev, "User forced SVA off via module param.\n"); 571 } 572 573 idxd_read_caps(idxd); 574 idxd_read_table_offsets(idxd); 575 576 rc = idxd_setup_internals(idxd); 577 if (rc) 578 goto err; 579 580 /* If the configs are readonly, then load them from device */ 581 if (!test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) { 582 dev_dbg(dev, "Loading RO device config\n"); 583 rc = idxd_device_load_config(idxd); 584 if (rc < 0) 585 goto err_config; 586 } 587 588 rc = idxd_setup_interrupts(idxd); 589 if (rc) 590 goto err_config; 591 592 idxd->major = idxd_cdev_get_major(idxd); 593 594 rc = perfmon_pmu_init(idxd); 595 if (rc < 0) 596 dev_warn(dev, "Failed to initialize perfmon. No PMU support: %d\n", rc); 597 598 dev_dbg(dev, "IDXD device %d probed successfully\n", idxd->id); 599 return 0; 600 601 err_config: 602 idxd_cleanup_internals(idxd); 603 err: 604 if (device_pasid_enabled(idxd)) 605 idxd_disable_system_pasid(idxd); 606 if (device_user_pasid_enabled(idxd)) 607 iommu_dev_disable_feature(dev, IOMMU_DEV_FEAT_SVA); 608 return rc; 609 } 610 611 static void idxd_cleanup(struct idxd_device *idxd) 612 { 613 struct device *dev = &idxd->pdev->dev; 614 615 perfmon_pmu_remove(idxd); 616 idxd_cleanup_interrupts(idxd); 617 idxd_cleanup_internals(idxd); 618 if (device_pasid_enabled(idxd)) 619 idxd_disable_system_pasid(idxd); 620 if (device_user_pasid_enabled(idxd)) 621 iommu_dev_disable_feature(dev, IOMMU_DEV_FEAT_SVA); 622 } 623 624 static int idxd_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 625 { 626 struct device *dev = &pdev->dev; 627 struct idxd_device *idxd; 628 struct idxd_driver_data *data = (struct idxd_driver_data *)id->driver_data; 629 int rc; 630 631 rc = pci_enable_device(pdev); 632 if (rc) 633 return rc; 634 635 dev_dbg(dev, "Alloc IDXD context\n"); 636 idxd = idxd_alloc(pdev, data); 637 if (!idxd) { 638 rc = -ENOMEM; 639 goto err_idxd_alloc; 640 } 641 642 dev_dbg(dev, "Mapping BARs\n"); 643 idxd->reg_base = pci_iomap(pdev, IDXD_MMIO_BAR, 0); 644 if (!idxd->reg_base) { 645 rc = -ENOMEM; 646 goto err_iomap; 647 } 648 649 dev_dbg(dev, "Set DMA masks\n"); 650 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 651 if (rc) 652 goto err; 653 654 dev_dbg(dev, "Set PCI master\n"); 655 pci_set_master(pdev); 656 pci_set_drvdata(pdev, idxd); 657 658 idxd->hw.version = ioread32(idxd->reg_base + IDXD_VER_OFFSET); 659 rc = idxd_probe(idxd); 660 if (rc) { 661 dev_err(dev, "Intel(R) IDXD DMA Engine init failed\n"); 662 goto err; 663 } 664 665 rc = idxd_register_devices(idxd); 666 if (rc) { 667 dev_err(dev, "IDXD sysfs setup failed\n"); 668 goto err_dev_register; 669 } 670 671 dev_info(&pdev->dev, "Intel(R) Accelerator Device (v%x)\n", 672 idxd->hw.version); 673 674 return 0; 675 676 err_dev_register: 677 idxd_cleanup(idxd); 678 err: 679 pci_iounmap(pdev, idxd->reg_base); 680 err_iomap: 681 put_device(idxd_confdev(idxd)); 682 err_idxd_alloc: 683 pci_disable_device(pdev); 684 return rc; 685 } 686 687 void idxd_wqs_quiesce(struct idxd_device *idxd) 688 { 689 struct idxd_wq *wq; 690 int i; 691 692 for (i = 0; i < idxd->max_wqs; i++) { 693 wq = idxd->wqs[i]; 694 if (wq->state == IDXD_WQ_ENABLED && wq->type == IDXD_WQT_KERNEL) 695 idxd_wq_quiesce(wq); 696 } 697 } 698 699 static void idxd_shutdown(struct pci_dev *pdev) 700 { 701 struct idxd_device *idxd = pci_get_drvdata(pdev); 702 struct idxd_irq_entry *irq_entry; 703 int rc; 704 705 rc = idxd_device_disable(idxd); 706 if (rc) 707 dev_err(&pdev->dev, "Disabling device failed\n"); 708 709 irq_entry = &idxd->ie; 710 synchronize_irq(irq_entry->vector); 711 idxd_mask_error_interrupts(idxd); 712 flush_workqueue(idxd->wq); 713 } 714 715 static void idxd_remove(struct pci_dev *pdev) 716 { 717 struct idxd_device *idxd = pci_get_drvdata(pdev); 718 struct idxd_irq_entry *irq_entry; 719 720 idxd_unregister_devices(idxd); 721 /* 722 * When ->release() is called for the idxd->conf_dev, it frees all the memory related 723 * to the idxd context. The driver still needs those bits in order to do the rest of 724 * the cleanup. However, we do need to unbound the idxd sub-driver. So take a ref 725 * on the device here to hold off the freeing while allowing the idxd sub-driver 726 * to unbind. 727 */ 728 get_device(idxd_confdev(idxd)); 729 device_unregister(idxd_confdev(idxd)); 730 idxd_shutdown(pdev); 731 if (device_pasid_enabled(idxd)) 732 idxd_disable_system_pasid(idxd); 733 734 irq_entry = idxd_get_ie(idxd, 0); 735 free_irq(irq_entry->vector, irq_entry); 736 pci_free_irq_vectors(pdev); 737 pci_iounmap(pdev, idxd->reg_base); 738 if (device_user_pasid_enabled(idxd)) 739 iommu_dev_disable_feature(&pdev->dev, IOMMU_DEV_FEAT_SVA); 740 pci_disable_device(pdev); 741 destroy_workqueue(idxd->wq); 742 perfmon_pmu_remove(idxd); 743 put_device(idxd_confdev(idxd)); 744 } 745 746 static struct pci_driver idxd_pci_driver = { 747 .name = DRV_NAME, 748 .id_table = idxd_pci_tbl, 749 .probe = idxd_pci_probe, 750 .remove = idxd_remove, 751 .shutdown = idxd_shutdown, 752 }; 753 754 static int __init idxd_init_module(void) 755 { 756 int err; 757 758 /* 759 * If the CPU does not support MOVDIR64B or ENQCMDS, there's no point in 760 * enumerating the device. We can not utilize it. 761 */ 762 if (!cpu_feature_enabled(X86_FEATURE_MOVDIR64B)) { 763 pr_warn("idxd driver failed to load without MOVDIR64B.\n"); 764 return -ENODEV; 765 } 766 767 if (!cpu_feature_enabled(X86_FEATURE_ENQCMD)) 768 pr_warn("Platform does not have ENQCMD(S) support.\n"); 769 else 770 support_enqcmd = true; 771 772 perfmon_init(); 773 774 err = idxd_driver_register(&idxd_drv); 775 if (err < 0) 776 goto err_idxd_driver_register; 777 778 err = idxd_driver_register(&idxd_dmaengine_drv); 779 if (err < 0) 780 goto err_idxd_dmaengine_driver_register; 781 782 err = idxd_driver_register(&idxd_user_drv); 783 if (err < 0) 784 goto err_idxd_user_driver_register; 785 786 err = idxd_cdev_register(); 787 if (err) 788 goto err_cdev_register; 789 790 err = pci_register_driver(&idxd_pci_driver); 791 if (err) 792 goto err_pci_register; 793 794 return 0; 795 796 err_pci_register: 797 idxd_cdev_remove(); 798 err_cdev_register: 799 idxd_driver_unregister(&idxd_user_drv); 800 err_idxd_user_driver_register: 801 idxd_driver_unregister(&idxd_dmaengine_drv); 802 err_idxd_dmaengine_driver_register: 803 idxd_driver_unregister(&idxd_drv); 804 err_idxd_driver_register: 805 return err; 806 } 807 module_init(idxd_init_module); 808 809 static void __exit idxd_exit_module(void) 810 { 811 idxd_driver_unregister(&idxd_user_drv); 812 idxd_driver_unregister(&idxd_dmaengine_drv); 813 idxd_driver_unregister(&idxd_drv); 814 pci_unregister_driver(&idxd_pci_driver); 815 idxd_cdev_remove(); 816 perfmon_exit(); 817 } 818 module_exit(idxd_exit_module); 819