1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */ 3 #ifndef _IDXD_H_ 4 #define _IDXD_H_ 5 6 #include <linux/sbitmap.h> 7 #include <linux/dmaengine.h> 8 #include <linux/percpu-rwsem.h> 9 #include <linux/wait.h> 10 #include <linux/cdev.h> 11 #include <linux/idr.h> 12 #include <linux/pci.h> 13 #include <linux/bitmap.h> 14 #include <linux/perf_event.h> 15 #include <linux/iommu.h> 16 #include <uapi/linux/idxd.h> 17 #include "registers.h" 18 19 #define IDXD_DRIVER_VERSION "1.00" 20 21 extern struct kmem_cache *idxd_desc_pool; 22 extern bool tc_override; 23 24 struct idxd_wq; 25 struct idxd_dev; 26 27 enum idxd_dev_type { 28 IDXD_DEV_NONE = -1, 29 IDXD_DEV_DSA = 0, 30 IDXD_DEV_IAX, 31 IDXD_DEV_WQ, 32 IDXD_DEV_GROUP, 33 IDXD_DEV_ENGINE, 34 IDXD_DEV_CDEV, 35 IDXD_DEV_CDEV_FILE, 36 IDXD_DEV_MAX_TYPE, 37 }; 38 39 struct idxd_dev { 40 struct device conf_dev; 41 enum idxd_dev_type type; 42 }; 43 44 #define IDXD_REG_TIMEOUT 50 45 #define IDXD_DRAIN_TIMEOUT 5000 46 47 enum idxd_type { 48 IDXD_TYPE_UNKNOWN = -1, 49 IDXD_TYPE_DSA = 0, 50 IDXD_TYPE_IAX, 51 IDXD_TYPE_MAX, 52 }; 53 54 #define IDXD_NAME_SIZE 128 55 #define IDXD_PMU_EVENT_MAX 64 56 57 #define IDXD_ENQCMDS_RETRIES 32 58 #define IDXD_ENQCMDS_MAX_RETRIES 64 59 60 struct idxd_device_driver { 61 const char *name; 62 enum idxd_dev_type *type; 63 int (*probe)(struct idxd_dev *idxd_dev); 64 void (*remove)(struct idxd_dev *idxd_dev); 65 struct device_driver drv; 66 }; 67 68 extern struct idxd_device_driver dsa_drv; 69 extern struct idxd_device_driver idxd_drv; 70 extern struct idxd_device_driver idxd_dmaengine_drv; 71 extern struct idxd_device_driver idxd_user_drv; 72 73 #define INVALID_INT_HANDLE -1 74 struct idxd_irq_entry { 75 int id; 76 int vector; 77 struct llist_head pending_llist; 78 struct list_head work_list; 79 /* 80 * Lock to protect access between irq thread process descriptor 81 * and irq thread processing error descriptor. 82 */ 83 spinlock_t list_lock; 84 int int_handle; 85 ioasid_t pasid; 86 }; 87 88 struct idxd_group { 89 struct idxd_dev idxd_dev; 90 struct idxd_device *idxd; 91 struct grpcfg grpcfg; 92 int id; 93 int num_engines; 94 int num_wqs; 95 bool use_rdbuf_limit; 96 u8 rdbufs_allowed; 97 u8 rdbufs_reserved; 98 int tc_a; 99 int tc_b; 100 int desc_progress_limit; 101 int batch_progress_limit; 102 }; 103 104 struct idxd_pmu { 105 struct idxd_device *idxd; 106 107 struct perf_event *event_list[IDXD_PMU_EVENT_MAX]; 108 int n_events; 109 110 DECLARE_BITMAP(used_mask, IDXD_PMU_EVENT_MAX); 111 112 struct pmu pmu; 113 char name[IDXD_NAME_SIZE]; 114 int cpu; 115 116 int n_counters; 117 int counter_width; 118 int n_event_categories; 119 120 bool per_counter_caps_supported; 121 unsigned long supported_event_categories; 122 123 unsigned long supported_filters; 124 int n_filters; 125 126 struct hlist_node cpuhp_node; 127 }; 128 129 #define IDXD_MAX_PRIORITY 0xf 130 131 enum { 132 COUNTER_FAULTS = 0, 133 COUNTER_FAULT_FAILS, 134 COUNTER_MAX 135 }; 136 137 enum idxd_wq_state { 138 IDXD_WQ_DISABLED = 0, 139 IDXD_WQ_ENABLED, 140 }; 141 142 enum idxd_wq_flag { 143 WQ_FLAG_DEDICATED = 0, 144 WQ_FLAG_BLOCK_ON_FAULT, 145 WQ_FLAG_ATS_DISABLE, 146 WQ_FLAG_PRS_DISABLE, 147 }; 148 149 enum idxd_wq_type { 150 IDXD_WQT_NONE = 0, 151 IDXD_WQT_KERNEL, 152 IDXD_WQT_USER, 153 }; 154 155 struct idxd_cdev { 156 struct idxd_wq *wq; 157 struct cdev cdev; 158 struct idxd_dev idxd_dev; 159 int minor; 160 }; 161 162 #define IDXD_ALLOCATED_BATCH_SIZE 128U 163 #define WQ_NAME_SIZE 1024 164 #define WQ_TYPE_SIZE 10 165 166 #define WQ_DEFAULT_QUEUE_DEPTH 16 167 #define WQ_DEFAULT_MAX_XFER SZ_2M 168 #define WQ_DEFAULT_MAX_BATCH 32 169 170 enum idxd_op_type { 171 IDXD_OP_BLOCK = 0, 172 IDXD_OP_NONBLOCK = 1, 173 }; 174 175 enum idxd_complete_type { 176 IDXD_COMPLETE_NORMAL = 0, 177 IDXD_COMPLETE_ABORT, 178 IDXD_COMPLETE_DEV_FAIL, 179 }; 180 181 struct idxd_dma_chan { 182 struct dma_chan chan; 183 struct idxd_wq *wq; 184 }; 185 186 struct idxd_wq { 187 void __iomem *portal; 188 u32 portal_offset; 189 unsigned int enqcmds_retries; 190 struct percpu_ref wq_active; 191 struct completion wq_dead; 192 struct completion wq_resurrect; 193 struct idxd_dev idxd_dev; 194 struct idxd_cdev *idxd_cdev; 195 struct wait_queue_head err_queue; 196 struct workqueue_struct *wq; 197 struct idxd_device *idxd; 198 int id; 199 struct idxd_irq_entry ie; 200 enum idxd_wq_type type; 201 struct idxd_group *group; 202 int client_count; 203 struct mutex wq_lock; /* mutex for workqueue */ 204 u32 size; 205 u32 threshold; 206 u32 priority; 207 enum idxd_wq_state state; 208 unsigned long flags; 209 union wqcfg *wqcfg; 210 unsigned long *opcap_bmap; 211 212 struct dsa_hw_desc **hw_descs; 213 int num_descs; 214 union { 215 struct dsa_completion_record *compls; 216 struct iax_completion_record *iax_compls; 217 }; 218 dma_addr_t compls_addr; 219 int compls_size; 220 struct idxd_desc **descs; 221 struct sbitmap_queue sbq; 222 struct idxd_dma_chan *idxd_chan; 223 char name[WQ_NAME_SIZE + 1]; 224 u64 max_xfer_bytes; 225 u32 max_batch_size; 226 227 /* Lock to protect upasid_xa access. */ 228 struct mutex uc_lock; 229 struct xarray upasid_xa; 230 }; 231 232 struct idxd_engine { 233 struct idxd_dev idxd_dev; 234 int id; 235 struct idxd_group *group; 236 struct idxd_device *idxd; 237 }; 238 239 /* shadow registers */ 240 struct idxd_hw { 241 u32 version; 242 union gen_cap_reg gen_cap; 243 union wq_cap_reg wq_cap; 244 union group_cap_reg group_cap; 245 union engine_cap_reg engine_cap; 246 struct opcap opcap; 247 u32 cmd_cap; 248 union iaa_cap_reg iaa_cap; 249 }; 250 251 enum idxd_device_state { 252 IDXD_DEV_HALTED = -1, 253 IDXD_DEV_DISABLED = 0, 254 IDXD_DEV_ENABLED, 255 }; 256 257 enum idxd_device_flag { 258 IDXD_FLAG_CONFIGURABLE = 0, 259 IDXD_FLAG_CMD_RUNNING, 260 IDXD_FLAG_PASID_ENABLED, 261 IDXD_FLAG_USER_PASID_ENABLED, 262 }; 263 264 struct idxd_dma_dev { 265 struct idxd_device *idxd; 266 struct dma_device dma; 267 }; 268 269 struct idxd_driver_data { 270 const char *name_prefix; 271 enum idxd_type type; 272 struct device_type *dev_type; 273 int compl_size; 274 int align; 275 int evl_cr_off; 276 int cr_status_off; 277 int cr_result_off; 278 }; 279 280 struct idxd_evl { 281 /* Lock to protect event log access. */ 282 spinlock_t lock; 283 void *log; 284 dma_addr_t dma; 285 /* Total size of event log = number of entries * entry size. */ 286 unsigned int log_size; 287 /* The number of entries in the event log. */ 288 u16 size; 289 u16 head; 290 unsigned long *bmap; 291 bool batch_fail[IDXD_MAX_BATCH_IDENT]; 292 }; 293 294 struct idxd_evl_fault { 295 struct work_struct work; 296 struct idxd_wq *wq; 297 u8 status; 298 299 /* make this last member always */ 300 struct __evl_entry entry[]; 301 }; 302 303 struct idxd_device { 304 struct idxd_dev idxd_dev; 305 struct idxd_driver_data *data; 306 struct list_head list; 307 struct idxd_hw hw; 308 enum idxd_device_state state; 309 unsigned long flags; 310 int id; 311 int major; 312 u32 cmd_status; 313 struct idxd_irq_entry ie; /* misc irq, msix 0 */ 314 315 struct pci_dev *pdev; 316 void __iomem *reg_base; 317 318 spinlock_t dev_lock; /* spinlock for device */ 319 spinlock_t cmd_lock; /* spinlock for device commands */ 320 struct completion *cmd_done; 321 struct idxd_group **groups; 322 struct idxd_wq **wqs; 323 struct idxd_engine **engines; 324 325 struct iommu_sva *sva; 326 unsigned int pasid; 327 328 int num_groups; 329 int irq_cnt; 330 bool request_int_handles; 331 332 u32 msix_perm_offset; 333 u32 wqcfg_offset; 334 u32 grpcfg_offset; 335 u32 perfmon_offset; 336 337 u64 max_xfer_bytes; 338 u32 max_batch_size; 339 int max_groups; 340 int max_engines; 341 int max_rdbufs; 342 int max_wqs; 343 int max_wq_size; 344 int rdbuf_limit; 345 int nr_rdbufs; /* non-reserved read buffers */ 346 unsigned int wqcfg_size; 347 unsigned long *wq_enable_map; 348 349 union sw_err_reg sw_err; 350 wait_queue_head_t cmd_waitq; 351 352 struct idxd_dma_dev *idxd_dma; 353 struct workqueue_struct *wq; 354 struct work_struct work; 355 356 struct idxd_pmu *idxd_pmu; 357 358 unsigned long *opcap_bmap; 359 struct idxd_evl *evl; 360 struct kmem_cache *evl_cache; 361 362 struct dentry *dbgfs_dir; 363 struct dentry *dbgfs_evl_file; 364 }; 365 366 static inline unsigned int evl_ent_size(struct idxd_device *idxd) 367 { 368 return idxd->hw.gen_cap.evl_support ? 369 (32 * (1 << idxd->hw.gen_cap.evl_support)) : 0; 370 } 371 372 static inline unsigned int evl_size(struct idxd_device *idxd) 373 { 374 return idxd->evl->size * evl_ent_size(idxd); 375 } 376 377 /* IDXD software descriptor */ 378 struct idxd_desc { 379 union { 380 struct dsa_hw_desc *hw; 381 struct iax_hw_desc *iax_hw; 382 }; 383 dma_addr_t desc_dma; 384 union { 385 struct dsa_completion_record *completion; 386 struct iax_completion_record *iax_completion; 387 }; 388 dma_addr_t compl_dma; 389 struct dma_async_tx_descriptor txd; 390 struct llist_node llnode; 391 struct list_head list; 392 int id; 393 int cpu; 394 struct idxd_wq *wq; 395 }; 396 397 /* 398 * This is software defined error for the completion status. We overload the error code 399 * that will never appear in completion status and only SWERR register. 400 */ 401 enum idxd_completion_status { 402 IDXD_COMP_DESC_ABORT = 0xff, 403 }; 404 405 #define idxd_confdev(idxd) &idxd->idxd_dev.conf_dev 406 #define wq_confdev(wq) &wq->idxd_dev.conf_dev 407 #define engine_confdev(engine) &engine->idxd_dev.conf_dev 408 #define group_confdev(group) &group->idxd_dev.conf_dev 409 #define cdev_dev(cdev) &cdev->idxd_dev.conf_dev 410 #define user_ctx_dev(ctx) (&(ctx)->idxd_dev.conf_dev) 411 412 #define confdev_to_idxd_dev(dev) container_of(dev, struct idxd_dev, conf_dev) 413 #define idxd_dev_to_idxd(idxd_dev) container_of(idxd_dev, struct idxd_device, idxd_dev) 414 #define idxd_dev_to_wq(idxd_dev) container_of(idxd_dev, struct idxd_wq, idxd_dev) 415 416 static inline struct idxd_device *confdev_to_idxd(struct device *dev) 417 { 418 struct idxd_dev *idxd_dev = confdev_to_idxd_dev(dev); 419 420 return idxd_dev_to_idxd(idxd_dev); 421 } 422 423 static inline struct idxd_wq *confdev_to_wq(struct device *dev) 424 { 425 struct idxd_dev *idxd_dev = confdev_to_idxd_dev(dev); 426 427 return idxd_dev_to_wq(idxd_dev); 428 } 429 430 static inline struct idxd_engine *confdev_to_engine(struct device *dev) 431 { 432 struct idxd_dev *idxd_dev = confdev_to_idxd_dev(dev); 433 434 return container_of(idxd_dev, struct idxd_engine, idxd_dev); 435 } 436 437 static inline struct idxd_group *confdev_to_group(struct device *dev) 438 { 439 struct idxd_dev *idxd_dev = confdev_to_idxd_dev(dev); 440 441 return container_of(idxd_dev, struct idxd_group, idxd_dev); 442 } 443 444 static inline struct idxd_cdev *dev_to_cdev(struct device *dev) 445 { 446 struct idxd_dev *idxd_dev = confdev_to_idxd_dev(dev); 447 448 return container_of(idxd_dev, struct idxd_cdev, idxd_dev); 449 } 450 451 static inline void idxd_dev_set_type(struct idxd_dev *idev, int type) 452 { 453 if (type >= IDXD_DEV_MAX_TYPE) { 454 idev->type = IDXD_DEV_NONE; 455 return; 456 } 457 458 idev->type = type; 459 } 460 461 static inline struct idxd_irq_entry *idxd_get_ie(struct idxd_device *idxd, int idx) 462 { 463 return (idx == 0) ? &idxd->ie : &idxd->wqs[idx - 1]->ie; 464 } 465 466 static inline struct idxd_wq *ie_to_wq(struct idxd_irq_entry *ie) 467 { 468 return container_of(ie, struct idxd_wq, ie); 469 } 470 471 static inline struct idxd_device *ie_to_idxd(struct idxd_irq_entry *ie) 472 { 473 return container_of(ie, struct idxd_device, ie); 474 } 475 476 extern struct bus_type dsa_bus_type; 477 478 extern bool support_enqcmd; 479 extern struct ida idxd_ida; 480 extern struct device_type dsa_device_type; 481 extern struct device_type iax_device_type; 482 extern struct device_type idxd_wq_device_type; 483 extern struct device_type idxd_engine_device_type; 484 extern struct device_type idxd_group_device_type; 485 486 static inline bool is_dsa_dev(struct idxd_dev *idxd_dev) 487 { 488 return idxd_dev->type == IDXD_DEV_DSA; 489 } 490 491 static inline bool is_iax_dev(struct idxd_dev *idxd_dev) 492 { 493 return idxd_dev->type == IDXD_DEV_IAX; 494 } 495 496 static inline bool is_idxd_dev(struct idxd_dev *idxd_dev) 497 { 498 return is_dsa_dev(idxd_dev) || is_iax_dev(idxd_dev); 499 } 500 501 static inline bool is_idxd_wq_dev(struct idxd_dev *idxd_dev) 502 { 503 return idxd_dev->type == IDXD_DEV_WQ; 504 } 505 506 static inline bool is_idxd_wq_dmaengine(struct idxd_wq *wq) 507 { 508 if (wq->type == IDXD_WQT_KERNEL && strcmp(wq->name, "dmaengine") == 0) 509 return true; 510 return false; 511 } 512 513 static inline bool is_idxd_wq_user(struct idxd_wq *wq) 514 { 515 return wq->type == IDXD_WQT_USER; 516 } 517 518 static inline bool is_idxd_wq_kernel(struct idxd_wq *wq) 519 { 520 return wq->type == IDXD_WQT_KERNEL; 521 } 522 523 static inline bool wq_dedicated(struct idxd_wq *wq) 524 { 525 return test_bit(WQ_FLAG_DEDICATED, &wq->flags); 526 } 527 528 static inline bool wq_shared(struct idxd_wq *wq) 529 { 530 return !test_bit(WQ_FLAG_DEDICATED, &wq->flags); 531 } 532 533 static inline bool device_pasid_enabled(struct idxd_device *idxd) 534 { 535 return test_bit(IDXD_FLAG_PASID_ENABLED, &idxd->flags); 536 } 537 538 static inline bool device_user_pasid_enabled(struct idxd_device *idxd) 539 { 540 return test_bit(IDXD_FLAG_USER_PASID_ENABLED, &idxd->flags); 541 } 542 543 static inline bool wq_pasid_enabled(struct idxd_wq *wq) 544 { 545 return (is_idxd_wq_kernel(wq) && device_pasid_enabled(wq->idxd)) || 546 (is_idxd_wq_user(wq) && device_user_pasid_enabled(wq->idxd)); 547 } 548 549 static inline bool wq_shared_supported(struct idxd_wq *wq) 550 { 551 return (support_enqcmd && wq_pasid_enabled(wq)); 552 } 553 554 enum idxd_portal_prot { 555 IDXD_PORTAL_UNLIMITED = 0, 556 IDXD_PORTAL_LIMITED, 557 }; 558 559 enum idxd_interrupt_type { 560 IDXD_IRQ_MSIX = 0, 561 IDXD_IRQ_IMS, 562 }; 563 564 static inline int idxd_get_wq_portal_offset(enum idxd_portal_prot prot) 565 { 566 return prot * 0x1000; 567 } 568 569 static inline int idxd_get_wq_portal_full_offset(int wq_id, 570 enum idxd_portal_prot prot) 571 { 572 return ((wq_id * 4) << PAGE_SHIFT) + idxd_get_wq_portal_offset(prot); 573 } 574 575 #define IDXD_PORTAL_MASK (PAGE_SIZE - 1) 576 577 /* 578 * Even though this function can be accessed by multiple threads, it is safe to use. 579 * At worst the address gets used more than once before it gets incremented. We don't 580 * hit a threshold until iops becomes many million times a second. So the occasional 581 * reuse of the same address is tolerable compare to using an atomic variable. This is 582 * safe on a system that has atomic load/store for 32bit integers. Given that this is an 583 * Intel iEP device, that should not be a problem. 584 */ 585 static inline void __iomem *idxd_wq_portal_addr(struct idxd_wq *wq) 586 { 587 int ofs = wq->portal_offset; 588 589 wq->portal_offset = (ofs + sizeof(struct dsa_raw_desc)) & IDXD_PORTAL_MASK; 590 return wq->portal + ofs; 591 } 592 593 static inline void idxd_wq_get(struct idxd_wq *wq) 594 { 595 wq->client_count++; 596 } 597 598 static inline void idxd_wq_put(struct idxd_wq *wq) 599 { 600 wq->client_count--; 601 } 602 603 static inline int idxd_wq_refcount(struct idxd_wq *wq) 604 { 605 return wq->client_count; 606 }; 607 608 /* 609 * Intel IAA does not support batch processing. 610 * The max batch size of device, max batch size of wq and 611 * max batch shift of wqcfg should be always 0 on IAA. 612 */ 613 static inline void idxd_set_max_batch_size(int idxd_type, struct idxd_device *idxd, 614 u32 max_batch_size) 615 { 616 if (idxd_type == IDXD_TYPE_IAX) 617 idxd->max_batch_size = 0; 618 else 619 idxd->max_batch_size = max_batch_size; 620 } 621 622 static inline void idxd_wq_set_max_batch_size(int idxd_type, struct idxd_wq *wq, 623 u32 max_batch_size) 624 { 625 if (idxd_type == IDXD_TYPE_IAX) 626 wq->max_batch_size = 0; 627 else 628 wq->max_batch_size = max_batch_size; 629 } 630 631 static inline void idxd_wqcfg_set_max_batch_shift(int idxd_type, union wqcfg *wqcfg, 632 u32 max_batch_shift) 633 { 634 if (idxd_type == IDXD_TYPE_IAX) 635 wqcfg->max_batch_shift = 0; 636 else 637 wqcfg->max_batch_shift = max_batch_shift; 638 } 639 640 int __must_check __idxd_driver_register(struct idxd_device_driver *idxd_drv, 641 struct module *module, const char *mod_name); 642 #define idxd_driver_register(driver) \ 643 __idxd_driver_register(driver, THIS_MODULE, KBUILD_MODNAME) 644 645 void idxd_driver_unregister(struct idxd_device_driver *idxd_drv); 646 647 #define module_idxd_driver(__idxd_driver) \ 648 module_driver(__idxd_driver, idxd_driver_register, idxd_driver_unregister) 649 650 int idxd_register_bus_type(void); 651 void idxd_unregister_bus_type(void); 652 int idxd_register_devices(struct idxd_device *idxd); 653 void idxd_unregister_devices(struct idxd_device *idxd); 654 int idxd_register_driver(void); 655 void idxd_unregister_driver(void); 656 void idxd_wqs_quiesce(struct idxd_device *idxd); 657 bool idxd_queue_int_handle_resubmit(struct idxd_desc *desc); 658 void multi_u64_to_bmap(unsigned long *bmap, u64 *val, int count); 659 660 /* device interrupt control */ 661 irqreturn_t idxd_misc_thread(int vec, void *data); 662 irqreturn_t idxd_wq_thread(int irq, void *data); 663 void idxd_mask_error_interrupts(struct idxd_device *idxd); 664 void idxd_unmask_error_interrupts(struct idxd_device *idxd); 665 666 /* device control */ 667 int idxd_register_idxd_drv(void); 668 void idxd_unregister_idxd_drv(void); 669 int idxd_device_drv_probe(struct idxd_dev *idxd_dev); 670 void idxd_device_drv_remove(struct idxd_dev *idxd_dev); 671 int drv_enable_wq(struct idxd_wq *wq); 672 void drv_disable_wq(struct idxd_wq *wq); 673 int idxd_device_init_reset(struct idxd_device *idxd); 674 int idxd_device_enable(struct idxd_device *idxd); 675 int idxd_device_disable(struct idxd_device *idxd); 676 void idxd_device_reset(struct idxd_device *idxd); 677 void idxd_device_clear_state(struct idxd_device *idxd); 678 int idxd_device_config(struct idxd_device *idxd); 679 void idxd_device_drain_pasid(struct idxd_device *idxd, int pasid); 680 int idxd_device_load_config(struct idxd_device *idxd); 681 int idxd_device_request_int_handle(struct idxd_device *idxd, int idx, int *handle, 682 enum idxd_interrupt_type irq_type); 683 int idxd_device_release_int_handle(struct idxd_device *idxd, int handle, 684 enum idxd_interrupt_type irq_type); 685 686 /* work queue control */ 687 void idxd_wqs_unmap_portal(struct idxd_device *idxd); 688 int idxd_wq_alloc_resources(struct idxd_wq *wq); 689 void idxd_wq_free_resources(struct idxd_wq *wq); 690 int idxd_wq_enable(struct idxd_wq *wq); 691 int idxd_wq_disable(struct idxd_wq *wq, bool reset_config); 692 void idxd_wq_drain(struct idxd_wq *wq); 693 void idxd_wq_reset(struct idxd_wq *wq); 694 int idxd_wq_map_portal(struct idxd_wq *wq); 695 void idxd_wq_unmap_portal(struct idxd_wq *wq); 696 int idxd_wq_set_pasid(struct idxd_wq *wq, int pasid); 697 int idxd_wq_disable_pasid(struct idxd_wq *wq); 698 void __idxd_wq_quiesce(struct idxd_wq *wq); 699 void idxd_wq_quiesce(struct idxd_wq *wq); 700 int idxd_wq_init_percpu_ref(struct idxd_wq *wq); 701 void idxd_wq_free_irq(struct idxd_wq *wq); 702 int idxd_wq_request_irq(struct idxd_wq *wq); 703 704 /* submission */ 705 int idxd_submit_desc(struct idxd_wq *wq, struct idxd_desc *desc); 706 struct idxd_desc *idxd_alloc_desc(struct idxd_wq *wq, enum idxd_op_type optype); 707 void idxd_free_desc(struct idxd_wq *wq, struct idxd_desc *desc); 708 int idxd_enqcmds(struct idxd_wq *wq, void __iomem *portal, const void *desc); 709 710 /* dmaengine */ 711 int idxd_register_dma_device(struct idxd_device *idxd); 712 void idxd_unregister_dma_device(struct idxd_device *idxd); 713 void idxd_parse_completion_status(u8 status, enum dmaengine_tx_result *res); 714 void idxd_dma_complete_txd(struct idxd_desc *desc, 715 enum idxd_complete_type comp_type, bool free_desc); 716 717 /* cdev */ 718 int idxd_cdev_register(void); 719 void idxd_cdev_remove(void); 720 int idxd_cdev_get_major(struct idxd_device *idxd); 721 int idxd_wq_add_cdev(struct idxd_wq *wq); 722 void idxd_wq_del_cdev(struct idxd_wq *wq); 723 int idxd_copy_cr(struct idxd_wq *wq, ioasid_t pasid, unsigned long addr, 724 void *buf, int len); 725 void idxd_user_counter_increment(struct idxd_wq *wq, u32 pasid, int index); 726 727 /* perfmon */ 728 #if IS_ENABLED(CONFIG_INTEL_IDXD_PERFMON) 729 int perfmon_pmu_init(struct idxd_device *idxd); 730 void perfmon_pmu_remove(struct idxd_device *idxd); 731 void perfmon_counter_overflow(struct idxd_device *idxd); 732 void perfmon_init(void); 733 void perfmon_exit(void); 734 #else 735 static inline int perfmon_pmu_init(struct idxd_device *idxd) { return 0; } 736 static inline void perfmon_pmu_remove(struct idxd_device *idxd) {} 737 static inline void perfmon_counter_overflow(struct idxd_device *idxd) {} 738 static inline void perfmon_init(void) {} 739 static inline void perfmon_exit(void) {} 740 #endif 741 742 /* debugfs */ 743 int idxd_device_init_debugfs(struct idxd_device *idxd); 744 void idxd_device_remove_debugfs(struct idxd_device *idxd); 745 int idxd_init_debugfs(void); 746 void idxd_remove_debugfs(void); 747 748 #endif 749