1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */ 3 #ifndef _IDXD_H_ 4 #define _IDXD_H_ 5 6 #include <linux/sbitmap.h> 7 #include <linux/dmaengine.h> 8 #include <linux/percpu-rwsem.h> 9 #include <linux/wait.h> 10 #include <linux/cdev.h> 11 #include <linux/idr.h> 12 #include <linux/pci.h> 13 #include <linux/ioasid.h> 14 #include <linux/perf_event.h> 15 #include <uapi/linux/idxd.h> 16 #include "registers.h" 17 18 #define IDXD_DRIVER_VERSION "1.00" 19 20 extern struct kmem_cache *idxd_desc_pool; 21 extern bool tc_override; 22 23 struct idxd_wq; 24 struct idxd_dev; 25 26 enum idxd_dev_type { 27 IDXD_DEV_NONE = -1, 28 IDXD_DEV_DSA = 0, 29 IDXD_DEV_IAX, 30 IDXD_DEV_WQ, 31 IDXD_DEV_GROUP, 32 IDXD_DEV_ENGINE, 33 IDXD_DEV_CDEV, 34 IDXD_DEV_MAX_TYPE, 35 }; 36 37 struct idxd_dev { 38 struct device conf_dev; 39 enum idxd_dev_type type; 40 }; 41 42 #define IDXD_REG_TIMEOUT 50 43 #define IDXD_DRAIN_TIMEOUT 5000 44 45 enum idxd_type { 46 IDXD_TYPE_UNKNOWN = -1, 47 IDXD_TYPE_DSA = 0, 48 IDXD_TYPE_IAX, 49 IDXD_TYPE_MAX, 50 }; 51 52 #define IDXD_NAME_SIZE 128 53 #define IDXD_PMU_EVENT_MAX 64 54 55 #define IDXD_ENQCMDS_RETRIES 32 56 #define IDXD_ENQCMDS_MAX_RETRIES 64 57 58 struct idxd_device_driver { 59 const char *name; 60 enum idxd_dev_type *type; 61 int (*probe)(struct idxd_dev *idxd_dev); 62 void (*remove)(struct idxd_dev *idxd_dev); 63 struct device_driver drv; 64 }; 65 66 extern struct idxd_device_driver dsa_drv; 67 extern struct idxd_device_driver idxd_drv; 68 extern struct idxd_device_driver idxd_dmaengine_drv; 69 extern struct idxd_device_driver idxd_user_drv; 70 71 #define INVALID_INT_HANDLE -1 72 struct idxd_irq_entry { 73 int id; 74 int vector; 75 struct llist_head pending_llist; 76 struct list_head work_list; 77 /* 78 * Lock to protect access between irq thread process descriptor 79 * and irq thread processing error descriptor. 80 */ 81 spinlock_t list_lock; 82 int int_handle; 83 ioasid_t pasid; 84 }; 85 86 struct idxd_group { 87 struct idxd_dev idxd_dev; 88 struct idxd_device *idxd; 89 struct grpcfg grpcfg; 90 int id; 91 int num_engines; 92 int num_wqs; 93 bool use_rdbuf_limit; 94 u8 rdbufs_allowed; 95 u8 rdbufs_reserved; 96 int tc_a; 97 int tc_b; 98 }; 99 100 struct idxd_pmu { 101 struct idxd_device *idxd; 102 103 struct perf_event *event_list[IDXD_PMU_EVENT_MAX]; 104 int n_events; 105 106 DECLARE_BITMAP(used_mask, IDXD_PMU_EVENT_MAX); 107 108 struct pmu pmu; 109 char name[IDXD_NAME_SIZE]; 110 int cpu; 111 112 int n_counters; 113 int counter_width; 114 int n_event_categories; 115 116 bool per_counter_caps_supported; 117 unsigned long supported_event_categories; 118 119 unsigned long supported_filters; 120 int n_filters; 121 122 struct hlist_node cpuhp_node; 123 }; 124 125 #define IDXD_MAX_PRIORITY 0xf 126 127 enum idxd_wq_state { 128 IDXD_WQ_DISABLED = 0, 129 IDXD_WQ_ENABLED, 130 }; 131 132 enum idxd_wq_flag { 133 WQ_FLAG_DEDICATED = 0, 134 WQ_FLAG_BLOCK_ON_FAULT, 135 }; 136 137 enum idxd_wq_type { 138 IDXD_WQT_NONE = 0, 139 IDXD_WQT_KERNEL, 140 IDXD_WQT_USER, 141 }; 142 143 struct idxd_cdev { 144 struct idxd_wq *wq; 145 struct cdev cdev; 146 struct idxd_dev idxd_dev; 147 int minor; 148 }; 149 150 #define IDXD_ALLOCATED_BATCH_SIZE 128U 151 #define WQ_NAME_SIZE 1024 152 #define WQ_TYPE_SIZE 10 153 154 #define WQ_DEFAULT_QUEUE_DEPTH 16 155 #define WQ_DEFAULT_MAX_XFER SZ_2M 156 #define WQ_DEFAULT_MAX_BATCH 32 157 158 enum idxd_op_type { 159 IDXD_OP_BLOCK = 0, 160 IDXD_OP_NONBLOCK = 1, 161 }; 162 163 enum idxd_complete_type { 164 IDXD_COMPLETE_NORMAL = 0, 165 IDXD_COMPLETE_ABORT, 166 IDXD_COMPLETE_DEV_FAIL, 167 }; 168 169 struct idxd_dma_chan { 170 struct dma_chan chan; 171 struct idxd_wq *wq; 172 }; 173 174 struct idxd_wq { 175 void __iomem *portal; 176 u32 portal_offset; 177 unsigned int enqcmds_retries; 178 struct percpu_ref wq_active; 179 struct completion wq_dead; 180 struct completion wq_resurrect; 181 struct idxd_dev idxd_dev; 182 struct idxd_cdev *idxd_cdev; 183 struct wait_queue_head err_queue; 184 struct idxd_device *idxd; 185 int id; 186 struct idxd_irq_entry ie; 187 enum idxd_wq_type type; 188 struct idxd_group *group; 189 int client_count; 190 struct mutex wq_lock; /* mutex for workqueue */ 191 u32 size; 192 u32 threshold; 193 u32 priority; 194 enum idxd_wq_state state; 195 unsigned long flags; 196 union wqcfg *wqcfg; 197 struct dsa_hw_desc **hw_descs; 198 int num_descs; 199 union { 200 struct dsa_completion_record *compls; 201 struct iax_completion_record *iax_compls; 202 }; 203 dma_addr_t compls_addr; 204 int compls_size; 205 struct idxd_desc **descs; 206 struct sbitmap_queue sbq; 207 struct idxd_dma_chan *idxd_chan; 208 char name[WQ_NAME_SIZE + 1]; 209 u64 max_xfer_bytes; 210 u32 max_batch_size; 211 bool ats_dis; 212 }; 213 214 struct idxd_engine { 215 struct idxd_dev idxd_dev; 216 int id; 217 struct idxd_group *group; 218 struct idxd_device *idxd; 219 }; 220 221 /* shadow registers */ 222 struct idxd_hw { 223 u32 version; 224 union gen_cap_reg gen_cap; 225 union wq_cap_reg wq_cap; 226 union group_cap_reg group_cap; 227 union engine_cap_reg engine_cap; 228 struct opcap opcap; 229 u32 cmd_cap; 230 }; 231 232 enum idxd_device_state { 233 IDXD_DEV_HALTED = -1, 234 IDXD_DEV_DISABLED = 0, 235 IDXD_DEV_ENABLED, 236 }; 237 238 enum idxd_device_flag { 239 IDXD_FLAG_CONFIGURABLE = 0, 240 IDXD_FLAG_CMD_RUNNING, 241 IDXD_FLAG_PASID_ENABLED, 242 }; 243 244 struct idxd_dma_dev { 245 struct idxd_device *idxd; 246 struct dma_device dma; 247 }; 248 249 struct idxd_driver_data { 250 const char *name_prefix; 251 enum idxd_type type; 252 struct device_type *dev_type; 253 int compl_size; 254 int align; 255 }; 256 257 struct idxd_device { 258 struct idxd_dev idxd_dev; 259 struct idxd_driver_data *data; 260 struct list_head list; 261 struct idxd_hw hw; 262 enum idxd_device_state state; 263 unsigned long flags; 264 int id; 265 int major; 266 u32 cmd_status; 267 struct idxd_irq_entry ie; /* misc irq, msix 0 */ 268 269 struct pci_dev *pdev; 270 void __iomem *reg_base; 271 272 spinlock_t dev_lock; /* spinlock for device */ 273 spinlock_t cmd_lock; /* spinlock for device commands */ 274 struct completion *cmd_done; 275 struct idxd_group **groups; 276 struct idxd_wq **wqs; 277 struct idxd_engine **engines; 278 279 struct iommu_sva *sva; 280 unsigned int pasid; 281 282 int num_groups; 283 int irq_cnt; 284 bool request_int_handles; 285 286 u32 msix_perm_offset; 287 u32 wqcfg_offset; 288 u32 grpcfg_offset; 289 u32 perfmon_offset; 290 291 u64 max_xfer_bytes; 292 u32 max_batch_size; 293 int max_groups; 294 int max_engines; 295 int max_rdbufs; 296 int max_wqs; 297 int max_wq_size; 298 int rdbuf_limit; 299 int nr_rdbufs; /* non-reserved read buffers */ 300 unsigned int wqcfg_size; 301 302 union sw_err_reg sw_err; 303 wait_queue_head_t cmd_waitq; 304 305 struct idxd_dma_dev *idxd_dma; 306 struct workqueue_struct *wq; 307 struct work_struct work; 308 309 struct idxd_pmu *idxd_pmu; 310 }; 311 312 /* IDXD software descriptor */ 313 struct idxd_desc { 314 union { 315 struct dsa_hw_desc *hw; 316 struct iax_hw_desc *iax_hw; 317 }; 318 dma_addr_t desc_dma; 319 union { 320 struct dsa_completion_record *completion; 321 struct iax_completion_record *iax_completion; 322 }; 323 dma_addr_t compl_dma; 324 struct dma_async_tx_descriptor txd; 325 struct llist_node llnode; 326 struct list_head list; 327 int id; 328 int cpu; 329 struct idxd_wq *wq; 330 }; 331 332 /* 333 * This is software defined error for the completion status. We overload the error code 334 * that will never appear in completion status and only SWERR register. 335 */ 336 enum idxd_completion_status { 337 IDXD_COMP_DESC_ABORT = 0xff, 338 }; 339 340 #define idxd_confdev(idxd) &idxd->idxd_dev.conf_dev 341 #define wq_confdev(wq) &wq->idxd_dev.conf_dev 342 #define engine_confdev(engine) &engine->idxd_dev.conf_dev 343 #define group_confdev(group) &group->idxd_dev.conf_dev 344 #define cdev_dev(cdev) &cdev->idxd_dev.conf_dev 345 346 #define confdev_to_idxd_dev(dev) container_of(dev, struct idxd_dev, conf_dev) 347 #define idxd_dev_to_idxd(idxd_dev) container_of(idxd_dev, struct idxd_device, idxd_dev) 348 #define idxd_dev_to_wq(idxd_dev) container_of(idxd_dev, struct idxd_wq, idxd_dev) 349 350 static inline struct idxd_device *confdev_to_idxd(struct device *dev) 351 { 352 struct idxd_dev *idxd_dev = confdev_to_idxd_dev(dev); 353 354 return idxd_dev_to_idxd(idxd_dev); 355 } 356 357 static inline struct idxd_wq *confdev_to_wq(struct device *dev) 358 { 359 struct idxd_dev *idxd_dev = confdev_to_idxd_dev(dev); 360 361 return idxd_dev_to_wq(idxd_dev); 362 } 363 364 static inline struct idxd_engine *confdev_to_engine(struct device *dev) 365 { 366 struct idxd_dev *idxd_dev = confdev_to_idxd_dev(dev); 367 368 return container_of(idxd_dev, struct idxd_engine, idxd_dev); 369 } 370 371 static inline struct idxd_group *confdev_to_group(struct device *dev) 372 { 373 struct idxd_dev *idxd_dev = confdev_to_idxd_dev(dev); 374 375 return container_of(idxd_dev, struct idxd_group, idxd_dev); 376 } 377 378 static inline struct idxd_cdev *dev_to_cdev(struct device *dev) 379 { 380 struct idxd_dev *idxd_dev = confdev_to_idxd_dev(dev); 381 382 return container_of(idxd_dev, struct idxd_cdev, idxd_dev); 383 } 384 385 static inline void idxd_dev_set_type(struct idxd_dev *idev, int type) 386 { 387 if (type >= IDXD_DEV_MAX_TYPE) { 388 idev->type = IDXD_DEV_NONE; 389 return; 390 } 391 392 idev->type = type; 393 } 394 395 static inline struct idxd_irq_entry *idxd_get_ie(struct idxd_device *idxd, int idx) 396 { 397 return (idx == 0) ? &idxd->ie : &idxd->wqs[idx - 1]->ie; 398 } 399 400 static inline struct idxd_wq *ie_to_wq(struct idxd_irq_entry *ie) 401 { 402 return container_of(ie, struct idxd_wq, ie); 403 } 404 405 static inline struct idxd_device *ie_to_idxd(struct idxd_irq_entry *ie) 406 { 407 return container_of(ie, struct idxd_device, ie); 408 } 409 410 extern struct bus_type dsa_bus_type; 411 412 extern bool support_enqcmd; 413 extern struct ida idxd_ida; 414 extern struct device_type dsa_device_type; 415 extern struct device_type iax_device_type; 416 extern struct device_type idxd_wq_device_type; 417 extern struct device_type idxd_engine_device_type; 418 extern struct device_type idxd_group_device_type; 419 420 static inline bool is_dsa_dev(struct idxd_dev *idxd_dev) 421 { 422 return idxd_dev->type == IDXD_DEV_DSA; 423 } 424 425 static inline bool is_iax_dev(struct idxd_dev *idxd_dev) 426 { 427 return idxd_dev->type == IDXD_DEV_IAX; 428 } 429 430 static inline bool is_idxd_dev(struct idxd_dev *idxd_dev) 431 { 432 return is_dsa_dev(idxd_dev) || is_iax_dev(idxd_dev); 433 } 434 435 static inline bool is_idxd_wq_dev(struct idxd_dev *idxd_dev) 436 { 437 return idxd_dev->type == IDXD_DEV_WQ; 438 } 439 440 static inline bool is_idxd_wq_dmaengine(struct idxd_wq *wq) 441 { 442 if (wq->type == IDXD_WQT_KERNEL && strcmp(wq->name, "dmaengine") == 0) 443 return true; 444 return false; 445 } 446 447 static inline bool is_idxd_wq_user(struct idxd_wq *wq) 448 { 449 return wq->type == IDXD_WQT_USER; 450 } 451 452 static inline bool is_idxd_wq_kernel(struct idxd_wq *wq) 453 { 454 return wq->type == IDXD_WQT_KERNEL; 455 } 456 457 static inline bool wq_dedicated(struct idxd_wq *wq) 458 { 459 return test_bit(WQ_FLAG_DEDICATED, &wq->flags); 460 } 461 462 static inline bool wq_shared(struct idxd_wq *wq) 463 { 464 return !test_bit(WQ_FLAG_DEDICATED, &wq->flags); 465 } 466 467 static inline bool device_pasid_enabled(struct idxd_device *idxd) 468 { 469 return test_bit(IDXD_FLAG_PASID_ENABLED, &idxd->flags); 470 } 471 472 static inline bool device_swq_supported(struct idxd_device *idxd) 473 { 474 return (support_enqcmd && device_pasid_enabled(idxd)); 475 } 476 477 enum idxd_portal_prot { 478 IDXD_PORTAL_UNLIMITED = 0, 479 IDXD_PORTAL_LIMITED, 480 }; 481 482 enum idxd_interrupt_type { 483 IDXD_IRQ_MSIX = 0, 484 IDXD_IRQ_IMS, 485 }; 486 487 static inline int idxd_get_wq_portal_offset(enum idxd_portal_prot prot) 488 { 489 return prot * 0x1000; 490 } 491 492 static inline int idxd_get_wq_portal_full_offset(int wq_id, 493 enum idxd_portal_prot prot) 494 { 495 return ((wq_id * 4) << PAGE_SHIFT) + idxd_get_wq_portal_offset(prot); 496 } 497 498 #define IDXD_PORTAL_MASK (PAGE_SIZE - 1) 499 500 /* 501 * Even though this function can be accessed by multiple threads, it is safe to use. 502 * At worst the address gets used more than once before it gets incremented. We don't 503 * hit a threshold until iops becomes many million times a second. So the occasional 504 * reuse of the same address is tolerable compare to using an atomic variable. This is 505 * safe on a system that has atomic load/store for 32bit integers. Given that this is an 506 * Intel iEP device, that should not be a problem. 507 */ 508 static inline void __iomem *idxd_wq_portal_addr(struct idxd_wq *wq) 509 { 510 int ofs = wq->portal_offset; 511 512 wq->portal_offset = (ofs + sizeof(struct dsa_raw_desc)) & IDXD_PORTAL_MASK; 513 return wq->portal + ofs; 514 } 515 516 static inline void idxd_wq_get(struct idxd_wq *wq) 517 { 518 wq->client_count++; 519 } 520 521 static inline void idxd_wq_put(struct idxd_wq *wq) 522 { 523 wq->client_count--; 524 } 525 526 static inline int idxd_wq_refcount(struct idxd_wq *wq) 527 { 528 return wq->client_count; 529 }; 530 531 int __must_check __idxd_driver_register(struct idxd_device_driver *idxd_drv, 532 struct module *module, const char *mod_name); 533 #define idxd_driver_register(driver) \ 534 __idxd_driver_register(driver, THIS_MODULE, KBUILD_MODNAME) 535 536 void idxd_driver_unregister(struct idxd_device_driver *idxd_drv); 537 538 #define module_idxd_driver(__idxd_driver) \ 539 module_driver(__idxd_driver, idxd_driver_register, idxd_driver_unregister) 540 541 int idxd_register_bus_type(void); 542 void idxd_unregister_bus_type(void); 543 int idxd_register_devices(struct idxd_device *idxd); 544 void idxd_unregister_devices(struct idxd_device *idxd); 545 int idxd_register_driver(void); 546 void idxd_unregister_driver(void); 547 void idxd_wqs_quiesce(struct idxd_device *idxd); 548 bool idxd_queue_int_handle_resubmit(struct idxd_desc *desc); 549 550 /* device interrupt control */ 551 irqreturn_t idxd_misc_thread(int vec, void *data); 552 irqreturn_t idxd_wq_thread(int irq, void *data); 553 void idxd_mask_error_interrupts(struct idxd_device *idxd); 554 void idxd_unmask_error_interrupts(struct idxd_device *idxd); 555 556 /* device control */ 557 int idxd_register_idxd_drv(void); 558 void idxd_unregister_idxd_drv(void); 559 int idxd_device_drv_probe(struct idxd_dev *idxd_dev); 560 void idxd_device_drv_remove(struct idxd_dev *idxd_dev); 561 int drv_enable_wq(struct idxd_wq *wq); 562 int __drv_enable_wq(struct idxd_wq *wq); 563 void drv_disable_wq(struct idxd_wq *wq); 564 void __drv_disable_wq(struct idxd_wq *wq); 565 int idxd_device_init_reset(struct idxd_device *idxd); 566 int idxd_device_enable(struct idxd_device *idxd); 567 int idxd_device_disable(struct idxd_device *idxd); 568 void idxd_device_reset(struct idxd_device *idxd); 569 void idxd_device_clear_state(struct idxd_device *idxd); 570 int idxd_device_config(struct idxd_device *idxd); 571 void idxd_device_drain_pasid(struct idxd_device *idxd, int pasid); 572 int idxd_device_load_config(struct idxd_device *idxd); 573 int idxd_device_request_int_handle(struct idxd_device *idxd, int idx, int *handle, 574 enum idxd_interrupt_type irq_type); 575 int idxd_device_release_int_handle(struct idxd_device *idxd, int handle, 576 enum idxd_interrupt_type irq_type); 577 578 /* work queue control */ 579 void idxd_wqs_unmap_portal(struct idxd_device *idxd); 580 int idxd_wq_alloc_resources(struct idxd_wq *wq); 581 void idxd_wq_free_resources(struct idxd_wq *wq); 582 int idxd_wq_enable(struct idxd_wq *wq); 583 int idxd_wq_disable(struct idxd_wq *wq, bool reset_config); 584 void idxd_wq_drain(struct idxd_wq *wq); 585 void idxd_wq_reset(struct idxd_wq *wq); 586 int idxd_wq_map_portal(struct idxd_wq *wq); 587 void idxd_wq_unmap_portal(struct idxd_wq *wq); 588 int idxd_wq_set_pasid(struct idxd_wq *wq, int pasid); 589 int idxd_wq_disable_pasid(struct idxd_wq *wq); 590 void __idxd_wq_quiesce(struct idxd_wq *wq); 591 void idxd_wq_quiesce(struct idxd_wq *wq); 592 int idxd_wq_init_percpu_ref(struct idxd_wq *wq); 593 void idxd_wq_free_irq(struct idxd_wq *wq); 594 int idxd_wq_request_irq(struct idxd_wq *wq); 595 596 /* submission */ 597 int idxd_submit_desc(struct idxd_wq *wq, struct idxd_desc *desc); 598 struct idxd_desc *idxd_alloc_desc(struct idxd_wq *wq, enum idxd_op_type optype); 599 void idxd_free_desc(struct idxd_wq *wq, struct idxd_desc *desc); 600 int idxd_enqcmds(struct idxd_wq *wq, void __iomem *portal, const void *desc); 601 602 /* dmaengine */ 603 int idxd_register_dma_device(struct idxd_device *idxd); 604 void idxd_unregister_dma_device(struct idxd_device *idxd); 605 int idxd_register_dma_channel(struct idxd_wq *wq); 606 void idxd_unregister_dma_channel(struct idxd_wq *wq); 607 void idxd_parse_completion_status(u8 status, enum dmaengine_tx_result *res); 608 void idxd_dma_complete_txd(struct idxd_desc *desc, 609 enum idxd_complete_type comp_type, bool free_desc); 610 611 /* cdev */ 612 int idxd_cdev_register(void); 613 void idxd_cdev_remove(void); 614 int idxd_cdev_get_major(struct idxd_device *idxd); 615 int idxd_wq_add_cdev(struct idxd_wq *wq); 616 void idxd_wq_del_cdev(struct idxd_wq *wq); 617 618 /* perfmon */ 619 #if IS_ENABLED(CONFIG_INTEL_IDXD_PERFMON) 620 int perfmon_pmu_init(struct idxd_device *idxd); 621 void perfmon_pmu_remove(struct idxd_device *idxd); 622 void perfmon_counter_overflow(struct idxd_device *idxd); 623 void perfmon_init(void); 624 void perfmon_exit(void); 625 #else 626 static inline int perfmon_pmu_init(struct idxd_device *idxd) { return 0; } 627 static inline void perfmon_pmu_remove(struct idxd_device *idxd) {} 628 static inline void perfmon_counter_overflow(struct idxd_device *idxd) {} 629 static inline void perfmon_init(void) {} 630 static inline void perfmon_exit(void) {} 631 #endif 632 633 #endif 634