1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */ 3 #ifndef _IDXD_H_ 4 #define _IDXD_H_ 5 6 #include <linux/sbitmap.h> 7 #include <linux/dmaengine.h> 8 #include <linux/percpu-rwsem.h> 9 #include <linux/wait.h> 10 #include <linux/cdev.h> 11 #include "registers.h" 12 13 #define IDXD_DRIVER_VERSION "1.00" 14 15 extern struct kmem_cache *idxd_desc_pool; 16 17 #define IDXD_REG_TIMEOUT 50 18 #define IDXD_DRAIN_TIMEOUT 5000 19 20 enum idxd_type { 21 IDXD_TYPE_UNKNOWN = -1, 22 IDXD_TYPE_DSA = 0, 23 IDXD_TYPE_MAX 24 }; 25 26 #define IDXD_NAME_SIZE 128 27 28 struct idxd_device_driver { 29 struct device_driver drv; 30 }; 31 32 struct idxd_irq_entry { 33 struct idxd_device *idxd; 34 int id; 35 struct llist_head pending_llist; 36 struct list_head work_list; 37 }; 38 39 struct idxd_group { 40 struct device conf_dev; 41 struct idxd_device *idxd; 42 struct grpcfg grpcfg; 43 int id; 44 int num_engines; 45 int num_wqs; 46 bool use_token_limit; 47 u8 tokens_allowed; 48 u8 tokens_reserved; 49 int tc_a; 50 int tc_b; 51 }; 52 53 #define IDXD_MAX_PRIORITY 0xf 54 55 enum idxd_wq_state { 56 IDXD_WQ_DISABLED = 0, 57 IDXD_WQ_ENABLED, 58 }; 59 60 enum idxd_wq_flag { 61 WQ_FLAG_DEDICATED = 0, 62 }; 63 64 enum idxd_wq_type { 65 IDXD_WQT_NONE = 0, 66 IDXD_WQT_KERNEL, 67 IDXD_WQT_USER, 68 }; 69 70 struct idxd_cdev { 71 struct cdev cdev; 72 struct device *dev; 73 int minor; 74 struct wait_queue_head err_queue; 75 }; 76 77 #define IDXD_ALLOCATED_BATCH_SIZE 128U 78 #define WQ_NAME_SIZE 1024 79 #define WQ_TYPE_SIZE 10 80 81 enum idxd_op_type { 82 IDXD_OP_BLOCK = 0, 83 IDXD_OP_NONBLOCK = 1, 84 }; 85 86 enum idxd_complete_type { 87 IDXD_COMPLETE_NORMAL = 0, 88 IDXD_COMPLETE_ABORT, 89 }; 90 91 struct idxd_wq { 92 void __iomem *dportal; 93 struct device conf_dev; 94 struct idxd_cdev idxd_cdev; 95 struct idxd_device *idxd; 96 int id; 97 enum idxd_wq_type type; 98 struct idxd_group *group; 99 int client_count; 100 struct mutex wq_lock; /* mutex for workqueue */ 101 u32 size; 102 u32 threshold; 103 u32 priority; 104 enum idxd_wq_state state; 105 unsigned long flags; 106 union wqcfg wqcfg; 107 u32 vec_ptr; /* interrupt steering */ 108 struct dsa_hw_desc **hw_descs; 109 int num_descs; 110 struct dsa_completion_record *compls; 111 dma_addr_t compls_addr; 112 int compls_size; 113 struct idxd_desc **descs; 114 struct sbitmap_queue sbq; 115 struct dma_chan dma_chan; 116 char name[WQ_NAME_SIZE + 1]; 117 }; 118 119 struct idxd_engine { 120 struct device conf_dev; 121 int id; 122 struct idxd_group *group; 123 struct idxd_device *idxd; 124 }; 125 126 /* shadow registers */ 127 struct idxd_hw { 128 u32 version; 129 union gen_cap_reg gen_cap; 130 union wq_cap_reg wq_cap; 131 union group_cap_reg group_cap; 132 union engine_cap_reg engine_cap; 133 struct opcap opcap; 134 }; 135 136 enum idxd_device_state { 137 IDXD_DEV_HALTED = -1, 138 IDXD_DEV_DISABLED = 0, 139 IDXD_DEV_CONF_READY, 140 IDXD_DEV_ENABLED, 141 }; 142 143 enum idxd_device_flag { 144 IDXD_FLAG_CONFIGURABLE = 0, 145 IDXD_FLAG_CMD_RUNNING, 146 }; 147 148 struct idxd_device { 149 enum idxd_type type; 150 struct device conf_dev; 151 struct list_head list; 152 struct idxd_hw hw; 153 enum idxd_device_state state; 154 unsigned long flags; 155 int id; 156 int major; 157 158 struct pci_dev *pdev; 159 void __iomem *reg_base; 160 161 spinlock_t dev_lock; /* spinlock for device */ 162 struct completion *cmd_done; 163 struct idxd_group *groups; 164 struct idxd_wq *wqs; 165 struct idxd_engine *engines; 166 167 int num_groups; 168 169 u32 msix_perm_offset; 170 u32 wqcfg_offset; 171 u32 grpcfg_offset; 172 u32 perfmon_offset; 173 174 u64 max_xfer_bytes; 175 u32 max_batch_size; 176 int max_groups; 177 int max_engines; 178 int max_tokens; 179 int max_wqs; 180 int max_wq_size; 181 int token_limit; 182 int nr_tokens; /* non-reserved tokens */ 183 184 union sw_err_reg sw_err; 185 wait_queue_head_t cmd_waitq; 186 struct msix_entry *msix_entries; 187 int num_wq_irqs; 188 struct idxd_irq_entry *irq_entries; 189 190 struct dma_device dma_dev; 191 struct workqueue_struct *wq; 192 struct work_struct work; 193 }; 194 195 /* IDXD software descriptor */ 196 struct idxd_desc { 197 struct dsa_hw_desc *hw; 198 dma_addr_t desc_dma; 199 struct dsa_completion_record *completion; 200 dma_addr_t compl_dma; 201 struct dma_async_tx_descriptor txd; 202 struct llist_node llnode; 203 struct list_head list; 204 int id; 205 int cpu; 206 struct idxd_wq *wq; 207 }; 208 209 #define confdev_to_idxd(dev) container_of(dev, struct idxd_device, conf_dev) 210 #define confdev_to_wq(dev) container_of(dev, struct idxd_wq, conf_dev) 211 212 extern struct bus_type dsa_bus_type; 213 214 static inline bool wq_dedicated(struct idxd_wq *wq) 215 { 216 return test_bit(WQ_FLAG_DEDICATED, &wq->flags); 217 } 218 219 enum idxd_portal_prot { 220 IDXD_PORTAL_UNLIMITED = 0, 221 IDXD_PORTAL_LIMITED, 222 }; 223 224 static inline int idxd_get_wq_portal_offset(enum idxd_portal_prot prot) 225 { 226 return prot * 0x1000; 227 } 228 229 static inline int idxd_get_wq_portal_full_offset(int wq_id, 230 enum idxd_portal_prot prot) 231 { 232 return ((wq_id * 4) << PAGE_SHIFT) + idxd_get_wq_portal_offset(prot); 233 } 234 235 static inline void idxd_set_type(struct idxd_device *idxd) 236 { 237 struct pci_dev *pdev = idxd->pdev; 238 239 if (pdev->device == PCI_DEVICE_ID_INTEL_DSA_SPR0) 240 idxd->type = IDXD_TYPE_DSA; 241 else 242 idxd->type = IDXD_TYPE_UNKNOWN; 243 } 244 245 static inline void idxd_wq_get(struct idxd_wq *wq) 246 { 247 wq->client_count++; 248 } 249 250 static inline void idxd_wq_put(struct idxd_wq *wq) 251 { 252 wq->client_count--; 253 } 254 255 static inline int idxd_wq_refcount(struct idxd_wq *wq) 256 { 257 return wq->client_count; 258 }; 259 260 const char *idxd_get_dev_name(struct idxd_device *idxd); 261 int idxd_register_bus_type(void); 262 void idxd_unregister_bus_type(void); 263 int idxd_setup_sysfs(struct idxd_device *idxd); 264 void idxd_cleanup_sysfs(struct idxd_device *idxd); 265 int idxd_register_driver(void); 266 void idxd_unregister_driver(void); 267 struct bus_type *idxd_get_bus_type(struct idxd_device *idxd); 268 269 /* device interrupt control */ 270 irqreturn_t idxd_irq_handler(int vec, void *data); 271 irqreturn_t idxd_misc_thread(int vec, void *data); 272 irqreturn_t idxd_wq_thread(int irq, void *data); 273 void idxd_mask_error_interrupts(struct idxd_device *idxd); 274 void idxd_unmask_error_interrupts(struct idxd_device *idxd); 275 void idxd_mask_msix_vectors(struct idxd_device *idxd); 276 void idxd_mask_msix_vector(struct idxd_device *idxd, int vec_id); 277 void idxd_unmask_msix_vector(struct idxd_device *idxd, int vec_id); 278 279 /* device control */ 280 void idxd_device_init_reset(struct idxd_device *idxd); 281 int idxd_device_enable(struct idxd_device *idxd); 282 int idxd_device_disable(struct idxd_device *idxd); 283 void idxd_device_reset(struct idxd_device *idxd); 284 void idxd_device_cleanup(struct idxd_device *idxd); 285 int idxd_device_config(struct idxd_device *idxd); 286 void idxd_device_wqs_clear_state(struct idxd_device *idxd); 287 288 /* work queue control */ 289 int idxd_wq_alloc_resources(struct idxd_wq *wq); 290 void idxd_wq_free_resources(struct idxd_wq *wq); 291 int idxd_wq_enable(struct idxd_wq *wq); 292 int idxd_wq_disable(struct idxd_wq *wq); 293 void idxd_wq_drain(struct idxd_wq *wq); 294 int idxd_wq_map_portal(struct idxd_wq *wq); 295 void idxd_wq_unmap_portal(struct idxd_wq *wq); 296 void idxd_wq_disable_cleanup(struct idxd_wq *wq); 297 298 /* submission */ 299 int idxd_submit_desc(struct idxd_wq *wq, struct idxd_desc *desc); 300 struct idxd_desc *idxd_alloc_desc(struct idxd_wq *wq, enum idxd_op_type optype); 301 void idxd_free_desc(struct idxd_wq *wq, struct idxd_desc *desc); 302 303 /* dmaengine */ 304 int idxd_register_dma_device(struct idxd_device *idxd); 305 void idxd_unregister_dma_device(struct idxd_device *idxd); 306 int idxd_register_dma_channel(struct idxd_wq *wq); 307 void idxd_unregister_dma_channel(struct idxd_wq *wq); 308 void idxd_parse_completion_status(u8 status, enum dmaengine_tx_result *res); 309 void idxd_dma_complete_txd(struct idxd_desc *desc, 310 enum idxd_complete_type comp_type); 311 dma_cookie_t idxd_dma_tx_submit(struct dma_async_tx_descriptor *tx); 312 313 /* cdev */ 314 int idxd_cdev_register(void); 315 void idxd_cdev_remove(void); 316 int idxd_cdev_get_major(struct idxd_device *idxd); 317 int idxd_wq_add_cdev(struct idxd_wq *wq); 318 void idxd_wq_del_cdev(struct idxd_wq *wq); 319 320 #endif 321