1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */ 3 #ifndef _IDXD_H_ 4 #define _IDXD_H_ 5 6 #include <linux/sbitmap.h> 7 #include <linux/dmaengine.h> 8 #include <linux/percpu-rwsem.h> 9 #include <linux/wait.h> 10 #include <linux/cdev.h> 11 #include <linux/idr.h> 12 #include <linux/pci.h> 13 #include <linux/perf_event.h> 14 #include <uapi/linux/idxd.h> 15 #include "registers.h" 16 17 #define IDXD_DRIVER_VERSION "1.00" 18 19 extern struct kmem_cache *idxd_desc_pool; 20 extern bool tc_override; 21 22 struct idxd_wq; 23 struct idxd_dev; 24 25 enum idxd_dev_type { 26 IDXD_DEV_NONE = -1, 27 IDXD_DEV_DSA = 0, 28 IDXD_DEV_IAX, 29 IDXD_DEV_WQ, 30 IDXD_DEV_GROUP, 31 IDXD_DEV_ENGINE, 32 IDXD_DEV_CDEV, 33 IDXD_DEV_MAX_TYPE, 34 }; 35 36 struct idxd_dev { 37 struct device conf_dev; 38 enum idxd_dev_type type; 39 }; 40 41 #define IDXD_REG_TIMEOUT 50 42 #define IDXD_DRAIN_TIMEOUT 5000 43 44 enum idxd_type { 45 IDXD_TYPE_UNKNOWN = -1, 46 IDXD_TYPE_DSA = 0, 47 IDXD_TYPE_IAX, 48 IDXD_TYPE_MAX, 49 }; 50 51 #define IDXD_NAME_SIZE 128 52 #define IDXD_PMU_EVENT_MAX 64 53 54 struct idxd_device_driver { 55 const char *name; 56 enum idxd_dev_type *type; 57 int (*probe)(struct idxd_dev *idxd_dev); 58 void (*remove)(struct idxd_dev *idxd_dev); 59 struct device_driver drv; 60 }; 61 62 extern struct idxd_device_driver dsa_drv; 63 extern struct idxd_device_driver idxd_drv; 64 extern struct idxd_device_driver idxd_dmaengine_drv; 65 extern struct idxd_device_driver idxd_user_drv; 66 67 struct idxd_irq_entry { 68 struct idxd_device *idxd; 69 int id; 70 int vector; 71 struct llist_head pending_llist; 72 struct list_head work_list; 73 /* 74 * Lock to protect access between irq thread process descriptor 75 * and irq thread processing error descriptor. 76 */ 77 spinlock_t list_lock; 78 }; 79 80 struct idxd_group { 81 struct idxd_dev idxd_dev; 82 struct idxd_device *idxd; 83 struct grpcfg grpcfg; 84 int id; 85 int num_engines; 86 int num_wqs; 87 bool use_token_limit; 88 u8 tokens_allowed; 89 u8 tokens_reserved; 90 int tc_a; 91 int tc_b; 92 }; 93 94 struct idxd_pmu { 95 struct idxd_device *idxd; 96 97 struct perf_event *event_list[IDXD_PMU_EVENT_MAX]; 98 int n_events; 99 100 DECLARE_BITMAP(used_mask, IDXD_PMU_EVENT_MAX); 101 102 struct pmu pmu; 103 char name[IDXD_NAME_SIZE]; 104 int cpu; 105 106 int n_counters; 107 int counter_width; 108 int n_event_categories; 109 110 bool per_counter_caps_supported; 111 unsigned long supported_event_categories; 112 113 unsigned long supported_filters; 114 int n_filters; 115 116 struct hlist_node cpuhp_node; 117 }; 118 119 #define IDXD_MAX_PRIORITY 0xf 120 121 enum idxd_wq_state { 122 IDXD_WQ_DISABLED = 0, 123 IDXD_WQ_ENABLED, 124 }; 125 126 enum idxd_wq_flag { 127 WQ_FLAG_DEDICATED = 0, 128 WQ_FLAG_BLOCK_ON_FAULT, 129 }; 130 131 enum idxd_wq_type { 132 IDXD_WQT_NONE = 0, 133 IDXD_WQT_KERNEL, 134 IDXD_WQT_USER, 135 }; 136 137 struct idxd_cdev { 138 struct idxd_wq *wq; 139 struct cdev cdev; 140 struct idxd_dev idxd_dev; 141 int minor; 142 }; 143 144 #define IDXD_ALLOCATED_BATCH_SIZE 128U 145 #define WQ_NAME_SIZE 1024 146 #define WQ_TYPE_SIZE 10 147 148 enum idxd_op_type { 149 IDXD_OP_BLOCK = 0, 150 IDXD_OP_NONBLOCK = 1, 151 }; 152 153 enum idxd_complete_type { 154 IDXD_COMPLETE_NORMAL = 0, 155 IDXD_COMPLETE_ABORT, 156 IDXD_COMPLETE_DEV_FAIL, 157 }; 158 159 struct idxd_dma_chan { 160 struct dma_chan chan; 161 struct idxd_wq *wq; 162 }; 163 164 struct idxd_wq { 165 void __iomem *portal; 166 u32 portal_offset; 167 struct percpu_ref wq_active; 168 struct completion wq_dead; 169 struct idxd_dev idxd_dev; 170 struct idxd_cdev *idxd_cdev; 171 struct wait_queue_head err_queue; 172 struct idxd_device *idxd; 173 int id; 174 enum idxd_wq_type type; 175 struct idxd_group *group; 176 int client_count; 177 struct mutex wq_lock; /* mutex for workqueue */ 178 u32 size; 179 u32 threshold; 180 u32 priority; 181 enum idxd_wq_state state; 182 unsigned long flags; 183 union wqcfg *wqcfg; 184 struct dsa_hw_desc **hw_descs; 185 int num_descs; 186 union { 187 struct dsa_completion_record *compls; 188 struct iax_completion_record *iax_compls; 189 }; 190 dma_addr_t compls_addr; 191 int compls_size; 192 struct idxd_desc **descs; 193 struct sbitmap_queue sbq; 194 struct idxd_dma_chan *idxd_chan; 195 char name[WQ_NAME_SIZE + 1]; 196 u64 max_xfer_bytes; 197 u32 max_batch_size; 198 bool ats_dis; 199 }; 200 201 struct idxd_engine { 202 struct idxd_dev idxd_dev; 203 int id; 204 struct idxd_group *group; 205 struct idxd_device *idxd; 206 }; 207 208 /* shadow registers */ 209 struct idxd_hw { 210 u32 version; 211 union gen_cap_reg gen_cap; 212 union wq_cap_reg wq_cap; 213 union group_cap_reg group_cap; 214 union engine_cap_reg engine_cap; 215 struct opcap opcap; 216 u32 cmd_cap; 217 }; 218 219 enum idxd_device_state { 220 IDXD_DEV_HALTED = -1, 221 IDXD_DEV_DISABLED = 0, 222 IDXD_DEV_ENABLED, 223 }; 224 225 enum idxd_device_flag { 226 IDXD_FLAG_CONFIGURABLE = 0, 227 IDXD_FLAG_CMD_RUNNING, 228 IDXD_FLAG_PASID_ENABLED, 229 }; 230 231 struct idxd_dma_dev { 232 struct idxd_device *idxd; 233 struct dma_device dma; 234 }; 235 236 struct idxd_driver_data { 237 const char *name_prefix; 238 enum idxd_type type; 239 struct device_type *dev_type; 240 int compl_size; 241 int align; 242 }; 243 244 struct idxd_device { 245 struct idxd_dev idxd_dev; 246 struct idxd_driver_data *data; 247 struct list_head list; 248 struct idxd_hw hw; 249 enum idxd_device_state state; 250 unsigned long flags; 251 int id; 252 int major; 253 u32 cmd_status; 254 255 struct pci_dev *pdev; 256 void __iomem *reg_base; 257 258 spinlock_t dev_lock; /* spinlock for device */ 259 spinlock_t cmd_lock; /* spinlock for device commands */ 260 struct completion *cmd_done; 261 struct idxd_group **groups; 262 struct idxd_wq **wqs; 263 struct idxd_engine **engines; 264 265 struct iommu_sva *sva; 266 unsigned int pasid; 267 268 int num_groups; 269 270 u32 msix_perm_offset; 271 u32 wqcfg_offset; 272 u32 grpcfg_offset; 273 u32 perfmon_offset; 274 275 u64 max_xfer_bytes; 276 u32 max_batch_size; 277 int max_groups; 278 int max_engines; 279 int max_tokens; 280 int max_wqs; 281 int max_wq_size; 282 int token_limit; 283 int nr_tokens; /* non-reserved tokens */ 284 unsigned int wqcfg_size; 285 286 union sw_err_reg sw_err; 287 wait_queue_head_t cmd_waitq; 288 int num_wq_irqs; 289 struct idxd_irq_entry *irq_entries; 290 291 struct idxd_dma_dev *idxd_dma; 292 struct workqueue_struct *wq; 293 struct work_struct work; 294 295 int *int_handles; 296 297 struct idxd_pmu *idxd_pmu; 298 }; 299 300 /* IDXD software descriptor */ 301 struct idxd_desc { 302 union { 303 struct dsa_hw_desc *hw; 304 struct iax_hw_desc *iax_hw; 305 }; 306 dma_addr_t desc_dma; 307 union { 308 struct dsa_completion_record *completion; 309 struct iax_completion_record *iax_completion; 310 }; 311 dma_addr_t compl_dma; 312 struct dma_async_tx_descriptor txd; 313 struct llist_node llnode; 314 struct list_head list; 315 int id; 316 int cpu; 317 struct idxd_wq *wq; 318 }; 319 320 /* 321 * This is software defined error for the completion status. We overload the error code 322 * that will never appear in completion status and only SWERR register. 323 */ 324 enum idxd_completion_status { 325 IDXD_COMP_DESC_ABORT = 0xff, 326 }; 327 328 #define idxd_confdev(idxd) &idxd->idxd_dev.conf_dev 329 #define wq_confdev(wq) &wq->idxd_dev.conf_dev 330 #define engine_confdev(engine) &engine->idxd_dev.conf_dev 331 #define group_confdev(group) &group->idxd_dev.conf_dev 332 #define cdev_dev(cdev) &cdev->idxd_dev.conf_dev 333 334 #define confdev_to_idxd_dev(dev) container_of(dev, struct idxd_dev, conf_dev) 335 #define idxd_dev_to_idxd(idxd_dev) container_of(idxd_dev, struct idxd_device, idxd_dev) 336 #define idxd_dev_to_wq(idxd_dev) container_of(idxd_dev, struct idxd_wq, idxd_dev) 337 338 static inline struct idxd_device *confdev_to_idxd(struct device *dev) 339 { 340 struct idxd_dev *idxd_dev = confdev_to_idxd_dev(dev); 341 342 return idxd_dev_to_idxd(idxd_dev); 343 } 344 345 static inline struct idxd_wq *confdev_to_wq(struct device *dev) 346 { 347 struct idxd_dev *idxd_dev = confdev_to_idxd_dev(dev); 348 349 return idxd_dev_to_wq(idxd_dev); 350 } 351 352 static inline struct idxd_engine *confdev_to_engine(struct device *dev) 353 { 354 struct idxd_dev *idxd_dev = confdev_to_idxd_dev(dev); 355 356 return container_of(idxd_dev, struct idxd_engine, idxd_dev); 357 } 358 359 static inline struct idxd_group *confdev_to_group(struct device *dev) 360 { 361 struct idxd_dev *idxd_dev = confdev_to_idxd_dev(dev); 362 363 return container_of(idxd_dev, struct idxd_group, idxd_dev); 364 } 365 366 static inline struct idxd_cdev *dev_to_cdev(struct device *dev) 367 { 368 struct idxd_dev *idxd_dev = confdev_to_idxd_dev(dev); 369 370 return container_of(idxd_dev, struct idxd_cdev, idxd_dev); 371 } 372 373 static inline void idxd_dev_set_type(struct idxd_dev *idev, int type) 374 { 375 if (type >= IDXD_DEV_MAX_TYPE) { 376 idev->type = IDXD_DEV_NONE; 377 return; 378 } 379 380 idev->type = type; 381 } 382 383 extern struct bus_type dsa_bus_type; 384 385 extern bool support_enqcmd; 386 extern struct ida idxd_ida; 387 extern struct device_type dsa_device_type; 388 extern struct device_type iax_device_type; 389 extern struct device_type idxd_wq_device_type; 390 extern struct device_type idxd_engine_device_type; 391 extern struct device_type idxd_group_device_type; 392 393 static inline bool is_dsa_dev(struct idxd_dev *idxd_dev) 394 { 395 return idxd_dev->type == IDXD_DEV_DSA; 396 } 397 398 static inline bool is_iax_dev(struct idxd_dev *idxd_dev) 399 { 400 return idxd_dev->type == IDXD_DEV_IAX; 401 } 402 403 static inline bool is_idxd_dev(struct idxd_dev *idxd_dev) 404 { 405 return is_dsa_dev(idxd_dev) || is_iax_dev(idxd_dev); 406 } 407 408 static inline bool is_idxd_wq_dev(struct idxd_dev *idxd_dev) 409 { 410 return idxd_dev->type == IDXD_DEV_WQ; 411 } 412 413 static inline bool is_idxd_wq_dmaengine(struct idxd_wq *wq) 414 { 415 if (wq->type == IDXD_WQT_KERNEL && strcmp(wq->name, "dmaengine") == 0) 416 return true; 417 return false; 418 } 419 420 static inline bool is_idxd_wq_user(struct idxd_wq *wq) 421 { 422 return wq->type == IDXD_WQT_USER; 423 } 424 425 static inline bool is_idxd_wq_kernel(struct idxd_wq *wq) 426 { 427 return wq->type == IDXD_WQT_KERNEL; 428 } 429 430 static inline bool wq_dedicated(struct idxd_wq *wq) 431 { 432 return test_bit(WQ_FLAG_DEDICATED, &wq->flags); 433 } 434 435 static inline bool wq_shared(struct idxd_wq *wq) 436 { 437 return !test_bit(WQ_FLAG_DEDICATED, &wq->flags); 438 } 439 440 static inline bool device_pasid_enabled(struct idxd_device *idxd) 441 { 442 return test_bit(IDXD_FLAG_PASID_ENABLED, &idxd->flags); 443 } 444 445 static inline bool device_swq_supported(struct idxd_device *idxd) 446 { 447 return (support_enqcmd && device_pasid_enabled(idxd)); 448 } 449 450 enum idxd_portal_prot { 451 IDXD_PORTAL_UNLIMITED = 0, 452 IDXD_PORTAL_LIMITED, 453 }; 454 455 enum idxd_interrupt_type { 456 IDXD_IRQ_MSIX = 0, 457 IDXD_IRQ_IMS, 458 }; 459 460 static inline int idxd_get_wq_portal_offset(enum idxd_portal_prot prot) 461 { 462 return prot * 0x1000; 463 } 464 465 static inline int idxd_get_wq_portal_full_offset(int wq_id, 466 enum idxd_portal_prot prot) 467 { 468 return ((wq_id * 4) << PAGE_SHIFT) + idxd_get_wq_portal_offset(prot); 469 } 470 471 #define IDXD_PORTAL_MASK (PAGE_SIZE - 1) 472 473 /* 474 * Even though this function can be accessed by multiple threads, it is safe to use. 475 * At worst the address gets used more than once before it gets incremented. We don't 476 * hit a threshold until iops becomes many million times a second. So the occasional 477 * reuse of the same address is tolerable compare to using an atomic variable. This is 478 * safe on a system that has atomic load/store for 32bit integers. Given that this is an 479 * Intel iEP device, that should not be a problem. 480 */ 481 static inline void __iomem *idxd_wq_portal_addr(struct idxd_wq *wq) 482 { 483 int ofs = wq->portal_offset; 484 485 wq->portal_offset = (ofs + sizeof(struct dsa_raw_desc)) & IDXD_PORTAL_MASK; 486 return wq->portal + ofs; 487 } 488 489 static inline void idxd_wq_get(struct idxd_wq *wq) 490 { 491 wq->client_count++; 492 } 493 494 static inline void idxd_wq_put(struct idxd_wq *wq) 495 { 496 wq->client_count--; 497 } 498 499 static inline int idxd_wq_refcount(struct idxd_wq *wq) 500 { 501 return wq->client_count; 502 }; 503 504 int __must_check __idxd_driver_register(struct idxd_device_driver *idxd_drv, 505 struct module *module, const char *mod_name); 506 #define idxd_driver_register(driver) \ 507 __idxd_driver_register(driver, THIS_MODULE, KBUILD_MODNAME) 508 509 void idxd_driver_unregister(struct idxd_device_driver *idxd_drv); 510 511 #define module_idxd_driver(__idxd_driver) \ 512 module_driver(__idxd_driver, idxd_driver_register, idxd_driver_unregister) 513 514 int idxd_register_bus_type(void); 515 void idxd_unregister_bus_type(void); 516 int idxd_register_devices(struct idxd_device *idxd); 517 void idxd_unregister_devices(struct idxd_device *idxd); 518 int idxd_register_driver(void); 519 void idxd_unregister_driver(void); 520 void idxd_wqs_quiesce(struct idxd_device *idxd); 521 522 /* device interrupt control */ 523 void idxd_msix_perm_setup(struct idxd_device *idxd); 524 void idxd_msix_perm_clear(struct idxd_device *idxd); 525 irqreturn_t idxd_misc_thread(int vec, void *data); 526 irqreturn_t idxd_wq_thread(int irq, void *data); 527 void idxd_mask_error_interrupts(struct idxd_device *idxd); 528 void idxd_unmask_error_interrupts(struct idxd_device *idxd); 529 void idxd_mask_msix_vectors(struct idxd_device *idxd); 530 void idxd_mask_msix_vector(struct idxd_device *idxd, int vec_id); 531 void idxd_unmask_msix_vector(struct idxd_device *idxd, int vec_id); 532 533 /* device control */ 534 int idxd_register_idxd_drv(void); 535 void idxd_unregister_idxd_drv(void); 536 int idxd_device_drv_probe(struct idxd_dev *idxd_dev); 537 void idxd_device_drv_remove(struct idxd_dev *idxd_dev); 538 int drv_enable_wq(struct idxd_wq *wq); 539 int __drv_enable_wq(struct idxd_wq *wq); 540 void drv_disable_wq(struct idxd_wq *wq); 541 void __drv_disable_wq(struct idxd_wq *wq); 542 int idxd_device_init_reset(struct idxd_device *idxd); 543 int idxd_device_enable(struct idxd_device *idxd); 544 int idxd_device_disable(struct idxd_device *idxd); 545 void idxd_device_reset(struct idxd_device *idxd); 546 void idxd_device_clear_state(struct idxd_device *idxd); 547 int idxd_device_config(struct idxd_device *idxd); 548 void idxd_device_drain_pasid(struct idxd_device *idxd, int pasid); 549 int idxd_device_load_config(struct idxd_device *idxd); 550 int idxd_device_request_int_handle(struct idxd_device *idxd, int idx, int *handle, 551 enum idxd_interrupt_type irq_type); 552 int idxd_device_release_int_handle(struct idxd_device *idxd, int handle, 553 enum idxd_interrupt_type irq_type); 554 555 /* work queue control */ 556 void idxd_wqs_unmap_portal(struct idxd_device *idxd); 557 int idxd_wq_alloc_resources(struct idxd_wq *wq); 558 void idxd_wq_free_resources(struct idxd_wq *wq); 559 int idxd_wq_enable(struct idxd_wq *wq); 560 int idxd_wq_disable(struct idxd_wq *wq, bool reset_config); 561 void idxd_wq_drain(struct idxd_wq *wq); 562 void idxd_wq_reset(struct idxd_wq *wq); 563 int idxd_wq_map_portal(struct idxd_wq *wq); 564 void idxd_wq_unmap_portal(struct idxd_wq *wq); 565 int idxd_wq_set_pasid(struct idxd_wq *wq, int pasid); 566 int idxd_wq_disable_pasid(struct idxd_wq *wq); 567 void idxd_wq_quiesce(struct idxd_wq *wq); 568 int idxd_wq_init_percpu_ref(struct idxd_wq *wq); 569 570 /* submission */ 571 int idxd_submit_desc(struct idxd_wq *wq, struct idxd_desc *desc); 572 struct idxd_desc *idxd_alloc_desc(struct idxd_wq *wq, enum idxd_op_type optype); 573 void idxd_free_desc(struct idxd_wq *wq, struct idxd_desc *desc); 574 575 /* dmaengine */ 576 int idxd_register_dma_device(struct idxd_device *idxd); 577 void idxd_unregister_dma_device(struct idxd_device *idxd); 578 int idxd_register_dma_channel(struct idxd_wq *wq); 579 void idxd_unregister_dma_channel(struct idxd_wq *wq); 580 void idxd_parse_completion_status(u8 status, enum dmaengine_tx_result *res); 581 void idxd_dma_complete_txd(struct idxd_desc *desc, 582 enum idxd_complete_type comp_type); 583 584 /* cdev */ 585 int idxd_cdev_register(void); 586 void idxd_cdev_remove(void); 587 int idxd_cdev_get_major(struct idxd_device *idxd); 588 int idxd_wq_add_cdev(struct idxd_wq *wq); 589 void idxd_wq_del_cdev(struct idxd_wq *wq); 590 591 /* perfmon */ 592 #if IS_ENABLED(CONFIG_INTEL_IDXD_PERFMON) 593 int perfmon_pmu_init(struct idxd_device *idxd); 594 void perfmon_pmu_remove(struct idxd_device *idxd); 595 void perfmon_counter_overflow(struct idxd_device *idxd); 596 void perfmon_init(void); 597 void perfmon_exit(void); 598 #else 599 static inline int perfmon_pmu_init(struct idxd_device *idxd) { return 0; } 600 static inline void perfmon_pmu_remove(struct idxd_device *idxd) {} 601 static inline void perfmon_counter_overflow(struct idxd_device *idxd) {} 602 static inline void perfmon_init(void) {} 603 static inline void perfmon_exit(void) {} 604 #endif 605 606 static inline void complete_desc(struct idxd_desc *desc, enum idxd_complete_type reason) 607 { 608 idxd_dma_complete_txd(desc, reason); 609 idxd_free_desc(desc->wq, desc); 610 } 611 612 #endif 613