1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */ 3 #include <linux/init.h> 4 #include <linux/kernel.h> 5 #include <linux/module.h> 6 #include <linux/pci.h> 7 #include <linux/io-64-nonatomic-lo-hi.h> 8 #include <linux/dmaengine.h> 9 #include <linux/irq.h> 10 #include <linux/msi.h> 11 #include <uapi/linux/idxd.h> 12 #include "../dmaengine.h" 13 #include "idxd.h" 14 #include "registers.h" 15 16 static void idxd_cmd_exec(struct idxd_device *idxd, int cmd_code, u32 operand, 17 u32 *status); 18 static void idxd_device_wqs_clear_state(struct idxd_device *idxd); 19 static void idxd_wq_disable_cleanup(struct idxd_wq *wq); 20 21 /* Interrupt control bits */ 22 void idxd_unmask_error_interrupts(struct idxd_device *idxd) 23 { 24 union genctrl_reg genctrl; 25 26 genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET); 27 genctrl.softerr_int_en = 1; 28 genctrl.halt_int_en = 1; 29 iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET); 30 } 31 32 void idxd_mask_error_interrupts(struct idxd_device *idxd) 33 { 34 union genctrl_reg genctrl; 35 36 genctrl.bits = ioread32(idxd->reg_base + IDXD_GENCTRL_OFFSET); 37 genctrl.softerr_int_en = 0; 38 genctrl.halt_int_en = 0; 39 iowrite32(genctrl.bits, idxd->reg_base + IDXD_GENCTRL_OFFSET); 40 } 41 42 static void free_hw_descs(struct idxd_wq *wq) 43 { 44 int i; 45 46 for (i = 0; i < wq->num_descs; i++) 47 kfree(wq->hw_descs[i]); 48 49 kfree(wq->hw_descs); 50 } 51 52 static int alloc_hw_descs(struct idxd_wq *wq, int num) 53 { 54 struct device *dev = &wq->idxd->pdev->dev; 55 int i; 56 int node = dev_to_node(dev); 57 58 wq->hw_descs = kcalloc_node(num, sizeof(struct dsa_hw_desc *), 59 GFP_KERNEL, node); 60 if (!wq->hw_descs) 61 return -ENOMEM; 62 63 for (i = 0; i < num; i++) { 64 wq->hw_descs[i] = kzalloc_node(sizeof(*wq->hw_descs[i]), 65 GFP_KERNEL, node); 66 if (!wq->hw_descs[i]) { 67 free_hw_descs(wq); 68 return -ENOMEM; 69 } 70 } 71 72 return 0; 73 } 74 75 static void free_descs(struct idxd_wq *wq) 76 { 77 int i; 78 79 for (i = 0; i < wq->num_descs; i++) 80 kfree(wq->descs[i]); 81 82 kfree(wq->descs); 83 } 84 85 static int alloc_descs(struct idxd_wq *wq, int num) 86 { 87 struct device *dev = &wq->idxd->pdev->dev; 88 int i; 89 int node = dev_to_node(dev); 90 91 wq->descs = kcalloc_node(num, sizeof(struct idxd_desc *), 92 GFP_KERNEL, node); 93 if (!wq->descs) 94 return -ENOMEM; 95 96 for (i = 0; i < num; i++) { 97 wq->descs[i] = kzalloc_node(sizeof(*wq->descs[i]), 98 GFP_KERNEL, node); 99 if (!wq->descs[i]) { 100 free_descs(wq); 101 return -ENOMEM; 102 } 103 } 104 105 return 0; 106 } 107 108 /* WQ control bits */ 109 int idxd_wq_alloc_resources(struct idxd_wq *wq) 110 { 111 struct idxd_device *idxd = wq->idxd; 112 struct device *dev = &idxd->pdev->dev; 113 int rc, num_descs, i; 114 115 if (wq->type != IDXD_WQT_KERNEL) 116 return 0; 117 118 num_descs = wq_dedicated(wq) ? wq->size : wq->threshold; 119 wq->num_descs = num_descs; 120 121 rc = alloc_hw_descs(wq, num_descs); 122 if (rc < 0) 123 return rc; 124 125 wq->compls_size = num_descs * idxd->data->compl_size; 126 wq->compls = dma_alloc_coherent(dev, wq->compls_size, &wq->compls_addr, GFP_KERNEL); 127 if (!wq->compls) { 128 rc = -ENOMEM; 129 goto fail_alloc_compls; 130 } 131 132 rc = alloc_descs(wq, num_descs); 133 if (rc < 0) 134 goto fail_alloc_descs; 135 136 rc = sbitmap_queue_init_node(&wq->sbq, num_descs, -1, false, GFP_KERNEL, 137 dev_to_node(dev)); 138 if (rc < 0) 139 goto fail_sbitmap_init; 140 141 for (i = 0; i < num_descs; i++) { 142 struct idxd_desc *desc = wq->descs[i]; 143 144 desc->hw = wq->hw_descs[i]; 145 if (idxd->data->type == IDXD_TYPE_DSA) 146 desc->completion = &wq->compls[i]; 147 else if (idxd->data->type == IDXD_TYPE_IAX) 148 desc->iax_completion = &wq->iax_compls[i]; 149 desc->compl_dma = wq->compls_addr + idxd->data->compl_size * i; 150 desc->id = i; 151 desc->wq = wq; 152 desc->cpu = -1; 153 } 154 155 return 0; 156 157 fail_sbitmap_init: 158 free_descs(wq); 159 fail_alloc_descs: 160 dma_free_coherent(dev, wq->compls_size, wq->compls, wq->compls_addr); 161 fail_alloc_compls: 162 free_hw_descs(wq); 163 return rc; 164 } 165 166 void idxd_wq_free_resources(struct idxd_wq *wq) 167 { 168 struct device *dev = &wq->idxd->pdev->dev; 169 170 if (wq->type != IDXD_WQT_KERNEL) 171 return; 172 173 free_hw_descs(wq); 174 free_descs(wq); 175 dma_free_coherent(dev, wq->compls_size, wq->compls, wq->compls_addr); 176 sbitmap_queue_free(&wq->sbq); 177 } 178 179 int idxd_wq_enable(struct idxd_wq *wq) 180 { 181 struct idxd_device *idxd = wq->idxd; 182 struct device *dev = &idxd->pdev->dev; 183 u32 status; 184 185 if (wq->state == IDXD_WQ_ENABLED) { 186 dev_dbg(dev, "WQ %d already enabled\n", wq->id); 187 return -ENXIO; 188 } 189 190 idxd_cmd_exec(idxd, IDXD_CMD_ENABLE_WQ, wq->id, &status); 191 192 if (status != IDXD_CMDSTS_SUCCESS && 193 status != IDXD_CMDSTS_ERR_WQ_ENABLED) { 194 dev_dbg(dev, "WQ enable failed: %#x\n", status); 195 return -ENXIO; 196 } 197 198 wq->state = IDXD_WQ_ENABLED; 199 dev_dbg(dev, "WQ %d enabled\n", wq->id); 200 return 0; 201 } 202 203 int idxd_wq_disable(struct idxd_wq *wq, bool reset_config) 204 { 205 struct idxd_device *idxd = wq->idxd; 206 struct device *dev = &idxd->pdev->dev; 207 u32 status, operand; 208 209 dev_dbg(dev, "Disabling WQ %d\n", wq->id); 210 211 if (wq->state != IDXD_WQ_ENABLED) { 212 dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state); 213 return 0; 214 } 215 216 operand = BIT(wq->id % 16) | ((wq->id / 16) << 16); 217 idxd_cmd_exec(idxd, IDXD_CMD_DISABLE_WQ, operand, &status); 218 219 if (status != IDXD_CMDSTS_SUCCESS) { 220 dev_dbg(dev, "WQ disable failed: %#x\n", status); 221 return -ENXIO; 222 } 223 224 if (reset_config) 225 idxd_wq_disable_cleanup(wq); 226 wq->state = IDXD_WQ_DISABLED; 227 dev_dbg(dev, "WQ %d disabled\n", wq->id); 228 return 0; 229 } 230 231 void idxd_wq_drain(struct idxd_wq *wq) 232 { 233 struct idxd_device *idxd = wq->idxd; 234 struct device *dev = &idxd->pdev->dev; 235 u32 operand; 236 237 if (wq->state != IDXD_WQ_ENABLED) { 238 dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state); 239 return; 240 } 241 242 dev_dbg(dev, "Draining WQ %d\n", wq->id); 243 operand = BIT(wq->id % 16) | ((wq->id / 16) << 16); 244 idxd_cmd_exec(idxd, IDXD_CMD_DRAIN_WQ, operand, NULL); 245 } 246 247 void idxd_wq_reset(struct idxd_wq *wq) 248 { 249 struct idxd_device *idxd = wq->idxd; 250 struct device *dev = &idxd->pdev->dev; 251 u32 operand; 252 253 if (wq->state != IDXD_WQ_ENABLED) { 254 dev_dbg(dev, "WQ %d in wrong state: %d\n", wq->id, wq->state); 255 return; 256 } 257 258 operand = BIT(wq->id % 16) | ((wq->id / 16) << 16); 259 idxd_cmd_exec(idxd, IDXD_CMD_RESET_WQ, operand, NULL); 260 idxd_wq_disable_cleanup(wq); 261 wq->state = IDXD_WQ_DISABLED; 262 } 263 264 int idxd_wq_map_portal(struct idxd_wq *wq) 265 { 266 struct idxd_device *idxd = wq->idxd; 267 struct pci_dev *pdev = idxd->pdev; 268 struct device *dev = &pdev->dev; 269 resource_size_t start; 270 271 start = pci_resource_start(pdev, IDXD_WQ_BAR); 272 start += idxd_get_wq_portal_full_offset(wq->id, IDXD_PORTAL_LIMITED); 273 274 wq->portal = devm_ioremap(dev, start, IDXD_PORTAL_SIZE); 275 if (!wq->portal) 276 return -ENOMEM; 277 278 return 0; 279 } 280 281 void idxd_wq_unmap_portal(struct idxd_wq *wq) 282 { 283 struct device *dev = &wq->idxd->pdev->dev; 284 285 devm_iounmap(dev, wq->portal); 286 wq->portal = NULL; 287 wq->portal_offset = 0; 288 } 289 290 void idxd_wqs_unmap_portal(struct idxd_device *idxd) 291 { 292 int i; 293 294 for (i = 0; i < idxd->max_wqs; i++) { 295 struct idxd_wq *wq = idxd->wqs[i]; 296 297 if (wq->portal) 298 idxd_wq_unmap_portal(wq); 299 } 300 } 301 302 static void __idxd_wq_set_priv_locked(struct idxd_wq *wq, int priv) 303 { 304 struct idxd_device *idxd = wq->idxd; 305 union wqcfg wqcfg; 306 unsigned int offset; 307 308 offset = WQCFG_OFFSET(idxd, wq->id, WQCFG_PRIVL_IDX); 309 spin_lock(&idxd->dev_lock); 310 wqcfg.bits[WQCFG_PRIVL_IDX] = ioread32(idxd->reg_base + offset); 311 wqcfg.priv = priv; 312 wq->wqcfg->bits[WQCFG_PRIVL_IDX] = wqcfg.bits[WQCFG_PRIVL_IDX]; 313 iowrite32(wqcfg.bits[WQCFG_PRIVL_IDX], idxd->reg_base + offset); 314 spin_unlock(&idxd->dev_lock); 315 } 316 317 static void __idxd_wq_set_pasid_locked(struct idxd_wq *wq, int pasid) 318 { 319 struct idxd_device *idxd = wq->idxd; 320 union wqcfg wqcfg; 321 unsigned int offset; 322 323 offset = WQCFG_OFFSET(idxd, wq->id, WQCFG_PASID_IDX); 324 spin_lock(&idxd->dev_lock); 325 wqcfg.bits[WQCFG_PASID_IDX] = ioread32(idxd->reg_base + offset); 326 wqcfg.pasid_en = 1; 327 wqcfg.pasid = pasid; 328 wq->wqcfg->bits[WQCFG_PASID_IDX] = wqcfg.bits[WQCFG_PASID_IDX]; 329 iowrite32(wqcfg.bits[WQCFG_PASID_IDX], idxd->reg_base + offset); 330 spin_unlock(&idxd->dev_lock); 331 } 332 333 int idxd_wq_set_pasid(struct idxd_wq *wq, int pasid) 334 { 335 int rc; 336 337 rc = idxd_wq_disable(wq, false); 338 if (rc < 0) 339 return rc; 340 341 __idxd_wq_set_pasid_locked(wq, pasid); 342 343 rc = idxd_wq_enable(wq); 344 if (rc < 0) 345 return rc; 346 347 return 0; 348 } 349 350 int idxd_wq_disable_pasid(struct idxd_wq *wq) 351 { 352 struct idxd_device *idxd = wq->idxd; 353 int rc; 354 union wqcfg wqcfg; 355 unsigned int offset; 356 357 rc = idxd_wq_disable(wq, false); 358 if (rc < 0) 359 return rc; 360 361 offset = WQCFG_OFFSET(idxd, wq->id, WQCFG_PASID_IDX); 362 spin_lock(&idxd->dev_lock); 363 wqcfg.bits[WQCFG_PASID_IDX] = ioread32(idxd->reg_base + offset); 364 wqcfg.pasid_en = 0; 365 wqcfg.pasid = 0; 366 iowrite32(wqcfg.bits[WQCFG_PASID_IDX], idxd->reg_base + offset); 367 spin_unlock(&idxd->dev_lock); 368 369 rc = idxd_wq_enable(wq); 370 if (rc < 0) 371 return rc; 372 373 return 0; 374 } 375 376 static void idxd_wq_disable_cleanup(struct idxd_wq *wq) 377 { 378 struct idxd_device *idxd = wq->idxd; 379 380 lockdep_assert_held(&wq->wq_lock); 381 memset(wq->wqcfg, 0, idxd->wqcfg_size); 382 wq->type = IDXD_WQT_NONE; 383 wq->threshold = 0; 384 wq->priority = 0; 385 wq->ats_dis = 0; 386 wq->enqcmds_retries = IDXD_ENQCMDS_RETRIES; 387 clear_bit(WQ_FLAG_DEDICATED, &wq->flags); 388 clear_bit(WQ_FLAG_BLOCK_ON_FAULT, &wq->flags); 389 memset(wq->name, 0, WQ_NAME_SIZE); 390 wq->max_xfer_bytes = WQ_DEFAULT_MAX_XFER; 391 wq->max_batch_size = WQ_DEFAULT_MAX_BATCH; 392 } 393 394 static void idxd_wq_device_reset_cleanup(struct idxd_wq *wq) 395 { 396 lockdep_assert_held(&wq->wq_lock); 397 398 idxd_wq_disable_cleanup(wq); 399 wq->size = 0; 400 wq->group = NULL; 401 } 402 403 static void idxd_wq_ref_release(struct percpu_ref *ref) 404 { 405 struct idxd_wq *wq = container_of(ref, struct idxd_wq, wq_active); 406 407 complete(&wq->wq_dead); 408 } 409 410 int idxd_wq_init_percpu_ref(struct idxd_wq *wq) 411 { 412 int rc; 413 414 memset(&wq->wq_active, 0, sizeof(wq->wq_active)); 415 rc = percpu_ref_init(&wq->wq_active, idxd_wq_ref_release, 416 PERCPU_REF_ALLOW_REINIT, GFP_KERNEL); 417 if (rc < 0) 418 return rc; 419 reinit_completion(&wq->wq_dead); 420 reinit_completion(&wq->wq_resurrect); 421 return 0; 422 } 423 424 void __idxd_wq_quiesce(struct idxd_wq *wq) 425 { 426 lockdep_assert_held(&wq->wq_lock); 427 reinit_completion(&wq->wq_resurrect); 428 percpu_ref_kill(&wq->wq_active); 429 complete_all(&wq->wq_resurrect); 430 wait_for_completion(&wq->wq_dead); 431 } 432 433 void idxd_wq_quiesce(struct idxd_wq *wq) 434 { 435 mutex_lock(&wq->wq_lock); 436 __idxd_wq_quiesce(wq); 437 mutex_unlock(&wq->wq_lock); 438 } 439 440 /* Device control bits */ 441 static inline bool idxd_is_enabled(struct idxd_device *idxd) 442 { 443 union gensts_reg gensts; 444 445 gensts.bits = ioread32(idxd->reg_base + IDXD_GENSTATS_OFFSET); 446 447 if (gensts.state == IDXD_DEVICE_STATE_ENABLED) 448 return true; 449 return false; 450 } 451 452 static inline bool idxd_device_is_halted(struct idxd_device *idxd) 453 { 454 union gensts_reg gensts; 455 456 gensts.bits = ioread32(idxd->reg_base + IDXD_GENSTATS_OFFSET); 457 458 return (gensts.state == IDXD_DEVICE_STATE_HALT); 459 } 460 461 /* 462 * This is function is only used for reset during probe and will 463 * poll for completion. Once the device is setup with interrupts, 464 * all commands will be done via interrupt completion. 465 */ 466 int idxd_device_init_reset(struct idxd_device *idxd) 467 { 468 struct device *dev = &idxd->pdev->dev; 469 union idxd_command_reg cmd; 470 471 if (idxd_device_is_halted(idxd)) { 472 dev_warn(&idxd->pdev->dev, "Device is HALTED!\n"); 473 return -ENXIO; 474 } 475 476 memset(&cmd, 0, sizeof(cmd)); 477 cmd.cmd = IDXD_CMD_RESET_DEVICE; 478 dev_dbg(dev, "%s: sending reset for init.\n", __func__); 479 spin_lock(&idxd->cmd_lock); 480 iowrite32(cmd.bits, idxd->reg_base + IDXD_CMD_OFFSET); 481 482 while (ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET) & 483 IDXD_CMDSTS_ACTIVE) 484 cpu_relax(); 485 spin_unlock(&idxd->cmd_lock); 486 return 0; 487 } 488 489 static void idxd_cmd_exec(struct idxd_device *idxd, int cmd_code, u32 operand, 490 u32 *status) 491 { 492 union idxd_command_reg cmd; 493 DECLARE_COMPLETION_ONSTACK(done); 494 u32 stat; 495 496 if (idxd_device_is_halted(idxd)) { 497 dev_warn(&idxd->pdev->dev, "Device is HALTED!\n"); 498 if (status) 499 *status = IDXD_CMDSTS_HW_ERR; 500 return; 501 } 502 503 memset(&cmd, 0, sizeof(cmd)); 504 cmd.cmd = cmd_code; 505 cmd.operand = operand; 506 cmd.int_req = 1; 507 508 spin_lock(&idxd->cmd_lock); 509 wait_event_lock_irq(idxd->cmd_waitq, 510 !test_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags), 511 idxd->cmd_lock); 512 513 dev_dbg(&idxd->pdev->dev, "%s: sending cmd: %#x op: %#x\n", 514 __func__, cmd_code, operand); 515 516 idxd->cmd_status = 0; 517 __set_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags); 518 idxd->cmd_done = &done; 519 iowrite32(cmd.bits, idxd->reg_base + IDXD_CMD_OFFSET); 520 521 /* 522 * After command submitted, release lock and go to sleep until 523 * the command completes via interrupt. 524 */ 525 spin_unlock(&idxd->cmd_lock); 526 wait_for_completion(&done); 527 stat = ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET); 528 spin_lock(&idxd->cmd_lock); 529 if (status) 530 *status = stat; 531 idxd->cmd_status = stat & GENMASK(7, 0); 532 533 __clear_bit(IDXD_FLAG_CMD_RUNNING, &idxd->flags); 534 /* Wake up other pending commands */ 535 wake_up(&idxd->cmd_waitq); 536 spin_unlock(&idxd->cmd_lock); 537 } 538 539 int idxd_device_enable(struct idxd_device *idxd) 540 { 541 struct device *dev = &idxd->pdev->dev; 542 u32 status; 543 544 if (idxd_is_enabled(idxd)) { 545 dev_dbg(dev, "Device already enabled\n"); 546 return -ENXIO; 547 } 548 549 idxd_cmd_exec(idxd, IDXD_CMD_ENABLE_DEVICE, 0, &status); 550 551 /* If the command is successful or if the device was enabled */ 552 if (status != IDXD_CMDSTS_SUCCESS && 553 status != IDXD_CMDSTS_ERR_DEV_ENABLED) { 554 dev_dbg(dev, "%s: err_code: %#x\n", __func__, status); 555 return -ENXIO; 556 } 557 558 idxd->state = IDXD_DEV_ENABLED; 559 return 0; 560 } 561 562 int idxd_device_disable(struct idxd_device *idxd) 563 { 564 struct device *dev = &idxd->pdev->dev; 565 u32 status; 566 567 if (!idxd_is_enabled(idxd)) { 568 dev_dbg(dev, "Device is not enabled\n"); 569 return 0; 570 } 571 572 idxd_cmd_exec(idxd, IDXD_CMD_DISABLE_DEVICE, 0, &status); 573 574 /* If the command is successful or if the device was disabled */ 575 if (status != IDXD_CMDSTS_SUCCESS && 576 !(status & IDXD_CMDSTS_ERR_DIS_DEV_EN)) { 577 dev_dbg(dev, "%s: err_code: %#x\n", __func__, status); 578 return -ENXIO; 579 } 580 581 spin_lock(&idxd->dev_lock); 582 idxd_device_clear_state(idxd); 583 idxd->state = IDXD_DEV_DISABLED; 584 spin_unlock(&idxd->dev_lock); 585 return 0; 586 } 587 588 void idxd_device_reset(struct idxd_device *idxd) 589 { 590 idxd_cmd_exec(idxd, IDXD_CMD_RESET_DEVICE, 0, NULL); 591 spin_lock(&idxd->dev_lock); 592 idxd_device_clear_state(idxd); 593 idxd->state = IDXD_DEV_DISABLED; 594 idxd_unmask_error_interrupts(idxd); 595 spin_unlock(&idxd->dev_lock); 596 } 597 598 void idxd_device_drain_pasid(struct idxd_device *idxd, int pasid) 599 { 600 struct device *dev = &idxd->pdev->dev; 601 u32 operand; 602 603 operand = pasid; 604 dev_dbg(dev, "cmd: %u operand: %#x\n", IDXD_CMD_DRAIN_PASID, operand); 605 idxd_cmd_exec(idxd, IDXD_CMD_DRAIN_PASID, operand, NULL); 606 dev_dbg(dev, "pasid %d drained\n", pasid); 607 } 608 609 int idxd_device_request_int_handle(struct idxd_device *idxd, int idx, int *handle, 610 enum idxd_interrupt_type irq_type) 611 { 612 struct device *dev = &idxd->pdev->dev; 613 u32 operand, status; 614 615 if (!(idxd->hw.cmd_cap & BIT(IDXD_CMD_REQUEST_INT_HANDLE))) 616 return -EOPNOTSUPP; 617 618 dev_dbg(dev, "get int handle, idx %d\n", idx); 619 620 operand = idx & GENMASK(15, 0); 621 if (irq_type == IDXD_IRQ_IMS) 622 operand |= CMD_INT_HANDLE_IMS; 623 624 dev_dbg(dev, "cmd: %u operand: %#x\n", IDXD_CMD_REQUEST_INT_HANDLE, operand); 625 626 idxd_cmd_exec(idxd, IDXD_CMD_REQUEST_INT_HANDLE, operand, &status); 627 628 if ((status & IDXD_CMDSTS_ERR_MASK) != IDXD_CMDSTS_SUCCESS) { 629 dev_dbg(dev, "request int handle failed: %#x\n", status); 630 return -ENXIO; 631 } 632 633 *handle = (status >> IDXD_CMDSTS_RES_SHIFT) & GENMASK(15, 0); 634 635 dev_dbg(dev, "int handle acquired: %u\n", *handle); 636 return 0; 637 } 638 639 int idxd_device_release_int_handle(struct idxd_device *idxd, int handle, 640 enum idxd_interrupt_type irq_type) 641 { 642 struct device *dev = &idxd->pdev->dev; 643 u32 operand, status; 644 union idxd_command_reg cmd; 645 646 if (!(idxd->hw.cmd_cap & BIT(IDXD_CMD_RELEASE_INT_HANDLE))) 647 return -EOPNOTSUPP; 648 649 dev_dbg(dev, "release int handle, handle %d\n", handle); 650 651 memset(&cmd, 0, sizeof(cmd)); 652 operand = handle & GENMASK(15, 0); 653 654 if (irq_type == IDXD_IRQ_IMS) 655 operand |= CMD_INT_HANDLE_IMS; 656 657 cmd.cmd = IDXD_CMD_RELEASE_INT_HANDLE; 658 cmd.operand = operand; 659 660 dev_dbg(dev, "cmd: %u operand: %#x\n", IDXD_CMD_RELEASE_INT_HANDLE, operand); 661 662 spin_lock(&idxd->cmd_lock); 663 iowrite32(cmd.bits, idxd->reg_base + IDXD_CMD_OFFSET); 664 665 while (ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET) & IDXD_CMDSTS_ACTIVE) 666 cpu_relax(); 667 status = ioread32(idxd->reg_base + IDXD_CMDSTS_OFFSET); 668 spin_unlock(&idxd->cmd_lock); 669 670 if ((status & IDXD_CMDSTS_ERR_MASK) != IDXD_CMDSTS_SUCCESS) { 671 dev_dbg(dev, "release int handle failed: %#x\n", status); 672 return -ENXIO; 673 } 674 675 dev_dbg(dev, "int handle released.\n"); 676 return 0; 677 } 678 679 /* Device configuration bits */ 680 static void idxd_engines_clear_state(struct idxd_device *idxd) 681 { 682 struct idxd_engine *engine; 683 int i; 684 685 lockdep_assert_held(&idxd->dev_lock); 686 for (i = 0; i < idxd->max_engines; i++) { 687 engine = idxd->engines[i]; 688 engine->group = NULL; 689 } 690 } 691 692 static void idxd_groups_clear_state(struct idxd_device *idxd) 693 { 694 struct idxd_group *group; 695 int i; 696 697 lockdep_assert_held(&idxd->dev_lock); 698 for (i = 0; i < idxd->max_groups; i++) { 699 group = idxd->groups[i]; 700 memset(&group->grpcfg, 0, sizeof(group->grpcfg)); 701 group->num_engines = 0; 702 group->num_wqs = 0; 703 group->use_rdbuf_limit = false; 704 group->rdbufs_allowed = 0; 705 group->rdbufs_reserved = 0; 706 if (idxd->hw.version < DEVICE_VERSION_2 && !tc_override) { 707 group->tc_a = 1; 708 group->tc_b = 1; 709 } else { 710 group->tc_a = -1; 711 group->tc_b = -1; 712 } 713 } 714 } 715 716 static void idxd_device_wqs_clear_state(struct idxd_device *idxd) 717 { 718 int i; 719 720 lockdep_assert_held(&idxd->dev_lock); 721 for (i = 0; i < idxd->max_wqs; i++) { 722 struct idxd_wq *wq = idxd->wqs[i]; 723 724 if (wq->state == IDXD_WQ_ENABLED) { 725 idxd_wq_disable_cleanup(wq); 726 idxd_wq_device_reset_cleanup(wq); 727 wq->state = IDXD_WQ_DISABLED; 728 } 729 } 730 } 731 732 void idxd_device_clear_state(struct idxd_device *idxd) 733 { 734 idxd_groups_clear_state(idxd); 735 idxd_engines_clear_state(idxd); 736 idxd_device_wqs_clear_state(idxd); 737 } 738 739 static void idxd_group_config_write(struct idxd_group *group) 740 { 741 struct idxd_device *idxd = group->idxd; 742 struct device *dev = &idxd->pdev->dev; 743 int i; 744 u32 grpcfg_offset; 745 746 dev_dbg(dev, "Writing group %d cfg registers\n", group->id); 747 748 /* setup GRPWQCFG */ 749 for (i = 0; i < GRPWQCFG_STRIDES; i++) { 750 grpcfg_offset = GRPWQCFG_OFFSET(idxd, group->id, i); 751 iowrite64(group->grpcfg.wqs[i], idxd->reg_base + grpcfg_offset); 752 dev_dbg(dev, "GRPCFG wq[%d:%d: %#x]: %#llx\n", 753 group->id, i, grpcfg_offset, 754 ioread64(idxd->reg_base + grpcfg_offset)); 755 } 756 757 /* setup GRPENGCFG */ 758 grpcfg_offset = GRPENGCFG_OFFSET(idxd, group->id); 759 iowrite64(group->grpcfg.engines, idxd->reg_base + grpcfg_offset); 760 dev_dbg(dev, "GRPCFG engs[%d: %#x]: %#llx\n", group->id, 761 grpcfg_offset, ioread64(idxd->reg_base + grpcfg_offset)); 762 763 /* setup GRPFLAGS */ 764 grpcfg_offset = GRPFLGCFG_OFFSET(idxd, group->id); 765 iowrite32(group->grpcfg.flags.bits, idxd->reg_base + grpcfg_offset); 766 dev_dbg(dev, "GRPFLAGS flags[%d: %#x]: %#x\n", 767 group->id, grpcfg_offset, 768 ioread32(idxd->reg_base + grpcfg_offset)); 769 } 770 771 static int idxd_groups_config_write(struct idxd_device *idxd) 772 773 { 774 union gencfg_reg reg; 775 int i; 776 struct device *dev = &idxd->pdev->dev; 777 778 /* Setup bandwidth rdbuf limit */ 779 if (idxd->hw.gen_cap.config_en && idxd->rdbuf_limit) { 780 reg.bits = ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET); 781 reg.rdbuf_limit = idxd->rdbuf_limit; 782 iowrite32(reg.bits, idxd->reg_base + IDXD_GENCFG_OFFSET); 783 } 784 785 dev_dbg(dev, "GENCFG(%#x): %#x\n", IDXD_GENCFG_OFFSET, 786 ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET)); 787 788 for (i = 0; i < idxd->max_groups; i++) { 789 struct idxd_group *group = idxd->groups[i]; 790 791 idxd_group_config_write(group); 792 } 793 794 return 0; 795 } 796 797 static bool idxd_device_pasid_priv_enabled(struct idxd_device *idxd) 798 { 799 struct pci_dev *pdev = idxd->pdev; 800 801 if (pdev->pasid_enabled && (pdev->pasid_features & PCI_PASID_CAP_PRIV)) 802 return true; 803 return false; 804 } 805 806 static int idxd_wq_config_write(struct idxd_wq *wq) 807 { 808 struct idxd_device *idxd = wq->idxd; 809 struct device *dev = &idxd->pdev->dev; 810 u32 wq_offset; 811 int i; 812 813 if (!wq->group) 814 return 0; 815 816 /* 817 * Instead of memset the entire shadow copy of WQCFG, copy from the hardware after 818 * wq reset. This will copy back the sticky values that are present on some devices. 819 */ 820 for (i = 0; i < WQCFG_STRIDES(idxd); i++) { 821 wq_offset = WQCFG_OFFSET(idxd, wq->id, i); 822 wq->wqcfg->bits[i] |= ioread32(idxd->reg_base + wq_offset); 823 } 824 825 if (wq->size == 0 && wq->type != IDXD_WQT_NONE) 826 wq->size = WQ_DEFAULT_QUEUE_DEPTH; 827 828 /* byte 0-3 */ 829 wq->wqcfg->wq_size = wq->size; 830 831 /* bytes 4-7 */ 832 wq->wqcfg->wq_thresh = wq->threshold; 833 834 /* byte 8-11 */ 835 if (wq_dedicated(wq)) 836 wq->wqcfg->mode = 1; 837 838 /* 839 * The WQ priv bit is set depending on the WQ type. priv = 1 if the 840 * WQ type is kernel to indicate privileged access. This setting only 841 * matters for dedicated WQ. According to the DSA spec: 842 * If the WQ is in dedicated mode, WQ PASID Enable is 1, and the 843 * Privileged Mode Enable field of the PCI Express PASID capability 844 * is 0, this field must be 0. 845 * 846 * In the case of a dedicated kernel WQ that is not able to support 847 * the PASID cap, then the configuration will be rejected. 848 */ 849 if (wq_dedicated(wq) && wq->wqcfg->pasid_en && 850 !idxd_device_pasid_priv_enabled(idxd) && 851 wq->type == IDXD_WQT_KERNEL) { 852 idxd->cmd_status = IDXD_SCMD_WQ_NO_PRIV; 853 return -EOPNOTSUPP; 854 } 855 856 wq->wqcfg->priority = wq->priority; 857 858 if (idxd->hw.gen_cap.block_on_fault && 859 test_bit(WQ_FLAG_BLOCK_ON_FAULT, &wq->flags)) 860 wq->wqcfg->bof = 1; 861 862 if (idxd->hw.wq_cap.wq_ats_support) 863 wq->wqcfg->wq_ats_disable = wq->ats_dis; 864 865 /* bytes 12-15 */ 866 wq->wqcfg->max_xfer_shift = ilog2(wq->max_xfer_bytes); 867 wq->wqcfg->max_batch_shift = ilog2(wq->max_batch_size); 868 869 dev_dbg(dev, "WQ %d CFGs\n", wq->id); 870 for (i = 0; i < WQCFG_STRIDES(idxd); i++) { 871 wq_offset = WQCFG_OFFSET(idxd, wq->id, i); 872 iowrite32(wq->wqcfg->bits[i], idxd->reg_base + wq_offset); 873 dev_dbg(dev, "WQ[%d][%d][%#x]: %#x\n", 874 wq->id, i, wq_offset, 875 ioread32(idxd->reg_base + wq_offset)); 876 } 877 878 return 0; 879 } 880 881 static int idxd_wqs_config_write(struct idxd_device *idxd) 882 { 883 int i, rc; 884 885 for (i = 0; i < idxd->max_wqs; i++) { 886 struct idxd_wq *wq = idxd->wqs[i]; 887 888 rc = idxd_wq_config_write(wq); 889 if (rc < 0) 890 return rc; 891 } 892 893 return 0; 894 } 895 896 static void idxd_group_flags_setup(struct idxd_device *idxd) 897 { 898 int i; 899 900 /* TC-A 0 and TC-B 1 should be defaults */ 901 for (i = 0; i < idxd->max_groups; i++) { 902 struct idxd_group *group = idxd->groups[i]; 903 904 if (group->tc_a == -1) 905 group->tc_a = group->grpcfg.flags.tc_a = 0; 906 else 907 group->grpcfg.flags.tc_a = group->tc_a; 908 if (group->tc_b == -1) 909 group->tc_b = group->grpcfg.flags.tc_b = 1; 910 else 911 group->grpcfg.flags.tc_b = group->tc_b; 912 group->grpcfg.flags.use_rdbuf_limit = group->use_rdbuf_limit; 913 group->grpcfg.flags.rdbufs_reserved = group->rdbufs_reserved; 914 if (group->rdbufs_allowed) 915 group->grpcfg.flags.rdbufs_allowed = group->rdbufs_allowed; 916 else 917 group->grpcfg.flags.rdbufs_allowed = idxd->max_rdbufs; 918 } 919 } 920 921 static int idxd_engines_setup(struct idxd_device *idxd) 922 { 923 int i, engines = 0; 924 struct idxd_engine *eng; 925 struct idxd_group *group; 926 927 for (i = 0; i < idxd->max_groups; i++) { 928 group = idxd->groups[i]; 929 group->grpcfg.engines = 0; 930 } 931 932 for (i = 0; i < idxd->max_engines; i++) { 933 eng = idxd->engines[i]; 934 group = eng->group; 935 936 if (!group) 937 continue; 938 939 group->grpcfg.engines |= BIT(eng->id); 940 engines++; 941 } 942 943 if (!engines) 944 return -EINVAL; 945 946 return 0; 947 } 948 949 static int idxd_wqs_setup(struct idxd_device *idxd) 950 { 951 struct idxd_wq *wq; 952 struct idxd_group *group; 953 int i, j, configured = 0; 954 struct device *dev = &idxd->pdev->dev; 955 956 for (i = 0; i < idxd->max_groups; i++) { 957 group = idxd->groups[i]; 958 for (j = 0; j < 4; j++) 959 group->grpcfg.wqs[j] = 0; 960 } 961 962 for (i = 0; i < idxd->max_wqs; i++) { 963 wq = idxd->wqs[i]; 964 group = wq->group; 965 966 if (!wq->group) 967 continue; 968 969 if (wq_shared(wq) && !device_swq_supported(idxd)) { 970 idxd->cmd_status = IDXD_SCMD_WQ_NO_SWQ_SUPPORT; 971 dev_warn(dev, "No shared wq support but configured.\n"); 972 return -EINVAL; 973 } 974 975 group->grpcfg.wqs[wq->id / 64] |= BIT(wq->id % 64); 976 configured++; 977 } 978 979 if (configured == 0) { 980 idxd->cmd_status = IDXD_SCMD_WQ_NONE_CONFIGURED; 981 return -EINVAL; 982 } 983 984 return 0; 985 } 986 987 int idxd_device_config(struct idxd_device *idxd) 988 { 989 int rc; 990 991 lockdep_assert_held(&idxd->dev_lock); 992 rc = idxd_wqs_setup(idxd); 993 if (rc < 0) 994 return rc; 995 996 rc = idxd_engines_setup(idxd); 997 if (rc < 0) 998 return rc; 999 1000 idxd_group_flags_setup(idxd); 1001 1002 rc = idxd_wqs_config_write(idxd); 1003 if (rc < 0) 1004 return rc; 1005 1006 rc = idxd_groups_config_write(idxd); 1007 if (rc < 0) 1008 return rc; 1009 1010 return 0; 1011 } 1012 1013 static int idxd_wq_load_config(struct idxd_wq *wq) 1014 { 1015 struct idxd_device *idxd = wq->idxd; 1016 struct device *dev = &idxd->pdev->dev; 1017 int wqcfg_offset; 1018 int i; 1019 1020 wqcfg_offset = WQCFG_OFFSET(idxd, wq->id, 0); 1021 memcpy_fromio(wq->wqcfg, idxd->reg_base + wqcfg_offset, idxd->wqcfg_size); 1022 1023 wq->size = wq->wqcfg->wq_size; 1024 wq->threshold = wq->wqcfg->wq_thresh; 1025 1026 /* The driver does not support shared WQ mode in read-only config yet */ 1027 if (wq->wqcfg->mode == 0 || wq->wqcfg->pasid_en) 1028 return -EOPNOTSUPP; 1029 1030 set_bit(WQ_FLAG_DEDICATED, &wq->flags); 1031 1032 wq->priority = wq->wqcfg->priority; 1033 1034 wq->max_xfer_bytes = 1ULL << wq->wqcfg->max_xfer_shift; 1035 wq->max_batch_size = 1ULL << wq->wqcfg->max_batch_shift; 1036 1037 for (i = 0; i < WQCFG_STRIDES(idxd); i++) { 1038 wqcfg_offset = WQCFG_OFFSET(idxd, wq->id, i); 1039 dev_dbg(dev, "WQ[%d][%d][%#x]: %#x\n", wq->id, i, wqcfg_offset, wq->wqcfg->bits[i]); 1040 } 1041 1042 return 0; 1043 } 1044 1045 static void idxd_group_load_config(struct idxd_group *group) 1046 { 1047 struct idxd_device *idxd = group->idxd; 1048 struct device *dev = &idxd->pdev->dev; 1049 int i, j, grpcfg_offset; 1050 1051 /* 1052 * Load WQS bit fields 1053 * Iterate through all 256 bits 64 bits at a time 1054 */ 1055 for (i = 0; i < GRPWQCFG_STRIDES; i++) { 1056 struct idxd_wq *wq; 1057 1058 grpcfg_offset = GRPWQCFG_OFFSET(idxd, group->id, i); 1059 group->grpcfg.wqs[i] = ioread64(idxd->reg_base + grpcfg_offset); 1060 dev_dbg(dev, "GRPCFG wq[%d:%d: %#x]: %#llx\n", 1061 group->id, i, grpcfg_offset, group->grpcfg.wqs[i]); 1062 1063 if (i * 64 >= idxd->max_wqs) 1064 break; 1065 1066 /* Iterate through all 64 bits and check for wq set */ 1067 for (j = 0; j < 64; j++) { 1068 int id = i * 64 + j; 1069 1070 /* No need to check beyond max wqs */ 1071 if (id >= idxd->max_wqs) 1072 break; 1073 1074 /* Set group assignment for wq if wq bit is set */ 1075 if (group->grpcfg.wqs[i] & BIT(j)) { 1076 wq = idxd->wqs[id]; 1077 wq->group = group; 1078 } 1079 } 1080 } 1081 1082 grpcfg_offset = GRPENGCFG_OFFSET(idxd, group->id); 1083 group->grpcfg.engines = ioread64(idxd->reg_base + grpcfg_offset); 1084 dev_dbg(dev, "GRPCFG engs[%d: %#x]: %#llx\n", group->id, 1085 grpcfg_offset, group->grpcfg.engines); 1086 1087 /* Iterate through all 64 bits to check engines set */ 1088 for (i = 0; i < 64; i++) { 1089 if (i >= idxd->max_engines) 1090 break; 1091 1092 if (group->grpcfg.engines & BIT(i)) { 1093 struct idxd_engine *engine = idxd->engines[i]; 1094 1095 engine->group = group; 1096 } 1097 } 1098 1099 grpcfg_offset = GRPFLGCFG_OFFSET(idxd, group->id); 1100 group->grpcfg.flags.bits = ioread32(idxd->reg_base + grpcfg_offset); 1101 dev_dbg(dev, "GRPFLAGS flags[%d: %#x]: %#x\n", 1102 group->id, grpcfg_offset, group->grpcfg.flags.bits); 1103 } 1104 1105 int idxd_device_load_config(struct idxd_device *idxd) 1106 { 1107 union gencfg_reg reg; 1108 int i, rc; 1109 1110 reg.bits = ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET); 1111 idxd->rdbuf_limit = reg.rdbuf_limit; 1112 1113 for (i = 0; i < idxd->max_groups; i++) { 1114 struct idxd_group *group = idxd->groups[i]; 1115 1116 idxd_group_load_config(group); 1117 } 1118 1119 for (i = 0; i < idxd->max_wqs; i++) { 1120 struct idxd_wq *wq = idxd->wqs[i]; 1121 1122 rc = idxd_wq_load_config(wq); 1123 if (rc < 0) 1124 return rc; 1125 } 1126 1127 return 0; 1128 } 1129 1130 static void idxd_flush_pending_descs(struct idxd_irq_entry *ie) 1131 { 1132 struct idxd_desc *desc, *itr; 1133 struct llist_node *head; 1134 LIST_HEAD(flist); 1135 enum idxd_complete_type ctype; 1136 1137 spin_lock(&ie->list_lock); 1138 head = llist_del_all(&ie->pending_llist); 1139 if (head) { 1140 llist_for_each_entry_safe(desc, itr, head, llnode) 1141 list_add_tail(&desc->list, &ie->work_list); 1142 } 1143 1144 list_for_each_entry_safe(desc, itr, &ie->work_list, list) 1145 list_move_tail(&desc->list, &flist); 1146 spin_unlock(&ie->list_lock); 1147 1148 list_for_each_entry_safe(desc, itr, &flist, list) { 1149 list_del(&desc->list); 1150 ctype = desc->completion->status ? IDXD_COMPLETE_NORMAL : IDXD_COMPLETE_ABORT; 1151 idxd_dma_complete_txd(desc, ctype, true); 1152 } 1153 } 1154 1155 static void idxd_device_set_perm_entry(struct idxd_device *idxd, 1156 struct idxd_irq_entry *ie) 1157 { 1158 union msix_perm mperm; 1159 1160 if (ie->pasid == INVALID_IOASID) 1161 return; 1162 1163 mperm.bits = 0; 1164 mperm.pasid = ie->pasid; 1165 mperm.pasid_en = 1; 1166 iowrite32(mperm.bits, idxd->reg_base + idxd->msix_perm_offset + ie->id * 8); 1167 } 1168 1169 static void idxd_device_clear_perm_entry(struct idxd_device *idxd, 1170 struct idxd_irq_entry *ie) 1171 { 1172 iowrite32(0, idxd->reg_base + idxd->msix_perm_offset + ie->id * 8); 1173 } 1174 1175 void idxd_wq_free_irq(struct idxd_wq *wq) 1176 { 1177 struct idxd_device *idxd = wq->idxd; 1178 struct idxd_irq_entry *ie = &wq->ie; 1179 1180 synchronize_irq(ie->vector); 1181 free_irq(ie->vector, ie); 1182 idxd_flush_pending_descs(ie); 1183 if (idxd->request_int_handles) 1184 idxd_device_release_int_handle(idxd, ie->int_handle, IDXD_IRQ_MSIX); 1185 idxd_device_clear_perm_entry(idxd, ie); 1186 ie->vector = -1; 1187 ie->int_handle = INVALID_INT_HANDLE; 1188 ie->pasid = INVALID_IOASID; 1189 } 1190 1191 int idxd_wq_request_irq(struct idxd_wq *wq) 1192 { 1193 struct idxd_device *idxd = wq->idxd; 1194 struct pci_dev *pdev = idxd->pdev; 1195 struct device *dev = &pdev->dev; 1196 struct idxd_irq_entry *ie; 1197 int rc; 1198 1199 ie = &wq->ie; 1200 ie->vector = pci_irq_vector(pdev, ie->id); 1201 ie->pasid = device_pasid_enabled(idxd) ? idxd->pasid : INVALID_IOASID; 1202 idxd_device_set_perm_entry(idxd, ie); 1203 1204 rc = request_threaded_irq(ie->vector, NULL, idxd_wq_thread, 0, "idxd-portal", ie); 1205 if (rc < 0) { 1206 dev_err(dev, "Failed to request irq %d.\n", ie->vector); 1207 goto err_irq; 1208 } 1209 1210 if (idxd->request_int_handles) { 1211 rc = idxd_device_request_int_handle(idxd, ie->id, &ie->int_handle, 1212 IDXD_IRQ_MSIX); 1213 if (rc < 0) 1214 goto err_int_handle; 1215 } else { 1216 ie->int_handle = ie->id; 1217 } 1218 1219 return 0; 1220 1221 err_int_handle: 1222 ie->int_handle = INVALID_INT_HANDLE; 1223 free_irq(ie->vector, ie); 1224 err_irq: 1225 idxd_device_clear_perm_entry(idxd, ie); 1226 ie->pasid = INVALID_IOASID; 1227 return rc; 1228 } 1229 1230 int __drv_enable_wq(struct idxd_wq *wq) 1231 { 1232 struct idxd_device *idxd = wq->idxd; 1233 struct device *dev = &idxd->pdev->dev; 1234 int rc = -ENXIO; 1235 1236 lockdep_assert_held(&wq->wq_lock); 1237 1238 if (idxd->state != IDXD_DEV_ENABLED) { 1239 idxd->cmd_status = IDXD_SCMD_DEV_NOT_ENABLED; 1240 goto err; 1241 } 1242 1243 if (wq->state != IDXD_WQ_DISABLED) { 1244 dev_dbg(dev, "wq %d already enabled.\n", wq->id); 1245 idxd->cmd_status = IDXD_SCMD_WQ_ENABLED; 1246 rc = -EBUSY; 1247 goto err; 1248 } 1249 1250 if (!wq->group) { 1251 dev_dbg(dev, "wq %d not attached to group.\n", wq->id); 1252 idxd->cmd_status = IDXD_SCMD_WQ_NO_GRP; 1253 goto err; 1254 } 1255 1256 if (strlen(wq->name) == 0) { 1257 idxd->cmd_status = IDXD_SCMD_WQ_NO_NAME; 1258 dev_dbg(dev, "wq %d name not set.\n", wq->id); 1259 goto err; 1260 } 1261 1262 /* Shared WQ checks */ 1263 if (wq_shared(wq)) { 1264 if (!device_swq_supported(idxd)) { 1265 idxd->cmd_status = IDXD_SCMD_WQ_NO_SVM; 1266 dev_dbg(dev, "PASID not enabled and shared wq.\n"); 1267 goto err; 1268 } 1269 /* 1270 * Shared wq with the threshold set to 0 means the user 1271 * did not set the threshold or transitioned from a 1272 * dedicated wq but did not set threshold. A value 1273 * of 0 would effectively disable the shared wq. The 1274 * driver does not allow a value of 0 to be set for 1275 * threshold via sysfs. 1276 */ 1277 if (wq->threshold == 0) { 1278 idxd->cmd_status = IDXD_SCMD_WQ_NO_THRESH; 1279 dev_dbg(dev, "Shared wq and threshold 0.\n"); 1280 goto err; 1281 } 1282 } 1283 1284 /* 1285 * In the event that the WQ is configurable for pasid and priv bits. 1286 * For kernel wq, the driver should setup the pasid, pasid_en, and priv bit. 1287 * However, for non-kernel wq, the driver should only set the pasid_en bit for 1288 * shared wq. A dedicated wq that is not 'kernel' type will configure pasid and 1289 * pasid_en later on so there is no need to setup. 1290 */ 1291 if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) { 1292 int priv = 0; 1293 1294 if (device_pasid_enabled(idxd)) { 1295 if (is_idxd_wq_kernel(wq) || wq_shared(wq)) { 1296 u32 pasid = wq_dedicated(wq) ? idxd->pasid : 0; 1297 1298 __idxd_wq_set_pasid_locked(wq, pasid); 1299 } 1300 } 1301 1302 if (is_idxd_wq_kernel(wq)) 1303 priv = 1; 1304 __idxd_wq_set_priv_locked(wq, priv); 1305 } 1306 1307 rc = 0; 1308 spin_lock(&idxd->dev_lock); 1309 if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) 1310 rc = idxd_device_config(idxd); 1311 spin_unlock(&idxd->dev_lock); 1312 if (rc < 0) { 1313 dev_dbg(dev, "Writing wq %d config failed: %d\n", wq->id, rc); 1314 goto err; 1315 } 1316 1317 rc = idxd_wq_enable(wq); 1318 if (rc < 0) { 1319 dev_dbg(dev, "wq %d enabling failed: %d\n", wq->id, rc); 1320 goto err; 1321 } 1322 1323 rc = idxd_wq_map_portal(wq); 1324 if (rc < 0) { 1325 idxd->cmd_status = IDXD_SCMD_WQ_PORTAL_ERR; 1326 dev_dbg(dev, "wq %d portal mapping failed: %d\n", wq->id, rc); 1327 goto err_map_portal; 1328 } 1329 1330 wq->client_count = 0; 1331 return 0; 1332 1333 err_map_portal: 1334 rc = idxd_wq_disable(wq, false); 1335 if (rc < 0) 1336 dev_dbg(dev, "wq %s disable failed\n", dev_name(wq_confdev(wq))); 1337 err: 1338 return rc; 1339 } 1340 1341 int drv_enable_wq(struct idxd_wq *wq) 1342 { 1343 int rc; 1344 1345 mutex_lock(&wq->wq_lock); 1346 rc = __drv_enable_wq(wq); 1347 mutex_unlock(&wq->wq_lock); 1348 return rc; 1349 } 1350 1351 void __drv_disable_wq(struct idxd_wq *wq) 1352 { 1353 struct idxd_device *idxd = wq->idxd; 1354 struct device *dev = &idxd->pdev->dev; 1355 1356 lockdep_assert_held(&wq->wq_lock); 1357 1358 if (idxd_wq_refcount(wq)) 1359 dev_warn(dev, "Clients has claim on wq %d: %d\n", 1360 wq->id, idxd_wq_refcount(wq)); 1361 1362 idxd_wq_unmap_portal(wq); 1363 1364 idxd_wq_drain(wq); 1365 idxd_wq_reset(wq); 1366 1367 wq->client_count = 0; 1368 } 1369 1370 void drv_disable_wq(struct idxd_wq *wq) 1371 { 1372 mutex_lock(&wq->wq_lock); 1373 __drv_disable_wq(wq); 1374 mutex_unlock(&wq->wq_lock); 1375 } 1376 1377 int idxd_device_drv_probe(struct idxd_dev *idxd_dev) 1378 { 1379 struct idxd_device *idxd = idxd_dev_to_idxd(idxd_dev); 1380 int rc = 0; 1381 1382 /* 1383 * Device should be in disabled state for the idxd_drv to load. If it's in 1384 * enabled state, then the device was altered outside of driver's control. 1385 * If the state is in halted state, then we don't want to proceed. 1386 */ 1387 if (idxd->state != IDXD_DEV_DISABLED) { 1388 idxd->cmd_status = IDXD_SCMD_DEV_ENABLED; 1389 return -ENXIO; 1390 } 1391 1392 /* Device configuration */ 1393 spin_lock(&idxd->dev_lock); 1394 if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) 1395 rc = idxd_device_config(idxd); 1396 spin_unlock(&idxd->dev_lock); 1397 if (rc < 0) 1398 return -ENXIO; 1399 1400 /* Start device */ 1401 rc = idxd_device_enable(idxd); 1402 if (rc < 0) 1403 return rc; 1404 1405 /* Setup DMA device without channels */ 1406 rc = idxd_register_dma_device(idxd); 1407 if (rc < 0) { 1408 idxd_device_disable(idxd); 1409 idxd->cmd_status = IDXD_SCMD_DEV_DMA_ERR; 1410 return rc; 1411 } 1412 1413 idxd->cmd_status = 0; 1414 return 0; 1415 } 1416 1417 void idxd_device_drv_remove(struct idxd_dev *idxd_dev) 1418 { 1419 struct device *dev = &idxd_dev->conf_dev; 1420 struct idxd_device *idxd = idxd_dev_to_idxd(idxd_dev); 1421 int i; 1422 1423 for (i = 0; i < idxd->max_wqs; i++) { 1424 struct idxd_wq *wq = idxd->wqs[i]; 1425 struct device *wq_dev = wq_confdev(wq); 1426 1427 if (wq->state == IDXD_WQ_DISABLED) 1428 continue; 1429 dev_warn(dev, "Active wq %d on disable %s.\n", i, dev_name(wq_dev)); 1430 device_release_driver(wq_dev); 1431 } 1432 1433 idxd_unregister_dma_device(idxd); 1434 idxd_device_disable(idxd); 1435 if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) 1436 idxd_device_reset(idxd); 1437 } 1438 1439 static enum idxd_dev_type dev_types[] = { 1440 IDXD_DEV_DSA, 1441 IDXD_DEV_IAX, 1442 IDXD_DEV_NONE, 1443 }; 1444 1445 struct idxd_device_driver idxd_drv = { 1446 .type = dev_types, 1447 .probe = idxd_device_drv_probe, 1448 .remove = idxd_device_drv_remove, 1449 .name = "idxd", 1450 }; 1451 EXPORT_SYMBOL_GPL(idxd_drv); 1452