1 /* 2 * Driver for the Intel integrated DMA 64-bit 3 * 4 * Copyright (C) 2015 Intel Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11 #ifndef __DMA_IDMA64_H__ 12 #define __DMA_IDMA64_H__ 13 14 #include <linux/device.h> 15 #include <linux/io.h> 16 #include <linux/spinlock.h> 17 #include <linux/types.h> 18 19 #include <asm-generic/io-64-nonatomic-lo-hi.h> 20 21 #include "virt-dma.h" 22 23 /* Channel registers */ 24 25 #define IDMA64_CH_SAR 0x00 /* Source Address Register */ 26 #define IDMA64_CH_DAR 0x08 /* Destination Address Register */ 27 #define IDMA64_CH_LLP 0x10 /* Linked List Pointer */ 28 #define IDMA64_CH_CTL_LO 0x18 /* Control Register Low */ 29 #define IDMA64_CH_CTL_HI 0x1c /* Control Register High */ 30 #define IDMA64_CH_SSTAT 0x20 31 #define IDMA64_CH_DSTAT 0x28 32 #define IDMA64_CH_SSTATAR 0x30 33 #define IDMA64_CH_DSTATAR 0x38 34 #define IDMA64_CH_CFG_LO 0x40 /* Configuration Register Low */ 35 #define IDMA64_CH_CFG_HI 0x44 /* Configuration Register High */ 36 #define IDMA64_CH_SGR 0x48 37 #define IDMA64_CH_DSR 0x50 38 39 #define IDMA64_CH_LENGTH 0x58 40 41 /* Bitfields in CTL_LO */ 42 #define IDMA64C_CTLL_INT_EN (1 << 0) /* irqs enabled? */ 43 #define IDMA64C_CTLL_DST_WIDTH(x) ((x) << 1) /* bytes per element */ 44 #define IDMA64C_CTLL_SRC_WIDTH(x) ((x) << 4) 45 #define IDMA64C_CTLL_DST_INC (0 << 8) /* DAR update/not */ 46 #define IDMA64C_CTLL_DST_FIX (1 << 8) 47 #define IDMA64C_CTLL_SRC_INC (0 << 10) /* SAR update/not */ 48 #define IDMA64C_CTLL_SRC_FIX (1 << 10) 49 #define IDMA64C_CTLL_DST_MSIZE(x) ((x) << 11) /* burst, #elements */ 50 #define IDMA64C_CTLL_SRC_MSIZE(x) ((x) << 14) 51 #define IDMA64C_CTLL_FC_M2P (1 << 20) /* mem-to-periph */ 52 #define IDMA64C_CTLL_FC_P2M (2 << 20) /* periph-to-mem */ 53 #define IDMA64C_CTLL_LLP_D_EN (1 << 27) /* dest block chain */ 54 #define IDMA64C_CTLL_LLP_S_EN (1 << 28) /* src block chain */ 55 56 /* Bitfields in CTL_HI */ 57 #define IDMA64C_CTLH_BLOCK_TS(x) ((x) & ((1 << 17) - 1)) 58 #define IDMA64C_CTLH_DONE (1 << 17) 59 60 /* Bitfields in CFG_LO */ 61 #define IDMA64C_CFGL_DST_BURST_ALIGN (1 << 0) /* dst burst align */ 62 #define IDMA64C_CFGL_SRC_BURST_ALIGN (1 << 1) /* src burst align */ 63 #define IDMA64C_CFGL_CH_SUSP (1 << 8) 64 #define IDMA64C_CFGL_FIFO_EMPTY (1 << 9) 65 #define IDMA64C_CFGL_CH_DRAIN (1 << 10) /* drain FIFO */ 66 #define IDMA64C_CFGL_DST_OPT_BL (1 << 20) /* optimize dst burst length */ 67 #define IDMA64C_CFGL_SRC_OPT_BL (1 << 21) /* optimize src burst length */ 68 69 /* Bitfields in CFG_HI */ 70 #define IDMA64C_CFGH_SRC_PER(x) ((x) << 0) /* src peripheral */ 71 #define IDMA64C_CFGH_DST_PER(x) ((x) << 4) /* dst peripheral */ 72 #define IDMA64C_CFGH_RD_ISSUE_THD(x) ((x) << 8) 73 #define IDMA64C_CFGH_RW_ISSUE_THD(x) ((x) << 18) 74 75 /* Interrupt registers */ 76 77 #define IDMA64_INT_XFER 0x00 78 #define IDMA64_INT_BLOCK 0x08 79 #define IDMA64_INT_SRC_TRAN 0x10 80 #define IDMA64_INT_DST_TRAN 0x18 81 #define IDMA64_INT_ERROR 0x20 82 83 #define IDMA64_RAW(x) (0x2c0 + IDMA64_INT_##x) /* r */ 84 #define IDMA64_STATUS(x) (0x2e8 + IDMA64_INT_##x) /* r (raw & mask) */ 85 #define IDMA64_MASK(x) (0x310 + IDMA64_INT_##x) /* rw (set = irq enabled) */ 86 #define IDMA64_CLEAR(x) (0x338 + IDMA64_INT_##x) /* w (ack, affects "raw") */ 87 88 /* Common registers */ 89 90 #define IDMA64_STATUS_INT 0x360 /* r */ 91 #define IDMA64_CFG 0x398 92 #define IDMA64_CH_EN 0x3a0 93 94 /* Bitfields in CFG */ 95 #define IDMA64_CFG_DMA_EN (1 << 0) 96 97 /* Hardware descriptor for Linked LIst transfers */ 98 struct idma64_lli { 99 u64 sar; 100 u64 dar; 101 u64 llp; 102 u32 ctllo; 103 u32 ctlhi; 104 u32 sstat; 105 u32 dstat; 106 }; 107 108 struct idma64_hw_desc { 109 struct idma64_lli *lli; 110 dma_addr_t llp; 111 dma_addr_t phys; 112 unsigned int len; 113 }; 114 115 struct idma64_desc { 116 struct virt_dma_desc vdesc; 117 enum dma_transfer_direction direction; 118 struct idma64_hw_desc *hw; 119 unsigned int ndesc; 120 size_t length; 121 enum dma_status status; 122 }; 123 124 static inline struct idma64_desc *to_idma64_desc(struct virt_dma_desc *vdesc) 125 { 126 return container_of(vdesc, struct idma64_desc, vdesc); 127 } 128 129 struct idma64_chan { 130 struct virt_dma_chan vchan; 131 132 void __iomem *regs; 133 134 /* hardware configuration */ 135 enum dma_transfer_direction direction; 136 unsigned int mask; 137 struct dma_slave_config config; 138 139 void *pool; 140 struct idma64_desc *desc; 141 }; 142 143 static inline struct idma64_chan *to_idma64_chan(struct dma_chan *chan) 144 { 145 return container_of(chan, struct idma64_chan, vchan.chan); 146 } 147 148 #define channel_set_bit(idma64, reg, mask) \ 149 dma_writel(idma64, reg, ((mask) << 8) | (mask)) 150 #define channel_clear_bit(idma64, reg, mask) \ 151 dma_writel(idma64, reg, ((mask) << 8) | 0) 152 153 static inline u32 idma64c_readl(struct idma64_chan *idma64c, int offset) 154 { 155 return readl(idma64c->regs + offset); 156 } 157 158 static inline void idma64c_writel(struct idma64_chan *idma64c, int offset, 159 u32 value) 160 { 161 writel(value, idma64c->regs + offset); 162 } 163 164 #define channel_readl(idma64c, reg) \ 165 idma64c_readl(idma64c, IDMA64_CH_##reg) 166 #define channel_writel(idma64c, reg, value) \ 167 idma64c_writel(idma64c, IDMA64_CH_##reg, (value)) 168 169 static inline u64 idma64c_readq(struct idma64_chan *idma64c, int offset) 170 { 171 return lo_hi_readq(idma64c->regs + offset); 172 } 173 174 static inline void idma64c_writeq(struct idma64_chan *idma64c, int offset, 175 u64 value) 176 { 177 lo_hi_writeq(value, idma64c->regs + offset); 178 } 179 180 #define channel_readq(idma64c, reg) \ 181 idma64c_readq(idma64c, IDMA64_CH_##reg) 182 #define channel_writeq(idma64c, reg, value) \ 183 idma64c_writeq(idma64c, IDMA64_CH_##reg, (value)) 184 185 struct idma64 { 186 struct dma_device dma; 187 188 void __iomem *regs; 189 190 /* channels */ 191 unsigned short all_chan_mask; 192 struct idma64_chan *chan; 193 }; 194 195 static inline struct idma64 *to_idma64(struct dma_device *ddev) 196 { 197 return container_of(ddev, struct idma64, dma); 198 } 199 200 static inline u32 idma64_readl(struct idma64 *idma64, int offset) 201 { 202 return readl(idma64->regs + offset); 203 } 204 205 static inline void idma64_writel(struct idma64 *idma64, int offset, u32 value) 206 { 207 writel(value, idma64->regs + offset); 208 } 209 210 #define dma_readl(idma64, reg) \ 211 idma64_readl(idma64, IDMA64_##reg) 212 #define dma_writel(idma64, reg, value) \ 213 idma64_writel(idma64, IDMA64_##reg, (value)) 214 215 /** 216 * struct idma64_chip - representation of iDMA 64-bit controller hardware 217 * @dev: struct device of the DMA controller 218 * @irq: irq line 219 * @regs: memory mapped I/O space 220 * @idma64: struct idma64 that is filed by idma64_probe() 221 */ 222 struct idma64_chip { 223 struct device *dev; 224 int irq; 225 void __iomem *regs; 226 struct idma64 *idma64; 227 }; 228 229 #endif /* __DMA_IDMA64_H__ */ 230