xref: /openbmc/linux/drivers/dma/idma64.c (revision fa0dadde) 
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Core driver for the Intel integrated DMA 64-bit
4  *
5  * Copyright (C) 2015 Intel Corporation
6  * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
7  */
8 
9 #include <linux/bitops.h>
10 #include <linux/delay.h>
11 #include <linux/dmaengine.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/dmapool.h>
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/platform_device.h>
17 #include <linux/slab.h>
18 
19 #include <linux/dma/idma64.h>
20 
21 #include "idma64.h"
22 
23 /* For now we support only two channels */
24 #define IDMA64_NR_CHAN		2
25 
26 /* ---------------------------------------------------------------------- */
27 
28 static struct device *chan2dev(struct dma_chan *chan)
29 {
30 	return &chan->dev->device;
31 }
32 
33 /* ---------------------------------------------------------------------- */
34 
35 static void idma64_off(struct idma64 *idma64)
36 {
37 	unsigned short count = 100;
38 
39 	dma_writel(idma64, CFG, 0);
40 
41 	channel_clear_bit(idma64, MASK(XFER), idma64->all_chan_mask);
42 	channel_clear_bit(idma64, MASK(BLOCK), idma64->all_chan_mask);
43 	channel_clear_bit(idma64, MASK(SRC_TRAN), idma64->all_chan_mask);
44 	channel_clear_bit(idma64, MASK(DST_TRAN), idma64->all_chan_mask);
45 	channel_clear_bit(idma64, MASK(ERROR), idma64->all_chan_mask);
46 
47 	do {
48 		cpu_relax();
49 	} while (dma_readl(idma64, CFG) & IDMA64_CFG_DMA_EN && --count);
50 }
51 
52 static void idma64_on(struct idma64 *idma64)
53 {
54 	dma_writel(idma64, CFG, IDMA64_CFG_DMA_EN);
55 }
56 
57 /* ---------------------------------------------------------------------- */
58 
59 static void idma64_chan_init(struct idma64 *idma64, struct idma64_chan *idma64c)
60 {
61 	u32 cfghi = IDMA64C_CFGH_SRC_PER(1) | IDMA64C_CFGH_DST_PER(0);
62 	u32 cfglo = 0;
63 
64 	/* Set default burst alignment */
65 	cfglo |= IDMA64C_CFGL_DST_BURST_ALIGN | IDMA64C_CFGL_SRC_BURST_ALIGN;
66 
67 	channel_writel(idma64c, CFG_LO, cfglo);
68 	channel_writel(idma64c, CFG_HI, cfghi);
69 
70 	/* Enable interrupts */
71 	channel_set_bit(idma64, MASK(XFER), idma64c->mask);
72 	channel_set_bit(idma64, MASK(ERROR), idma64c->mask);
73 
74 	/*
75 	 * Enforce the controller to be turned on.
76 	 *
77 	 * The iDMA is turned off in ->probe() and looses context during system
78 	 * suspend / resume cycle. That's why we have to enable it each time we
79 	 * use it.
80 	 */
81 	idma64_on(idma64);
82 }
83 
84 static void idma64_chan_stop(struct idma64 *idma64, struct idma64_chan *idma64c)
85 {
86 	channel_clear_bit(idma64, CH_EN, idma64c->mask);
87 }
88 
89 static void idma64_chan_start(struct idma64 *idma64, struct idma64_chan *idma64c)
90 {
91 	struct idma64_desc *desc = idma64c->desc;
92 	struct idma64_hw_desc *hw = &desc->hw[0];
93 
94 	channel_writeq(idma64c, SAR, 0);
95 	channel_writeq(idma64c, DAR, 0);
96 
97 	channel_writel(idma64c, CTL_HI, IDMA64C_CTLH_BLOCK_TS(~0UL));
98 	channel_writel(idma64c, CTL_LO, IDMA64C_CTLL_LLP_S_EN | IDMA64C_CTLL_LLP_D_EN);
99 
100 	channel_writeq(idma64c, LLP, hw->llp);
101 
102 	channel_set_bit(idma64, CH_EN, idma64c->mask);
103 }
104 
105 static void idma64_stop_transfer(struct idma64_chan *idma64c)
106 {
107 	struct idma64 *idma64 = to_idma64(idma64c->vchan.chan.device);
108 
109 	idma64_chan_stop(idma64, idma64c);
110 }
111 
112 static void idma64_start_transfer(struct idma64_chan *idma64c)
113 {
114 	struct idma64 *idma64 = to_idma64(idma64c->vchan.chan.device);
115 	struct virt_dma_desc *vdesc;
116 
117 	/* Get the next descriptor */
118 	vdesc = vchan_next_desc(&idma64c->vchan);
119 	if (!vdesc) {
120 		idma64c->desc = NULL;
121 		return;
122 	}
123 
124 	list_del(&vdesc->node);
125 	idma64c->desc = to_idma64_desc(vdesc);
126 
127 	/* Configure the channel */
128 	idma64_chan_init(idma64, idma64c);
129 
130 	/* Start the channel with a new descriptor */
131 	idma64_chan_start(idma64, idma64c);
132 }
133 
134 /* ---------------------------------------------------------------------- */
135 
136 static void idma64_chan_irq(struct idma64 *idma64, unsigned short c,
137 		u32 status_err, u32 status_xfer)
138 {
139 	struct idma64_chan *idma64c = &idma64->chan[c];
140 	struct dma_chan_percpu *stat;
141 	struct idma64_desc *desc;
142 
143 	stat = this_cpu_ptr(idma64c->vchan.chan.local);
144 
145 	spin_lock(&idma64c->vchan.lock);
146 	desc = idma64c->desc;
147 	if (desc) {
148 		if (status_err & (1 << c)) {
149 			dma_writel(idma64, CLEAR(ERROR), idma64c->mask);
150 			desc->status = DMA_ERROR;
151 		} else if (status_xfer & (1 << c)) {
152 			dma_writel(idma64, CLEAR(XFER), idma64c->mask);
153 			desc->status = DMA_COMPLETE;
154 			vchan_cookie_complete(&desc->vdesc);
155 			stat->bytes_transferred += desc->length;
156 			idma64_start_transfer(idma64c);
157 		}
158 
159 		/* idma64_start_transfer() updates idma64c->desc */
160 		if (idma64c->desc == NULL || desc->status == DMA_ERROR)
161 			idma64_stop_transfer(idma64c);
162 	}
163 	spin_unlock(&idma64c->vchan.lock);
164 }
165 
166 static irqreturn_t idma64_irq(int irq, void *dev)
167 {
168 	struct idma64 *idma64 = dev;
169 	u32 status = dma_readl(idma64, STATUS_INT);
170 	u32 status_xfer;
171 	u32 status_err;
172 	unsigned short i;
173 
174 	dev_vdbg(idma64->dma.dev, "%s: status=%#x\n", __func__, status);
175 
176 	/* Check if we have any interrupt from the DMA controller */
177 	if (!status)
178 		return IRQ_NONE;
179 
180 	status_xfer = dma_readl(idma64, RAW(XFER));
181 	status_err = dma_readl(idma64, RAW(ERROR));
182 
183 	for (i = 0; i < idma64->dma.chancnt; i++)
184 		idma64_chan_irq(idma64, i, status_err, status_xfer);
185 
186 	return IRQ_HANDLED;
187 }
188 
189 /* ---------------------------------------------------------------------- */
190 
191 static struct idma64_desc *idma64_alloc_desc(unsigned int ndesc)
192 {
193 	struct idma64_desc *desc;
194 
195 	desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
196 	if (!desc)
197 		return NULL;
198 
199 	desc->hw = kcalloc(ndesc, sizeof(*desc->hw), GFP_NOWAIT);
200 	if (!desc->hw) {
201 		kfree(desc);
202 		return NULL;
203 	}
204 
205 	return desc;
206 }
207 
208 static void idma64_desc_free(struct idma64_chan *idma64c,
209 		struct idma64_desc *desc)
210 {
211 	struct idma64_hw_desc *hw;
212 
213 	if (desc->ndesc) {
214 		unsigned int i = desc->ndesc;
215 
216 		do {
217 			hw = &desc->hw[--i];
218 			dma_pool_free(idma64c->pool, hw->lli, hw->llp);
219 		} while (i);
220 	}
221 
222 	kfree(desc->hw);
223 	kfree(desc);
224 }
225 
226 static void idma64_vdesc_free(struct virt_dma_desc *vdesc)
227 {
228 	struct idma64_chan *idma64c = to_idma64_chan(vdesc->tx.chan);
229 
230 	idma64_desc_free(idma64c, to_idma64_desc(vdesc));
231 }
232 
233 static void idma64_hw_desc_fill(struct idma64_hw_desc *hw,
234 		struct dma_slave_config *config,
235 		enum dma_transfer_direction direction, u64 llp)
236 {
237 	struct idma64_lli *lli = hw->lli;
238 	u64 sar, dar;
239 	u32 ctlhi = IDMA64C_CTLH_BLOCK_TS(hw->len);
240 	u32 ctllo = IDMA64C_CTLL_LLP_S_EN | IDMA64C_CTLL_LLP_D_EN;
241 	u32 src_width, dst_width;
242 
243 	if (direction == DMA_MEM_TO_DEV) {
244 		sar = hw->phys;
245 		dar = config->dst_addr;
246 		ctllo |= IDMA64C_CTLL_DST_FIX | IDMA64C_CTLL_SRC_INC |
247 			 IDMA64C_CTLL_FC_M2P;
248 		src_width = __ffs(sar | hw->len | 4);
249 		dst_width = __ffs(config->dst_addr_width);
250 	} else {	/* DMA_DEV_TO_MEM */
251 		sar = config->src_addr;
252 		dar = hw->phys;
253 		ctllo |= IDMA64C_CTLL_DST_INC | IDMA64C_CTLL_SRC_FIX |
254 			 IDMA64C_CTLL_FC_P2M;
255 		src_width = __ffs(config->src_addr_width);
256 		dst_width = __ffs(dar | hw->len | 4);
257 	}
258 
259 	lli->sar = sar;
260 	lli->dar = dar;
261 
262 	lli->ctlhi = ctlhi;
263 	lli->ctllo = ctllo |
264 		     IDMA64C_CTLL_SRC_MSIZE(config->src_maxburst) |
265 		     IDMA64C_CTLL_DST_MSIZE(config->dst_maxburst) |
266 		     IDMA64C_CTLL_DST_WIDTH(dst_width) |
267 		     IDMA64C_CTLL_SRC_WIDTH(src_width);
268 
269 	lli->llp = llp;
270 }
271 
272 static void idma64_desc_fill(struct idma64_chan *idma64c,
273 		struct idma64_desc *desc)
274 {
275 	struct dma_slave_config *config = &idma64c->config;
276 	unsigned int i = desc->ndesc;
277 	struct idma64_hw_desc *hw = &desc->hw[i - 1];
278 	struct idma64_lli *lli = hw->lli;
279 	u64 llp = 0;
280 
281 	/* Fill the hardware descriptors and link them to a list */
282 	do {
283 		hw = &desc->hw[--i];
284 		idma64_hw_desc_fill(hw, config, desc->direction, llp);
285 		llp = hw->llp;
286 		desc->length += hw->len;
287 	} while (i);
288 
289 	/* Trigger an interrupt after the last block is transfered */
290 	lli->ctllo |= IDMA64C_CTLL_INT_EN;
291 
292 	/* Disable LLP transfer in the last block */
293 	lli->ctllo &= ~(IDMA64C_CTLL_LLP_S_EN | IDMA64C_CTLL_LLP_D_EN);
294 }
295 
296 static struct dma_async_tx_descriptor *idma64_prep_slave_sg(
297 		struct dma_chan *chan, struct scatterlist *sgl,
298 		unsigned int sg_len, enum dma_transfer_direction direction,
299 		unsigned long flags, void *context)
300 {
301 	struct idma64_chan *idma64c = to_idma64_chan(chan);
302 	struct idma64_desc *desc;
303 	struct scatterlist *sg;
304 	unsigned int i;
305 
306 	desc = idma64_alloc_desc(sg_len);
307 	if (!desc)
308 		return NULL;
309 
310 	for_each_sg(sgl, sg, sg_len, i) {
311 		struct idma64_hw_desc *hw = &desc->hw[i];
312 
313 		/* Allocate DMA capable memory for hardware descriptor */
314 		hw->lli = dma_pool_alloc(idma64c->pool, GFP_NOWAIT, &hw->llp);
315 		if (!hw->lli) {
316 			desc->ndesc = i;
317 			idma64_desc_free(idma64c, desc);
318 			return NULL;
319 		}
320 
321 		hw->phys = sg_dma_address(sg);
322 		hw->len = sg_dma_len(sg);
323 	}
324 
325 	desc->ndesc = sg_len;
326 	desc->direction = direction;
327 	desc->status = DMA_IN_PROGRESS;
328 
329 	idma64_desc_fill(idma64c, desc);
330 	return vchan_tx_prep(&idma64c->vchan, &desc->vdesc, flags);
331 }
332 
333 static void idma64_issue_pending(struct dma_chan *chan)
334 {
335 	struct idma64_chan *idma64c = to_idma64_chan(chan);
336 	unsigned long flags;
337 
338 	spin_lock_irqsave(&idma64c->vchan.lock, flags);
339 	if (vchan_issue_pending(&idma64c->vchan) && !idma64c->desc)
340 		idma64_start_transfer(idma64c);
341 	spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
342 }
343 
344 static size_t idma64_active_desc_size(struct idma64_chan *idma64c)
345 {
346 	struct idma64_desc *desc = idma64c->desc;
347 	struct idma64_hw_desc *hw;
348 	size_t bytes = desc->length;
349 	u64 llp = channel_readq(idma64c, LLP);
350 	u32 ctlhi = channel_readl(idma64c, CTL_HI);
351 	unsigned int i = 0;
352 
353 	do {
354 		hw = &desc->hw[i];
355 		if (hw->llp == llp)
356 			break;
357 		bytes -= hw->len;
358 	} while (++i < desc->ndesc);
359 
360 	if (!i)
361 		return bytes;
362 
363 	/* The current chunk is not fully transfered yet */
364 	bytes += desc->hw[--i].len;
365 
366 	return bytes - IDMA64C_CTLH_BLOCK_TS(ctlhi);
367 }
368 
369 static enum dma_status idma64_tx_status(struct dma_chan *chan,
370 		dma_cookie_t cookie, struct dma_tx_state *state)
371 {
372 	struct idma64_chan *idma64c = to_idma64_chan(chan);
373 	struct virt_dma_desc *vdesc;
374 	enum dma_status status;
375 	size_t bytes;
376 	unsigned long flags;
377 
378 	status = dma_cookie_status(chan, cookie, state);
379 	if (status == DMA_COMPLETE)
380 		return status;
381 
382 	spin_lock_irqsave(&idma64c->vchan.lock, flags);
383 	vdesc = vchan_find_desc(&idma64c->vchan, cookie);
384 	if (idma64c->desc && cookie == idma64c->desc->vdesc.tx.cookie) {
385 		bytes = idma64_active_desc_size(idma64c);
386 		dma_set_residue(state, bytes);
387 		status = idma64c->desc->status;
388 	} else if (vdesc) {
389 		bytes = to_idma64_desc(vdesc)->length;
390 		dma_set_residue(state, bytes);
391 	}
392 	spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
393 
394 	return status;
395 }
396 
397 static void convert_burst(u32 *maxburst)
398 {
399 	if (*maxburst)
400 		*maxburst = __fls(*maxburst);
401 	else
402 		*maxburst = 0;
403 }
404 
405 static int idma64_slave_config(struct dma_chan *chan,
406 		struct dma_slave_config *config)
407 {
408 	struct idma64_chan *idma64c = to_idma64_chan(chan);
409 
410 	memcpy(&idma64c->config, config, sizeof(idma64c->config));
411 
412 	convert_burst(&idma64c->config.src_maxburst);
413 	convert_burst(&idma64c->config.dst_maxburst);
414 
415 	return 0;
416 }
417 
418 static void idma64_chan_deactivate(struct idma64_chan *idma64c, bool drain)
419 {
420 	unsigned short count = 100;
421 	u32 cfglo;
422 
423 	cfglo = channel_readl(idma64c, CFG_LO);
424 	if (drain)
425 		cfglo |= IDMA64C_CFGL_CH_DRAIN;
426 	else
427 		cfglo &= ~IDMA64C_CFGL_CH_DRAIN;
428 
429 	channel_writel(idma64c, CFG_LO, cfglo | IDMA64C_CFGL_CH_SUSP);
430 	do {
431 		udelay(1);
432 		cfglo = channel_readl(idma64c, CFG_LO);
433 	} while (!(cfglo & IDMA64C_CFGL_FIFO_EMPTY) && --count);
434 }
435 
436 static void idma64_chan_activate(struct idma64_chan *idma64c)
437 {
438 	u32 cfglo;
439 
440 	cfglo = channel_readl(idma64c, CFG_LO);
441 	channel_writel(idma64c, CFG_LO, cfglo & ~IDMA64C_CFGL_CH_SUSP);
442 }
443 
444 static int idma64_pause(struct dma_chan *chan)
445 {
446 	struct idma64_chan *idma64c = to_idma64_chan(chan);
447 	unsigned long flags;
448 
449 	spin_lock_irqsave(&idma64c->vchan.lock, flags);
450 	if (idma64c->desc && idma64c->desc->status == DMA_IN_PROGRESS) {
451 		idma64_chan_deactivate(idma64c, false);
452 		idma64c->desc->status = DMA_PAUSED;
453 	}
454 	spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
455 
456 	return 0;
457 }
458 
459 static int idma64_resume(struct dma_chan *chan)
460 {
461 	struct idma64_chan *idma64c = to_idma64_chan(chan);
462 	unsigned long flags;
463 
464 	spin_lock_irqsave(&idma64c->vchan.lock, flags);
465 	if (idma64c->desc && idma64c->desc->status == DMA_PAUSED) {
466 		idma64c->desc->status = DMA_IN_PROGRESS;
467 		idma64_chan_activate(idma64c);
468 	}
469 	spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
470 
471 	return 0;
472 }
473 
474 static int idma64_terminate_all(struct dma_chan *chan)
475 {
476 	struct idma64_chan *idma64c = to_idma64_chan(chan);
477 	unsigned long flags;
478 	LIST_HEAD(head);
479 
480 	spin_lock_irqsave(&idma64c->vchan.lock, flags);
481 	idma64_chan_deactivate(idma64c, true);
482 	idma64_stop_transfer(idma64c);
483 	if (idma64c->desc) {
484 		idma64_vdesc_free(&idma64c->desc->vdesc);
485 		idma64c->desc = NULL;
486 	}
487 	vchan_get_all_descriptors(&idma64c->vchan, &head);
488 	spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
489 
490 	vchan_dma_desc_free_list(&idma64c->vchan, &head);
491 	return 0;
492 }
493 
494 static void idma64_synchronize(struct dma_chan *chan)
495 {
496 	struct idma64_chan *idma64c = to_idma64_chan(chan);
497 
498 	vchan_synchronize(&idma64c->vchan);
499 }
500 
501 static int idma64_alloc_chan_resources(struct dma_chan *chan)
502 {
503 	struct idma64_chan *idma64c = to_idma64_chan(chan);
504 
505 	/* Create a pool of consistent memory blocks for hardware descriptors */
506 	idma64c->pool = dma_pool_create(dev_name(chan2dev(chan)),
507 					chan->device->dev,
508 					sizeof(struct idma64_lli), 8, 0);
509 	if (!idma64c->pool) {
510 		dev_err(chan2dev(chan), "No memory for descriptors\n");
511 		return -ENOMEM;
512 	}
513 
514 	return 0;
515 }
516 
517 static void idma64_free_chan_resources(struct dma_chan *chan)
518 {
519 	struct idma64_chan *idma64c = to_idma64_chan(chan);
520 
521 	vchan_free_chan_resources(to_virt_chan(chan));
522 	dma_pool_destroy(idma64c->pool);
523 	idma64c->pool = NULL;
524 }
525 
526 /* ---------------------------------------------------------------------- */
527 
528 #define IDMA64_BUSWIDTHS				\
529 	BIT(DMA_SLAVE_BUSWIDTH_1_BYTE)		|	\
530 	BIT(DMA_SLAVE_BUSWIDTH_2_BYTES)		|	\
531 	BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
532 
533 static int idma64_probe(struct idma64_chip *chip)
534 {
535 	struct idma64 *idma64;
536 	unsigned short nr_chan = IDMA64_NR_CHAN;
537 	unsigned short i;
538 	int ret;
539 
540 	idma64 = devm_kzalloc(chip->dev, sizeof(*idma64), GFP_KERNEL);
541 	if (!idma64)
542 		return -ENOMEM;
543 
544 	idma64->regs = chip->regs;
545 	chip->idma64 = idma64;
546 
547 	idma64->chan = devm_kcalloc(chip->dev, nr_chan, sizeof(*idma64->chan),
548 				    GFP_KERNEL);
549 	if (!idma64->chan)
550 		return -ENOMEM;
551 
552 	idma64->all_chan_mask = (1 << nr_chan) - 1;
553 
554 	/* Turn off iDMA controller */
555 	idma64_off(idma64);
556 
557 	ret = devm_request_irq(chip->dev, chip->irq, idma64_irq, IRQF_SHARED,
558 			       dev_name(chip->dev), idma64);
559 	if (ret)
560 		return ret;
561 
562 	INIT_LIST_HEAD(&idma64->dma.channels);
563 	for (i = 0; i < nr_chan; i++) {
564 		struct idma64_chan *idma64c = &idma64->chan[i];
565 
566 		idma64c->vchan.desc_free = idma64_vdesc_free;
567 		vchan_init(&idma64c->vchan, &idma64->dma);
568 
569 		idma64c->regs = idma64->regs + i * IDMA64_CH_LENGTH;
570 		idma64c->mask = BIT(i);
571 	}
572 
573 	dma_cap_set(DMA_SLAVE, idma64->dma.cap_mask);
574 	dma_cap_set(DMA_PRIVATE, idma64->dma.cap_mask);
575 
576 	idma64->dma.device_alloc_chan_resources = idma64_alloc_chan_resources;
577 	idma64->dma.device_free_chan_resources = idma64_free_chan_resources;
578 
579 	idma64->dma.device_prep_slave_sg = idma64_prep_slave_sg;
580 
581 	idma64->dma.device_issue_pending = idma64_issue_pending;
582 	idma64->dma.device_tx_status = idma64_tx_status;
583 
584 	idma64->dma.device_config = idma64_slave_config;
585 	idma64->dma.device_pause = idma64_pause;
586 	idma64->dma.device_resume = idma64_resume;
587 	idma64->dma.device_terminate_all = idma64_terminate_all;
588 	idma64->dma.device_synchronize = idma64_synchronize;
589 
590 	idma64->dma.src_addr_widths = IDMA64_BUSWIDTHS;
591 	idma64->dma.dst_addr_widths = IDMA64_BUSWIDTHS;
592 	idma64->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
593 	idma64->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
594 
595 	idma64->dma.dev = chip->sysdev;
596 
597 	dma_set_max_seg_size(idma64->dma.dev, IDMA64C_CTLH_BLOCK_TS_MASK);
598 
599 	ret = dma_async_device_register(&idma64->dma);
600 	if (ret)
601 		return ret;
602 
603 	dev_info(chip->dev, "Found Intel integrated DMA 64-bit\n");
604 	return 0;
605 }
606 
607 static void idma64_remove(struct idma64_chip *chip)
608 {
609 	struct idma64 *idma64 = chip->idma64;
610 	unsigned short i;
611 
612 	dma_async_device_unregister(&idma64->dma);
613 
614 	/*
615 	 * Explicitly call devm_request_irq() to avoid the side effects with
616 	 * the scheduled tasklets.
617 	 */
618 	devm_free_irq(chip->dev, chip->irq, idma64);
619 
620 	for (i = 0; i < idma64->dma.chancnt; i++) {
621 		struct idma64_chan *idma64c = &idma64->chan[i];
622 
623 		tasklet_kill(&idma64c->vchan.task);
624 	}
625 }
626 
627 /* ---------------------------------------------------------------------- */
628 
629 static int idma64_platform_probe(struct platform_device *pdev)
630 {
631 	struct idma64_chip *chip;
632 	struct device *dev = &pdev->dev;
633 	struct device *sysdev = dev->parent;
634 	int ret;
635 
636 	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
637 	if (!chip)
638 		return -ENOMEM;
639 
640 	chip->irq = platform_get_irq(pdev, 0);
641 	if (chip->irq < 0)
642 		return chip->irq;
643 
644 	chip->regs = devm_platform_ioremap_resource(pdev, 0);
645 	if (IS_ERR(chip->regs))
646 		return PTR_ERR(chip->regs);
647 
648 	ret = dma_coerce_mask_and_coherent(sysdev, DMA_BIT_MASK(64));
649 	if (ret)
650 		return ret;
651 
652 	chip->dev = dev;
653 	chip->sysdev = sysdev;
654 
655 	ret = idma64_probe(chip);
656 	if (ret)
657 		return ret;
658 
659 	platform_set_drvdata(pdev, chip);
660 	return 0;
661 }
662 
663 static int idma64_platform_remove(struct platform_device *pdev)
664 {
665 	struct idma64_chip *chip = platform_get_drvdata(pdev);
666 
667 	idma64_remove(chip);
668 
669 	return 0;
670 }
671 
672 static int __maybe_unused idma64_pm_suspend(struct device *dev)
673 {
674 	struct idma64_chip *chip = dev_get_drvdata(dev);
675 
676 	idma64_off(chip->idma64);
677 	return 0;
678 }
679 
680 static int __maybe_unused idma64_pm_resume(struct device *dev)
681 {
682 	struct idma64_chip *chip = dev_get_drvdata(dev);
683 
684 	idma64_on(chip->idma64);
685 	return 0;
686 }
687 
688 static const struct dev_pm_ops idma64_dev_pm_ops = {
689 	SET_SYSTEM_SLEEP_PM_OPS(idma64_pm_suspend, idma64_pm_resume)
690 };
691 
692 static struct platform_driver idma64_platform_driver = {
693 	.probe		= idma64_platform_probe,
694 	.remove		= idma64_platform_remove,
695 	.driver = {
696 		.name	= LPSS_IDMA64_DRIVER_NAME,
697 		.pm	= &idma64_dev_pm_ops,
698 	},
699 };
700 
701 module_platform_driver(idma64_platform_driver);
702 
703 MODULE_LICENSE("GPL v2");
704 MODULE_DESCRIPTION("iDMA64 core driver");
705 MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
706 MODULE_ALIAS("platform:" LPSS_IDMA64_DRIVER_NAME);
707