xref: /openbmc/linux/drivers/dma/idma64.c (revision 4c9ca2fd) 
1 /*
2  * Core driver for the Intel integrated DMA 64-bit
3  *
4  * Copyright (C) 2015 Intel Corporation
5  * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10  */
11 
12 #include <linux/bitops.h>
13 #include <linux/delay.h>
14 #include <linux/dmaengine.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/dmapool.h>
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/platform_device.h>
20 #include <linux/slab.h>
21 
22 #include "idma64.h"
23 
24 /* Platform driver name */
25 #define DRV_NAME		"idma64"
26 
27 /* For now we support only two channels */
28 #define IDMA64_NR_CHAN		2
29 
30 /* ---------------------------------------------------------------------- */
31 
32 static struct device *chan2dev(struct dma_chan *chan)
33 {
34 	return &chan->dev->device;
35 }
36 
37 /* ---------------------------------------------------------------------- */
38 
39 static void idma64_off(struct idma64 *idma64)
40 {
41 	unsigned short count = 100;
42 
43 	dma_writel(idma64, CFG, 0);
44 
45 	channel_clear_bit(idma64, MASK(XFER), idma64->all_chan_mask);
46 	channel_clear_bit(idma64, MASK(BLOCK), idma64->all_chan_mask);
47 	channel_clear_bit(idma64, MASK(SRC_TRAN), idma64->all_chan_mask);
48 	channel_clear_bit(idma64, MASK(DST_TRAN), idma64->all_chan_mask);
49 	channel_clear_bit(idma64, MASK(ERROR), idma64->all_chan_mask);
50 
51 	do {
52 		cpu_relax();
53 	} while (dma_readl(idma64, CFG) & IDMA64_CFG_DMA_EN && --count);
54 }
55 
56 static void idma64_on(struct idma64 *idma64)
57 {
58 	dma_writel(idma64, CFG, IDMA64_CFG_DMA_EN);
59 }
60 
61 /* ---------------------------------------------------------------------- */
62 
63 static void idma64_chan_init(struct idma64 *idma64, struct idma64_chan *idma64c)
64 {
65 	u32 cfghi = IDMA64C_CFGH_SRC_PER(1) | IDMA64C_CFGH_DST_PER(0);
66 	u32 cfglo = 0;
67 
68 	/* Set default burst alignment */
69 	cfglo |= IDMA64C_CFGL_DST_BURST_ALIGN | IDMA64C_CFGL_SRC_BURST_ALIGN;
70 
71 	channel_writel(idma64c, CFG_LO, cfglo);
72 	channel_writel(idma64c, CFG_HI, cfghi);
73 
74 	/* Enable interrupts */
75 	channel_set_bit(idma64, MASK(XFER), idma64c->mask);
76 	channel_set_bit(idma64, MASK(ERROR), idma64c->mask);
77 
78 	/*
79 	 * Enforce the controller to be turned on.
80 	 *
81 	 * The iDMA is turned off in ->probe() and looses context during system
82 	 * suspend / resume cycle. That's why we have to enable it each time we
83 	 * use it.
84 	 */
85 	idma64_on(idma64);
86 }
87 
88 static void idma64_chan_stop(struct idma64 *idma64, struct idma64_chan *idma64c)
89 {
90 	channel_clear_bit(idma64, CH_EN, idma64c->mask);
91 }
92 
93 static void idma64_chan_start(struct idma64 *idma64, struct idma64_chan *idma64c)
94 {
95 	struct idma64_desc *desc = idma64c->desc;
96 	struct idma64_hw_desc *hw = &desc->hw[0];
97 
98 	channel_writeq(idma64c, SAR, 0);
99 	channel_writeq(idma64c, DAR, 0);
100 
101 	channel_writel(idma64c, CTL_HI, IDMA64C_CTLH_BLOCK_TS(~0UL));
102 	channel_writel(idma64c, CTL_LO, IDMA64C_CTLL_LLP_S_EN | IDMA64C_CTLL_LLP_D_EN);
103 
104 	channel_writeq(idma64c, LLP, hw->llp);
105 
106 	channel_set_bit(idma64, CH_EN, idma64c->mask);
107 }
108 
109 static void idma64_stop_transfer(struct idma64_chan *idma64c)
110 {
111 	struct idma64 *idma64 = to_idma64(idma64c->vchan.chan.device);
112 
113 	idma64_chan_stop(idma64, idma64c);
114 }
115 
116 static void idma64_start_transfer(struct idma64_chan *idma64c)
117 {
118 	struct idma64 *idma64 = to_idma64(idma64c->vchan.chan.device);
119 	struct virt_dma_desc *vdesc;
120 
121 	/* Get the next descriptor */
122 	vdesc = vchan_next_desc(&idma64c->vchan);
123 	if (!vdesc) {
124 		idma64c->desc = NULL;
125 		return;
126 	}
127 
128 	list_del(&vdesc->node);
129 	idma64c->desc = to_idma64_desc(vdesc);
130 
131 	/* Configure the channel */
132 	idma64_chan_init(idma64, idma64c);
133 
134 	/* Start the channel with a new descriptor */
135 	idma64_chan_start(idma64, idma64c);
136 }
137 
138 /* ---------------------------------------------------------------------- */
139 
140 static void idma64_chan_irq(struct idma64 *idma64, unsigned short c,
141 		u32 status_err, u32 status_xfer)
142 {
143 	struct idma64_chan *idma64c = &idma64->chan[c];
144 	struct idma64_desc *desc;
145 	unsigned long flags;
146 
147 	spin_lock_irqsave(&idma64c->vchan.lock, flags);
148 	desc = idma64c->desc;
149 	if (desc) {
150 		if (status_err & (1 << c)) {
151 			dma_writel(idma64, CLEAR(ERROR), idma64c->mask);
152 			desc->status = DMA_ERROR;
153 		} else if (status_xfer & (1 << c)) {
154 			dma_writel(idma64, CLEAR(XFER), idma64c->mask);
155 			desc->status = DMA_COMPLETE;
156 			vchan_cookie_complete(&desc->vdesc);
157 			idma64_start_transfer(idma64c);
158 		}
159 
160 		/* idma64_start_transfer() updates idma64c->desc */
161 		if (idma64c->desc == NULL || desc->status == DMA_ERROR)
162 			idma64_stop_transfer(idma64c);
163 	}
164 	spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
165 }
166 
167 static irqreturn_t idma64_irq(int irq, void *dev)
168 {
169 	struct idma64 *idma64 = dev;
170 	u32 status = dma_readl(idma64, STATUS_INT);
171 	u32 status_xfer;
172 	u32 status_err;
173 	unsigned short i;
174 
175 	dev_vdbg(idma64->dma.dev, "%s: status=%#x\n", __func__, status);
176 
177 	/* Check if we have any interrupt from the DMA controller */
178 	if (!status)
179 		return IRQ_NONE;
180 
181 	status_xfer = dma_readl(idma64, RAW(XFER));
182 	status_err = dma_readl(idma64, RAW(ERROR));
183 
184 	for (i = 0; i < idma64->dma.chancnt; i++)
185 		idma64_chan_irq(idma64, i, status_err, status_xfer);
186 
187 	return IRQ_HANDLED;
188 }
189 
190 /* ---------------------------------------------------------------------- */
191 
192 static struct idma64_desc *idma64_alloc_desc(unsigned int ndesc)
193 {
194 	struct idma64_desc *desc;
195 
196 	desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
197 	if (!desc)
198 		return NULL;
199 
200 	desc->hw = kcalloc(ndesc, sizeof(*desc->hw), GFP_NOWAIT);
201 	if (!desc->hw) {
202 		kfree(desc);
203 		return NULL;
204 	}
205 
206 	return desc;
207 }
208 
209 static void idma64_desc_free(struct idma64_chan *idma64c,
210 		struct idma64_desc *desc)
211 {
212 	struct idma64_hw_desc *hw;
213 
214 	if (desc->ndesc) {
215 		unsigned int i = desc->ndesc;
216 
217 		do {
218 			hw = &desc->hw[--i];
219 			dma_pool_free(idma64c->pool, hw->lli, hw->llp);
220 		} while (i);
221 	}
222 
223 	kfree(desc->hw);
224 	kfree(desc);
225 }
226 
227 static void idma64_vdesc_free(struct virt_dma_desc *vdesc)
228 {
229 	struct idma64_chan *idma64c = to_idma64_chan(vdesc->tx.chan);
230 
231 	idma64_desc_free(idma64c, to_idma64_desc(vdesc));
232 }
233 
234 static void idma64_hw_desc_fill(struct idma64_hw_desc *hw,
235 		struct dma_slave_config *config,
236 		enum dma_transfer_direction direction, u64 llp)
237 {
238 	struct idma64_lli *lli = hw->lli;
239 	u64 sar, dar;
240 	u32 ctlhi = IDMA64C_CTLH_BLOCK_TS(hw->len);
241 	u32 ctllo = IDMA64C_CTLL_LLP_S_EN | IDMA64C_CTLL_LLP_D_EN;
242 	u32 src_width, dst_width;
243 
244 	if (direction == DMA_MEM_TO_DEV) {
245 		sar = hw->phys;
246 		dar = config->dst_addr;
247 		ctllo |= IDMA64C_CTLL_DST_FIX | IDMA64C_CTLL_SRC_INC |
248 			 IDMA64C_CTLL_FC_M2P;
249 		src_width = __ffs(sar | hw->len | 4);
250 		dst_width = __ffs(config->dst_addr_width);
251 	} else {	/* DMA_DEV_TO_MEM */
252 		sar = config->src_addr;
253 		dar = hw->phys;
254 		ctllo |= IDMA64C_CTLL_DST_INC | IDMA64C_CTLL_SRC_FIX |
255 			 IDMA64C_CTLL_FC_P2M;
256 		src_width = __ffs(config->src_addr_width);
257 		dst_width = __ffs(dar | hw->len | 4);
258 	}
259 
260 	lli->sar = sar;
261 	lli->dar = dar;
262 
263 	lli->ctlhi = ctlhi;
264 	lli->ctllo = ctllo |
265 		     IDMA64C_CTLL_SRC_MSIZE(config->src_maxburst) |
266 		     IDMA64C_CTLL_DST_MSIZE(config->dst_maxburst) |
267 		     IDMA64C_CTLL_DST_WIDTH(dst_width) |
268 		     IDMA64C_CTLL_SRC_WIDTH(src_width);
269 
270 	lli->llp = llp;
271 }
272 
273 static void idma64_desc_fill(struct idma64_chan *idma64c,
274 		struct idma64_desc *desc)
275 {
276 	struct dma_slave_config *config = &idma64c->config;
277 	unsigned int i = desc->ndesc;
278 	struct idma64_hw_desc *hw = &desc->hw[i - 1];
279 	struct idma64_lli *lli = hw->lli;
280 	u64 llp = 0;
281 
282 	/* Fill the hardware descriptors and link them to a list */
283 	do {
284 		hw = &desc->hw[--i];
285 		idma64_hw_desc_fill(hw, config, desc->direction, llp);
286 		llp = hw->llp;
287 		desc->length += hw->len;
288 	} while (i);
289 
290 	/* Trigger an interrupt after the last block is transfered */
291 	lli->ctllo |= IDMA64C_CTLL_INT_EN;
292 
293 	/* Disable LLP transfer in the last block */
294 	lli->ctllo &= ~(IDMA64C_CTLL_LLP_S_EN | IDMA64C_CTLL_LLP_D_EN);
295 }
296 
297 static struct dma_async_tx_descriptor *idma64_prep_slave_sg(
298 		struct dma_chan *chan, struct scatterlist *sgl,
299 		unsigned int sg_len, enum dma_transfer_direction direction,
300 		unsigned long flags, void *context)
301 {
302 	struct idma64_chan *idma64c = to_idma64_chan(chan);
303 	struct idma64_desc *desc;
304 	struct scatterlist *sg;
305 	unsigned int i;
306 
307 	desc = idma64_alloc_desc(sg_len);
308 	if (!desc)
309 		return NULL;
310 
311 	for_each_sg(sgl, sg, sg_len, i) {
312 		struct idma64_hw_desc *hw = &desc->hw[i];
313 
314 		/* Allocate DMA capable memory for hardware descriptor */
315 		hw->lli = dma_pool_alloc(idma64c->pool, GFP_NOWAIT, &hw->llp);
316 		if (!hw->lli) {
317 			desc->ndesc = i;
318 			idma64_desc_free(idma64c, desc);
319 			return NULL;
320 		}
321 
322 		hw->phys = sg_dma_address(sg);
323 		hw->len = sg_dma_len(sg);
324 	}
325 
326 	desc->ndesc = sg_len;
327 	desc->direction = direction;
328 	desc->status = DMA_IN_PROGRESS;
329 
330 	idma64_desc_fill(idma64c, desc);
331 	return vchan_tx_prep(&idma64c->vchan, &desc->vdesc, flags);
332 }
333 
334 static void idma64_issue_pending(struct dma_chan *chan)
335 {
336 	struct idma64_chan *idma64c = to_idma64_chan(chan);
337 	unsigned long flags;
338 
339 	spin_lock_irqsave(&idma64c->vchan.lock, flags);
340 	if (vchan_issue_pending(&idma64c->vchan) && !idma64c->desc)
341 		idma64_start_transfer(idma64c);
342 	spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
343 }
344 
345 static size_t idma64_active_desc_size(struct idma64_chan *idma64c)
346 {
347 	struct idma64_desc *desc = idma64c->desc;
348 	struct idma64_hw_desc *hw;
349 	size_t bytes = desc->length;
350 	u64 llp = channel_readq(idma64c, LLP);
351 	u32 ctlhi = channel_readl(idma64c, CTL_HI);
352 	unsigned int i = 0;
353 
354 	do {
355 		hw = &desc->hw[i];
356 		if (hw->llp == llp)
357 			break;
358 		bytes -= hw->len;
359 	} while (++i < desc->ndesc);
360 
361 	if (!i)
362 		return bytes;
363 
364 	/* The current chunk is not fully transfered yet */
365 	bytes += desc->hw[--i].len;
366 
367 	return bytes - IDMA64C_CTLH_BLOCK_TS(ctlhi);
368 }
369 
370 static enum dma_status idma64_tx_status(struct dma_chan *chan,
371 		dma_cookie_t cookie, struct dma_tx_state *state)
372 {
373 	struct idma64_chan *idma64c = to_idma64_chan(chan);
374 	struct virt_dma_desc *vdesc;
375 	enum dma_status status;
376 	size_t bytes;
377 	unsigned long flags;
378 
379 	status = dma_cookie_status(chan, cookie, state);
380 	if (status == DMA_COMPLETE)
381 		return status;
382 
383 	spin_lock_irqsave(&idma64c->vchan.lock, flags);
384 	vdesc = vchan_find_desc(&idma64c->vchan, cookie);
385 	if (idma64c->desc && cookie == idma64c->desc->vdesc.tx.cookie) {
386 		bytes = idma64_active_desc_size(idma64c);
387 		dma_set_residue(state, bytes);
388 		status = idma64c->desc->status;
389 	} else if (vdesc) {
390 		bytes = to_idma64_desc(vdesc)->length;
391 		dma_set_residue(state, bytes);
392 	}
393 	spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
394 
395 	return status;
396 }
397 
398 static void convert_burst(u32 *maxburst)
399 {
400 	if (*maxburst)
401 		*maxburst = __fls(*maxburst);
402 	else
403 		*maxburst = 0;
404 }
405 
406 static int idma64_slave_config(struct dma_chan *chan,
407 		struct dma_slave_config *config)
408 {
409 	struct idma64_chan *idma64c = to_idma64_chan(chan);
410 
411 	/* Check if chan will be configured for slave transfers */
412 	if (!is_slave_direction(config->direction))
413 		return -EINVAL;
414 
415 	memcpy(&idma64c->config, config, sizeof(idma64c->config));
416 
417 	convert_burst(&idma64c->config.src_maxburst);
418 	convert_burst(&idma64c->config.dst_maxburst);
419 
420 	return 0;
421 }
422 
423 static void idma64_chan_deactivate(struct idma64_chan *idma64c, bool drain)
424 {
425 	unsigned short count = 100;
426 	u32 cfglo;
427 
428 	cfglo = channel_readl(idma64c, CFG_LO);
429 	if (drain)
430 		cfglo |= IDMA64C_CFGL_CH_DRAIN;
431 	else
432 		cfglo &= ~IDMA64C_CFGL_CH_DRAIN;
433 
434 	channel_writel(idma64c, CFG_LO, cfglo | IDMA64C_CFGL_CH_SUSP);
435 	do {
436 		udelay(1);
437 		cfglo = channel_readl(idma64c, CFG_LO);
438 	} while (!(cfglo & IDMA64C_CFGL_FIFO_EMPTY) && --count);
439 }
440 
441 static void idma64_chan_activate(struct idma64_chan *idma64c)
442 {
443 	u32 cfglo;
444 
445 	cfglo = channel_readl(idma64c, CFG_LO);
446 	channel_writel(idma64c, CFG_LO, cfglo & ~IDMA64C_CFGL_CH_SUSP);
447 }
448 
449 static int idma64_pause(struct dma_chan *chan)
450 {
451 	struct idma64_chan *idma64c = to_idma64_chan(chan);
452 	unsigned long flags;
453 
454 	spin_lock_irqsave(&idma64c->vchan.lock, flags);
455 	if (idma64c->desc && idma64c->desc->status == DMA_IN_PROGRESS) {
456 		idma64_chan_deactivate(idma64c, false);
457 		idma64c->desc->status = DMA_PAUSED;
458 	}
459 	spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
460 
461 	return 0;
462 }
463 
464 static int idma64_resume(struct dma_chan *chan)
465 {
466 	struct idma64_chan *idma64c = to_idma64_chan(chan);
467 	unsigned long flags;
468 
469 	spin_lock_irqsave(&idma64c->vchan.lock, flags);
470 	if (idma64c->desc && idma64c->desc->status == DMA_PAUSED) {
471 		idma64c->desc->status = DMA_IN_PROGRESS;
472 		idma64_chan_activate(idma64c);
473 	}
474 	spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
475 
476 	return 0;
477 }
478 
479 static int idma64_terminate_all(struct dma_chan *chan)
480 {
481 	struct idma64_chan *idma64c = to_idma64_chan(chan);
482 	unsigned long flags;
483 	LIST_HEAD(head);
484 
485 	spin_lock_irqsave(&idma64c->vchan.lock, flags);
486 	idma64_chan_deactivate(idma64c, true);
487 	idma64_stop_transfer(idma64c);
488 	if (idma64c->desc) {
489 		idma64_vdesc_free(&idma64c->desc->vdesc);
490 		idma64c->desc = NULL;
491 	}
492 	vchan_get_all_descriptors(&idma64c->vchan, &head);
493 	spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
494 
495 	vchan_dma_desc_free_list(&idma64c->vchan, &head);
496 	return 0;
497 }
498 
499 static int idma64_alloc_chan_resources(struct dma_chan *chan)
500 {
501 	struct idma64_chan *idma64c = to_idma64_chan(chan);
502 
503 	/* Create a pool of consistent memory blocks for hardware descriptors */
504 	idma64c->pool = dma_pool_create(dev_name(chan2dev(chan)),
505 					chan->device->dev,
506 					sizeof(struct idma64_lli), 8, 0);
507 	if (!idma64c->pool) {
508 		dev_err(chan2dev(chan), "No memory for descriptors\n");
509 		return -ENOMEM;
510 	}
511 
512 	return 0;
513 }
514 
515 static void idma64_free_chan_resources(struct dma_chan *chan)
516 {
517 	struct idma64_chan *idma64c = to_idma64_chan(chan);
518 
519 	vchan_free_chan_resources(to_virt_chan(chan));
520 	dma_pool_destroy(idma64c->pool);
521 	idma64c->pool = NULL;
522 }
523 
524 /* ---------------------------------------------------------------------- */
525 
526 #define IDMA64_BUSWIDTHS				\
527 	BIT(DMA_SLAVE_BUSWIDTH_1_BYTE)		|	\
528 	BIT(DMA_SLAVE_BUSWIDTH_2_BYTES)		|	\
529 	BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
530 
531 static int idma64_probe(struct idma64_chip *chip)
532 {
533 	struct idma64 *idma64;
534 	unsigned short nr_chan = IDMA64_NR_CHAN;
535 	unsigned short i;
536 	int ret;
537 
538 	idma64 = devm_kzalloc(chip->dev, sizeof(*idma64), GFP_KERNEL);
539 	if (!idma64)
540 		return -ENOMEM;
541 
542 	idma64->regs = chip->regs;
543 	chip->idma64 = idma64;
544 
545 	idma64->chan = devm_kcalloc(chip->dev, nr_chan, sizeof(*idma64->chan),
546 				    GFP_KERNEL);
547 	if (!idma64->chan)
548 		return -ENOMEM;
549 
550 	idma64->all_chan_mask = (1 << nr_chan) - 1;
551 
552 	/* Turn off iDMA controller */
553 	idma64_off(idma64);
554 
555 	ret = devm_request_irq(chip->dev, chip->irq, idma64_irq, IRQF_SHARED,
556 			       dev_name(chip->dev), idma64);
557 	if (ret)
558 		return ret;
559 
560 	INIT_LIST_HEAD(&idma64->dma.channels);
561 	for (i = 0; i < nr_chan; i++) {
562 		struct idma64_chan *idma64c = &idma64->chan[i];
563 
564 		idma64c->vchan.desc_free = idma64_vdesc_free;
565 		vchan_init(&idma64c->vchan, &idma64->dma);
566 
567 		idma64c->regs = idma64->regs + i * IDMA64_CH_LENGTH;
568 		idma64c->mask = BIT(i);
569 	}
570 
571 	dma_cap_set(DMA_SLAVE, idma64->dma.cap_mask);
572 	dma_cap_set(DMA_PRIVATE, idma64->dma.cap_mask);
573 
574 	idma64->dma.device_alloc_chan_resources = idma64_alloc_chan_resources;
575 	idma64->dma.device_free_chan_resources = idma64_free_chan_resources;
576 
577 	idma64->dma.device_prep_slave_sg = idma64_prep_slave_sg;
578 
579 	idma64->dma.device_issue_pending = idma64_issue_pending;
580 	idma64->dma.device_tx_status = idma64_tx_status;
581 
582 	idma64->dma.device_config = idma64_slave_config;
583 	idma64->dma.device_pause = idma64_pause;
584 	idma64->dma.device_resume = idma64_resume;
585 	idma64->dma.device_terminate_all = idma64_terminate_all;
586 
587 	idma64->dma.src_addr_widths = IDMA64_BUSWIDTHS;
588 	idma64->dma.dst_addr_widths = IDMA64_BUSWIDTHS;
589 	idma64->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
590 	idma64->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
591 
592 	idma64->dma.dev = chip->dev;
593 
594 	dma_set_max_seg_size(idma64->dma.dev, IDMA64C_CTLH_BLOCK_TS_MASK);
595 
596 	ret = dma_async_device_register(&idma64->dma);
597 	if (ret)
598 		return ret;
599 
600 	dev_info(chip->dev, "Found Intel integrated DMA 64-bit\n");
601 	return 0;
602 }
603 
604 static int idma64_remove(struct idma64_chip *chip)
605 {
606 	struct idma64 *idma64 = chip->idma64;
607 	unsigned short i;
608 
609 	dma_async_device_unregister(&idma64->dma);
610 
611 	/*
612 	 * Explicitly call devm_request_irq() to avoid the side effects with
613 	 * the scheduled tasklets.
614 	 */
615 	devm_free_irq(chip->dev, chip->irq, idma64);
616 
617 	for (i = 0; i < idma64->dma.chancnt; i++) {
618 		struct idma64_chan *idma64c = &idma64->chan[i];
619 
620 		tasklet_kill(&idma64c->vchan.task);
621 	}
622 
623 	return 0;
624 }
625 
626 /* ---------------------------------------------------------------------- */
627 
628 static int idma64_platform_probe(struct platform_device *pdev)
629 {
630 	struct idma64_chip *chip;
631 	struct device *dev = &pdev->dev;
632 	struct resource *mem;
633 	int ret;
634 
635 	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
636 	if (!chip)
637 		return -ENOMEM;
638 
639 	chip->irq = platform_get_irq(pdev, 0);
640 	if (chip->irq < 0)
641 		return chip->irq;
642 
643 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
644 	chip->regs = devm_ioremap_resource(dev, mem);
645 	if (IS_ERR(chip->regs))
646 		return PTR_ERR(chip->regs);
647 
648 	ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
649 	if (ret)
650 		return ret;
651 
652 	chip->dev = dev;
653 
654 	ret = idma64_probe(chip);
655 	if (ret)
656 		return ret;
657 
658 	platform_set_drvdata(pdev, chip);
659 	return 0;
660 }
661 
662 static int idma64_platform_remove(struct platform_device *pdev)
663 {
664 	struct idma64_chip *chip = platform_get_drvdata(pdev);
665 
666 	return idma64_remove(chip);
667 }
668 
669 #ifdef CONFIG_PM_SLEEP
670 
671 static int idma64_pm_suspend(struct device *dev)
672 {
673 	struct idma64_chip *chip = dev_get_drvdata(dev);
674 
675 	idma64_off(chip->idma64);
676 	return 0;
677 }
678 
679 static int idma64_pm_resume(struct device *dev)
680 {
681 	struct idma64_chip *chip = dev_get_drvdata(dev);
682 
683 	idma64_on(chip->idma64);
684 	return 0;
685 }
686 
687 #endif /* CONFIG_PM_SLEEP */
688 
689 static const struct dev_pm_ops idma64_dev_pm_ops = {
690 	SET_SYSTEM_SLEEP_PM_OPS(idma64_pm_suspend, idma64_pm_resume)
691 };
692 
693 static struct platform_driver idma64_platform_driver = {
694 	.probe		= idma64_platform_probe,
695 	.remove		= idma64_platform_remove,
696 	.driver = {
697 		.name	= DRV_NAME,
698 		.pm	= &idma64_dev_pm_ops,
699 	},
700 };
701 
702 module_platform_driver(idma64_platform_driver);
703 
704 MODULE_LICENSE("GPL v2");
705 MODULE_DESCRIPTION("iDMA64 core driver");
706 MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
707 MODULE_ALIAS("platform:" DRV_NAME);
708