1667dfed9SAndy Shevchenko /* 2667dfed9SAndy Shevchenko * Core driver for the Intel integrated DMA 64-bit 3667dfed9SAndy Shevchenko * 4667dfed9SAndy Shevchenko * Copyright (C) 2015 Intel Corporation 5667dfed9SAndy Shevchenko * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com> 6667dfed9SAndy Shevchenko * 7667dfed9SAndy Shevchenko * This program is free software; you can redistribute it and/or modify 8667dfed9SAndy Shevchenko * it under the terms of the GNU General Public License version 2 as 9667dfed9SAndy Shevchenko * published by the Free Software Foundation. 10667dfed9SAndy Shevchenko */ 11667dfed9SAndy Shevchenko 12667dfed9SAndy Shevchenko #include <linux/bitops.h> 13667dfed9SAndy Shevchenko #include <linux/delay.h> 14667dfed9SAndy Shevchenko #include <linux/dmaengine.h> 15667dfed9SAndy Shevchenko #include <linux/dma-mapping.h> 16667dfed9SAndy Shevchenko #include <linux/dmapool.h> 17667dfed9SAndy Shevchenko #include <linux/init.h> 18667dfed9SAndy Shevchenko #include <linux/module.h> 19667dfed9SAndy Shevchenko #include <linux/platform_device.h> 20667dfed9SAndy Shevchenko #include <linux/slab.h> 21667dfed9SAndy Shevchenko 22667dfed9SAndy Shevchenko #include "idma64.h" 23667dfed9SAndy Shevchenko 24667dfed9SAndy Shevchenko /* Platform driver name */ 25667dfed9SAndy Shevchenko #define DRV_NAME "idma64" 26667dfed9SAndy Shevchenko 27667dfed9SAndy Shevchenko /* For now we support only two channels */ 28667dfed9SAndy Shevchenko #define IDMA64_NR_CHAN 2 29667dfed9SAndy Shevchenko 30667dfed9SAndy Shevchenko /* ---------------------------------------------------------------------- */ 31667dfed9SAndy Shevchenko 32667dfed9SAndy Shevchenko static struct device *chan2dev(struct dma_chan *chan) 33667dfed9SAndy Shevchenko { 34667dfed9SAndy Shevchenko return &chan->dev->device; 35667dfed9SAndy Shevchenko } 36667dfed9SAndy Shevchenko 37667dfed9SAndy Shevchenko /* ---------------------------------------------------------------------- */ 38667dfed9SAndy Shevchenko 39667dfed9SAndy Shevchenko static void idma64_off(struct idma64 *idma64) 40667dfed9SAndy Shevchenko { 41667dfed9SAndy Shevchenko unsigned short count = 100; 42667dfed9SAndy Shevchenko 43667dfed9SAndy Shevchenko dma_writel(idma64, CFG, 0); 44667dfed9SAndy Shevchenko 45667dfed9SAndy Shevchenko channel_clear_bit(idma64, MASK(XFER), idma64->all_chan_mask); 46667dfed9SAndy Shevchenko channel_clear_bit(idma64, MASK(BLOCK), idma64->all_chan_mask); 47667dfed9SAndy Shevchenko channel_clear_bit(idma64, MASK(SRC_TRAN), idma64->all_chan_mask); 48667dfed9SAndy Shevchenko channel_clear_bit(idma64, MASK(DST_TRAN), idma64->all_chan_mask); 49667dfed9SAndy Shevchenko channel_clear_bit(idma64, MASK(ERROR), idma64->all_chan_mask); 50667dfed9SAndy Shevchenko 51667dfed9SAndy Shevchenko do { 52667dfed9SAndy Shevchenko cpu_relax(); 53667dfed9SAndy Shevchenko } while (dma_readl(idma64, CFG) & IDMA64_CFG_DMA_EN && --count); 54667dfed9SAndy Shevchenko } 55667dfed9SAndy Shevchenko 56667dfed9SAndy Shevchenko static void idma64_on(struct idma64 *idma64) 57667dfed9SAndy Shevchenko { 58667dfed9SAndy Shevchenko dma_writel(idma64, CFG, IDMA64_CFG_DMA_EN); 59667dfed9SAndy Shevchenko } 60667dfed9SAndy Shevchenko 61667dfed9SAndy Shevchenko /* ---------------------------------------------------------------------- */ 62667dfed9SAndy Shevchenko 63667dfed9SAndy Shevchenko static void idma64_chan_init(struct idma64 *idma64, struct idma64_chan *idma64c) 64667dfed9SAndy Shevchenko { 65667dfed9SAndy Shevchenko u32 cfghi = IDMA64C_CFGH_SRC_PER(1) | IDMA64C_CFGH_DST_PER(0); 66667dfed9SAndy Shevchenko u32 cfglo = 0; 67667dfed9SAndy Shevchenko 68667dfed9SAndy Shevchenko /* Enforce FIFO drain when channel is suspended */ 69667dfed9SAndy Shevchenko cfglo |= IDMA64C_CFGL_CH_DRAIN; 70667dfed9SAndy Shevchenko 71667dfed9SAndy Shevchenko /* Set default burst alignment */ 72667dfed9SAndy Shevchenko cfglo |= IDMA64C_CFGL_DST_BURST_ALIGN | IDMA64C_CFGL_SRC_BURST_ALIGN; 73667dfed9SAndy Shevchenko 74667dfed9SAndy Shevchenko channel_writel(idma64c, CFG_LO, cfglo); 75667dfed9SAndy Shevchenko channel_writel(idma64c, CFG_HI, cfghi); 76667dfed9SAndy Shevchenko 77667dfed9SAndy Shevchenko /* Enable interrupts */ 78667dfed9SAndy Shevchenko channel_set_bit(idma64, MASK(XFER), idma64c->mask); 79667dfed9SAndy Shevchenko channel_set_bit(idma64, MASK(ERROR), idma64c->mask); 80667dfed9SAndy Shevchenko 81667dfed9SAndy Shevchenko /* 82667dfed9SAndy Shevchenko * Enforce the controller to be turned on. 83667dfed9SAndy Shevchenko * 84667dfed9SAndy Shevchenko * The iDMA is turned off in ->probe() and looses context during system 85667dfed9SAndy Shevchenko * suspend / resume cycle. That's why we have to enable it each time we 86667dfed9SAndy Shevchenko * use it. 87667dfed9SAndy Shevchenko */ 88667dfed9SAndy Shevchenko idma64_on(idma64); 89667dfed9SAndy Shevchenko } 90667dfed9SAndy Shevchenko 91667dfed9SAndy Shevchenko static void idma64_chan_stop(struct idma64 *idma64, struct idma64_chan *idma64c) 92667dfed9SAndy Shevchenko { 93667dfed9SAndy Shevchenko channel_clear_bit(idma64, CH_EN, idma64c->mask); 94667dfed9SAndy Shevchenko } 95667dfed9SAndy Shevchenko 96667dfed9SAndy Shevchenko static void idma64_chan_start(struct idma64 *idma64, struct idma64_chan *idma64c) 97667dfed9SAndy Shevchenko { 98667dfed9SAndy Shevchenko struct idma64_desc *desc = idma64c->desc; 99667dfed9SAndy Shevchenko struct idma64_hw_desc *hw = &desc->hw[0]; 100667dfed9SAndy Shevchenko 101667dfed9SAndy Shevchenko channel_writeq(idma64c, SAR, 0); 102667dfed9SAndy Shevchenko channel_writeq(idma64c, DAR, 0); 103667dfed9SAndy Shevchenko 104667dfed9SAndy Shevchenko channel_writel(idma64c, CTL_HI, IDMA64C_CTLH_BLOCK_TS(~0UL)); 105667dfed9SAndy Shevchenko channel_writel(idma64c, CTL_LO, IDMA64C_CTLL_LLP_S_EN | IDMA64C_CTLL_LLP_D_EN); 106667dfed9SAndy Shevchenko 107667dfed9SAndy Shevchenko channel_writeq(idma64c, LLP, hw->llp); 108667dfed9SAndy Shevchenko 109667dfed9SAndy Shevchenko channel_set_bit(idma64, CH_EN, idma64c->mask); 110667dfed9SAndy Shevchenko } 111667dfed9SAndy Shevchenko 112667dfed9SAndy Shevchenko static void idma64_stop_transfer(struct idma64_chan *idma64c) 113667dfed9SAndy Shevchenko { 114667dfed9SAndy Shevchenko struct idma64 *idma64 = to_idma64(idma64c->vchan.chan.device); 115667dfed9SAndy Shevchenko 116667dfed9SAndy Shevchenko idma64_chan_stop(idma64, idma64c); 117667dfed9SAndy Shevchenko } 118667dfed9SAndy Shevchenko 119667dfed9SAndy Shevchenko static void idma64_start_transfer(struct idma64_chan *idma64c) 120667dfed9SAndy Shevchenko { 121667dfed9SAndy Shevchenko struct idma64 *idma64 = to_idma64(idma64c->vchan.chan.device); 122667dfed9SAndy Shevchenko struct virt_dma_desc *vdesc; 123667dfed9SAndy Shevchenko 124667dfed9SAndy Shevchenko /* Get the next descriptor */ 125667dfed9SAndy Shevchenko vdesc = vchan_next_desc(&idma64c->vchan); 126667dfed9SAndy Shevchenko if (!vdesc) { 127667dfed9SAndy Shevchenko idma64c->desc = NULL; 128667dfed9SAndy Shevchenko return; 129667dfed9SAndy Shevchenko } 130667dfed9SAndy Shevchenko 131667dfed9SAndy Shevchenko list_del(&vdesc->node); 132667dfed9SAndy Shevchenko idma64c->desc = to_idma64_desc(vdesc); 133667dfed9SAndy Shevchenko 134667dfed9SAndy Shevchenko /* Configure the channel */ 135667dfed9SAndy Shevchenko idma64_chan_init(idma64, idma64c); 136667dfed9SAndy Shevchenko 137667dfed9SAndy Shevchenko /* Start the channel with a new descriptor */ 138667dfed9SAndy Shevchenko idma64_chan_start(idma64, idma64c); 139667dfed9SAndy Shevchenko } 140667dfed9SAndy Shevchenko 141667dfed9SAndy Shevchenko /* ---------------------------------------------------------------------- */ 142667dfed9SAndy Shevchenko 143667dfed9SAndy Shevchenko static void idma64_chan_irq(struct idma64 *idma64, unsigned short c, 144667dfed9SAndy Shevchenko u32 status_err, u32 status_xfer) 145667dfed9SAndy Shevchenko { 146667dfed9SAndy Shevchenko struct idma64_chan *idma64c = &idma64->chan[c]; 147667dfed9SAndy Shevchenko struct idma64_desc *desc; 148667dfed9SAndy Shevchenko unsigned long flags; 149667dfed9SAndy Shevchenko 150667dfed9SAndy Shevchenko spin_lock_irqsave(&idma64c->vchan.lock, flags); 151667dfed9SAndy Shevchenko desc = idma64c->desc; 152667dfed9SAndy Shevchenko if (desc) { 153667dfed9SAndy Shevchenko if (status_err & (1 << c)) { 154667dfed9SAndy Shevchenko dma_writel(idma64, CLEAR(ERROR), idma64c->mask); 155667dfed9SAndy Shevchenko desc->status = DMA_ERROR; 156667dfed9SAndy Shevchenko } else if (status_xfer & (1 << c)) { 157667dfed9SAndy Shevchenko dma_writel(idma64, CLEAR(XFER), idma64c->mask); 158667dfed9SAndy Shevchenko desc->status = DMA_COMPLETE; 159667dfed9SAndy Shevchenko vchan_cookie_complete(&desc->vdesc); 160667dfed9SAndy Shevchenko idma64_start_transfer(idma64c); 161667dfed9SAndy Shevchenko } 162667dfed9SAndy Shevchenko 163667dfed9SAndy Shevchenko /* idma64_start_transfer() updates idma64c->desc */ 164667dfed9SAndy Shevchenko if (idma64c->desc == NULL || desc->status == DMA_ERROR) 165667dfed9SAndy Shevchenko idma64_stop_transfer(idma64c); 166667dfed9SAndy Shevchenko } 167667dfed9SAndy Shevchenko spin_unlock_irqrestore(&idma64c->vchan.lock, flags); 168667dfed9SAndy Shevchenko } 169667dfed9SAndy Shevchenko 170667dfed9SAndy Shevchenko static irqreturn_t idma64_irq(int irq, void *dev) 171667dfed9SAndy Shevchenko { 172667dfed9SAndy Shevchenko struct idma64 *idma64 = dev; 173667dfed9SAndy Shevchenko u32 status = dma_readl(idma64, STATUS_INT); 174667dfed9SAndy Shevchenko u32 status_xfer; 175667dfed9SAndy Shevchenko u32 status_err; 176667dfed9SAndy Shevchenko unsigned short i; 177667dfed9SAndy Shevchenko 178667dfed9SAndy Shevchenko dev_vdbg(idma64->dma.dev, "%s: status=%#x\n", __func__, status); 179667dfed9SAndy Shevchenko 180667dfed9SAndy Shevchenko /* Check if we have any interrupt from the DMA controller */ 181667dfed9SAndy Shevchenko if (!status) 182667dfed9SAndy Shevchenko return IRQ_NONE; 183667dfed9SAndy Shevchenko 184667dfed9SAndy Shevchenko /* Disable interrupts */ 185667dfed9SAndy Shevchenko channel_clear_bit(idma64, MASK(XFER), idma64->all_chan_mask); 186667dfed9SAndy Shevchenko channel_clear_bit(idma64, MASK(ERROR), idma64->all_chan_mask); 187667dfed9SAndy Shevchenko 188667dfed9SAndy Shevchenko status_xfer = dma_readl(idma64, RAW(XFER)); 189667dfed9SAndy Shevchenko status_err = dma_readl(idma64, RAW(ERROR)); 190667dfed9SAndy Shevchenko 191667dfed9SAndy Shevchenko for (i = 0; i < idma64->dma.chancnt; i++) 192667dfed9SAndy Shevchenko idma64_chan_irq(idma64, i, status_err, status_xfer); 193667dfed9SAndy Shevchenko 194667dfed9SAndy Shevchenko /* Re-enable interrupts */ 195667dfed9SAndy Shevchenko channel_set_bit(idma64, MASK(XFER), idma64->all_chan_mask); 196667dfed9SAndy Shevchenko channel_set_bit(idma64, MASK(ERROR), idma64->all_chan_mask); 197667dfed9SAndy Shevchenko 198667dfed9SAndy Shevchenko return IRQ_HANDLED; 199667dfed9SAndy Shevchenko } 200667dfed9SAndy Shevchenko 201667dfed9SAndy Shevchenko /* ---------------------------------------------------------------------- */ 202667dfed9SAndy Shevchenko 203667dfed9SAndy Shevchenko static struct idma64_desc *idma64_alloc_desc(unsigned int ndesc) 204667dfed9SAndy Shevchenko { 205667dfed9SAndy Shevchenko struct idma64_desc *desc; 206667dfed9SAndy Shevchenko 207667dfed9SAndy Shevchenko desc = kzalloc(sizeof(*desc), GFP_NOWAIT); 208667dfed9SAndy Shevchenko if (!desc) 209667dfed9SAndy Shevchenko return NULL; 210667dfed9SAndy Shevchenko 211667dfed9SAndy Shevchenko desc->hw = kcalloc(ndesc, sizeof(*desc->hw), GFP_NOWAIT); 212667dfed9SAndy Shevchenko if (!desc->hw) { 213667dfed9SAndy Shevchenko kfree(desc); 214667dfed9SAndy Shevchenko return NULL; 215667dfed9SAndy Shevchenko } 216667dfed9SAndy Shevchenko 217667dfed9SAndy Shevchenko return desc; 218667dfed9SAndy Shevchenko } 219667dfed9SAndy Shevchenko 220667dfed9SAndy Shevchenko static void idma64_desc_free(struct idma64_chan *idma64c, 221667dfed9SAndy Shevchenko struct idma64_desc *desc) 222667dfed9SAndy Shevchenko { 223667dfed9SAndy Shevchenko struct idma64_hw_desc *hw; 224667dfed9SAndy Shevchenko 225667dfed9SAndy Shevchenko if (desc->ndesc) { 226667dfed9SAndy Shevchenko unsigned int i = desc->ndesc; 227667dfed9SAndy Shevchenko 228667dfed9SAndy Shevchenko do { 229667dfed9SAndy Shevchenko hw = &desc->hw[--i]; 230667dfed9SAndy Shevchenko dma_pool_free(idma64c->pool, hw->lli, hw->llp); 231667dfed9SAndy Shevchenko } while (i); 232667dfed9SAndy Shevchenko } 233667dfed9SAndy Shevchenko 234667dfed9SAndy Shevchenko kfree(desc->hw); 235667dfed9SAndy Shevchenko kfree(desc); 236667dfed9SAndy Shevchenko } 237667dfed9SAndy Shevchenko 238667dfed9SAndy Shevchenko static void idma64_vdesc_free(struct virt_dma_desc *vdesc) 239667dfed9SAndy Shevchenko { 240667dfed9SAndy Shevchenko struct idma64_chan *idma64c = to_idma64_chan(vdesc->tx.chan); 241667dfed9SAndy Shevchenko 242667dfed9SAndy Shevchenko idma64_desc_free(idma64c, to_idma64_desc(vdesc)); 243667dfed9SAndy Shevchenko } 244667dfed9SAndy Shevchenko 245667dfed9SAndy Shevchenko static u64 idma64_hw_desc_fill(struct idma64_hw_desc *hw, 246667dfed9SAndy Shevchenko struct dma_slave_config *config, 247667dfed9SAndy Shevchenko enum dma_transfer_direction direction, u64 llp) 248667dfed9SAndy Shevchenko { 249667dfed9SAndy Shevchenko struct idma64_lli *lli = hw->lli; 250667dfed9SAndy Shevchenko u64 sar, dar; 251667dfed9SAndy Shevchenko u32 ctlhi = IDMA64C_CTLH_BLOCK_TS(hw->len); 252667dfed9SAndy Shevchenko u32 ctllo = IDMA64C_CTLL_LLP_S_EN | IDMA64C_CTLL_LLP_D_EN; 253667dfed9SAndy Shevchenko u32 src_width, dst_width; 254667dfed9SAndy Shevchenko 255667dfed9SAndy Shevchenko if (direction == DMA_MEM_TO_DEV) { 256667dfed9SAndy Shevchenko sar = hw->phys; 257667dfed9SAndy Shevchenko dar = config->dst_addr; 258667dfed9SAndy Shevchenko ctllo |= IDMA64C_CTLL_DST_FIX | IDMA64C_CTLL_SRC_INC | 259667dfed9SAndy Shevchenko IDMA64C_CTLL_FC_M2P; 26087b04596SAndy Shevchenko src_width = min_t(u32, 2, __ffs(sar | hw->len)); 26187b04596SAndy Shevchenko dst_width = __ffs(config->dst_addr_width); 262667dfed9SAndy Shevchenko } else { /* DMA_DEV_TO_MEM */ 263667dfed9SAndy Shevchenko sar = config->src_addr; 264667dfed9SAndy Shevchenko dar = hw->phys; 265667dfed9SAndy Shevchenko ctllo |= IDMA64C_CTLL_DST_INC | IDMA64C_CTLL_SRC_FIX | 266667dfed9SAndy Shevchenko IDMA64C_CTLL_FC_P2M; 26787b04596SAndy Shevchenko src_width = __ffs(config->src_addr_width); 26887b04596SAndy Shevchenko dst_width = min_t(u32, 2, __ffs(dar | hw->len)); 269667dfed9SAndy Shevchenko } 270667dfed9SAndy Shevchenko 271667dfed9SAndy Shevchenko lli->sar = sar; 272667dfed9SAndy Shevchenko lli->dar = dar; 273667dfed9SAndy Shevchenko 274667dfed9SAndy Shevchenko lli->ctlhi = ctlhi; 275667dfed9SAndy Shevchenko lli->ctllo = ctllo | 276667dfed9SAndy Shevchenko IDMA64C_CTLL_SRC_MSIZE(config->src_maxburst) | 277667dfed9SAndy Shevchenko IDMA64C_CTLL_DST_MSIZE(config->dst_maxburst) | 278667dfed9SAndy Shevchenko IDMA64C_CTLL_DST_WIDTH(dst_width) | 279667dfed9SAndy Shevchenko IDMA64C_CTLL_SRC_WIDTH(src_width); 280667dfed9SAndy Shevchenko 281667dfed9SAndy Shevchenko lli->llp = llp; 282667dfed9SAndy Shevchenko return hw->llp; 283667dfed9SAndy Shevchenko } 284667dfed9SAndy Shevchenko 285667dfed9SAndy Shevchenko static void idma64_desc_fill(struct idma64_chan *idma64c, 286667dfed9SAndy Shevchenko struct idma64_desc *desc) 287667dfed9SAndy Shevchenko { 288667dfed9SAndy Shevchenko struct dma_slave_config *config = &idma64c->config; 289667dfed9SAndy Shevchenko struct idma64_hw_desc *hw = &desc->hw[desc->ndesc - 1]; 290667dfed9SAndy Shevchenko struct idma64_lli *lli = hw->lli; 291667dfed9SAndy Shevchenko u64 llp = 0; 292667dfed9SAndy Shevchenko unsigned int i = desc->ndesc; 293667dfed9SAndy Shevchenko 294667dfed9SAndy Shevchenko /* Fill the hardware descriptors and link them to a list */ 295667dfed9SAndy Shevchenko do { 296667dfed9SAndy Shevchenko hw = &desc->hw[--i]; 297667dfed9SAndy Shevchenko llp = idma64_hw_desc_fill(hw, config, desc->direction, llp); 298667dfed9SAndy Shevchenko desc->length += hw->len; 299667dfed9SAndy Shevchenko } while (i); 300667dfed9SAndy Shevchenko 301667dfed9SAndy Shevchenko /* Trigger interrupt after last block */ 302667dfed9SAndy Shevchenko lli->ctllo |= IDMA64C_CTLL_INT_EN; 303667dfed9SAndy Shevchenko } 304667dfed9SAndy Shevchenko 305667dfed9SAndy Shevchenko static struct dma_async_tx_descriptor *idma64_prep_slave_sg( 306667dfed9SAndy Shevchenko struct dma_chan *chan, struct scatterlist *sgl, 307667dfed9SAndy Shevchenko unsigned int sg_len, enum dma_transfer_direction direction, 308667dfed9SAndy Shevchenko unsigned long flags, void *context) 309667dfed9SAndy Shevchenko { 310667dfed9SAndy Shevchenko struct idma64_chan *idma64c = to_idma64_chan(chan); 311667dfed9SAndy Shevchenko struct idma64_desc *desc; 312667dfed9SAndy Shevchenko struct scatterlist *sg; 313667dfed9SAndy Shevchenko unsigned int i; 314667dfed9SAndy Shevchenko 315667dfed9SAndy Shevchenko desc = idma64_alloc_desc(sg_len); 316667dfed9SAndy Shevchenko if (!desc) 317667dfed9SAndy Shevchenko return NULL; 318667dfed9SAndy Shevchenko 319667dfed9SAndy Shevchenko for_each_sg(sgl, sg, sg_len, i) { 320667dfed9SAndy Shevchenko struct idma64_hw_desc *hw = &desc->hw[i]; 321667dfed9SAndy Shevchenko 322667dfed9SAndy Shevchenko /* Allocate DMA capable memory for hardware descriptor */ 323667dfed9SAndy Shevchenko hw->lli = dma_pool_alloc(idma64c->pool, GFP_NOWAIT, &hw->llp); 324667dfed9SAndy Shevchenko if (!hw->lli) { 325667dfed9SAndy Shevchenko desc->ndesc = i; 326667dfed9SAndy Shevchenko idma64_desc_free(idma64c, desc); 327667dfed9SAndy Shevchenko return NULL; 328667dfed9SAndy Shevchenko } 329667dfed9SAndy Shevchenko 330667dfed9SAndy Shevchenko hw->phys = sg_dma_address(sg); 331667dfed9SAndy Shevchenko hw->len = sg_dma_len(sg); 332667dfed9SAndy Shevchenko } 333667dfed9SAndy Shevchenko 334667dfed9SAndy Shevchenko desc->ndesc = sg_len; 335667dfed9SAndy Shevchenko desc->direction = direction; 336667dfed9SAndy Shevchenko desc->status = DMA_IN_PROGRESS; 337667dfed9SAndy Shevchenko 338667dfed9SAndy Shevchenko idma64_desc_fill(idma64c, desc); 339667dfed9SAndy Shevchenko return vchan_tx_prep(&idma64c->vchan, &desc->vdesc, flags); 340667dfed9SAndy Shevchenko } 341667dfed9SAndy Shevchenko 342667dfed9SAndy Shevchenko static void idma64_issue_pending(struct dma_chan *chan) 343667dfed9SAndy Shevchenko { 344667dfed9SAndy Shevchenko struct idma64_chan *idma64c = to_idma64_chan(chan); 345667dfed9SAndy Shevchenko unsigned long flags; 346667dfed9SAndy Shevchenko 347667dfed9SAndy Shevchenko spin_lock_irqsave(&idma64c->vchan.lock, flags); 348667dfed9SAndy Shevchenko if (vchan_issue_pending(&idma64c->vchan) && !idma64c->desc) 349667dfed9SAndy Shevchenko idma64_start_transfer(idma64c); 350667dfed9SAndy Shevchenko spin_unlock_irqrestore(&idma64c->vchan.lock, flags); 351667dfed9SAndy Shevchenko } 352667dfed9SAndy Shevchenko 353667dfed9SAndy Shevchenko static size_t idma64_active_desc_size(struct idma64_chan *idma64c) 354667dfed9SAndy Shevchenko { 355667dfed9SAndy Shevchenko struct idma64_desc *desc = idma64c->desc; 356667dfed9SAndy Shevchenko struct idma64_hw_desc *hw; 357667dfed9SAndy Shevchenko size_t bytes = desc->length; 358667dfed9SAndy Shevchenko u64 llp; 359667dfed9SAndy Shevchenko u32 ctlhi; 360667dfed9SAndy Shevchenko unsigned int i = 0; 361667dfed9SAndy Shevchenko 362667dfed9SAndy Shevchenko llp = channel_readq(idma64c, LLP); 363667dfed9SAndy Shevchenko do { 364667dfed9SAndy Shevchenko hw = &desc->hw[i]; 365667dfed9SAndy Shevchenko } while ((hw->llp != llp) && (++i < desc->ndesc)); 366667dfed9SAndy Shevchenko 367667dfed9SAndy Shevchenko if (!i) 368667dfed9SAndy Shevchenko return bytes; 369667dfed9SAndy Shevchenko 370667dfed9SAndy Shevchenko do { 371667dfed9SAndy Shevchenko bytes -= desc->hw[--i].len; 372667dfed9SAndy Shevchenko } while (i); 373667dfed9SAndy Shevchenko 374667dfed9SAndy Shevchenko ctlhi = channel_readl(idma64c, CTL_HI); 375667dfed9SAndy Shevchenko return bytes - IDMA64C_CTLH_BLOCK_TS(ctlhi); 376667dfed9SAndy Shevchenko } 377667dfed9SAndy Shevchenko 378667dfed9SAndy Shevchenko static enum dma_status idma64_tx_status(struct dma_chan *chan, 379667dfed9SAndy Shevchenko dma_cookie_t cookie, struct dma_tx_state *state) 380667dfed9SAndy Shevchenko { 381667dfed9SAndy Shevchenko struct idma64_chan *idma64c = to_idma64_chan(chan); 382667dfed9SAndy Shevchenko struct virt_dma_desc *vdesc; 383667dfed9SAndy Shevchenko enum dma_status status; 384667dfed9SAndy Shevchenko size_t bytes; 385667dfed9SAndy Shevchenko unsigned long flags; 386667dfed9SAndy Shevchenko 387667dfed9SAndy Shevchenko status = dma_cookie_status(chan, cookie, state); 388667dfed9SAndy Shevchenko if (status == DMA_COMPLETE) 389667dfed9SAndy Shevchenko return status; 390667dfed9SAndy Shevchenko 391667dfed9SAndy Shevchenko spin_lock_irqsave(&idma64c->vchan.lock, flags); 392667dfed9SAndy Shevchenko vdesc = vchan_find_desc(&idma64c->vchan, cookie); 393667dfed9SAndy Shevchenko if (idma64c->desc && cookie == idma64c->desc->vdesc.tx.cookie) { 394667dfed9SAndy Shevchenko bytes = idma64_active_desc_size(idma64c); 395667dfed9SAndy Shevchenko dma_set_residue(state, bytes); 396667dfed9SAndy Shevchenko status = idma64c->desc->status; 397667dfed9SAndy Shevchenko } else if (vdesc) { 398667dfed9SAndy Shevchenko bytes = to_idma64_desc(vdesc)->length; 399667dfed9SAndy Shevchenko dma_set_residue(state, bytes); 400667dfed9SAndy Shevchenko } 401667dfed9SAndy Shevchenko spin_unlock_irqrestore(&idma64c->vchan.lock, flags); 402667dfed9SAndy Shevchenko 403667dfed9SAndy Shevchenko return status; 404667dfed9SAndy Shevchenko } 405667dfed9SAndy Shevchenko 406667dfed9SAndy Shevchenko static void convert_burst(u32 *maxburst) 407667dfed9SAndy Shevchenko { 408667dfed9SAndy Shevchenko if (*maxburst) 409667dfed9SAndy Shevchenko *maxburst = __fls(*maxburst); 410667dfed9SAndy Shevchenko else 411667dfed9SAndy Shevchenko *maxburst = 0; 412667dfed9SAndy Shevchenko } 413667dfed9SAndy Shevchenko 414667dfed9SAndy Shevchenko static int idma64_slave_config(struct dma_chan *chan, 415667dfed9SAndy Shevchenko struct dma_slave_config *config) 416667dfed9SAndy Shevchenko { 417667dfed9SAndy Shevchenko struct idma64_chan *idma64c = to_idma64_chan(chan); 418667dfed9SAndy Shevchenko 419667dfed9SAndy Shevchenko /* Check if chan will be configured for slave transfers */ 420667dfed9SAndy Shevchenko if (!is_slave_direction(config->direction)) 421667dfed9SAndy Shevchenko return -EINVAL; 422667dfed9SAndy Shevchenko 423667dfed9SAndy Shevchenko memcpy(&idma64c->config, config, sizeof(idma64c->config)); 424667dfed9SAndy Shevchenko 425667dfed9SAndy Shevchenko convert_burst(&idma64c->config.src_maxburst); 426667dfed9SAndy Shevchenko convert_burst(&idma64c->config.dst_maxburst); 427667dfed9SAndy Shevchenko 428667dfed9SAndy Shevchenko return 0; 429667dfed9SAndy Shevchenko } 430667dfed9SAndy Shevchenko 431667dfed9SAndy Shevchenko static void idma64_chan_deactivate(struct idma64_chan *idma64c) 432667dfed9SAndy Shevchenko { 433667dfed9SAndy Shevchenko unsigned short count = 100; 434667dfed9SAndy Shevchenko u32 cfglo; 435667dfed9SAndy Shevchenko 436667dfed9SAndy Shevchenko cfglo = channel_readl(idma64c, CFG_LO); 437667dfed9SAndy Shevchenko channel_writel(idma64c, CFG_LO, cfglo | IDMA64C_CFGL_CH_SUSP); 438667dfed9SAndy Shevchenko do { 439667dfed9SAndy Shevchenko udelay(1); 440667dfed9SAndy Shevchenko cfglo = channel_readl(idma64c, CFG_LO); 441667dfed9SAndy Shevchenko } while (!(cfglo & IDMA64C_CFGL_FIFO_EMPTY) && --count); 442667dfed9SAndy Shevchenko } 443667dfed9SAndy Shevchenko 444667dfed9SAndy Shevchenko static void idma64_chan_activate(struct idma64_chan *idma64c) 445667dfed9SAndy Shevchenko { 446667dfed9SAndy Shevchenko u32 cfglo; 447667dfed9SAndy Shevchenko 448667dfed9SAndy Shevchenko cfglo = channel_readl(idma64c, CFG_LO); 449667dfed9SAndy Shevchenko channel_writel(idma64c, CFG_LO, cfglo & ~IDMA64C_CFGL_CH_SUSP); 450667dfed9SAndy Shevchenko } 451667dfed9SAndy Shevchenko 452667dfed9SAndy Shevchenko static int idma64_pause(struct dma_chan *chan) 453667dfed9SAndy Shevchenko { 454667dfed9SAndy Shevchenko struct idma64_chan *idma64c = to_idma64_chan(chan); 455667dfed9SAndy Shevchenko unsigned long flags; 456667dfed9SAndy Shevchenko 457667dfed9SAndy Shevchenko spin_lock_irqsave(&idma64c->vchan.lock, flags); 458667dfed9SAndy Shevchenko if (idma64c->desc && idma64c->desc->status == DMA_IN_PROGRESS) { 459667dfed9SAndy Shevchenko idma64_chan_deactivate(idma64c); 460667dfed9SAndy Shevchenko idma64c->desc->status = DMA_PAUSED; 461667dfed9SAndy Shevchenko } 462667dfed9SAndy Shevchenko spin_unlock_irqrestore(&idma64c->vchan.lock, flags); 463667dfed9SAndy Shevchenko 464667dfed9SAndy Shevchenko return 0; 465667dfed9SAndy Shevchenko } 466667dfed9SAndy Shevchenko 467667dfed9SAndy Shevchenko static int idma64_resume(struct dma_chan *chan) 468667dfed9SAndy Shevchenko { 469667dfed9SAndy Shevchenko struct idma64_chan *idma64c = to_idma64_chan(chan); 470667dfed9SAndy Shevchenko unsigned long flags; 471667dfed9SAndy Shevchenko 472667dfed9SAndy Shevchenko spin_lock_irqsave(&idma64c->vchan.lock, flags); 473667dfed9SAndy Shevchenko if (idma64c->desc && idma64c->desc->status == DMA_PAUSED) { 474667dfed9SAndy Shevchenko idma64c->desc->status = DMA_IN_PROGRESS; 475667dfed9SAndy Shevchenko idma64_chan_activate(idma64c); 476667dfed9SAndy Shevchenko } 477667dfed9SAndy Shevchenko spin_unlock_irqrestore(&idma64c->vchan.lock, flags); 478667dfed9SAndy Shevchenko 479667dfed9SAndy Shevchenko return 0; 480667dfed9SAndy Shevchenko } 481667dfed9SAndy Shevchenko 482667dfed9SAndy Shevchenko static int idma64_terminate_all(struct dma_chan *chan) 483667dfed9SAndy Shevchenko { 484667dfed9SAndy Shevchenko struct idma64_chan *idma64c = to_idma64_chan(chan); 485667dfed9SAndy Shevchenko unsigned long flags; 486667dfed9SAndy Shevchenko LIST_HEAD(head); 487667dfed9SAndy Shevchenko 488667dfed9SAndy Shevchenko spin_lock_irqsave(&idma64c->vchan.lock, flags); 489667dfed9SAndy Shevchenko idma64_chan_deactivate(idma64c); 490667dfed9SAndy Shevchenko idma64_stop_transfer(idma64c); 491667dfed9SAndy Shevchenko if (idma64c->desc) { 492667dfed9SAndy Shevchenko idma64_vdesc_free(&idma64c->desc->vdesc); 493667dfed9SAndy Shevchenko idma64c->desc = NULL; 494667dfed9SAndy Shevchenko } 495667dfed9SAndy Shevchenko vchan_get_all_descriptors(&idma64c->vchan, &head); 496667dfed9SAndy Shevchenko spin_unlock_irqrestore(&idma64c->vchan.lock, flags); 497667dfed9SAndy Shevchenko 498667dfed9SAndy Shevchenko vchan_dma_desc_free_list(&idma64c->vchan, &head); 499667dfed9SAndy Shevchenko return 0; 500667dfed9SAndy Shevchenko } 501667dfed9SAndy Shevchenko 502667dfed9SAndy Shevchenko static int idma64_alloc_chan_resources(struct dma_chan *chan) 503667dfed9SAndy Shevchenko { 504667dfed9SAndy Shevchenko struct idma64_chan *idma64c = to_idma64_chan(chan); 505667dfed9SAndy Shevchenko 506667dfed9SAndy Shevchenko /* Create a pool of consistent memory blocks for hardware descriptors */ 507667dfed9SAndy Shevchenko idma64c->pool = dma_pool_create(dev_name(chan2dev(chan)), 508667dfed9SAndy Shevchenko chan->device->dev, 509667dfed9SAndy Shevchenko sizeof(struct idma64_lli), 8, 0); 510667dfed9SAndy Shevchenko if (!idma64c->pool) { 511667dfed9SAndy Shevchenko dev_err(chan2dev(chan), "No memory for descriptors\n"); 512667dfed9SAndy Shevchenko return -ENOMEM; 513667dfed9SAndy Shevchenko } 514667dfed9SAndy Shevchenko 515667dfed9SAndy Shevchenko return 0; 516667dfed9SAndy Shevchenko } 517667dfed9SAndy Shevchenko 518667dfed9SAndy Shevchenko static void idma64_free_chan_resources(struct dma_chan *chan) 519667dfed9SAndy Shevchenko { 520667dfed9SAndy Shevchenko struct idma64_chan *idma64c = to_idma64_chan(chan); 521667dfed9SAndy Shevchenko 522667dfed9SAndy Shevchenko vchan_free_chan_resources(to_virt_chan(chan)); 523667dfed9SAndy Shevchenko dma_pool_destroy(idma64c->pool); 524667dfed9SAndy Shevchenko idma64c->pool = NULL; 525667dfed9SAndy Shevchenko } 526667dfed9SAndy Shevchenko 527667dfed9SAndy Shevchenko /* ---------------------------------------------------------------------- */ 528667dfed9SAndy Shevchenko 529667dfed9SAndy Shevchenko #define IDMA64_BUSWIDTHS \ 530667dfed9SAndy Shevchenko BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ 531667dfed9SAndy Shevchenko BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ 532667dfed9SAndy Shevchenko BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) 533667dfed9SAndy Shevchenko 534667dfed9SAndy Shevchenko static int idma64_probe(struct idma64_chip *chip) 535667dfed9SAndy Shevchenko { 536667dfed9SAndy Shevchenko struct idma64 *idma64; 537667dfed9SAndy Shevchenko unsigned short nr_chan = IDMA64_NR_CHAN; 538667dfed9SAndy Shevchenko unsigned short i; 539667dfed9SAndy Shevchenko int ret; 540667dfed9SAndy Shevchenko 541667dfed9SAndy Shevchenko idma64 = devm_kzalloc(chip->dev, sizeof(*idma64), GFP_KERNEL); 542667dfed9SAndy Shevchenko if (!idma64) 543667dfed9SAndy Shevchenko return -ENOMEM; 544667dfed9SAndy Shevchenko 545667dfed9SAndy Shevchenko idma64->regs = chip->regs; 546667dfed9SAndy Shevchenko chip->idma64 = idma64; 547667dfed9SAndy Shevchenko 548667dfed9SAndy Shevchenko idma64->chan = devm_kcalloc(chip->dev, nr_chan, sizeof(*idma64->chan), 549667dfed9SAndy Shevchenko GFP_KERNEL); 550667dfed9SAndy Shevchenko if (!idma64->chan) 551667dfed9SAndy Shevchenko return -ENOMEM; 552667dfed9SAndy Shevchenko 553667dfed9SAndy Shevchenko idma64->all_chan_mask = (1 << nr_chan) - 1; 554667dfed9SAndy Shevchenko 555667dfed9SAndy Shevchenko /* Turn off iDMA controller */ 556667dfed9SAndy Shevchenko idma64_off(idma64); 557667dfed9SAndy Shevchenko 558667dfed9SAndy Shevchenko ret = devm_request_irq(chip->dev, chip->irq, idma64_irq, IRQF_SHARED, 559667dfed9SAndy Shevchenko dev_name(chip->dev), idma64); 560667dfed9SAndy Shevchenko if (ret) 561667dfed9SAndy Shevchenko return ret; 562667dfed9SAndy Shevchenko 563667dfed9SAndy Shevchenko INIT_LIST_HEAD(&idma64->dma.channels); 564667dfed9SAndy Shevchenko for (i = 0; i < nr_chan; i++) { 565667dfed9SAndy Shevchenko struct idma64_chan *idma64c = &idma64->chan[i]; 566667dfed9SAndy Shevchenko 567667dfed9SAndy Shevchenko idma64c->vchan.desc_free = idma64_vdesc_free; 568667dfed9SAndy Shevchenko vchan_init(&idma64c->vchan, &idma64->dma); 569667dfed9SAndy Shevchenko 570667dfed9SAndy Shevchenko idma64c->regs = idma64->regs + i * IDMA64_CH_LENGTH; 571667dfed9SAndy Shevchenko idma64c->mask = BIT(i); 572667dfed9SAndy Shevchenko } 573667dfed9SAndy Shevchenko 574667dfed9SAndy Shevchenko dma_cap_set(DMA_SLAVE, idma64->dma.cap_mask); 575667dfed9SAndy Shevchenko dma_cap_set(DMA_PRIVATE, idma64->dma.cap_mask); 576667dfed9SAndy Shevchenko 577667dfed9SAndy Shevchenko idma64->dma.device_alloc_chan_resources = idma64_alloc_chan_resources; 578667dfed9SAndy Shevchenko idma64->dma.device_free_chan_resources = idma64_free_chan_resources; 579667dfed9SAndy Shevchenko 580667dfed9SAndy Shevchenko idma64->dma.device_prep_slave_sg = idma64_prep_slave_sg; 581667dfed9SAndy Shevchenko 582667dfed9SAndy Shevchenko idma64->dma.device_issue_pending = idma64_issue_pending; 583667dfed9SAndy Shevchenko idma64->dma.device_tx_status = idma64_tx_status; 584667dfed9SAndy Shevchenko 585667dfed9SAndy Shevchenko idma64->dma.device_config = idma64_slave_config; 586667dfed9SAndy Shevchenko idma64->dma.device_pause = idma64_pause; 587667dfed9SAndy Shevchenko idma64->dma.device_resume = idma64_resume; 588667dfed9SAndy Shevchenko idma64->dma.device_terminate_all = idma64_terminate_all; 589667dfed9SAndy Shevchenko 590667dfed9SAndy Shevchenko idma64->dma.src_addr_widths = IDMA64_BUSWIDTHS; 591667dfed9SAndy Shevchenko idma64->dma.dst_addr_widths = IDMA64_BUSWIDTHS; 592667dfed9SAndy Shevchenko idma64->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); 593667dfed9SAndy Shevchenko idma64->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; 594667dfed9SAndy Shevchenko 595667dfed9SAndy Shevchenko idma64->dma.dev = chip->dev; 596667dfed9SAndy Shevchenko 597667dfed9SAndy Shevchenko ret = dma_async_device_register(&idma64->dma); 598667dfed9SAndy Shevchenko if (ret) 599667dfed9SAndy Shevchenko return ret; 600667dfed9SAndy Shevchenko 601667dfed9SAndy Shevchenko dev_info(chip->dev, "Found Intel integrated DMA 64-bit\n"); 602667dfed9SAndy Shevchenko return 0; 603667dfed9SAndy Shevchenko } 604667dfed9SAndy Shevchenko 605667dfed9SAndy Shevchenko static int idma64_remove(struct idma64_chip *chip) 606667dfed9SAndy Shevchenko { 607667dfed9SAndy Shevchenko struct idma64 *idma64 = chip->idma64; 608667dfed9SAndy Shevchenko unsigned short i; 609667dfed9SAndy Shevchenko 610667dfed9SAndy Shevchenko dma_async_device_unregister(&idma64->dma); 611667dfed9SAndy Shevchenko 612667dfed9SAndy Shevchenko /* 613667dfed9SAndy Shevchenko * Explicitly call devm_request_irq() to avoid the side effects with 614667dfed9SAndy Shevchenko * the scheduled tasklets. 615667dfed9SAndy Shevchenko */ 616667dfed9SAndy Shevchenko devm_free_irq(chip->dev, chip->irq, idma64); 617667dfed9SAndy Shevchenko 618667dfed9SAndy Shevchenko for (i = 0; i < idma64->dma.chancnt; i++) { 619667dfed9SAndy Shevchenko struct idma64_chan *idma64c = &idma64->chan[i]; 620667dfed9SAndy Shevchenko 621667dfed9SAndy Shevchenko tasklet_kill(&idma64c->vchan.task); 622667dfed9SAndy Shevchenko } 623667dfed9SAndy Shevchenko 624667dfed9SAndy Shevchenko return 0; 625667dfed9SAndy Shevchenko } 626667dfed9SAndy Shevchenko 627667dfed9SAndy Shevchenko /* ---------------------------------------------------------------------- */ 628667dfed9SAndy Shevchenko 629667dfed9SAndy Shevchenko static int idma64_platform_probe(struct platform_device *pdev) 630667dfed9SAndy Shevchenko { 631667dfed9SAndy Shevchenko struct idma64_chip *chip; 632667dfed9SAndy Shevchenko struct device *dev = &pdev->dev; 633667dfed9SAndy Shevchenko struct resource *mem; 634667dfed9SAndy Shevchenko int ret; 635667dfed9SAndy Shevchenko 636667dfed9SAndy Shevchenko chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 637667dfed9SAndy Shevchenko if (!chip) 638667dfed9SAndy Shevchenko return -ENOMEM; 639667dfed9SAndy Shevchenko 640667dfed9SAndy Shevchenko chip->irq = platform_get_irq(pdev, 0); 641667dfed9SAndy Shevchenko if (chip->irq < 0) 642667dfed9SAndy Shevchenko return chip->irq; 643667dfed9SAndy Shevchenko 644667dfed9SAndy Shevchenko mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 645667dfed9SAndy Shevchenko chip->regs = devm_ioremap_resource(dev, mem); 646667dfed9SAndy Shevchenko if (IS_ERR(chip->regs)) 647667dfed9SAndy Shevchenko return PTR_ERR(chip->regs); 648667dfed9SAndy Shevchenko 649667dfed9SAndy Shevchenko ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 650667dfed9SAndy Shevchenko if (ret) 651667dfed9SAndy Shevchenko return ret; 652667dfed9SAndy Shevchenko 653667dfed9SAndy Shevchenko chip->dev = dev; 654667dfed9SAndy Shevchenko 655667dfed9SAndy Shevchenko ret = idma64_probe(chip); 656667dfed9SAndy Shevchenko if (ret) 657667dfed9SAndy Shevchenko return ret; 658667dfed9SAndy Shevchenko 659667dfed9SAndy Shevchenko platform_set_drvdata(pdev, chip); 660667dfed9SAndy Shevchenko return 0; 661667dfed9SAndy Shevchenko } 662667dfed9SAndy Shevchenko 663667dfed9SAndy Shevchenko static int idma64_platform_remove(struct platform_device *pdev) 664667dfed9SAndy Shevchenko { 665667dfed9SAndy Shevchenko struct idma64_chip *chip = platform_get_drvdata(pdev); 666667dfed9SAndy Shevchenko 667667dfed9SAndy Shevchenko return idma64_remove(chip); 668667dfed9SAndy Shevchenko } 669667dfed9SAndy Shevchenko 670667dfed9SAndy Shevchenko #ifdef CONFIG_PM_SLEEP 671667dfed9SAndy Shevchenko 672667dfed9SAndy Shevchenko static int idma64_pm_suspend(struct device *dev) 673667dfed9SAndy Shevchenko { 674667dfed9SAndy Shevchenko struct platform_device *pdev = to_platform_device(dev); 675667dfed9SAndy Shevchenko struct idma64_chip *chip = platform_get_drvdata(pdev); 676667dfed9SAndy Shevchenko 677667dfed9SAndy Shevchenko idma64_off(chip->idma64); 678667dfed9SAndy Shevchenko return 0; 679667dfed9SAndy Shevchenko } 680667dfed9SAndy Shevchenko 681667dfed9SAndy Shevchenko static int idma64_pm_resume(struct device *dev) 682667dfed9SAndy Shevchenko { 683667dfed9SAndy Shevchenko struct platform_device *pdev = to_platform_device(dev); 684667dfed9SAndy Shevchenko struct idma64_chip *chip = platform_get_drvdata(pdev); 685667dfed9SAndy Shevchenko 686667dfed9SAndy Shevchenko idma64_on(chip->idma64); 687667dfed9SAndy Shevchenko return 0; 688667dfed9SAndy Shevchenko } 689667dfed9SAndy Shevchenko 690667dfed9SAndy Shevchenko #endif /* CONFIG_PM_SLEEP */ 691667dfed9SAndy Shevchenko 692667dfed9SAndy Shevchenko static const struct dev_pm_ops idma64_dev_pm_ops = { 693667dfed9SAndy Shevchenko SET_SYSTEM_SLEEP_PM_OPS(idma64_pm_suspend, idma64_pm_resume) 694667dfed9SAndy Shevchenko }; 695667dfed9SAndy Shevchenko 696667dfed9SAndy Shevchenko static struct platform_driver idma64_platform_driver = { 697667dfed9SAndy Shevchenko .probe = idma64_platform_probe, 698667dfed9SAndy Shevchenko .remove = idma64_platform_remove, 699667dfed9SAndy Shevchenko .driver = { 700667dfed9SAndy Shevchenko .name = DRV_NAME, 701667dfed9SAndy Shevchenko .pm = &idma64_dev_pm_ops, 702667dfed9SAndy Shevchenko }, 703667dfed9SAndy Shevchenko }; 704667dfed9SAndy Shevchenko 705667dfed9SAndy Shevchenko module_platform_driver(idma64_platform_driver); 706667dfed9SAndy Shevchenko 707667dfed9SAndy Shevchenko MODULE_LICENSE("GPL v2"); 708667dfed9SAndy Shevchenko MODULE_DESCRIPTION("iDMA64 core driver"); 709667dfed9SAndy Shevchenko MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>"); 710667dfed9SAndy Shevchenko MODULE_ALIAS("platform:" DRV_NAME); 711