1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2667dfed9SAndy Shevchenko /* 3667dfed9SAndy Shevchenko * Core driver for the Intel integrated DMA 64-bit 4667dfed9SAndy Shevchenko * 5667dfed9SAndy Shevchenko * Copyright (C) 2015 Intel Corporation 6667dfed9SAndy Shevchenko * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com> 7667dfed9SAndy Shevchenko */ 8667dfed9SAndy Shevchenko 9667dfed9SAndy Shevchenko #include <linux/bitops.h> 10667dfed9SAndy Shevchenko #include <linux/delay.h> 11667dfed9SAndy Shevchenko #include <linux/dmaengine.h> 12667dfed9SAndy Shevchenko #include <linux/dma-mapping.h> 13667dfed9SAndy Shevchenko #include <linux/dmapool.h> 14667dfed9SAndy Shevchenko #include <linux/init.h> 15667dfed9SAndy Shevchenko #include <linux/module.h> 16667dfed9SAndy Shevchenko #include <linux/platform_device.h> 17667dfed9SAndy Shevchenko #include <linux/slab.h> 18667dfed9SAndy Shevchenko 19ffcfc20fSAndy Shevchenko #include <linux/dma/idma64.h> 20667dfed9SAndy Shevchenko 21ffcfc20fSAndy Shevchenko #include "idma64.h" 22667dfed9SAndy Shevchenko 23667dfed9SAndy Shevchenko /* For now we support only two channels */ 24667dfed9SAndy Shevchenko #define IDMA64_NR_CHAN 2 25667dfed9SAndy Shevchenko 26667dfed9SAndy Shevchenko /* ---------------------------------------------------------------------- */ 27667dfed9SAndy Shevchenko 28667dfed9SAndy Shevchenko static struct device *chan2dev(struct dma_chan *chan) 29667dfed9SAndy Shevchenko { 30667dfed9SAndy Shevchenko return &chan->dev->device; 31667dfed9SAndy Shevchenko } 32667dfed9SAndy Shevchenko 33667dfed9SAndy Shevchenko /* ---------------------------------------------------------------------- */ 34667dfed9SAndy Shevchenko 35667dfed9SAndy Shevchenko static void idma64_off(struct idma64 *idma64) 36667dfed9SAndy Shevchenko { 37667dfed9SAndy Shevchenko unsigned short count = 100; 38667dfed9SAndy Shevchenko 39667dfed9SAndy Shevchenko dma_writel(idma64, CFG, 0); 40667dfed9SAndy Shevchenko 41667dfed9SAndy Shevchenko channel_clear_bit(idma64, MASK(XFER), idma64->all_chan_mask); 42667dfed9SAndy Shevchenko channel_clear_bit(idma64, MASK(BLOCK), idma64->all_chan_mask); 43667dfed9SAndy Shevchenko channel_clear_bit(idma64, MASK(SRC_TRAN), idma64->all_chan_mask); 44667dfed9SAndy Shevchenko channel_clear_bit(idma64, MASK(DST_TRAN), idma64->all_chan_mask); 45667dfed9SAndy Shevchenko channel_clear_bit(idma64, MASK(ERROR), idma64->all_chan_mask); 46667dfed9SAndy Shevchenko 47667dfed9SAndy Shevchenko do { 48667dfed9SAndy Shevchenko cpu_relax(); 49667dfed9SAndy Shevchenko } while (dma_readl(idma64, CFG) & IDMA64_CFG_DMA_EN && --count); 50667dfed9SAndy Shevchenko } 51667dfed9SAndy Shevchenko 52667dfed9SAndy Shevchenko static void idma64_on(struct idma64 *idma64) 53667dfed9SAndy Shevchenko { 54667dfed9SAndy Shevchenko dma_writel(idma64, CFG, IDMA64_CFG_DMA_EN); 55667dfed9SAndy Shevchenko } 56667dfed9SAndy Shevchenko 57667dfed9SAndy Shevchenko /* ---------------------------------------------------------------------- */ 58667dfed9SAndy Shevchenko 59667dfed9SAndy Shevchenko static void idma64_chan_init(struct idma64 *idma64, struct idma64_chan *idma64c) 60667dfed9SAndy Shevchenko { 61667dfed9SAndy Shevchenko u32 cfghi = IDMA64C_CFGH_SRC_PER(1) | IDMA64C_CFGH_DST_PER(0); 62667dfed9SAndy Shevchenko u32 cfglo = 0; 63667dfed9SAndy Shevchenko 64667dfed9SAndy Shevchenko /* Set default burst alignment */ 65667dfed9SAndy Shevchenko cfglo |= IDMA64C_CFGL_DST_BURST_ALIGN | IDMA64C_CFGL_SRC_BURST_ALIGN; 66667dfed9SAndy Shevchenko 67667dfed9SAndy Shevchenko channel_writel(idma64c, CFG_LO, cfglo); 68667dfed9SAndy Shevchenko channel_writel(idma64c, CFG_HI, cfghi); 69667dfed9SAndy Shevchenko 70667dfed9SAndy Shevchenko /* Enable interrupts */ 71667dfed9SAndy Shevchenko channel_set_bit(idma64, MASK(XFER), idma64c->mask); 72667dfed9SAndy Shevchenko channel_set_bit(idma64, MASK(ERROR), idma64c->mask); 73667dfed9SAndy Shevchenko 74667dfed9SAndy Shevchenko /* 75667dfed9SAndy Shevchenko * Enforce the controller to be turned on. 76667dfed9SAndy Shevchenko * 77667dfed9SAndy Shevchenko * The iDMA is turned off in ->probe() and looses context during system 78667dfed9SAndy Shevchenko * suspend / resume cycle. That's why we have to enable it each time we 79667dfed9SAndy Shevchenko * use it. 80667dfed9SAndy Shevchenko */ 81667dfed9SAndy Shevchenko idma64_on(idma64); 82667dfed9SAndy Shevchenko } 83667dfed9SAndy Shevchenko 84667dfed9SAndy Shevchenko static void idma64_chan_stop(struct idma64 *idma64, struct idma64_chan *idma64c) 85667dfed9SAndy Shevchenko { 86667dfed9SAndy Shevchenko channel_clear_bit(idma64, CH_EN, idma64c->mask); 87667dfed9SAndy Shevchenko } 88667dfed9SAndy Shevchenko 89667dfed9SAndy Shevchenko static void idma64_chan_start(struct idma64 *idma64, struct idma64_chan *idma64c) 90667dfed9SAndy Shevchenko { 91667dfed9SAndy Shevchenko struct idma64_desc *desc = idma64c->desc; 92667dfed9SAndy Shevchenko struct idma64_hw_desc *hw = &desc->hw[0]; 93667dfed9SAndy Shevchenko 94667dfed9SAndy Shevchenko channel_writeq(idma64c, SAR, 0); 95667dfed9SAndy Shevchenko channel_writeq(idma64c, DAR, 0); 96667dfed9SAndy Shevchenko 97667dfed9SAndy Shevchenko channel_writel(idma64c, CTL_HI, IDMA64C_CTLH_BLOCK_TS(~0UL)); 98667dfed9SAndy Shevchenko channel_writel(idma64c, CTL_LO, IDMA64C_CTLL_LLP_S_EN | IDMA64C_CTLL_LLP_D_EN); 99667dfed9SAndy Shevchenko 100667dfed9SAndy Shevchenko channel_writeq(idma64c, LLP, hw->llp); 101667dfed9SAndy Shevchenko 102667dfed9SAndy Shevchenko channel_set_bit(idma64, CH_EN, idma64c->mask); 103667dfed9SAndy Shevchenko } 104667dfed9SAndy Shevchenko 105667dfed9SAndy Shevchenko static void idma64_stop_transfer(struct idma64_chan *idma64c) 106667dfed9SAndy Shevchenko { 107667dfed9SAndy Shevchenko struct idma64 *idma64 = to_idma64(idma64c->vchan.chan.device); 108667dfed9SAndy Shevchenko 109667dfed9SAndy Shevchenko idma64_chan_stop(idma64, idma64c); 110667dfed9SAndy Shevchenko } 111667dfed9SAndy Shevchenko 112667dfed9SAndy Shevchenko static void idma64_start_transfer(struct idma64_chan *idma64c) 113667dfed9SAndy Shevchenko { 114667dfed9SAndy Shevchenko struct idma64 *idma64 = to_idma64(idma64c->vchan.chan.device); 115667dfed9SAndy Shevchenko struct virt_dma_desc *vdesc; 116667dfed9SAndy Shevchenko 117667dfed9SAndy Shevchenko /* Get the next descriptor */ 118667dfed9SAndy Shevchenko vdesc = vchan_next_desc(&idma64c->vchan); 119667dfed9SAndy Shevchenko if (!vdesc) { 120667dfed9SAndy Shevchenko idma64c->desc = NULL; 121667dfed9SAndy Shevchenko return; 122667dfed9SAndy Shevchenko } 123667dfed9SAndy Shevchenko 124667dfed9SAndy Shevchenko list_del(&vdesc->node); 125667dfed9SAndy Shevchenko idma64c->desc = to_idma64_desc(vdesc); 126667dfed9SAndy Shevchenko 127667dfed9SAndy Shevchenko /* Configure the channel */ 128667dfed9SAndy Shevchenko idma64_chan_init(idma64, idma64c); 129667dfed9SAndy Shevchenko 130667dfed9SAndy Shevchenko /* Start the channel with a new descriptor */ 131667dfed9SAndy Shevchenko idma64_chan_start(idma64, idma64c); 132667dfed9SAndy Shevchenko } 133667dfed9SAndy Shevchenko 134667dfed9SAndy Shevchenko /* ---------------------------------------------------------------------- */ 135667dfed9SAndy Shevchenko 136667dfed9SAndy Shevchenko static void idma64_chan_irq(struct idma64 *idma64, unsigned short c, 137667dfed9SAndy Shevchenko u32 status_err, u32 status_xfer) 138667dfed9SAndy Shevchenko { 139667dfed9SAndy Shevchenko struct idma64_chan *idma64c = &idma64->chan[c]; 140e922bbf3SAman Kumar struct dma_chan_percpu *stat; 141667dfed9SAndy Shevchenko struct idma64_desc *desc; 142667dfed9SAndy Shevchenko 143e922bbf3SAman Kumar stat = this_cpu_ptr(idma64c->vchan.chan.local); 144e922bbf3SAman Kumar 1457645d26fSZhaoxiong Yuan spin_lock(&idma64c->vchan.lock); 146667dfed9SAndy Shevchenko desc = idma64c->desc; 147667dfed9SAndy Shevchenko if (desc) { 148667dfed9SAndy Shevchenko if (status_err & (1 << c)) { 149667dfed9SAndy Shevchenko dma_writel(idma64, CLEAR(ERROR), idma64c->mask); 150667dfed9SAndy Shevchenko desc->status = DMA_ERROR; 151667dfed9SAndy Shevchenko } else if (status_xfer & (1 << c)) { 152667dfed9SAndy Shevchenko dma_writel(idma64, CLEAR(XFER), idma64c->mask); 153667dfed9SAndy Shevchenko desc->status = DMA_COMPLETE; 154667dfed9SAndy Shevchenko vchan_cookie_complete(&desc->vdesc); 155e922bbf3SAman Kumar stat->bytes_transferred += desc->length; 156667dfed9SAndy Shevchenko idma64_start_transfer(idma64c); 157667dfed9SAndy Shevchenko } 158667dfed9SAndy Shevchenko 159667dfed9SAndy Shevchenko /* idma64_start_transfer() updates idma64c->desc */ 160667dfed9SAndy Shevchenko if (idma64c->desc == NULL || desc->status == DMA_ERROR) 161667dfed9SAndy Shevchenko idma64_stop_transfer(idma64c); 162667dfed9SAndy Shevchenko } 1637645d26fSZhaoxiong Yuan spin_unlock(&idma64c->vchan.lock); 164667dfed9SAndy Shevchenko } 165667dfed9SAndy Shevchenko 166667dfed9SAndy Shevchenko static irqreturn_t idma64_irq(int irq, void *dev) 167667dfed9SAndy Shevchenko { 168667dfed9SAndy Shevchenko struct idma64 *idma64 = dev; 169667dfed9SAndy Shevchenko u32 status = dma_readl(idma64, STATUS_INT); 170667dfed9SAndy Shevchenko u32 status_xfer; 171667dfed9SAndy Shevchenko u32 status_err; 172667dfed9SAndy Shevchenko unsigned short i; 173667dfed9SAndy Shevchenko 1744b80c026SAndy Shevchenko /* Since IRQ may be shared, check if DMA controller is powered on */ 1754b80c026SAndy Shevchenko if (status == GENMASK(31, 0)) 1764b80c026SAndy Shevchenko return IRQ_NONE; 1774b80c026SAndy Shevchenko 178667dfed9SAndy Shevchenko dev_vdbg(idma64->dma.dev, "%s: status=%#x\n", __func__, status); 179667dfed9SAndy Shevchenko 180667dfed9SAndy Shevchenko /* Check if we have any interrupt from the DMA controller */ 181667dfed9SAndy Shevchenko if (!status) 182667dfed9SAndy Shevchenko return IRQ_NONE; 183667dfed9SAndy Shevchenko 184667dfed9SAndy Shevchenko status_xfer = dma_readl(idma64, RAW(XFER)); 185667dfed9SAndy Shevchenko status_err = dma_readl(idma64, RAW(ERROR)); 186667dfed9SAndy Shevchenko 187667dfed9SAndy Shevchenko for (i = 0; i < idma64->dma.chancnt; i++) 188667dfed9SAndy Shevchenko idma64_chan_irq(idma64, i, status_err, status_xfer); 189667dfed9SAndy Shevchenko 190667dfed9SAndy Shevchenko return IRQ_HANDLED; 191667dfed9SAndy Shevchenko } 192667dfed9SAndy Shevchenko 193667dfed9SAndy Shevchenko /* ---------------------------------------------------------------------- */ 194667dfed9SAndy Shevchenko 195667dfed9SAndy Shevchenko static struct idma64_desc *idma64_alloc_desc(unsigned int ndesc) 196667dfed9SAndy Shevchenko { 197667dfed9SAndy Shevchenko struct idma64_desc *desc; 198667dfed9SAndy Shevchenko 199667dfed9SAndy Shevchenko desc = kzalloc(sizeof(*desc), GFP_NOWAIT); 200667dfed9SAndy Shevchenko if (!desc) 201667dfed9SAndy Shevchenko return NULL; 202667dfed9SAndy Shevchenko 203667dfed9SAndy Shevchenko desc->hw = kcalloc(ndesc, sizeof(*desc->hw), GFP_NOWAIT); 204667dfed9SAndy Shevchenko if (!desc->hw) { 205667dfed9SAndy Shevchenko kfree(desc); 206667dfed9SAndy Shevchenko return NULL; 207667dfed9SAndy Shevchenko } 208667dfed9SAndy Shevchenko 209667dfed9SAndy Shevchenko return desc; 210667dfed9SAndy Shevchenko } 211667dfed9SAndy Shevchenko 212667dfed9SAndy Shevchenko static void idma64_desc_free(struct idma64_chan *idma64c, 213667dfed9SAndy Shevchenko struct idma64_desc *desc) 214667dfed9SAndy Shevchenko { 215667dfed9SAndy Shevchenko struct idma64_hw_desc *hw; 216667dfed9SAndy Shevchenko 217667dfed9SAndy Shevchenko if (desc->ndesc) { 218667dfed9SAndy Shevchenko unsigned int i = desc->ndesc; 219667dfed9SAndy Shevchenko 220667dfed9SAndy Shevchenko do { 221667dfed9SAndy Shevchenko hw = &desc->hw[--i]; 222667dfed9SAndy Shevchenko dma_pool_free(idma64c->pool, hw->lli, hw->llp); 223667dfed9SAndy Shevchenko } while (i); 224667dfed9SAndy Shevchenko } 225667dfed9SAndy Shevchenko 226667dfed9SAndy Shevchenko kfree(desc->hw); 227667dfed9SAndy Shevchenko kfree(desc); 228667dfed9SAndy Shevchenko } 229667dfed9SAndy Shevchenko 230667dfed9SAndy Shevchenko static void idma64_vdesc_free(struct virt_dma_desc *vdesc) 231667dfed9SAndy Shevchenko { 232667dfed9SAndy Shevchenko struct idma64_chan *idma64c = to_idma64_chan(vdesc->tx.chan); 233667dfed9SAndy Shevchenko 234667dfed9SAndy Shevchenko idma64_desc_free(idma64c, to_idma64_desc(vdesc)); 235667dfed9SAndy Shevchenko } 236667dfed9SAndy Shevchenko 237ac029794SAndy Shevchenko static void idma64_hw_desc_fill(struct idma64_hw_desc *hw, 238667dfed9SAndy Shevchenko struct dma_slave_config *config, 239667dfed9SAndy Shevchenko enum dma_transfer_direction direction, u64 llp) 240667dfed9SAndy Shevchenko { 241667dfed9SAndy Shevchenko struct idma64_lli *lli = hw->lli; 242667dfed9SAndy Shevchenko u64 sar, dar; 243667dfed9SAndy Shevchenko u32 ctlhi = IDMA64C_CTLH_BLOCK_TS(hw->len); 244667dfed9SAndy Shevchenko u32 ctllo = IDMA64C_CTLL_LLP_S_EN | IDMA64C_CTLL_LLP_D_EN; 245667dfed9SAndy Shevchenko u32 src_width, dst_width; 246667dfed9SAndy Shevchenko 247667dfed9SAndy Shevchenko if (direction == DMA_MEM_TO_DEV) { 248667dfed9SAndy Shevchenko sar = hw->phys; 249667dfed9SAndy Shevchenko dar = config->dst_addr; 250667dfed9SAndy Shevchenko ctllo |= IDMA64C_CTLL_DST_FIX | IDMA64C_CTLL_SRC_INC | 251667dfed9SAndy Shevchenko IDMA64C_CTLL_FC_M2P; 25222b74406SAndy Shevchenko src_width = __ffs(sar | hw->len | 4); 25387b04596SAndy Shevchenko dst_width = __ffs(config->dst_addr_width); 254667dfed9SAndy Shevchenko } else { /* DMA_DEV_TO_MEM */ 255667dfed9SAndy Shevchenko sar = config->src_addr; 256667dfed9SAndy Shevchenko dar = hw->phys; 257667dfed9SAndy Shevchenko ctllo |= IDMA64C_CTLL_DST_INC | IDMA64C_CTLL_SRC_FIX | 258667dfed9SAndy Shevchenko IDMA64C_CTLL_FC_P2M; 25987b04596SAndy Shevchenko src_width = __ffs(config->src_addr_width); 26022b74406SAndy Shevchenko dst_width = __ffs(dar | hw->len | 4); 261667dfed9SAndy Shevchenko } 262667dfed9SAndy Shevchenko 263667dfed9SAndy Shevchenko lli->sar = sar; 264667dfed9SAndy Shevchenko lli->dar = dar; 265667dfed9SAndy Shevchenko 266667dfed9SAndy Shevchenko lli->ctlhi = ctlhi; 267667dfed9SAndy Shevchenko lli->ctllo = ctllo | 268667dfed9SAndy Shevchenko IDMA64C_CTLL_SRC_MSIZE(config->src_maxburst) | 269667dfed9SAndy Shevchenko IDMA64C_CTLL_DST_MSIZE(config->dst_maxburst) | 270667dfed9SAndy Shevchenko IDMA64C_CTLL_DST_WIDTH(dst_width) | 271667dfed9SAndy Shevchenko IDMA64C_CTLL_SRC_WIDTH(src_width); 272667dfed9SAndy Shevchenko 273667dfed9SAndy Shevchenko lli->llp = llp; 274667dfed9SAndy Shevchenko } 275667dfed9SAndy Shevchenko 276667dfed9SAndy Shevchenko static void idma64_desc_fill(struct idma64_chan *idma64c, 277667dfed9SAndy Shevchenko struct idma64_desc *desc) 278667dfed9SAndy Shevchenko { 279667dfed9SAndy Shevchenko struct dma_slave_config *config = &idma64c->config; 280390c49f7SAndy Shevchenko unsigned int i = desc->ndesc; 281390c49f7SAndy Shevchenko struct idma64_hw_desc *hw = &desc->hw[i - 1]; 282667dfed9SAndy Shevchenko struct idma64_lli *lli = hw->lli; 283667dfed9SAndy Shevchenko u64 llp = 0; 284667dfed9SAndy Shevchenko 285667dfed9SAndy Shevchenko /* Fill the hardware descriptors and link them to a list */ 286667dfed9SAndy Shevchenko do { 287667dfed9SAndy Shevchenko hw = &desc->hw[--i]; 288ac029794SAndy Shevchenko idma64_hw_desc_fill(hw, config, desc->direction, llp); 289ac029794SAndy Shevchenko llp = hw->llp; 290667dfed9SAndy Shevchenko desc->length += hw->len; 291667dfed9SAndy Shevchenko } while (i); 292667dfed9SAndy Shevchenko 293390c49f7SAndy Shevchenko /* Trigger an interrupt after the last block is transfered */ 294667dfed9SAndy Shevchenko lli->ctllo |= IDMA64C_CTLL_INT_EN; 295a2826e66SAndy Shevchenko 296a2826e66SAndy Shevchenko /* Disable LLP transfer in the last block */ 297a2826e66SAndy Shevchenko lli->ctllo &= ~(IDMA64C_CTLL_LLP_S_EN | IDMA64C_CTLL_LLP_D_EN); 298667dfed9SAndy Shevchenko } 299667dfed9SAndy Shevchenko 300667dfed9SAndy Shevchenko static struct dma_async_tx_descriptor *idma64_prep_slave_sg( 301667dfed9SAndy Shevchenko struct dma_chan *chan, struct scatterlist *sgl, 302667dfed9SAndy Shevchenko unsigned int sg_len, enum dma_transfer_direction direction, 303667dfed9SAndy Shevchenko unsigned long flags, void *context) 304667dfed9SAndy Shevchenko { 305667dfed9SAndy Shevchenko struct idma64_chan *idma64c = to_idma64_chan(chan); 306667dfed9SAndy Shevchenko struct idma64_desc *desc; 307667dfed9SAndy Shevchenko struct scatterlist *sg; 308667dfed9SAndy Shevchenko unsigned int i; 309667dfed9SAndy Shevchenko 310667dfed9SAndy Shevchenko desc = idma64_alloc_desc(sg_len); 311667dfed9SAndy Shevchenko if (!desc) 312667dfed9SAndy Shevchenko return NULL; 313667dfed9SAndy Shevchenko 314667dfed9SAndy Shevchenko for_each_sg(sgl, sg, sg_len, i) { 315667dfed9SAndy Shevchenko struct idma64_hw_desc *hw = &desc->hw[i]; 316667dfed9SAndy Shevchenko 317667dfed9SAndy Shevchenko /* Allocate DMA capable memory for hardware descriptor */ 318667dfed9SAndy Shevchenko hw->lli = dma_pool_alloc(idma64c->pool, GFP_NOWAIT, &hw->llp); 319667dfed9SAndy Shevchenko if (!hw->lli) { 320667dfed9SAndy Shevchenko desc->ndesc = i; 321667dfed9SAndy Shevchenko idma64_desc_free(idma64c, desc); 322667dfed9SAndy Shevchenko return NULL; 323667dfed9SAndy Shevchenko } 324667dfed9SAndy Shevchenko 325667dfed9SAndy Shevchenko hw->phys = sg_dma_address(sg); 326667dfed9SAndy Shevchenko hw->len = sg_dma_len(sg); 327667dfed9SAndy Shevchenko } 328667dfed9SAndy Shevchenko 329667dfed9SAndy Shevchenko desc->ndesc = sg_len; 330667dfed9SAndy Shevchenko desc->direction = direction; 331667dfed9SAndy Shevchenko desc->status = DMA_IN_PROGRESS; 332667dfed9SAndy Shevchenko 333667dfed9SAndy Shevchenko idma64_desc_fill(idma64c, desc); 334667dfed9SAndy Shevchenko return vchan_tx_prep(&idma64c->vchan, &desc->vdesc, flags); 335667dfed9SAndy Shevchenko } 336667dfed9SAndy Shevchenko 337667dfed9SAndy Shevchenko static void idma64_issue_pending(struct dma_chan *chan) 338667dfed9SAndy Shevchenko { 339667dfed9SAndy Shevchenko struct idma64_chan *idma64c = to_idma64_chan(chan); 340667dfed9SAndy Shevchenko unsigned long flags; 341667dfed9SAndy Shevchenko 342667dfed9SAndy Shevchenko spin_lock_irqsave(&idma64c->vchan.lock, flags); 343667dfed9SAndy Shevchenko if (vchan_issue_pending(&idma64c->vchan) && !idma64c->desc) 344667dfed9SAndy Shevchenko idma64_start_transfer(idma64c); 345667dfed9SAndy Shevchenko spin_unlock_irqrestore(&idma64c->vchan.lock, flags); 346667dfed9SAndy Shevchenko } 347667dfed9SAndy Shevchenko 348667dfed9SAndy Shevchenko static size_t idma64_active_desc_size(struct idma64_chan *idma64c) 349667dfed9SAndy Shevchenko { 350667dfed9SAndy Shevchenko struct idma64_desc *desc = idma64c->desc; 351667dfed9SAndy Shevchenko struct idma64_hw_desc *hw; 352667dfed9SAndy Shevchenko size_t bytes = desc->length; 3530b23a1ecSAndy Shevchenko u64 llp = channel_readq(idma64c, LLP); 3540b23a1ecSAndy Shevchenko u32 ctlhi = channel_readl(idma64c, CTL_HI); 355667dfed9SAndy Shevchenko unsigned int i = 0; 356667dfed9SAndy Shevchenko 357667dfed9SAndy Shevchenko do { 358667dfed9SAndy Shevchenko hw = &desc->hw[i]; 3590b23a1ecSAndy Shevchenko if (hw->llp == llp) 3600b23a1ecSAndy Shevchenko break; 3610b23a1ecSAndy Shevchenko bytes -= hw->len; 3620b23a1ecSAndy Shevchenko } while (++i < desc->ndesc); 363667dfed9SAndy Shevchenko 364667dfed9SAndy Shevchenko if (!i) 365667dfed9SAndy Shevchenko return bytes; 366667dfed9SAndy Shevchenko 3670b23a1ecSAndy Shevchenko /* The current chunk is not fully transfered yet */ 3680b23a1ecSAndy Shevchenko bytes += desc->hw[--i].len; 369667dfed9SAndy Shevchenko 370667dfed9SAndy Shevchenko return bytes - IDMA64C_CTLH_BLOCK_TS(ctlhi); 371667dfed9SAndy Shevchenko } 372667dfed9SAndy Shevchenko 373667dfed9SAndy Shevchenko static enum dma_status idma64_tx_status(struct dma_chan *chan, 374667dfed9SAndy Shevchenko dma_cookie_t cookie, struct dma_tx_state *state) 375667dfed9SAndy Shevchenko { 376667dfed9SAndy Shevchenko struct idma64_chan *idma64c = to_idma64_chan(chan); 377667dfed9SAndy Shevchenko struct virt_dma_desc *vdesc; 378667dfed9SAndy Shevchenko enum dma_status status; 379667dfed9SAndy Shevchenko size_t bytes; 380667dfed9SAndy Shevchenko unsigned long flags; 381667dfed9SAndy Shevchenko 382667dfed9SAndy Shevchenko status = dma_cookie_status(chan, cookie, state); 383667dfed9SAndy Shevchenko if (status == DMA_COMPLETE) 384667dfed9SAndy Shevchenko return status; 385667dfed9SAndy Shevchenko 386667dfed9SAndy Shevchenko spin_lock_irqsave(&idma64c->vchan.lock, flags); 387667dfed9SAndy Shevchenko vdesc = vchan_find_desc(&idma64c->vchan, cookie); 388667dfed9SAndy Shevchenko if (idma64c->desc && cookie == idma64c->desc->vdesc.tx.cookie) { 389667dfed9SAndy Shevchenko bytes = idma64_active_desc_size(idma64c); 390667dfed9SAndy Shevchenko dma_set_residue(state, bytes); 391667dfed9SAndy Shevchenko status = idma64c->desc->status; 392667dfed9SAndy Shevchenko } else if (vdesc) { 393667dfed9SAndy Shevchenko bytes = to_idma64_desc(vdesc)->length; 394667dfed9SAndy Shevchenko dma_set_residue(state, bytes); 395667dfed9SAndy Shevchenko } 396667dfed9SAndy Shevchenko spin_unlock_irqrestore(&idma64c->vchan.lock, flags); 397667dfed9SAndy Shevchenko 398667dfed9SAndy Shevchenko return status; 399667dfed9SAndy Shevchenko } 400667dfed9SAndy Shevchenko 401667dfed9SAndy Shevchenko static void convert_burst(u32 *maxburst) 402667dfed9SAndy Shevchenko { 403667dfed9SAndy Shevchenko if (*maxburst) 404667dfed9SAndy Shevchenko *maxburst = __fls(*maxburst); 405667dfed9SAndy Shevchenko else 406667dfed9SAndy Shevchenko *maxburst = 0; 407667dfed9SAndy Shevchenko } 408667dfed9SAndy Shevchenko 409667dfed9SAndy Shevchenko static int idma64_slave_config(struct dma_chan *chan, 410667dfed9SAndy Shevchenko struct dma_slave_config *config) 411667dfed9SAndy Shevchenko { 412667dfed9SAndy Shevchenko struct idma64_chan *idma64c = to_idma64_chan(chan); 413667dfed9SAndy Shevchenko 414667dfed9SAndy Shevchenko memcpy(&idma64c->config, config, sizeof(idma64c->config)); 415667dfed9SAndy Shevchenko 416667dfed9SAndy Shevchenko convert_burst(&idma64c->config.src_maxburst); 417667dfed9SAndy Shevchenko convert_burst(&idma64c->config.dst_maxburst); 418667dfed9SAndy Shevchenko 419667dfed9SAndy Shevchenko return 0; 420667dfed9SAndy Shevchenko } 421667dfed9SAndy Shevchenko 4222e9b55beSAndy Shevchenko static void idma64_chan_deactivate(struct idma64_chan *idma64c, bool drain) 423667dfed9SAndy Shevchenko { 424667dfed9SAndy Shevchenko unsigned short count = 100; 425667dfed9SAndy Shevchenko u32 cfglo; 426667dfed9SAndy Shevchenko 427667dfed9SAndy Shevchenko cfglo = channel_readl(idma64c, CFG_LO); 4282e9b55beSAndy Shevchenko if (drain) 4292e9b55beSAndy Shevchenko cfglo |= IDMA64C_CFGL_CH_DRAIN; 4302e9b55beSAndy Shevchenko else 4312e9b55beSAndy Shevchenko cfglo &= ~IDMA64C_CFGL_CH_DRAIN; 4322e9b55beSAndy Shevchenko 433667dfed9SAndy Shevchenko channel_writel(idma64c, CFG_LO, cfglo | IDMA64C_CFGL_CH_SUSP); 434667dfed9SAndy Shevchenko do { 435667dfed9SAndy Shevchenko udelay(1); 436667dfed9SAndy Shevchenko cfglo = channel_readl(idma64c, CFG_LO); 437667dfed9SAndy Shevchenko } while (!(cfglo & IDMA64C_CFGL_FIFO_EMPTY) && --count); 438667dfed9SAndy Shevchenko } 439667dfed9SAndy Shevchenko 440667dfed9SAndy Shevchenko static void idma64_chan_activate(struct idma64_chan *idma64c) 441667dfed9SAndy Shevchenko { 442667dfed9SAndy Shevchenko u32 cfglo; 443667dfed9SAndy Shevchenko 444667dfed9SAndy Shevchenko cfglo = channel_readl(idma64c, CFG_LO); 445667dfed9SAndy Shevchenko channel_writel(idma64c, CFG_LO, cfglo & ~IDMA64C_CFGL_CH_SUSP); 446667dfed9SAndy Shevchenko } 447667dfed9SAndy Shevchenko 448667dfed9SAndy Shevchenko static int idma64_pause(struct dma_chan *chan) 449667dfed9SAndy Shevchenko { 450667dfed9SAndy Shevchenko struct idma64_chan *idma64c = to_idma64_chan(chan); 451667dfed9SAndy Shevchenko unsigned long flags; 452667dfed9SAndy Shevchenko 453667dfed9SAndy Shevchenko spin_lock_irqsave(&idma64c->vchan.lock, flags); 454667dfed9SAndy Shevchenko if (idma64c->desc && idma64c->desc->status == DMA_IN_PROGRESS) { 4552e9b55beSAndy Shevchenko idma64_chan_deactivate(idma64c, false); 456667dfed9SAndy Shevchenko idma64c->desc->status = DMA_PAUSED; 457667dfed9SAndy Shevchenko } 458667dfed9SAndy Shevchenko spin_unlock_irqrestore(&idma64c->vchan.lock, flags); 459667dfed9SAndy Shevchenko 460667dfed9SAndy Shevchenko return 0; 461667dfed9SAndy Shevchenko } 462667dfed9SAndy Shevchenko 463667dfed9SAndy Shevchenko static int idma64_resume(struct dma_chan *chan) 464667dfed9SAndy Shevchenko { 465667dfed9SAndy Shevchenko struct idma64_chan *idma64c = to_idma64_chan(chan); 466667dfed9SAndy Shevchenko unsigned long flags; 467667dfed9SAndy Shevchenko 468667dfed9SAndy Shevchenko spin_lock_irqsave(&idma64c->vchan.lock, flags); 469667dfed9SAndy Shevchenko if (idma64c->desc && idma64c->desc->status == DMA_PAUSED) { 470667dfed9SAndy Shevchenko idma64c->desc->status = DMA_IN_PROGRESS; 471667dfed9SAndy Shevchenko idma64_chan_activate(idma64c); 472667dfed9SAndy Shevchenko } 473667dfed9SAndy Shevchenko spin_unlock_irqrestore(&idma64c->vchan.lock, flags); 474667dfed9SAndy Shevchenko 475667dfed9SAndy Shevchenko return 0; 476667dfed9SAndy Shevchenko } 477667dfed9SAndy Shevchenko 478667dfed9SAndy Shevchenko static int idma64_terminate_all(struct dma_chan *chan) 479667dfed9SAndy Shevchenko { 480667dfed9SAndy Shevchenko struct idma64_chan *idma64c = to_idma64_chan(chan); 481667dfed9SAndy Shevchenko unsigned long flags; 482667dfed9SAndy Shevchenko LIST_HEAD(head); 483667dfed9SAndy Shevchenko 484667dfed9SAndy Shevchenko spin_lock_irqsave(&idma64c->vchan.lock, flags); 4852e9b55beSAndy Shevchenko idma64_chan_deactivate(idma64c, true); 486667dfed9SAndy Shevchenko idma64_stop_transfer(idma64c); 487667dfed9SAndy Shevchenko if (idma64c->desc) { 488667dfed9SAndy Shevchenko idma64_vdesc_free(&idma64c->desc->vdesc); 489667dfed9SAndy Shevchenko idma64c->desc = NULL; 490667dfed9SAndy Shevchenko } 491667dfed9SAndy Shevchenko vchan_get_all_descriptors(&idma64c->vchan, &head); 492667dfed9SAndy Shevchenko spin_unlock_irqrestore(&idma64c->vchan.lock, flags); 493667dfed9SAndy Shevchenko 494667dfed9SAndy Shevchenko vchan_dma_desc_free_list(&idma64c->vchan, &head); 495667dfed9SAndy Shevchenko return 0; 496667dfed9SAndy Shevchenko } 497667dfed9SAndy Shevchenko 498bbacb8e7SAndy Shevchenko static void idma64_synchronize(struct dma_chan *chan) 499bbacb8e7SAndy Shevchenko { 500bbacb8e7SAndy Shevchenko struct idma64_chan *idma64c = to_idma64_chan(chan); 501bbacb8e7SAndy Shevchenko 502bbacb8e7SAndy Shevchenko vchan_synchronize(&idma64c->vchan); 503bbacb8e7SAndy Shevchenko } 504bbacb8e7SAndy Shevchenko 505667dfed9SAndy Shevchenko static int idma64_alloc_chan_resources(struct dma_chan *chan) 506667dfed9SAndy Shevchenko { 507667dfed9SAndy Shevchenko struct idma64_chan *idma64c = to_idma64_chan(chan); 508667dfed9SAndy Shevchenko 509667dfed9SAndy Shevchenko /* Create a pool of consistent memory blocks for hardware descriptors */ 510667dfed9SAndy Shevchenko idma64c->pool = dma_pool_create(dev_name(chan2dev(chan)), 511667dfed9SAndy Shevchenko chan->device->dev, 512667dfed9SAndy Shevchenko sizeof(struct idma64_lli), 8, 0); 513667dfed9SAndy Shevchenko if (!idma64c->pool) { 514667dfed9SAndy Shevchenko dev_err(chan2dev(chan), "No memory for descriptors\n"); 515667dfed9SAndy Shevchenko return -ENOMEM; 516667dfed9SAndy Shevchenko } 517667dfed9SAndy Shevchenko 518667dfed9SAndy Shevchenko return 0; 519667dfed9SAndy Shevchenko } 520667dfed9SAndy Shevchenko 521667dfed9SAndy Shevchenko static void idma64_free_chan_resources(struct dma_chan *chan) 522667dfed9SAndy Shevchenko { 523667dfed9SAndy Shevchenko struct idma64_chan *idma64c = to_idma64_chan(chan); 524667dfed9SAndy Shevchenko 525667dfed9SAndy Shevchenko vchan_free_chan_resources(to_virt_chan(chan)); 526667dfed9SAndy Shevchenko dma_pool_destroy(idma64c->pool); 527667dfed9SAndy Shevchenko idma64c->pool = NULL; 528667dfed9SAndy Shevchenko } 529667dfed9SAndy Shevchenko 530667dfed9SAndy Shevchenko /* ---------------------------------------------------------------------- */ 531667dfed9SAndy Shevchenko 532667dfed9SAndy Shevchenko #define IDMA64_BUSWIDTHS \ 533667dfed9SAndy Shevchenko BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ 534667dfed9SAndy Shevchenko BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ 535667dfed9SAndy Shevchenko BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) 536667dfed9SAndy Shevchenko 537667dfed9SAndy Shevchenko static int idma64_probe(struct idma64_chip *chip) 538667dfed9SAndy Shevchenko { 539667dfed9SAndy Shevchenko struct idma64 *idma64; 540667dfed9SAndy Shevchenko unsigned short nr_chan = IDMA64_NR_CHAN; 541667dfed9SAndy Shevchenko unsigned short i; 542667dfed9SAndy Shevchenko int ret; 543667dfed9SAndy Shevchenko 544667dfed9SAndy Shevchenko idma64 = devm_kzalloc(chip->dev, sizeof(*idma64), GFP_KERNEL); 545667dfed9SAndy Shevchenko if (!idma64) 546667dfed9SAndy Shevchenko return -ENOMEM; 547667dfed9SAndy Shevchenko 548667dfed9SAndy Shevchenko idma64->regs = chip->regs; 549667dfed9SAndy Shevchenko chip->idma64 = idma64; 550667dfed9SAndy Shevchenko 551667dfed9SAndy Shevchenko idma64->chan = devm_kcalloc(chip->dev, nr_chan, sizeof(*idma64->chan), 552667dfed9SAndy Shevchenko GFP_KERNEL); 553667dfed9SAndy Shevchenko if (!idma64->chan) 554667dfed9SAndy Shevchenko return -ENOMEM; 555667dfed9SAndy Shevchenko 556667dfed9SAndy Shevchenko idma64->all_chan_mask = (1 << nr_chan) - 1; 557667dfed9SAndy Shevchenko 558667dfed9SAndy Shevchenko /* Turn off iDMA controller */ 559667dfed9SAndy Shevchenko idma64_off(idma64); 560667dfed9SAndy Shevchenko 561667dfed9SAndy Shevchenko ret = devm_request_irq(chip->dev, chip->irq, idma64_irq, IRQF_SHARED, 562667dfed9SAndy Shevchenko dev_name(chip->dev), idma64); 563667dfed9SAndy Shevchenko if (ret) 564667dfed9SAndy Shevchenko return ret; 565667dfed9SAndy Shevchenko 566667dfed9SAndy Shevchenko INIT_LIST_HEAD(&idma64->dma.channels); 567667dfed9SAndy Shevchenko for (i = 0; i < nr_chan; i++) { 568667dfed9SAndy Shevchenko struct idma64_chan *idma64c = &idma64->chan[i]; 569667dfed9SAndy Shevchenko 570667dfed9SAndy Shevchenko idma64c->vchan.desc_free = idma64_vdesc_free; 571667dfed9SAndy Shevchenko vchan_init(&idma64c->vchan, &idma64->dma); 572667dfed9SAndy Shevchenko 573667dfed9SAndy Shevchenko idma64c->regs = idma64->regs + i * IDMA64_CH_LENGTH; 574667dfed9SAndy Shevchenko idma64c->mask = BIT(i); 575667dfed9SAndy Shevchenko } 576667dfed9SAndy Shevchenko 577667dfed9SAndy Shevchenko dma_cap_set(DMA_SLAVE, idma64->dma.cap_mask); 578667dfed9SAndy Shevchenko dma_cap_set(DMA_PRIVATE, idma64->dma.cap_mask); 579667dfed9SAndy Shevchenko 580667dfed9SAndy Shevchenko idma64->dma.device_alloc_chan_resources = idma64_alloc_chan_resources; 581667dfed9SAndy Shevchenko idma64->dma.device_free_chan_resources = idma64_free_chan_resources; 582667dfed9SAndy Shevchenko 583667dfed9SAndy Shevchenko idma64->dma.device_prep_slave_sg = idma64_prep_slave_sg; 584667dfed9SAndy Shevchenko 585667dfed9SAndy Shevchenko idma64->dma.device_issue_pending = idma64_issue_pending; 586667dfed9SAndy Shevchenko idma64->dma.device_tx_status = idma64_tx_status; 587667dfed9SAndy Shevchenko 588667dfed9SAndy Shevchenko idma64->dma.device_config = idma64_slave_config; 589667dfed9SAndy Shevchenko idma64->dma.device_pause = idma64_pause; 590667dfed9SAndy Shevchenko idma64->dma.device_resume = idma64_resume; 591667dfed9SAndy Shevchenko idma64->dma.device_terminate_all = idma64_terminate_all; 592bbacb8e7SAndy Shevchenko idma64->dma.device_synchronize = idma64_synchronize; 593667dfed9SAndy Shevchenko 594667dfed9SAndy Shevchenko idma64->dma.src_addr_widths = IDMA64_BUSWIDTHS; 595667dfed9SAndy Shevchenko idma64->dma.dst_addr_widths = IDMA64_BUSWIDTHS; 596667dfed9SAndy Shevchenko idma64->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); 597667dfed9SAndy Shevchenko idma64->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; 598667dfed9SAndy Shevchenko 5995ba846b1SAndy Shevchenko idma64->dma.dev = chip->sysdev; 600667dfed9SAndy Shevchenko 601e3fdb189SAndy Shevchenko dma_set_max_seg_size(idma64->dma.dev, IDMA64C_CTLH_BLOCK_TS_MASK); 602e3fdb189SAndy Shevchenko 603667dfed9SAndy Shevchenko ret = dma_async_device_register(&idma64->dma); 604667dfed9SAndy Shevchenko if (ret) 605667dfed9SAndy Shevchenko return ret; 606667dfed9SAndy Shevchenko 607667dfed9SAndy Shevchenko dev_info(chip->dev, "Found Intel integrated DMA 64-bit\n"); 608667dfed9SAndy Shevchenko return 0; 609667dfed9SAndy Shevchenko } 610667dfed9SAndy Shevchenko 611c3b63380SUwe Kleine-König static void idma64_remove(struct idma64_chip *chip) 612667dfed9SAndy Shevchenko { 613667dfed9SAndy Shevchenko struct idma64 *idma64 = chip->idma64; 614667dfed9SAndy Shevchenko unsigned short i; 615667dfed9SAndy Shevchenko 616667dfed9SAndy Shevchenko dma_async_device_unregister(&idma64->dma); 617667dfed9SAndy Shevchenko 618667dfed9SAndy Shevchenko /* 619667dfed9SAndy Shevchenko * Explicitly call devm_request_irq() to avoid the side effects with 620667dfed9SAndy Shevchenko * the scheduled tasklets. 621667dfed9SAndy Shevchenko */ 622667dfed9SAndy Shevchenko devm_free_irq(chip->dev, chip->irq, idma64); 623667dfed9SAndy Shevchenko 624667dfed9SAndy Shevchenko for (i = 0; i < idma64->dma.chancnt; i++) { 625667dfed9SAndy Shevchenko struct idma64_chan *idma64c = &idma64->chan[i]; 626667dfed9SAndy Shevchenko 627667dfed9SAndy Shevchenko tasklet_kill(&idma64c->vchan.task); 628667dfed9SAndy Shevchenko } 629667dfed9SAndy Shevchenko } 630667dfed9SAndy Shevchenko 631667dfed9SAndy Shevchenko /* ---------------------------------------------------------------------- */ 632667dfed9SAndy Shevchenko 633667dfed9SAndy Shevchenko static int idma64_platform_probe(struct platform_device *pdev) 634667dfed9SAndy Shevchenko { 635667dfed9SAndy Shevchenko struct idma64_chip *chip; 636667dfed9SAndy Shevchenko struct device *dev = &pdev->dev; 6375ba846b1SAndy Shevchenko struct device *sysdev = dev->parent; 638667dfed9SAndy Shevchenko int ret; 639667dfed9SAndy Shevchenko 640667dfed9SAndy Shevchenko chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 641667dfed9SAndy Shevchenko if (!chip) 642667dfed9SAndy Shevchenko return -ENOMEM; 643667dfed9SAndy Shevchenko 644667dfed9SAndy Shevchenko chip->irq = platform_get_irq(pdev, 0); 645667dfed9SAndy Shevchenko if (chip->irq < 0) 646667dfed9SAndy Shevchenko return chip->irq; 647667dfed9SAndy Shevchenko 6484b23603aSTudor Ambarus chip->regs = devm_platform_ioremap_resource(pdev, 0); 649667dfed9SAndy Shevchenko if (IS_ERR(chip->regs)) 650667dfed9SAndy Shevchenko return PTR_ERR(chip->regs); 651667dfed9SAndy Shevchenko 6525ba846b1SAndy Shevchenko ret = dma_coerce_mask_and_coherent(sysdev, DMA_BIT_MASK(64)); 653667dfed9SAndy Shevchenko if (ret) 654667dfed9SAndy Shevchenko return ret; 655667dfed9SAndy Shevchenko 656667dfed9SAndy Shevchenko chip->dev = dev; 6575ba846b1SAndy Shevchenko chip->sysdev = sysdev; 658667dfed9SAndy Shevchenko 659667dfed9SAndy Shevchenko ret = idma64_probe(chip); 660667dfed9SAndy Shevchenko if (ret) 661667dfed9SAndy Shevchenko return ret; 662667dfed9SAndy Shevchenko 663667dfed9SAndy Shevchenko platform_set_drvdata(pdev, chip); 664667dfed9SAndy Shevchenko return 0; 665667dfed9SAndy Shevchenko } 666667dfed9SAndy Shevchenko 667667dfed9SAndy Shevchenko static int idma64_platform_remove(struct platform_device *pdev) 668667dfed9SAndy Shevchenko { 669667dfed9SAndy Shevchenko struct idma64_chip *chip = platform_get_drvdata(pdev); 670667dfed9SAndy Shevchenko 671c3b63380SUwe Kleine-König idma64_remove(chip); 672c3b63380SUwe Kleine-König 673c3b63380SUwe Kleine-König return 0; 674667dfed9SAndy Shevchenko } 675667dfed9SAndy Shevchenko 67663497532SAndy Shevchenko static int __maybe_unused idma64_pm_suspend(struct device *dev) 677667dfed9SAndy Shevchenko { 678b7d69799SWolfram Sang struct idma64_chip *chip = dev_get_drvdata(dev); 679667dfed9SAndy Shevchenko 680667dfed9SAndy Shevchenko idma64_off(chip->idma64); 681667dfed9SAndy Shevchenko return 0; 682667dfed9SAndy Shevchenko } 683667dfed9SAndy Shevchenko 68463497532SAndy Shevchenko static int __maybe_unused idma64_pm_resume(struct device *dev) 685667dfed9SAndy Shevchenko { 686b7d69799SWolfram Sang struct idma64_chip *chip = dev_get_drvdata(dev); 687667dfed9SAndy Shevchenko 688667dfed9SAndy Shevchenko idma64_on(chip->idma64); 689667dfed9SAndy Shevchenko return 0; 690667dfed9SAndy Shevchenko } 691667dfed9SAndy Shevchenko 692667dfed9SAndy Shevchenko static const struct dev_pm_ops idma64_dev_pm_ops = { 693667dfed9SAndy Shevchenko SET_SYSTEM_SLEEP_PM_OPS(idma64_pm_suspend, idma64_pm_resume) 694667dfed9SAndy Shevchenko }; 695667dfed9SAndy Shevchenko 696667dfed9SAndy Shevchenko static struct platform_driver idma64_platform_driver = { 697667dfed9SAndy Shevchenko .probe = idma64_platform_probe, 698667dfed9SAndy Shevchenko .remove = idma64_platform_remove, 699667dfed9SAndy Shevchenko .driver = { 700ffcfc20fSAndy Shevchenko .name = LPSS_IDMA64_DRIVER_NAME, 701667dfed9SAndy Shevchenko .pm = &idma64_dev_pm_ops, 702667dfed9SAndy Shevchenko }, 703667dfed9SAndy Shevchenko }; 704667dfed9SAndy Shevchenko 705667dfed9SAndy Shevchenko module_platform_driver(idma64_platform_driver); 706667dfed9SAndy Shevchenko 707667dfed9SAndy Shevchenko MODULE_LICENSE("GPL v2"); 708667dfed9SAndy Shevchenko MODULE_DESCRIPTION("iDMA64 core driver"); 709667dfed9SAndy Shevchenko MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>"); 710ffcfc20fSAndy Shevchenko MODULE_ALIAS("platform:" LPSS_IDMA64_DRIVER_NAME); 711