1 /* 2 * PCI driver for the High Speed UART DMA 3 * 4 * Copyright (C) 2015 Intel Corporation 5 * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com> 6 * 7 * Partially based on the bits found in drivers/tty/serial/mfd.c. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14 #include <linux/bitops.h> 15 #include <linux/device.h> 16 #include <linux/module.h> 17 #include <linux/pci.h> 18 19 #include "hsu.h" 20 21 #define HSU_PCI_DMASR 0x00 22 #define HSU_PCI_DMAISR 0x04 23 24 #define HSU_PCI_CHAN_OFFSET 0x100 25 26 #define PCI_DEVICE_ID_INTEL_MFLD_HSU_DMA 0x081e 27 #define PCI_DEVICE_ID_INTEL_MRFLD_HSU_DMA 0x1192 28 29 static irqreturn_t hsu_pci_irq(int irq, void *dev) 30 { 31 struct hsu_dma_chip *chip = dev; 32 struct pci_dev *pdev = to_pci_dev(chip->dev); 33 u32 dmaisr; 34 u32 status; 35 unsigned short i; 36 int ret = 0; 37 int err; 38 39 /* 40 * On Intel Tangier B0 and Anniedale the interrupt line, disregarding 41 * to have different numbers, is shared between HSU DMA and UART IPs. 42 * Thus on such SoCs we are expecting that IRQ handler is called in 43 * UART driver only. 44 */ 45 if (pdev->device == PCI_DEVICE_ID_INTEL_MRFLD_HSU_DMA) 46 return IRQ_HANDLED; 47 48 dmaisr = readl(chip->regs + HSU_PCI_DMAISR); 49 for (i = 0; i < chip->hsu->nr_channels; i++) { 50 if (dmaisr & 0x1) { 51 err = hsu_dma_get_status(chip, i, &status); 52 if (err > 0) 53 ret |= 1; 54 else if (err == 0) 55 ret |= hsu_dma_do_irq(chip, i, status); 56 } 57 dmaisr >>= 1; 58 } 59 60 return IRQ_RETVAL(ret); 61 } 62 63 static int hsu_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 64 { 65 struct hsu_dma_chip *chip; 66 int ret; 67 68 ret = pcim_enable_device(pdev); 69 if (ret) 70 return ret; 71 72 ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev)); 73 if (ret) { 74 dev_err(&pdev->dev, "I/O memory remapping failed\n"); 75 return ret; 76 } 77 78 pci_set_master(pdev); 79 pci_try_set_mwi(pdev); 80 81 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 82 if (ret) 83 return ret; 84 85 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); 86 if (ret) 87 return ret; 88 89 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 90 if (!chip) 91 return -ENOMEM; 92 93 ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 94 if (ret < 0) 95 return ret; 96 97 chip->dev = &pdev->dev; 98 chip->regs = pcim_iomap_table(pdev)[0]; 99 chip->length = pci_resource_len(pdev, 0); 100 chip->offset = HSU_PCI_CHAN_OFFSET; 101 chip->irq = pci_irq_vector(pdev, 0); 102 103 ret = hsu_dma_probe(chip); 104 if (ret) 105 return ret; 106 107 ret = request_irq(chip->irq, hsu_pci_irq, 0, "hsu_dma_pci", chip); 108 if (ret) 109 goto err_register_irq; 110 111 pci_set_drvdata(pdev, chip); 112 113 return 0; 114 115 err_register_irq: 116 hsu_dma_remove(chip); 117 return ret; 118 } 119 120 static void hsu_pci_remove(struct pci_dev *pdev) 121 { 122 struct hsu_dma_chip *chip = pci_get_drvdata(pdev); 123 124 free_irq(chip->irq, chip); 125 hsu_dma_remove(chip); 126 } 127 128 static const struct pci_device_id hsu_pci_id_table[] = { 129 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MFLD_HSU_DMA), 0 }, 130 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MRFLD_HSU_DMA), 0 }, 131 { } 132 }; 133 MODULE_DEVICE_TABLE(pci, hsu_pci_id_table); 134 135 static struct pci_driver hsu_pci_driver = { 136 .name = "hsu_dma_pci", 137 .id_table = hsu_pci_id_table, 138 .probe = hsu_pci_probe, 139 .remove = hsu_pci_remove, 140 }; 141 142 module_pci_driver(hsu_pci_driver); 143 144 MODULE_LICENSE("GPL v2"); 145 MODULE_DESCRIPTION("High Speed UART DMA PCI driver"); 146 MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>"); 147