xref: /openbmc/linux/drivers/dma/hsu/pci.c (revision 0d3b051a)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * PCI driver for the High Speed UART DMA
4  *
5  * Copyright (C) 2015 Intel Corporation
6  * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
7  *
8  * Partially based on the bits found in drivers/tty/serial/mfd.c.
9  */
10 
11 #include <linux/bitops.h>
12 #include <linux/device.h>
13 #include <linux/module.h>
14 #include <linux/pci.h>
15 
16 #include "hsu.h"
17 
18 #define HSU_PCI_DMASR		0x00
19 #define HSU_PCI_DMAISR		0x04
20 
21 #define HSU_PCI_CHAN_OFFSET	0x100
22 
23 #define PCI_DEVICE_ID_INTEL_MFLD_HSU_DMA	0x081e
24 #define PCI_DEVICE_ID_INTEL_MRFLD_HSU_DMA	0x1192
25 
26 static irqreturn_t hsu_pci_irq(int irq, void *dev)
27 {
28 	struct hsu_dma_chip *chip = dev;
29 	struct pci_dev *pdev = to_pci_dev(chip->dev);
30 	u32 dmaisr;
31 	u32 status;
32 	unsigned short i;
33 	int ret = 0;
34 	int err;
35 
36 	/*
37 	 * On Intel Tangier B0 and Anniedale the interrupt line, disregarding
38 	 * to have different numbers, is shared between HSU DMA and UART IPs.
39 	 * Thus on such SoCs we are expecting that IRQ handler is called in
40 	 * UART driver only.
41 	 */
42 	if (pdev->device == PCI_DEVICE_ID_INTEL_MRFLD_HSU_DMA)
43 		return IRQ_HANDLED;
44 
45 	dmaisr = readl(chip->regs + HSU_PCI_DMAISR);
46 	for (i = 0; i < chip->hsu->nr_channels; i++) {
47 		if (dmaisr & 0x1) {
48 			err = hsu_dma_get_status(chip, i, &status);
49 			if (err > 0)
50 				ret |= 1;
51 			else if (err == 0)
52 				ret |= hsu_dma_do_irq(chip, i, status);
53 		}
54 		dmaisr >>= 1;
55 	}
56 
57 	return IRQ_RETVAL(ret);
58 }
59 
60 static int hsu_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
61 {
62 	struct hsu_dma_chip *chip;
63 	int ret;
64 
65 	ret = pcim_enable_device(pdev);
66 	if (ret)
67 		return ret;
68 
69 	ret = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev));
70 	if (ret) {
71 		dev_err(&pdev->dev, "I/O memory remapping failed\n");
72 		return ret;
73 	}
74 
75 	pci_set_master(pdev);
76 	pci_try_set_mwi(pdev);
77 
78 	ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
79 	if (ret)
80 		return ret;
81 
82 	ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
83 	if (ret)
84 		return ret;
85 
86 	chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
87 	if (!chip)
88 		return -ENOMEM;
89 
90 	ret = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
91 	if (ret < 0)
92 		return ret;
93 
94 	chip->dev = &pdev->dev;
95 	chip->regs = pcim_iomap_table(pdev)[0];
96 	chip->length = pci_resource_len(pdev, 0);
97 	chip->offset = HSU_PCI_CHAN_OFFSET;
98 	chip->irq = pci_irq_vector(pdev, 0);
99 
100 	ret = hsu_dma_probe(chip);
101 	if (ret)
102 		return ret;
103 
104 	ret = request_irq(chip->irq, hsu_pci_irq, 0, "hsu_dma_pci", chip);
105 	if (ret)
106 		goto err_register_irq;
107 
108 	pci_set_drvdata(pdev, chip);
109 
110 	return 0;
111 
112 err_register_irq:
113 	hsu_dma_remove(chip);
114 	return ret;
115 }
116 
117 static void hsu_pci_remove(struct pci_dev *pdev)
118 {
119 	struct hsu_dma_chip *chip = pci_get_drvdata(pdev);
120 
121 	free_irq(chip->irq, chip);
122 	hsu_dma_remove(chip);
123 }
124 
125 static const struct pci_device_id hsu_pci_id_table[] = {
126 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MFLD_HSU_DMA), 0 },
127 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MRFLD_HSU_DMA), 0 },
128 	{ }
129 };
130 MODULE_DEVICE_TABLE(pci, hsu_pci_id_table);
131 
132 static struct pci_driver hsu_pci_driver = {
133 	.name		= "hsu_dma_pci",
134 	.id_table	= hsu_pci_id_table,
135 	.probe		= hsu_pci_probe,
136 	.remove		= hsu_pci_remove,
137 };
138 
139 module_pci_driver(hsu_pci_driver);
140 
141 MODULE_LICENSE("GPL v2");
142 MODULE_DESCRIPTION("High Speed UART DMA PCI driver");
143 MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
144