1 /* 2 * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved. 3 * 4 * Author: 5 * Zhang Wei <wei.zhang@freescale.com>, Jul 2007 6 * Ebony Zhu <ebony.zhu@freescale.com>, May 2007 7 * 8 * This is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 */ 14 #ifndef __DMA_FSLDMA_H 15 #define __DMA_FSLDMA_H 16 17 #include <linux/device.h> 18 #include <linux/dmapool.h> 19 #include <linux/dmaengine.h> 20 21 /* Define data structures needed by Freescale 22 * MPC8540 and MPC8349 DMA controller. 23 */ 24 #define FSL_DMA_MR_CS 0x00000001 25 #define FSL_DMA_MR_CC 0x00000002 26 #define FSL_DMA_MR_CA 0x00000008 27 #define FSL_DMA_MR_EIE 0x00000040 28 #define FSL_DMA_MR_XFE 0x00000020 29 #define FSL_DMA_MR_EOLNIE 0x00000100 30 #define FSL_DMA_MR_EOLSIE 0x00000080 31 #define FSL_DMA_MR_EOSIE 0x00000200 32 #define FSL_DMA_MR_CDSM 0x00000010 33 #define FSL_DMA_MR_CTM 0x00000004 34 #define FSL_DMA_MR_EMP_EN 0x00200000 35 #define FSL_DMA_MR_EMS_EN 0x00040000 36 #define FSL_DMA_MR_DAHE 0x00002000 37 #define FSL_DMA_MR_SAHE 0x00001000 38 39 /* Special MR definition for MPC8349 */ 40 #define FSL_DMA_MR_EOTIE 0x00000080 41 #define FSL_DMA_MR_PRC_RM 0x00000800 42 43 #define FSL_DMA_SR_CH 0x00000020 44 #define FSL_DMA_SR_PE 0x00000010 45 #define FSL_DMA_SR_CB 0x00000004 46 #define FSL_DMA_SR_TE 0x00000080 47 #define FSL_DMA_SR_EOSI 0x00000002 48 #define FSL_DMA_SR_EOLSI 0x00000001 49 #define FSL_DMA_SR_EOCDI 0x00000001 50 #define FSL_DMA_SR_EOLNI 0x00000008 51 52 #define FSL_DMA_SATR_SBPATMU 0x20000000 53 #define FSL_DMA_SATR_STRANSINT_RIO 0x00c00000 54 #define FSL_DMA_SATR_SREADTYPE_SNOOP_READ 0x00050000 55 #define FSL_DMA_SATR_SREADTYPE_BP_IORH 0x00020000 56 #define FSL_DMA_SATR_SREADTYPE_BP_NREAD 0x00040000 57 #define FSL_DMA_SATR_SREADTYPE_BP_MREAD 0x00070000 58 59 #define FSL_DMA_DATR_DBPATMU 0x20000000 60 #define FSL_DMA_DATR_DTRANSINT_RIO 0x00c00000 61 #define FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE 0x00050000 62 #define FSL_DMA_DATR_DWRITETYPE_BP_FLUSH 0x00010000 63 64 #define FSL_DMA_EOL ((u64)0x1) 65 #define FSL_DMA_SNEN ((u64)0x10) 66 #define FSL_DMA_EOSIE 0x8 67 #define FSL_DMA_NLDA_MASK (~(u64)0x1f) 68 69 #define FSL_DMA_BCR_MAX_CNT 0x03ffffffu 70 71 #define FSL_DMA_DGSR_TE 0x80 72 #define FSL_DMA_DGSR_CH 0x20 73 #define FSL_DMA_DGSR_PE 0x10 74 #define FSL_DMA_DGSR_EOLNI 0x08 75 #define FSL_DMA_DGSR_CB 0x04 76 #define FSL_DMA_DGSR_EOSI 0x02 77 #define FSL_DMA_DGSR_EOLSI 0x01 78 79 typedef u64 __bitwise v64; 80 typedef u32 __bitwise v32; 81 82 struct fsl_dma_ld_hw { 83 v64 src_addr; 84 v64 dst_addr; 85 v64 next_ln_addr; 86 v32 count; 87 v32 reserve; 88 } __attribute__((aligned(32))); 89 90 struct fsl_desc_sw { 91 struct fsl_dma_ld_hw hw; 92 struct list_head node; 93 struct list_head tx_list; 94 struct dma_async_tx_descriptor async_tx; 95 struct list_head *ld; 96 void *priv; 97 } __attribute__((aligned(32))); 98 99 struct fsl_dma_chan_regs { 100 u32 mr; /* 0x00 - Mode Register */ 101 u32 sr; /* 0x04 - Status Register */ 102 u64 cdar; /* 0x08 - Current descriptor address register */ 103 u64 sar; /* 0x10 - Source Address Register */ 104 u64 dar; /* 0x18 - Destination Address Register */ 105 u32 bcr; /* 0x20 - Byte Count Register */ 106 u64 ndar; /* 0x24 - Next Descriptor Address Register */ 107 }; 108 109 struct fsl_dma_chan; 110 #define FSL_DMA_MAX_CHANS_PER_DEVICE 4 111 112 struct fsl_dma_device { 113 void __iomem *reg_base; /* DGSR register base */ 114 struct resource reg; /* Resource for register */ 115 struct device *dev; 116 struct dma_device common; 117 struct fsl_dma_chan *chan[FSL_DMA_MAX_CHANS_PER_DEVICE]; 118 u32 feature; /* The same as DMA channels */ 119 int irq; /* Channel IRQ */ 120 }; 121 122 /* Define macros for fsl_dma_chan->feature property */ 123 #define FSL_DMA_LITTLE_ENDIAN 0x00000000 124 #define FSL_DMA_BIG_ENDIAN 0x00000001 125 126 #define FSL_DMA_IP_MASK 0x00000ff0 127 #define FSL_DMA_IP_85XX 0x00000010 128 #define FSL_DMA_IP_83XX 0x00000020 129 130 #define FSL_DMA_CHAN_PAUSE_EXT 0x00001000 131 #define FSL_DMA_CHAN_START_EXT 0x00002000 132 133 struct fsl_dma_chan { 134 struct fsl_dma_chan_regs __iomem *reg_base; 135 dma_cookie_t completed_cookie; /* The maximum cookie completed */ 136 spinlock_t desc_lock; /* Descriptor operation lock */ 137 struct list_head ld_queue; /* Link descriptors queue */ 138 struct dma_chan common; /* DMA common channel */ 139 struct dma_pool *desc_pool; /* Descriptors pool */ 140 struct device *dev; /* Channel device */ 141 struct resource reg; /* Resource for register */ 142 int irq; /* Channel IRQ */ 143 int id; /* Raw id of this channel */ 144 struct tasklet_struct tasklet; 145 u32 feature; 146 147 void (*toggle_ext_pause)(struct fsl_dma_chan *fsl_chan, int enable); 148 void (*toggle_ext_start)(struct fsl_dma_chan *fsl_chan, int enable); 149 void (*set_src_loop_size)(struct fsl_dma_chan *fsl_chan, int size); 150 void (*set_dest_loop_size)(struct fsl_dma_chan *fsl_chan, int size); 151 void (*set_request_count)(struct fsl_dma_chan *fsl_chan, int size); 152 }; 153 154 #define to_fsl_chan(chan) container_of(chan, struct fsl_dma_chan, common) 155 #define to_fsl_desc(lh) container_of(lh, struct fsl_desc_sw, node) 156 #define tx_to_fsl_desc(tx) container_of(tx, struct fsl_desc_sw, async_tx) 157 158 #ifndef __powerpc64__ 159 static u64 in_be64(const u64 __iomem *addr) 160 { 161 return ((u64)in_be32((u32 __iomem *)addr) << 32) | 162 (in_be32((u32 __iomem *)addr + 1)); 163 } 164 165 static void out_be64(u64 __iomem *addr, u64 val) 166 { 167 out_be32((u32 __iomem *)addr, val >> 32); 168 out_be32((u32 __iomem *)addr + 1, (u32)val); 169 } 170 171 /* There is no asm instructions for 64 bits reverse loads and stores */ 172 static u64 in_le64(const u64 __iomem *addr) 173 { 174 return ((u64)in_le32((u32 __iomem *)addr + 1) << 32) | 175 (in_le32((u32 __iomem *)addr)); 176 } 177 178 static void out_le64(u64 __iomem *addr, u64 val) 179 { 180 out_le32((u32 __iomem *)addr + 1, val >> 32); 181 out_le32((u32 __iomem *)addr, (u32)val); 182 } 183 #endif 184 185 #define DMA_IN(fsl_chan, addr, width) \ 186 (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \ 187 in_be##width(addr) : in_le##width(addr)) 188 #define DMA_OUT(fsl_chan, addr, val, width) \ 189 (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \ 190 out_be##width(addr, val) : out_le##width(addr, val)) 191 192 #define DMA_TO_CPU(fsl_chan, d, width) \ 193 (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \ 194 be##width##_to_cpu((__force __be##width)(v##width)d) : \ 195 le##width##_to_cpu((__force __le##width)(v##width)d)) 196 #define CPU_TO_DMA(fsl_chan, c, width) \ 197 (((fsl_chan)->feature & FSL_DMA_BIG_ENDIAN) ? \ 198 (__force v##width)cpu_to_be##width(c) : \ 199 (__force v##width)cpu_to_le##width(c)) 200 201 #endif /* __DMA_FSLDMA_H */ 202