1 /* 2 * Freescale MPC85xx, MPC83xx DMA Engine support 3 * 4 * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved. 5 * 6 * Author: 7 * Zhang Wei <wei.zhang@freescale.com>, Jul 2007 8 * Ebony Zhu <ebony.zhu@freescale.com>, May 2007 9 * 10 * Description: 11 * DMA engine driver for Freescale MPC8540 DMA controller, which is 12 * also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc. 13 * The support for MPC8349 DMA contorller is also added. 14 * 15 * This driver instructs the DMA controller to issue the PCI Read Multiple 16 * command for PCI read operations, instead of using the default PCI Read Line 17 * command. Please be aware that this setting may result in read pre-fetching 18 * on some platforms. 19 * 20 * This is free software; you can redistribute it and/or modify 21 * it under the terms of the GNU General Public License as published by 22 * the Free Software Foundation; either version 2 of the License, or 23 * (at your option) any later version. 24 * 25 */ 26 27 #include <linux/init.h> 28 #include <linux/module.h> 29 #include <linux/pci.h> 30 #include <linux/interrupt.h> 31 #include <linux/dmaengine.h> 32 #include <linux/delay.h> 33 #include <linux/dma-mapping.h> 34 #include <linux/dmapool.h> 35 #include <linux/of_platform.h> 36 37 #include <asm/fsldma.h> 38 #include "fsldma.h" 39 40 static void dma_init(struct fsldma_chan *chan) 41 { 42 /* Reset the channel */ 43 DMA_OUT(chan, &chan->regs->mr, 0, 32); 44 45 switch (chan->feature & FSL_DMA_IP_MASK) { 46 case FSL_DMA_IP_85XX: 47 /* Set the channel to below modes: 48 * EIE - Error interrupt enable 49 * EOSIE - End of segments interrupt enable (basic mode) 50 * EOLNIE - End of links interrupt enable 51 */ 52 DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EIE 53 | FSL_DMA_MR_EOLNIE | FSL_DMA_MR_EOSIE, 32); 54 break; 55 case FSL_DMA_IP_83XX: 56 /* Set the channel to below modes: 57 * EOTIE - End-of-transfer interrupt enable 58 * PRC_RM - PCI read multiple 59 */ 60 DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EOTIE 61 | FSL_DMA_MR_PRC_RM, 32); 62 break; 63 } 64 } 65 66 static void set_sr(struct fsldma_chan *chan, u32 val) 67 { 68 DMA_OUT(chan, &chan->regs->sr, val, 32); 69 } 70 71 static u32 get_sr(struct fsldma_chan *chan) 72 { 73 return DMA_IN(chan, &chan->regs->sr, 32); 74 } 75 76 static void set_desc_cnt(struct fsldma_chan *chan, 77 struct fsl_dma_ld_hw *hw, u32 count) 78 { 79 hw->count = CPU_TO_DMA(chan, count, 32); 80 } 81 82 static void set_desc_src(struct fsldma_chan *chan, 83 struct fsl_dma_ld_hw *hw, dma_addr_t src) 84 { 85 u64 snoop_bits; 86 87 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) 88 ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0; 89 hw->src_addr = CPU_TO_DMA(chan, snoop_bits | src, 64); 90 } 91 92 static void set_desc_dst(struct fsldma_chan *chan, 93 struct fsl_dma_ld_hw *hw, dma_addr_t dst) 94 { 95 u64 snoop_bits; 96 97 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) 98 ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0; 99 hw->dst_addr = CPU_TO_DMA(chan, snoop_bits | dst, 64); 100 } 101 102 static void set_desc_next(struct fsldma_chan *chan, 103 struct fsl_dma_ld_hw *hw, dma_addr_t next) 104 { 105 u64 snoop_bits; 106 107 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) 108 ? FSL_DMA_SNEN : 0; 109 hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64); 110 } 111 112 static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr) 113 { 114 DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64); 115 } 116 117 static dma_addr_t get_cdar(struct fsldma_chan *chan) 118 { 119 return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN; 120 } 121 122 static dma_addr_t get_ndar(struct fsldma_chan *chan) 123 { 124 return DMA_IN(chan, &chan->regs->ndar, 64); 125 } 126 127 static u32 get_bcr(struct fsldma_chan *chan) 128 { 129 return DMA_IN(chan, &chan->regs->bcr, 32); 130 } 131 132 static int dma_is_idle(struct fsldma_chan *chan) 133 { 134 u32 sr = get_sr(chan); 135 return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH); 136 } 137 138 static void dma_start(struct fsldma_chan *chan) 139 { 140 u32 mode; 141 142 mode = DMA_IN(chan, &chan->regs->mr, 32); 143 144 if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) { 145 if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) { 146 DMA_OUT(chan, &chan->regs->bcr, 0, 32); 147 mode |= FSL_DMA_MR_EMP_EN; 148 } else { 149 mode &= ~FSL_DMA_MR_EMP_EN; 150 } 151 } 152 153 if (chan->feature & FSL_DMA_CHAN_START_EXT) 154 mode |= FSL_DMA_MR_EMS_EN; 155 else 156 mode |= FSL_DMA_MR_CS; 157 158 DMA_OUT(chan, &chan->regs->mr, mode, 32); 159 } 160 161 static void dma_halt(struct fsldma_chan *chan) 162 { 163 u32 mode; 164 int i; 165 166 mode = DMA_IN(chan, &chan->regs->mr, 32); 167 mode |= FSL_DMA_MR_CA; 168 DMA_OUT(chan, &chan->regs->mr, mode, 32); 169 170 mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN | FSL_DMA_MR_CA); 171 DMA_OUT(chan, &chan->regs->mr, mode, 32); 172 173 for (i = 0; i < 100; i++) { 174 if (dma_is_idle(chan)) 175 return; 176 177 udelay(10); 178 } 179 180 if (!dma_is_idle(chan)) 181 dev_err(chan->dev, "DMA halt timeout!\n"); 182 } 183 184 static void set_ld_eol(struct fsldma_chan *chan, 185 struct fsl_desc_sw *desc) 186 { 187 u64 snoop_bits; 188 189 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) 190 ? FSL_DMA_SNEN : 0; 191 192 desc->hw.next_ln_addr = CPU_TO_DMA(chan, 193 DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL 194 | snoop_bits, 64); 195 } 196 197 /** 198 * fsl_chan_set_src_loop_size - Set source address hold transfer size 199 * @chan : Freescale DMA channel 200 * @size : Address loop size, 0 for disable loop 201 * 202 * The set source address hold transfer size. The source 203 * address hold or loop transfer size is when the DMA transfer 204 * data from source address (SA), if the loop size is 4, the DMA will 205 * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA, 206 * SA + 1 ... and so on. 207 */ 208 static void fsl_chan_set_src_loop_size(struct fsldma_chan *chan, int size) 209 { 210 u32 mode; 211 212 mode = DMA_IN(chan, &chan->regs->mr, 32); 213 214 switch (size) { 215 case 0: 216 mode &= ~FSL_DMA_MR_SAHE; 217 break; 218 case 1: 219 case 2: 220 case 4: 221 case 8: 222 mode |= FSL_DMA_MR_SAHE | (__ilog2(size) << 14); 223 break; 224 } 225 226 DMA_OUT(chan, &chan->regs->mr, mode, 32); 227 } 228 229 /** 230 * fsl_chan_set_dst_loop_size - Set destination address hold transfer size 231 * @chan : Freescale DMA channel 232 * @size : Address loop size, 0 for disable loop 233 * 234 * The set destination address hold transfer size. The destination 235 * address hold or loop transfer size is when the DMA transfer 236 * data to destination address (TA), if the loop size is 4, the DMA will 237 * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA, 238 * TA + 1 ... and so on. 239 */ 240 static void fsl_chan_set_dst_loop_size(struct fsldma_chan *chan, int size) 241 { 242 u32 mode; 243 244 mode = DMA_IN(chan, &chan->regs->mr, 32); 245 246 switch (size) { 247 case 0: 248 mode &= ~FSL_DMA_MR_DAHE; 249 break; 250 case 1: 251 case 2: 252 case 4: 253 case 8: 254 mode |= FSL_DMA_MR_DAHE | (__ilog2(size) << 16); 255 break; 256 } 257 258 DMA_OUT(chan, &chan->regs->mr, mode, 32); 259 } 260 261 /** 262 * fsl_chan_set_request_count - Set DMA Request Count for external control 263 * @chan : Freescale DMA channel 264 * @size : Number of bytes to transfer in a single request 265 * 266 * The Freescale DMA channel can be controlled by the external signal DREQ#. 267 * The DMA request count is how many bytes are allowed to transfer before 268 * pausing the channel, after which a new assertion of DREQ# resumes channel 269 * operation. 270 * 271 * A size of 0 disables external pause control. The maximum size is 1024. 272 */ 273 static void fsl_chan_set_request_count(struct fsldma_chan *chan, int size) 274 { 275 u32 mode; 276 277 BUG_ON(size > 1024); 278 279 mode = DMA_IN(chan, &chan->regs->mr, 32); 280 mode |= (__ilog2(size) << 24) & 0x0f000000; 281 282 DMA_OUT(chan, &chan->regs->mr, mode, 32); 283 } 284 285 /** 286 * fsl_chan_toggle_ext_pause - Toggle channel external pause status 287 * @chan : Freescale DMA channel 288 * @enable : 0 is disabled, 1 is enabled. 289 * 290 * The Freescale DMA channel can be controlled by the external signal DREQ#. 291 * The DMA Request Count feature should be used in addition to this feature 292 * to set the number of bytes to transfer before pausing the channel. 293 */ 294 static void fsl_chan_toggle_ext_pause(struct fsldma_chan *chan, int enable) 295 { 296 if (enable) 297 chan->feature |= FSL_DMA_CHAN_PAUSE_EXT; 298 else 299 chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT; 300 } 301 302 /** 303 * fsl_chan_toggle_ext_start - Toggle channel external start status 304 * @chan : Freescale DMA channel 305 * @enable : 0 is disabled, 1 is enabled. 306 * 307 * If enable the external start, the channel can be started by an 308 * external DMA start pin. So the dma_start() does not start the 309 * transfer immediately. The DMA channel will wait for the 310 * control pin asserted. 311 */ 312 static void fsl_chan_toggle_ext_start(struct fsldma_chan *chan, int enable) 313 { 314 if (enable) 315 chan->feature |= FSL_DMA_CHAN_START_EXT; 316 else 317 chan->feature &= ~FSL_DMA_CHAN_START_EXT; 318 } 319 320 static void append_ld_queue(struct fsldma_chan *chan, 321 struct fsl_desc_sw *desc) 322 { 323 struct fsl_desc_sw *tail = to_fsl_desc(chan->ld_pending.prev); 324 325 if (list_empty(&chan->ld_pending)) 326 goto out_splice; 327 328 /* 329 * Add the hardware descriptor to the chain of hardware descriptors 330 * that already exists in memory. 331 * 332 * This will un-set the EOL bit of the existing transaction, and the 333 * last link in this transaction will become the EOL descriptor. 334 */ 335 set_desc_next(chan, &tail->hw, desc->async_tx.phys); 336 337 /* 338 * Add the software descriptor and all children to the list 339 * of pending transactions 340 */ 341 out_splice: 342 list_splice_tail_init(&desc->tx_list, &chan->ld_pending); 343 } 344 345 static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx) 346 { 347 struct fsldma_chan *chan = to_fsl_chan(tx->chan); 348 struct fsl_desc_sw *desc = tx_to_fsl_desc(tx); 349 struct fsl_desc_sw *child; 350 unsigned long flags; 351 dma_cookie_t cookie; 352 353 spin_lock_irqsave(&chan->desc_lock, flags); 354 355 /* 356 * assign cookies to all of the software descriptors 357 * that make up this transaction 358 */ 359 cookie = chan->common.cookie; 360 list_for_each_entry(child, &desc->tx_list, node) { 361 cookie++; 362 if (cookie < 0) 363 cookie = 1; 364 365 child->async_tx.cookie = cookie; 366 } 367 368 chan->common.cookie = cookie; 369 370 /* put this transaction onto the tail of the pending queue */ 371 append_ld_queue(chan, desc); 372 373 spin_unlock_irqrestore(&chan->desc_lock, flags); 374 375 return cookie; 376 } 377 378 /** 379 * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool. 380 * @chan : Freescale DMA channel 381 * 382 * Return - The descriptor allocated. NULL for failed. 383 */ 384 static struct fsl_desc_sw *fsl_dma_alloc_descriptor( 385 struct fsldma_chan *chan) 386 { 387 struct fsl_desc_sw *desc; 388 dma_addr_t pdesc; 389 390 desc = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc); 391 if (!desc) { 392 dev_dbg(chan->dev, "out of memory for link desc\n"); 393 return NULL; 394 } 395 396 memset(desc, 0, sizeof(*desc)); 397 INIT_LIST_HEAD(&desc->tx_list); 398 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); 399 desc->async_tx.tx_submit = fsl_dma_tx_submit; 400 desc->async_tx.phys = pdesc; 401 402 return desc; 403 } 404 405 406 /** 407 * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel. 408 * @chan : Freescale DMA channel 409 * 410 * This function will create a dma pool for descriptor allocation. 411 * 412 * Return - The number of descriptors allocated. 413 */ 414 static int fsl_dma_alloc_chan_resources(struct dma_chan *dchan) 415 { 416 struct fsldma_chan *chan = to_fsl_chan(dchan); 417 418 /* Has this channel already been allocated? */ 419 if (chan->desc_pool) 420 return 1; 421 422 /* 423 * We need the descriptor to be aligned to 32bytes 424 * for meeting FSL DMA specification requirement. 425 */ 426 chan->desc_pool = dma_pool_create("fsl_dma_engine_desc_pool", 427 chan->dev, 428 sizeof(struct fsl_desc_sw), 429 __alignof__(struct fsl_desc_sw), 0); 430 if (!chan->desc_pool) { 431 dev_err(chan->dev, "unable to allocate channel %d " 432 "descriptor pool\n", chan->id); 433 return -ENOMEM; 434 } 435 436 /* there is at least one descriptor free to be allocated */ 437 return 1; 438 } 439 440 /** 441 * fsldma_free_desc_list - Free all descriptors in a queue 442 * @chan: Freescae DMA channel 443 * @list: the list to free 444 * 445 * LOCKING: must hold chan->desc_lock 446 */ 447 static void fsldma_free_desc_list(struct fsldma_chan *chan, 448 struct list_head *list) 449 { 450 struct fsl_desc_sw *desc, *_desc; 451 452 list_for_each_entry_safe(desc, _desc, list, node) { 453 list_del(&desc->node); 454 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); 455 } 456 } 457 458 static void fsldma_free_desc_list_reverse(struct fsldma_chan *chan, 459 struct list_head *list) 460 { 461 struct fsl_desc_sw *desc, *_desc; 462 463 list_for_each_entry_safe_reverse(desc, _desc, list, node) { 464 list_del(&desc->node); 465 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); 466 } 467 } 468 469 /** 470 * fsl_dma_free_chan_resources - Free all resources of the channel. 471 * @chan : Freescale DMA channel 472 */ 473 static void fsl_dma_free_chan_resources(struct dma_chan *dchan) 474 { 475 struct fsldma_chan *chan = to_fsl_chan(dchan); 476 unsigned long flags; 477 478 dev_dbg(chan->dev, "Free all channel resources.\n"); 479 spin_lock_irqsave(&chan->desc_lock, flags); 480 fsldma_free_desc_list(chan, &chan->ld_pending); 481 fsldma_free_desc_list(chan, &chan->ld_running); 482 spin_unlock_irqrestore(&chan->desc_lock, flags); 483 484 dma_pool_destroy(chan->desc_pool); 485 chan->desc_pool = NULL; 486 } 487 488 static struct dma_async_tx_descriptor * 489 fsl_dma_prep_interrupt(struct dma_chan *dchan, unsigned long flags) 490 { 491 struct fsldma_chan *chan; 492 struct fsl_desc_sw *new; 493 494 if (!dchan) 495 return NULL; 496 497 chan = to_fsl_chan(dchan); 498 499 new = fsl_dma_alloc_descriptor(chan); 500 if (!new) { 501 dev_err(chan->dev, "No free memory for link descriptor\n"); 502 return NULL; 503 } 504 505 new->async_tx.cookie = -EBUSY; 506 new->async_tx.flags = flags; 507 508 /* Insert the link descriptor to the LD ring */ 509 list_add_tail(&new->node, &new->tx_list); 510 511 /* Set End-of-link to the last link descriptor of new list*/ 512 set_ld_eol(chan, new); 513 514 return &new->async_tx; 515 } 516 517 static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy( 518 struct dma_chan *dchan, dma_addr_t dma_dst, dma_addr_t dma_src, 519 size_t len, unsigned long flags) 520 { 521 struct fsldma_chan *chan; 522 struct fsl_desc_sw *first = NULL, *prev = NULL, *new; 523 size_t copy; 524 525 if (!dchan) 526 return NULL; 527 528 if (!len) 529 return NULL; 530 531 chan = to_fsl_chan(dchan); 532 533 do { 534 535 /* Allocate the link descriptor from DMA pool */ 536 new = fsl_dma_alloc_descriptor(chan); 537 if (!new) { 538 dev_err(chan->dev, 539 "No free memory for link descriptor\n"); 540 goto fail; 541 } 542 #ifdef FSL_DMA_LD_DEBUG 543 dev_dbg(chan->dev, "new link desc alloc %p\n", new); 544 #endif 545 546 copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT); 547 548 set_desc_cnt(chan, &new->hw, copy); 549 set_desc_src(chan, &new->hw, dma_src); 550 set_desc_dst(chan, &new->hw, dma_dst); 551 552 if (!first) 553 first = new; 554 else 555 set_desc_next(chan, &prev->hw, new->async_tx.phys); 556 557 new->async_tx.cookie = 0; 558 async_tx_ack(&new->async_tx); 559 560 prev = new; 561 len -= copy; 562 dma_src += copy; 563 dma_dst += copy; 564 565 /* Insert the link descriptor to the LD ring */ 566 list_add_tail(&new->node, &first->tx_list); 567 } while (len); 568 569 new->async_tx.flags = flags; /* client is in control of this ack */ 570 new->async_tx.cookie = -EBUSY; 571 572 /* Set End-of-link to the last link descriptor of new list*/ 573 set_ld_eol(chan, new); 574 575 return &first->async_tx; 576 577 fail: 578 if (!first) 579 return NULL; 580 581 fsldma_free_desc_list_reverse(chan, &first->tx_list); 582 return NULL; 583 } 584 585 /** 586 * fsl_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction 587 * @chan: DMA channel 588 * @sgl: scatterlist to transfer to/from 589 * @sg_len: number of entries in @scatterlist 590 * @direction: DMA direction 591 * @flags: DMAEngine flags 592 * 593 * Prepare a set of descriptors for a DMA_SLAVE transaction. Following the 594 * DMA_SLAVE API, this gets the device-specific information from the 595 * chan->private variable. 596 */ 597 static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg( 598 struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len, 599 enum dma_data_direction direction, unsigned long flags) 600 { 601 struct fsldma_chan *chan; 602 struct fsl_desc_sw *first = NULL, *prev = NULL, *new = NULL; 603 struct fsl_dma_slave *slave; 604 size_t copy; 605 606 int i; 607 struct scatterlist *sg; 608 size_t sg_used; 609 size_t hw_used; 610 struct fsl_dma_hw_addr *hw; 611 dma_addr_t dma_dst, dma_src; 612 613 if (!dchan) 614 return NULL; 615 616 if (!dchan->private) 617 return NULL; 618 619 chan = to_fsl_chan(dchan); 620 slave = dchan->private; 621 622 if (list_empty(&slave->addresses)) 623 return NULL; 624 625 hw = list_first_entry(&slave->addresses, struct fsl_dma_hw_addr, entry); 626 hw_used = 0; 627 628 /* 629 * Build the hardware transaction to copy from the scatterlist to 630 * the hardware, or from the hardware to the scatterlist 631 * 632 * If you are copying from the hardware to the scatterlist and it 633 * takes two hardware entries to fill an entire page, then both 634 * hardware entries will be coalesced into the same page 635 * 636 * If you are copying from the scatterlist to the hardware and a 637 * single page can fill two hardware entries, then the data will 638 * be read out of the page into the first hardware entry, and so on 639 */ 640 for_each_sg(sgl, sg, sg_len, i) { 641 sg_used = 0; 642 643 /* Loop until the entire scatterlist entry is used */ 644 while (sg_used < sg_dma_len(sg)) { 645 646 /* 647 * If we've used up the current hardware address/length 648 * pair, we need to load a new one 649 * 650 * This is done in a while loop so that descriptors with 651 * length == 0 will be skipped 652 */ 653 while (hw_used >= hw->length) { 654 655 /* 656 * If the current hardware entry is the last 657 * entry in the list, we're finished 658 */ 659 if (list_is_last(&hw->entry, &slave->addresses)) 660 goto finished; 661 662 /* Get the next hardware address/length pair */ 663 hw = list_entry(hw->entry.next, 664 struct fsl_dma_hw_addr, entry); 665 hw_used = 0; 666 } 667 668 /* Allocate the link descriptor from DMA pool */ 669 new = fsl_dma_alloc_descriptor(chan); 670 if (!new) { 671 dev_err(chan->dev, "No free memory for " 672 "link descriptor\n"); 673 goto fail; 674 } 675 #ifdef FSL_DMA_LD_DEBUG 676 dev_dbg(chan->dev, "new link desc alloc %p\n", new); 677 #endif 678 679 /* 680 * Calculate the maximum number of bytes to transfer, 681 * making sure it is less than the DMA controller limit 682 */ 683 copy = min_t(size_t, sg_dma_len(sg) - sg_used, 684 hw->length - hw_used); 685 copy = min_t(size_t, copy, FSL_DMA_BCR_MAX_CNT); 686 687 /* 688 * DMA_FROM_DEVICE 689 * from the hardware to the scatterlist 690 * 691 * DMA_TO_DEVICE 692 * from the scatterlist to the hardware 693 */ 694 if (direction == DMA_FROM_DEVICE) { 695 dma_src = hw->address + hw_used; 696 dma_dst = sg_dma_address(sg) + sg_used; 697 } else { 698 dma_src = sg_dma_address(sg) + sg_used; 699 dma_dst = hw->address + hw_used; 700 } 701 702 /* Fill in the descriptor */ 703 set_desc_cnt(chan, &new->hw, copy); 704 set_desc_src(chan, &new->hw, dma_src); 705 set_desc_dst(chan, &new->hw, dma_dst); 706 707 /* 708 * If this is not the first descriptor, chain the 709 * current descriptor after the previous descriptor 710 */ 711 if (!first) { 712 first = new; 713 } else { 714 set_desc_next(chan, &prev->hw, 715 new->async_tx.phys); 716 } 717 718 new->async_tx.cookie = 0; 719 async_tx_ack(&new->async_tx); 720 721 prev = new; 722 sg_used += copy; 723 hw_used += copy; 724 725 /* Insert the link descriptor into the LD ring */ 726 list_add_tail(&new->node, &first->tx_list); 727 } 728 } 729 730 finished: 731 732 /* All of the hardware address/length pairs had length == 0 */ 733 if (!first || !new) 734 return NULL; 735 736 new->async_tx.flags = flags; 737 new->async_tx.cookie = -EBUSY; 738 739 /* Set End-of-link to the last link descriptor of new list */ 740 set_ld_eol(chan, new); 741 742 /* Enable extra controller features */ 743 if (chan->set_src_loop_size) 744 chan->set_src_loop_size(chan, slave->src_loop_size); 745 746 if (chan->set_dst_loop_size) 747 chan->set_dst_loop_size(chan, slave->dst_loop_size); 748 749 if (chan->toggle_ext_start) 750 chan->toggle_ext_start(chan, slave->external_start); 751 752 if (chan->toggle_ext_pause) 753 chan->toggle_ext_pause(chan, slave->external_pause); 754 755 if (chan->set_request_count) 756 chan->set_request_count(chan, slave->request_count); 757 758 return &first->async_tx; 759 760 fail: 761 /* If first was not set, then we failed to allocate the very first 762 * descriptor, and we're done */ 763 if (!first) 764 return NULL; 765 766 /* 767 * First is set, so all of the descriptors we allocated have been added 768 * to first->tx_list, INCLUDING "first" itself. Therefore we 769 * must traverse the list backwards freeing each descriptor in turn 770 * 771 * We're re-using variables for the loop, oh well 772 */ 773 fsldma_free_desc_list_reverse(chan, &first->tx_list); 774 return NULL; 775 } 776 777 static int fsl_dma_device_control(struct dma_chan *dchan, 778 enum dma_ctrl_cmd cmd) 779 { 780 struct fsldma_chan *chan; 781 unsigned long flags; 782 783 /* Only supports DMA_TERMINATE_ALL */ 784 if (cmd != DMA_TERMINATE_ALL) 785 return -ENXIO; 786 787 if (!dchan) 788 return -EINVAL; 789 790 chan = to_fsl_chan(dchan); 791 792 /* Halt the DMA engine */ 793 dma_halt(chan); 794 795 spin_lock_irqsave(&chan->desc_lock, flags); 796 797 /* Remove and free all of the descriptors in the LD queue */ 798 fsldma_free_desc_list(chan, &chan->ld_pending); 799 fsldma_free_desc_list(chan, &chan->ld_running); 800 801 spin_unlock_irqrestore(&chan->desc_lock, flags); 802 803 return 0; 804 } 805 806 /** 807 * fsl_dma_update_completed_cookie - Update the completed cookie. 808 * @chan : Freescale DMA channel 809 * 810 * CONTEXT: hardirq 811 */ 812 static void fsl_dma_update_completed_cookie(struct fsldma_chan *chan) 813 { 814 struct fsl_desc_sw *desc; 815 unsigned long flags; 816 dma_cookie_t cookie; 817 818 spin_lock_irqsave(&chan->desc_lock, flags); 819 820 if (list_empty(&chan->ld_running)) { 821 dev_dbg(chan->dev, "no running descriptors\n"); 822 goto out_unlock; 823 } 824 825 /* Get the last descriptor, update the cookie to that */ 826 desc = to_fsl_desc(chan->ld_running.prev); 827 if (dma_is_idle(chan)) 828 cookie = desc->async_tx.cookie; 829 else { 830 cookie = desc->async_tx.cookie - 1; 831 if (unlikely(cookie < DMA_MIN_COOKIE)) 832 cookie = DMA_MAX_COOKIE; 833 } 834 835 chan->completed_cookie = cookie; 836 837 out_unlock: 838 spin_unlock_irqrestore(&chan->desc_lock, flags); 839 } 840 841 /** 842 * fsldma_desc_status - Check the status of a descriptor 843 * @chan: Freescale DMA channel 844 * @desc: DMA SW descriptor 845 * 846 * This function will return the status of the given descriptor 847 */ 848 static enum dma_status fsldma_desc_status(struct fsldma_chan *chan, 849 struct fsl_desc_sw *desc) 850 { 851 return dma_async_is_complete(desc->async_tx.cookie, 852 chan->completed_cookie, 853 chan->common.cookie); 854 } 855 856 /** 857 * fsl_chan_ld_cleanup - Clean up link descriptors 858 * @chan : Freescale DMA channel 859 * 860 * This function clean up the ld_queue of DMA channel. 861 */ 862 static void fsl_chan_ld_cleanup(struct fsldma_chan *chan) 863 { 864 struct fsl_desc_sw *desc, *_desc; 865 unsigned long flags; 866 867 spin_lock_irqsave(&chan->desc_lock, flags); 868 869 dev_dbg(chan->dev, "chan completed_cookie = %d\n", chan->completed_cookie); 870 list_for_each_entry_safe(desc, _desc, &chan->ld_running, node) { 871 dma_async_tx_callback callback; 872 void *callback_param; 873 874 if (fsldma_desc_status(chan, desc) == DMA_IN_PROGRESS) 875 break; 876 877 /* Remove from the list of running transactions */ 878 list_del(&desc->node); 879 880 /* Run the link descriptor callback function */ 881 callback = desc->async_tx.callback; 882 callback_param = desc->async_tx.callback_param; 883 if (callback) { 884 spin_unlock_irqrestore(&chan->desc_lock, flags); 885 dev_dbg(chan->dev, "LD %p callback\n", desc); 886 callback(callback_param); 887 spin_lock_irqsave(&chan->desc_lock, flags); 888 } 889 890 /* Run any dependencies, then free the descriptor */ 891 dma_run_dependencies(&desc->async_tx); 892 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); 893 } 894 895 spin_unlock_irqrestore(&chan->desc_lock, flags); 896 } 897 898 /** 899 * fsl_chan_xfer_ld_queue - transfer any pending transactions 900 * @chan : Freescale DMA channel 901 * 902 * This will make sure that any pending transactions will be run. 903 * If the DMA controller is idle, it will be started. Otherwise, 904 * the DMA controller's interrupt handler will start any pending 905 * transactions when it becomes idle. 906 */ 907 static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan) 908 { 909 struct fsl_desc_sw *desc; 910 unsigned long flags; 911 912 spin_lock_irqsave(&chan->desc_lock, flags); 913 914 /* 915 * If the list of pending descriptors is empty, then we 916 * don't need to do any work at all 917 */ 918 if (list_empty(&chan->ld_pending)) { 919 dev_dbg(chan->dev, "no pending LDs\n"); 920 goto out_unlock; 921 } 922 923 /* 924 * The DMA controller is not idle, which means the interrupt 925 * handler will start any queued transactions when it runs 926 * at the end of the current transaction 927 */ 928 if (!dma_is_idle(chan)) { 929 dev_dbg(chan->dev, "DMA controller still busy\n"); 930 goto out_unlock; 931 } 932 933 /* 934 * TODO: 935 * make sure the dma_halt() function really un-wedges the 936 * controller as much as possible 937 */ 938 dma_halt(chan); 939 940 /* 941 * If there are some link descriptors which have not been 942 * transferred, we need to start the controller 943 */ 944 945 /* 946 * Move all elements from the queue of pending transactions 947 * onto the list of running transactions 948 */ 949 desc = list_first_entry(&chan->ld_pending, struct fsl_desc_sw, node); 950 list_splice_tail_init(&chan->ld_pending, &chan->ld_running); 951 952 /* 953 * Program the descriptor's address into the DMA controller, 954 * then start the DMA transaction 955 */ 956 set_cdar(chan, desc->async_tx.phys); 957 dma_start(chan); 958 959 out_unlock: 960 spin_unlock_irqrestore(&chan->desc_lock, flags); 961 } 962 963 /** 964 * fsl_dma_memcpy_issue_pending - Issue the DMA start command 965 * @chan : Freescale DMA channel 966 */ 967 static void fsl_dma_memcpy_issue_pending(struct dma_chan *dchan) 968 { 969 struct fsldma_chan *chan = to_fsl_chan(dchan); 970 fsl_chan_xfer_ld_queue(chan); 971 } 972 973 /** 974 * fsl_dma_is_complete - Determine the DMA status 975 * @chan : Freescale DMA channel 976 */ 977 static enum dma_status fsl_dma_is_complete(struct dma_chan *dchan, 978 dma_cookie_t cookie, 979 dma_cookie_t *done, 980 dma_cookie_t *used) 981 { 982 struct fsldma_chan *chan = to_fsl_chan(dchan); 983 dma_cookie_t last_used; 984 dma_cookie_t last_complete; 985 986 fsl_chan_ld_cleanup(chan); 987 988 last_used = dchan->cookie; 989 last_complete = chan->completed_cookie; 990 991 if (done) 992 *done = last_complete; 993 994 if (used) 995 *used = last_used; 996 997 return dma_async_is_complete(cookie, last_complete, last_used); 998 } 999 1000 /*----------------------------------------------------------------------------*/ 1001 /* Interrupt Handling */ 1002 /*----------------------------------------------------------------------------*/ 1003 1004 static irqreturn_t fsldma_chan_irq(int irq, void *data) 1005 { 1006 struct fsldma_chan *chan = data; 1007 int update_cookie = 0; 1008 int xfer_ld_q = 0; 1009 u32 stat; 1010 1011 /* save and clear the status register */ 1012 stat = get_sr(chan); 1013 set_sr(chan, stat); 1014 dev_dbg(chan->dev, "irq: channel %d, stat = 0x%x\n", chan->id, stat); 1015 1016 stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH); 1017 if (!stat) 1018 return IRQ_NONE; 1019 1020 if (stat & FSL_DMA_SR_TE) 1021 dev_err(chan->dev, "Transfer Error!\n"); 1022 1023 /* 1024 * Programming Error 1025 * The DMA_INTERRUPT async_tx is a NULL transfer, which will 1026 * triger a PE interrupt. 1027 */ 1028 if (stat & FSL_DMA_SR_PE) { 1029 dev_dbg(chan->dev, "irq: Programming Error INT\n"); 1030 if (get_bcr(chan) == 0) { 1031 /* BCR register is 0, this is a DMA_INTERRUPT async_tx. 1032 * Now, update the completed cookie, and continue the 1033 * next uncompleted transfer. 1034 */ 1035 update_cookie = 1; 1036 xfer_ld_q = 1; 1037 } 1038 stat &= ~FSL_DMA_SR_PE; 1039 } 1040 1041 /* 1042 * If the link descriptor segment transfer finishes, 1043 * we will recycle the used descriptor. 1044 */ 1045 if (stat & FSL_DMA_SR_EOSI) { 1046 dev_dbg(chan->dev, "irq: End-of-segments INT\n"); 1047 dev_dbg(chan->dev, "irq: clndar 0x%llx, nlndar 0x%llx\n", 1048 (unsigned long long)get_cdar(chan), 1049 (unsigned long long)get_ndar(chan)); 1050 stat &= ~FSL_DMA_SR_EOSI; 1051 update_cookie = 1; 1052 } 1053 1054 /* 1055 * For MPC8349, EOCDI event need to update cookie 1056 * and start the next transfer if it exist. 1057 */ 1058 if (stat & FSL_DMA_SR_EOCDI) { 1059 dev_dbg(chan->dev, "irq: End-of-Chain link INT\n"); 1060 stat &= ~FSL_DMA_SR_EOCDI; 1061 update_cookie = 1; 1062 xfer_ld_q = 1; 1063 } 1064 1065 /* 1066 * If it current transfer is the end-of-transfer, 1067 * we should clear the Channel Start bit for 1068 * prepare next transfer. 1069 */ 1070 if (stat & FSL_DMA_SR_EOLNI) { 1071 dev_dbg(chan->dev, "irq: End-of-link INT\n"); 1072 stat &= ~FSL_DMA_SR_EOLNI; 1073 xfer_ld_q = 1; 1074 } 1075 1076 if (update_cookie) 1077 fsl_dma_update_completed_cookie(chan); 1078 if (xfer_ld_q) 1079 fsl_chan_xfer_ld_queue(chan); 1080 if (stat) 1081 dev_dbg(chan->dev, "irq: unhandled sr 0x%02x\n", stat); 1082 1083 dev_dbg(chan->dev, "irq: Exit\n"); 1084 tasklet_schedule(&chan->tasklet); 1085 return IRQ_HANDLED; 1086 } 1087 1088 static void dma_do_tasklet(unsigned long data) 1089 { 1090 struct fsldma_chan *chan = (struct fsldma_chan *)data; 1091 fsl_chan_ld_cleanup(chan); 1092 } 1093 1094 static irqreturn_t fsldma_ctrl_irq(int irq, void *data) 1095 { 1096 struct fsldma_device *fdev = data; 1097 struct fsldma_chan *chan; 1098 unsigned int handled = 0; 1099 u32 gsr, mask; 1100 int i; 1101 1102 gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->regs) 1103 : in_le32(fdev->regs); 1104 mask = 0xff000000; 1105 dev_dbg(fdev->dev, "IRQ: gsr 0x%.8x\n", gsr); 1106 1107 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { 1108 chan = fdev->chan[i]; 1109 if (!chan) 1110 continue; 1111 1112 if (gsr & mask) { 1113 dev_dbg(fdev->dev, "IRQ: chan %d\n", chan->id); 1114 fsldma_chan_irq(irq, chan); 1115 handled++; 1116 } 1117 1118 gsr &= ~mask; 1119 mask >>= 8; 1120 } 1121 1122 return IRQ_RETVAL(handled); 1123 } 1124 1125 static void fsldma_free_irqs(struct fsldma_device *fdev) 1126 { 1127 struct fsldma_chan *chan; 1128 int i; 1129 1130 if (fdev->irq != NO_IRQ) { 1131 dev_dbg(fdev->dev, "free per-controller IRQ\n"); 1132 free_irq(fdev->irq, fdev); 1133 return; 1134 } 1135 1136 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { 1137 chan = fdev->chan[i]; 1138 if (chan && chan->irq != NO_IRQ) { 1139 dev_dbg(fdev->dev, "free channel %d IRQ\n", chan->id); 1140 free_irq(chan->irq, chan); 1141 } 1142 } 1143 } 1144 1145 static int fsldma_request_irqs(struct fsldma_device *fdev) 1146 { 1147 struct fsldma_chan *chan; 1148 int ret; 1149 int i; 1150 1151 /* if we have a per-controller IRQ, use that */ 1152 if (fdev->irq != NO_IRQ) { 1153 dev_dbg(fdev->dev, "request per-controller IRQ\n"); 1154 ret = request_irq(fdev->irq, fsldma_ctrl_irq, IRQF_SHARED, 1155 "fsldma-controller", fdev); 1156 return ret; 1157 } 1158 1159 /* no per-controller IRQ, use the per-channel IRQs */ 1160 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { 1161 chan = fdev->chan[i]; 1162 if (!chan) 1163 continue; 1164 1165 if (chan->irq == NO_IRQ) { 1166 dev_err(fdev->dev, "no interrupts property defined for " 1167 "DMA channel %d. Please fix your " 1168 "device tree\n", chan->id); 1169 ret = -ENODEV; 1170 goto out_unwind; 1171 } 1172 1173 dev_dbg(fdev->dev, "request channel %d IRQ\n", chan->id); 1174 ret = request_irq(chan->irq, fsldma_chan_irq, IRQF_SHARED, 1175 "fsldma-chan", chan); 1176 if (ret) { 1177 dev_err(fdev->dev, "unable to request IRQ for DMA " 1178 "channel %d\n", chan->id); 1179 goto out_unwind; 1180 } 1181 } 1182 1183 return 0; 1184 1185 out_unwind: 1186 for (/* none */; i >= 0; i--) { 1187 chan = fdev->chan[i]; 1188 if (!chan) 1189 continue; 1190 1191 if (chan->irq == NO_IRQ) 1192 continue; 1193 1194 free_irq(chan->irq, chan); 1195 } 1196 1197 return ret; 1198 } 1199 1200 /*----------------------------------------------------------------------------*/ 1201 /* OpenFirmware Subsystem */ 1202 /*----------------------------------------------------------------------------*/ 1203 1204 static int __devinit fsl_dma_chan_probe(struct fsldma_device *fdev, 1205 struct device_node *node, u32 feature, const char *compatible) 1206 { 1207 struct fsldma_chan *chan; 1208 struct resource res; 1209 int err; 1210 1211 /* alloc channel */ 1212 chan = kzalloc(sizeof(*chan), GFP_KERNEL); 1213 if (!chan) { 1214 dev_err(fdev->dev, "no free memory for DMA channels!\n"); 1215 err = -ENOMEM; 1216 goto out_return; 1217 } 1218 1219 /* ioremap registers for use */ 1220 chan->regs = of_iomap(node, 0); 1221 if (!chan->regs) { 1222 dev_err(fdev->dev, "unable to ioremap registers\n"); 1223 err = -ENOMEM; 1224 goto out_free_chan; 1225 } 1226 1227 err = of_address_to_resource(node, 0, &res); 1228 if (err) { 1229 dev_err(fdev->dev, "unable to find 'reg' property\n"); 1230 goto out_iounmap_regs; 1231 } 1232 1233 chan->feature = feature; 1234 if (!fdev->feature) 1235 fdev->feature = chan->feature; 1236 1237 /* 1238 * If the DMA device's feature is different than the feature 1239 * of its channels, report the bug 1240 */ 1241 WARN_ON(fdev->feature != chan->feature); 1242 1243 chan->dev = fdev->dev; 1244 chan->id = ((res.start - 0x100) & 0xfff) >> 7; 1245 if (chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) { 1246 dev_err(fdev->dev, "too many channels for device\n"); 1247 err = -EINVAL; 1248 goto out_iounmap_regs; 1249 } 1250 1251 fdev->chan[chan->id] = chan; 1252 tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan); 1253 1254 /* Initialize the channel */ 1255 dma_init(chan); 1256 1257 /* Clear cdar registers */ 1258 set_cdar(chan, 0); 1259 1260 switch (chan->feature & FSL_DMA_IP_MASK) { 1261 case FSL_DMA_IP_85XX: 1262 chan->toggle_ext_pause = fsl_chan_toggle_ext_pause; 1263 case FSL_DMA_IP_83XX: 1264 chan->toggle_ext_start = fsl_chan_toggle_ext_start; 1265 chan->set_src_loop_size = fsl_chan_set_src_loop_size; 1266 chan->set_dst_loop_size = fsl_chan_set_dst_loop_size; 1267 chan->set_request_count = fsl_chan_set_request_count; 1268 } 1269 1270 spin_lock_init(&chan->desc_lock); 1271 INIT_LIST_HEAD(&chan->ld_pending); 1272 INIT_LIST_HEAD(&chan->ld_running); 1273 1274 chan->common.device = &fdev->common; 1275 1276 /* find the IRQ line, if it exists in the device tree */ 1277 chan->irq = irq_of_parse_and_map(node, 0); 1278 1279 /* Add the channel to DMA device channel list */ 1280 list_add_tail(&chan->common.device_node, &fdev->common.channels); 1281 fdev->common.chancnt++; 1282 1283 dev_info(fdev->dev, "#%d (%s), irq %d\n", chan->id, compatible, 1284 chan->irq != NO_IRQ ? chan->irq : fdev->irq); 1285 1286 return 0; 1287 1288 out_iounmap_regs: 1289 iounmap(chan->regs); 1290 out_free_chan: 1291 kfree(chan); 1292 out_return: 1293 return err; 1294 } 1295 1296 static void fsl_dma_chan_remove(struct fsldma_chan *chan) 1297 { 1298 irq_dispose_mapping(chan->irq); 1299 list_del(&chan->common.device_node); 1300 iounmap(chan->regs); 1301 kfree(chan); 1302 } 1303 1304 static int __devinit fsldma_of_probe(struct of_device *op, 1305 const struct of_device_id *match) 1306 { 1307 struct fsldma_device *fdev; 1308 struct device_node *child; 1309 int err; 1310 1311 fdev = kzalloc(sizeof(*fdev), GFP_KERNEL); 1312 if (!fdev) { 1313 dev_err(&op->dev, "No enough memory for 'priv'\n"); 1314 err = -ENOMEM; 1315 goto out_return; 1316 } 1317 1318 fdev->dev = &op->dev; 1319 INIT_LIST_HEAD(&fdev->common.channels); 1320 1321 /* ioremap the registers for use */ 1322 fdev->regs = of_iomap(op->node, 0); 1323 if (!fdev->regs) { 1324 dev_err(&op->dev, "unable to ioremap registers\n"); 1325 err = -ENOMEM; 1326 goto out_free_fdev; 1327 } 1328 1329 /* map the channel IRQ if it exists, but don't hookup the handler yet */ 1330 fdev->irq = irq_of_parse_and_map(op->node, 0); 1331 1332 dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask); 1333 dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask); 1334 dma_cap_set(DMA_SLAVE, fdev->common.cap_mask); 1335 fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources; 1336 fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources; 1337 fdev->common.device_prep_dma_interrupt = fsl_dma_prep_interrupt; 1338 fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy; 1339 fdev->common.device_is_tx_complete = fsl_dma_is_complete; 1340 fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending; 1341 fdev->common.device_prep_slave_sg = fsl_dma_prep_slave_sg; 1342 fdev->common.device_control = fsl_dma_device_control; 1343 fdev->common.dev = &op->dev; 1344 1345 dev_set_drvdata(&op->dev, fdev); 1346 1347 /* 1348 * We cannot use of_platform_bus_probe() because there is no 1349 * of_platform_bus_remove(). Instead, we manually instantiate every DMA 1350 * channel object. 1351 */ 1352 for_each_child_of_node(op->node, child) { 1353 if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) { 1354 fsl_dma_chan_probe(fdev, child, 1355 FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN, 1356 "fsl,eloplus-dma-channel"); 1357 } 1358 1359 if (of_device_is_compatible(child, "fsl,elo-dma-channel")) { 1360 fsl_dma_chan_probe(fdev, child, 1361 FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN, 1362 "fsl,elo-dma-channel"); 1363 } 1364 } 1365 1366 /* 1367 * Hookup the IRQ handler(s) 1368 * 1369 * If we have a per-controller interrupt, we prefer that to the 1370 * per-channel interrupts to reduce the number of shared interrupt 1371 * handlers on the same IRQ line 1372 */ 1373 err = fsldma_request_irqs(fdev); 1374 if (err) { 1375 dev_err(fdev->dev, "unable to request IRQs\n"); 1376 goto out_free_fdev; 1377 } 1378 1379 dma_async_device_register(&fdev->common); 1380 return 0; 1381 1382 out_free_fdev: 1383 irq_dispose_mapping(fdev->irq); 1384 kfree(fdev); 1385 out_return: 1386 return err; 1387 } 1388 1389 static int fsldma_of_remove(struct of_device *op) 1390 { 1391 struct fsldma_device *fdev; 1392 unsigned int i; 1393 1394 fdev = dev_get_drvdata(&op->dev); 1395 dma_async_device_unregister(&fdev->common); 1396 1397 fsldma_free_irqs(fdev); 1398 1399 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { 1400 if (fdev->chan[i]) 1401 fsl_dma_chan_remove(fdev->chan[i]); 1402 } 1403 1404 iounmap(fdev->regs); 1405 dev_set_drvdata(&op->dev, NULL); 1406 kfree(fdev); 1407 1408 return 0; 1409 } 1410 1411 static const struct of_device_id fsldma_of_ids[] = { 1412 { .compatible = "fsl,eloplus-dma", }, 1413 { .compatible = "fsl,elo-dma", }, 1414 {} 1415 }; 1416 1417 static struct of_platform_driver fsldma_of_driver = { 1418 .name = "fsl-elo-dma", 1419 .match_table = fsldma_of_ids, 1420 .probe = fsldma_of_probe, 1421 .remove = fsldma_of_remove, 1422 }; 1423 1424 /*----------------------------------------------------------------------------*/ 1425 /* Module Init / Exit */ 1426 /*----------------------------------------------------------------------------*/ 1427 1428 static __init int fsldma_init(void) 1429 { 1430 int ret; 1431 1432 pr_info("Freescale Elo / Elo Plus DMA driver\n"); 1433 1434 ret = of_register_platform_driver(&fsldma_of_driver); 1435 if (ret) 1436 pr_err("fsldma: failed to register platform driver\n"); 1437 1438 return ret; 1439 } 1440 1441 static void __exit fsldma_exit(void) 1442 { 1443 of_unregister_platform_driver(&fsldma_of_driver); 1444 } 1445 1446 subsys_initcall(fsldma_init); 1447 module_exit(fsldma_exit); 1448 1449 MODULE_DESCRIPTION("Freescale Elo / Elo Plus DMA driver"); 1450 MODULE_LICENSE("GPL"); 1451