1173acc7cSZhang Wei /* 2173acc7cSZhang Wei * Freescale MPC85xx, MPC83xx DMA Engine support 3173acc7cSZhang Wei * 4173acc7cSZhang Wei * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved. 5173acc7cSZhang Wei * 6173acc7cSZhang Wei * Author: 7173acc7cSZhang Wei * Zhang Wei <wei.zhang@freescale.com>, Jul 2007 8173acc7cSZhang Wei * Ebony Zhu <ebony.zhu@freescale.com>, May 2007 9173acc7cSZhang Wei * 10173acc7cSZhang Wei * Description: 11173acc7cSZhang Wei * DMA engine driver for Freescale MPC8540 DMA controller, which is 12173acc7cSZhang Wei * also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc. 13173acc7cSZhang Wei * The support for MPC8349 DMA contorller is also added. 14173acc7cSZhang Wei * 15173acc7cSZhang Wei * This is free software; you can redistribute it and/or modify 16173acc7cSZhang Wei * it under the terms of the GNU General Public License as published by 17173acc7cSZhang Wei * the Free Software Foundation; either version 2 of the License, or 18173acc7cSZhang Wei * (at your option) any later version. 19173acc7cSZhang Wei * 20173acc7cSZhang Wei */ 21173acc7cSZhang Wei 22173acc7cSZhang Wei #include <linux/init.h> 23173acc7cSZhang Wei #include <linux/module.h> 24173acc7cSZhang Wei #include <linux/pci.h> 25173acc7cSZhang Wei #include <linux/interrupt.h> 26173acc7cSZhang Wei #include <linux/dmaengine.h> 27173acc7cSZhang Wei #include <linux/delay.h> 28173acc7cSZhang Wei #include <linux/dma-mapping.h> 29173acc7cSZhang Wei #include <linux/dmapool.h> 30173acc7cSZhang Wei #include <linux/of_platform.h> 31173acc7cSZhang Wei 32173acc7cSZhang Wei #include "fsldma.h" 33173acc7cSZhang Wei 34173acc7cSZhang Wei static void dma_init(struct fsl_dma_chan *fsl_chan) 35173acc7cSZhang Wei { 36173acc7cSZhang Wei /* Reset the channel */ 37173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 0, 32); 38173acc7cSZhang Wei 39173acc7cSZhang Wei switch (fsl_chan->feature & FSL_DMA_IP_MASK) { 40173acc7cSZhang Wei case FSL_DMA_IP_85XX: 41173acc7cSZhang Wei /* Set the channel to below modes: 42173acc7cSZhang Wei * EIE - Error interrupt enable 43173acc7cSZhang Wei * EOSIE - End of segments interrupt enable (basic mode) 44173acc7cSZhang Wei * EOLNIE - End of links interrupt enable 45173acc7cSZhang Wei */ 46173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, FSL_DMA_MR_EIE 47173acc7cSZhang Wei | FSL_DMA_MR_EOLNIE | FSL_DMA_MR_EOSIE, 32); 48173acc7cSZhang Wei break; 49173acc7cSZhang Wei case FSL_DMA_IP_83XX: 50173acc7cSZhang Wei /* Set the channel to below modes: 51173acc7cSZhang Wei * EOTIE - End-of-transfer interrupt enable 52173acc7cSZhang Wei */ 53173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, FSL_DMA_MR_EOTIE, 54173acc7cSZhang Wei 32); 55173acc7cSZhang Wei break; 56173acc7cSZhang Wei } 57173acc7cSZhang Wei 58173acc7cSZhang Wei } 59173acc7cSZhang Wei 6056822843SZhang Wei static void set_sr(struct fsl_dma_chan *fsl_chan, u32 val) 61173acc7cSZhang Wei { 62173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->sr, val, 32); 63173acc7cSZhang Wei } 64173acc7cSZhang Wei 6556822843SZhang Wei static u32 get_sr(struct fsl_dma_chan *fsl_chan) 66173acc7cSZhang Wei { 67173acc7cSZhang Wei return DMA_IN(fsl_chan, &fsl_chan->reg_base->sr, 32); 68173acc7cSZhang Wei } 69173acc7cSZhang Wei 70173acc7cSZhang Wei static void set_desc_cnt(struct fsl_dma_chan *fsl_chan, 71173acc7cSZhang Wei struct fsl_dma_ld_hw *hw, u32 count) 72173acc7cSZhang Wei { 73173acc7cSZhang Wei hw->count = CPU_TO_DMA(fsl_chan, count, 32); 74173acc7cSZhang Wei } 75173acc7cSZhang Wei 76173acc7cSZhang Wei static void set_desc_src(struct fsl_dma_chan *fsl_chan, 77173acc7cSZhang Wei struct fsl_dma_ld_hw *hw, dma_addr_t src) 78173acc7cSZhang Wei { 79173acc7cSZhang Wei u64 snoop_bits; 80173acc7cSZhang Wei 81173acc7cSZhang Wei snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) 82173acc7cSZhang Wei ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0; 83173acc7cSZhang Wei hw->src_addr = CPU_TO_DMA(fsl_chan, snoop_bits | src, 64); 84173acc7cSZhang Wei } 85173acc7cSZhang Wei 86173acc7cSZhang Wei static void set_desc_dest(struct fsl_dma_chan *fsl_chan, 87173acc7cSZhang Wei struct fsl_dma_ld_hw *hw, dma_addr_t dest) 88173acc7cSZhang Wei { 89173acc7cSZhang Wei u64 snoop_bits; 90173acc7cSZhang Wei 91173acc7cSZhang Wei snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) 92173acc7cSZhang Wei ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0; 93173acc7cSZhang Wei hw->dst_addr = CPU_TO_DMA(fsl_chan, snoop_bits | dest, 64); 94173acc7cSZhang Wei } 95173acc7cSZhang Wei 96173acc7cSZhang Wei static void set_desc_next(struct fsl_dma_chan *fsl_chan, 97173acc7cSZhang Wei struct fsl_dma_ld_hw *hw, dma_addr_t next) 98173acc7cSZhang Wei { 99173acc7cSZhang Wei u64 snoop_bits; 100173acc7cSZhang Wei 101173acc7cSZhang Wei snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) 102173acc7cSZhang Wei ? FSL_DMA_SNEN : 0; 103173acc7cSZhang Wei hw->next_ln_addr = CPU_TO_DMA(fsl_chan, snoop_bits | next, 64); 104173acc7cSZhang Wei } 105173acc7cSZhang Wei 106173acc7cSZhang Wei static void set_cdar(struct fsl_dma_chan *fsl_chan, dma_addr_t addr) 107173acc7cSZhang Wei { 108173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->cdar, addr | FSL_DMA_SNEN, 64); 109173acc7cSZhang Wei } 110173acc7cSZhang Wei 111173acc7cSZhang Wei static dma_addr_t get_cdar(struct fsl_dma_chan *fsl_chan) 112173acc7cSZhang Wei { 113173acc7cSZhang Wei return DMA_IN(fsl_chan, &fsl_chan->reg_base->cdar, 64) & ~FSL_DMA_SNEN; 114173acc7cSZhang Wei } 115173acc7cSZhang Wei 116173acc7cSZhang Wei static void set_ndar(struct fsl_dma_chan *fsl_chan, dma_addr_t addr) 117173acc7cSZhang Wei { 118173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->ndar, addr, 64); 119173acc7cSZhang Wei } 120173acc7cSZhang Wei 121173acc7cSZhang Wei static dma_addr_t get_ndar(struct fsl_dma_chan *fsl_chan) 122173acc7cSZhang Wei { 123173acc7cSZhang Wei return DMA_IN(fsl_chan, &fsl_chan->reg_base->ndar, 64); 124173acc7cSZhang Wei } 125173acc7cSZhang Wei 126f79abb62SZhang Wei static u32 get_bcr(struct fsl_dma_chan *fsl_chan) 127f79abb62SZhang Wei { 128f79abb62SZhang Wei return DMA_IN(fsl_chan, &fsl_chan->reg_base->bcr, 32); 129f79abb62SZhang Wei } 130f79abb62SZhang Wei 131173acc7cSZhang Wei static int dma_is_idle(struct fsl_dma_chan *fsl_chan) 132173acc7cSZhang Wei { 133173acc7cSZhang Wei u32 sr = get_sr(fsl_chan); 134173acc7cSZhang Wei return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH); 135173acc7cSZhang Wei } 136173acc7cSZhang Wei 137173acc7cSZhang Wei static void dma_start(struct fsl_dma_chan *fsl_chan) 138173acc7cSZhang Wei { 139173acc7cSZhang Wei u32 mr_set = 0;; 140173acc7cSZhang Wei 141173acc7cSZhang Wei if (fsl_chan->feature & FSL_DMA_CHAN_PAUSE_EXT) { 142173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->bcr, 0, 32); 143173acc7cSZhang Wei mr_set |= FSL_DMA_MR_EMP_EN; 144173acc7cSZhang Wei } else 145173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 146173acc7cSZhang Wei DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) 147173acc7cSZhang Wei & ~FSL_DMA_MR_EMP_EN, 32); 148173acc7cSZhang Wei 149173acc7cSZhang Wei if (fsl_chan->feature & FSL_DMA_CHAN_START_EXT) 150173acc7cSZhang Wei mr_set |= FSL_DMA_MR_EMS_EN; 151173acc7cSZhang Wei else 152173acc7cSZhang Wei mr_set |= FSL_DMA_MR_CS; 153173acc7cSZhang Wei 154173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 155173acc7cSZhang Wei DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) 156173acc7cSZhang Wei | mr_set, 32); 157173acc7cSZhang Wei } 158173acc7cSZhang Wei 159173acc7cSZhang Wei static void dma_halt(struct fsl_dma_chan *fsl_chan) 160173acc7cSZhang Wei { 161173acc7cSZhang Wei int i = 0; 162173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 163173acc7cSZhang Wei DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) | FSL_DMA_MR_CA, 164173acc7cSZhang Wei 32); 165173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 166173acc7cSZhang Wei DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) & ~(FSL_DMA_MR_CS 167173acc7cSZhang Wei | FSL_DMA_MR_EMS_EN | FSL_DMA_MR_CA), 32); 168173acc7cSZhang Wei 169173acc7cSZhang Wei while (!dma_is_idle(fsl_chan) && (i++ < 100)) 170173acc7cSZhang Wei udelay(10); 171173acc7cSZhang Wei if (i >= 100 && !dma_is_idle(fsl_chan)) 172173acc7cSZhang Wei dev_err(fsl_chan->dev, "DMA halt timeout!\n"); 173173acc7cSZhang Wei } 174173acc7cSZhang Wei 175173acc7cSZhang Wei static void set_ld_eol(struct fsl_dma_chan *fsl_chan, 176173acc7cSZhang Wei struct fsl_desc_sw *desc) 177173acc7cSZhang Wei { 178173acc7cSZhang Wei desc->hw.next_ln_addr = CPU_TO_DMA(fsl_chan, 179173acc7cSZhang Wei DMA_TO_CPU(fsl_chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL, 180173acc7cSZhang Wei 64); 181173acc7cSZhang Wei } 182173acc7cSZhang Wei 183173acc7cSZhang Wei static void append_ld_queue(struct fsl_dma_chan *fsl_chan, 184173acc7cSZhang Wei struct fsl_desc_sw *new_desc) 185173acc7cSZhang Wei { 186173acc7cSZhang Wei struct fsl_desc_sw *queue_tail = to_fsl_desc(fsl_chan->ld_queue.prev); 187173acc7cSZhang Wei 188173acc7cSZhang Wei if (list_empty(&fsl_chan->ld_queue)) 189173acc7cSZhang Wei return; 190173acc7cSZhang Wei 191173acc7cSZhang Wei /* Link to the new descriptor physical address and 192173acc7cSZhang Wei * Enable End-of-segment interrupt for 193173acc7cSZhang Wei * the last link descriptor. 194173acc7cSZhang Wei * (the previous node's next link descriptor) 195173acc7cSZhang Wei * 196173acc7cSZhang Wei * For FSL_DMA_IP_83xx, the snoop enable bit need be set. 197173acc7cSZhang Wei */ 198173acc7cSZhang Wei queue_tail->hw.next_ln_addr = CPU_TO_DMA(fsl_chan, 199173acc7cSZhang Wei new_desc->async_tx.phys | FSL_DMA_EOSIE | 200173acc7cSZhang Wei (((fsl_chan->feature & FSL_DMA_IP_MASK) 201173acc7cSZhang Wei == FSL_DMA_IP_83XX) ? FSL_DMA_SNEN : 0), 64); 202173acc7cSZhang Wei } 203173acc7cSZhang Wei 204173acc7cSZhang Wei /** 205173acc7cSZhang Wei * fsl_chan_set_src_loop_size - Set source address hold transfer size 206173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 207173acc7cSZhang Wei * @size : Address loop size, 0 for disable loop 208173acc7cSZhang Wei * 209173acc7cSZhang Wei * The set source address hold transfer size. The source 210173acc7cSZhang Wei * address hold or loop transfer size is when the DMA transfer 211173acc7cSZhang Wei * data from source address (SA), if the loop size is 4, the DMA will 212173acc7cSZhang Wei * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA, 213173acc7cSZhang Wei * SA + 1 ... and so on. 214173acc7cSZhang Wei */ 215173acc7cSZhang Wei static void fsl_chan_set_src_loop_size(struct fsl_dma_chan *fsl_chan, int size) 216173acc7cSZhang Wei { 217173acc7cSZhang Wei switch (size) { 218173acc7cSZhang Wei case 0: 219173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 220173acc7cSZhang Wei DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) & 221173acc7cSZhang Wei (~FSL_DMA_MR_SAHE), 32); 222173acc7cSZhang Wei break; 223173acc7cSZhang Wei case 1: 224173acc7cSZhang Wei case 2: 225173acc7cSZhang Wei case 4: 226173acc7cSZhang Wei case 8: 227173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 228173acc7cSZhang Wei DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) | 229173acc7cSZhang Wei FSL_DMA_MR_SAHE | (__ilog2(size) << 14), 230173acc7cSZhang Wei 32); 231173acc7cSZhang Wei break; 232173acc7cSZhang Wei } 233173acc7cSZhang Wei } 234173acc7cSZhang Wei 235173acc7cSZhang Wei /** 236173acc7cSZhang Wei * fsl_chan_set_dest_loop_size - Set destination address hold transfer size 237173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 238173acc7cSZhang Wei * @size : Address loop size, 0 for disable loop 239173acc7cSZhang Wei * 240173acc7cSZhang Wei * The set destination address hold transfer size. The destination 241173acc7cSZhang Wei * address hold or loop transfer size is when the DMA transfer 242173acc7cSZhang Wei * data to destination address (TA), if the loop size is 4, the DMA will 243173acc7cSZhang Wei * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA, 244173acc7cSZhang Wei * TA + 1 ... and so on. 245173acc7cSZhang Wei */ 246173acc7cSZhang Wei static void fsl_chan_set_dest_loop_size(struct fsl_dma_chan *fsl_chan, int size) 247173acc7cSZhang Wei { 248173acc7cSZhang Wei switch (size) { 249173acc7cSZhang Wei case 0: 250173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 251173acc7cSZhang Wei DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) & 252173acc7cSZhang Wei (~FSL_DMA_MR_DAHE), 32); 253173acc7cSZhang Wei break; 254173acc7cSZhang Wei case 1: 255173acc7cSZhang Wei case 2: 256173acc7cSZhang Wei case 4: 257173acc7cSZhang Wei case 8: 258173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 259173acc7cSZhang Wei DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) | 260173acc7cSZhang Wei FSL_DMA_MR_DAHE | (__ilog2(size) << 16), 261173acc7cSZhang Wei 32); 262173acc7cSZhang Wei break; 263173acc7cSZhang Wei } 264173acc7cSZhang Wei } 265173acc7cSZhang Wei 266173acc7cSZhang Wei /** 267173acc7cSZhang Wei * fsl_chan_toggle_ext_pause - Toggle channel external pause status 268173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 269173acc7cSZhang Wei * @size : Pause control size, 0 for disable external pause control. 270173acc7cSZhang Wei * The maximum is 1024. 271173acc7cSZhang Wei * 272173acc7cSZhang Wei * The Freescale DMA channel can be controlled by the external 273173acc7cSZhang Wei * signal DREQ#. The pause control size is how many bytes are allowed 274173acc7cSZhang Wei * to transfer before pausing the channel, after which a new assertion 275173acc7cSZhang Wei * of DREQ# resumes channel operation. 276173acc7cSZhang Wei */ 277173acc7cSZhang Wei static void fsl_chan_toggle_ext_pause(struct fsl_dma_chan *fsl_chan, int size) 278173acc7cSZhang Wei { 279173acc7cSZhang Wei if (size > 1024) 280173acc7cSZhang Wei return; 281173acc7cSZhang Wei 282173acc7cSZhang Wei if (size) { 283173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 284173acc7cSZhang Wei DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) 285173acc7cSZhang Wei | ((__ilog2(size) << 24) & 0x0f000000), 286173acc7cSZhang Wei 32); 287173acc7cSZhang Wei fsl_chan->feature |= FSL_DMA_CHAN_PAUSE_EXT; 288173acc7cSZhang Wei } else 289173acc7cSZhang Wei fsl_chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT; 290173acc7cSZhang Wei } 291173acc7cSZhang Wei 292173acc7cSZhang Wei /** 293173acc7cSZhang Wei * fsl_chan_toggle_ext_start - Toggle channel external start status 294173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 295173acc7cSZhang Wei * @enable : 0 is disabled, 1 is enabled. 296173acc7cSZhang Wei * 297173acc7cSZhang Wei * If enable the external start, the channel can be started by an 298173acc7cSZhang Wei * external DMA start pin. So the dma_start() does not start the 299173acc7cSZhang Wei * transfer immediately. The DMA channel will wait for the 300173acc7cSZhang Wei * control pin asserted. 301173acc7cSZhang Wei */ 302173acc7cSZhang Wei static void fsl_chan_toggle_ext_start(struct fsl_dma_chan *fsl_chan, int enable) 303173acc7cSZhang Wei { 304173acc7cSZhang Wei if (enable) 305173acc7cSZhang Wei fsl_chan->feature |= FSL_DMA_CHAN_START_EXT; 306173acc7cSZhang Wei else 307173acc7cSZhang Wei fsl_chan->feature &= ~FSL_DMA_CHAN_START_EXT; 308173acc7cSZhang Wei } 309173acc7cSZhang Wei 310173acc7cSZhang Wei static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx) 311173acc7cSZhang Wei { 312173acc7cSZhang Wei struct fsl_desc_sw *desc = tx_to_fsl_desc(tx); 313173acc7cSZhang Wei struct fsl_dma_chan *fsl_chan = to_fsl_chan(tx->chan); 314173acc7cSZhang Wei unsigned long flags; 315173acc7cSZhang Wei dma_cookie_t cookie; 316173acc7cSZhang Wei 317173acc7cSZhang Wei /* cookie increment and adding to ld_queue must be atomic */ 318173acc7cSZhang Wei spin_lock_irqsave(&fsl_chan->desc_lock, flags); 319173acc7cSZhang Wei 320173acc7cSZhang Wei cookie = fsl_chan->common.cookie; 321173acc7cSZhang Wei cookie++; 322173acc7cSZhang Wei if (cookie < 0) 323173acc7cSZhang Wei cookie = 1; 324173acc7cSZhang Wei desc->async_tx.cookie = cookie; 325173acc7cSZhang Wei fsl_chan->common.cookie = desc->async_tx.cookie; 326173acc7cSZhang Wei 327173acc7cSZhang Wei append_ld_queue(fsl_chan, desc); 328173acc7cSZhang Wei list_splice_init(&desc->async_tx.tx_list, fsl_chan->ld_queue.prev); 329173acc7cSZhang Wei 330173acc7cSZhang Wei spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); 331173acc7cSZhang Wei 332173acc7cSZhang Wei return cookie; 333173acc7cSZhang Wei } 334173acc7cSZhang Wei 335173acc7cSZhang Wei /** 336173acc7cSZhang Wei * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool. 337173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 338173acc7cSZhang Wei * 339173acc7cSZhang Wei * Return - The descriptor allocated. NULL for failed. 340173acc7cSZhang Wei */ 341173acc7cSZhang Wei static struct fsl_desc_sw *fsl_dma_alloc_descriptor( 342173acc7cSZhang Wei struct fsl_dma_chan *fsl_chan) 343173acc7cSZhang Wei { 344173acc7cSZhang Wei dma_addr_t pdesc; 345173acc7cSZhang Wei struct fsl_desc_sw *desc_sw; 346173acc7cSZhang Wei 347173acc7cSZhang Wei desc_sw = dma_pool_alloc(fsl_chan->desc_pool, GFP_ATOMIC, &pdesc); 348173acc7cSZhang Wei if (desc_sw) { 349173acc7cSZhang Wei memset(desc_sw, 0, sizeof(struct fsl_desc_sw)); 350173acc7cSZhang Wei dma_async_tx_descriptor_init(&desc_sw->async_tx, 351173acc7cSZhang Wei &fsl_chan->common); 352173acc7cSZhang Wei desc_sw->async_tx.tx_submit = fsl_dma_tx_submit; 353173acc7cSZhang Wei INIT_LIST_HEAD(&desc_sw->async_tx.tx_list); 354173acc7cSZhang Wei desc_sw->async_tx.phys = pdesc; 355173acc7cSZhang Wei } 356173acc7cSZhang Wei 357173acc7cSZhang Wei return desc_sw; 358173acc7cSZhang Wei } 359173acc7cSZhang Wei 360173acc7cSZhang Wei 361173acc7cSZhang Wei /** 362173acc7cSZhang Wei * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel. 363173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 364173acc7cSZhang Wei * 365173acc7cSZhang Wei * This function will create a dma pool for descriptor allocation. 366173acc7cSZhang Wei * 367173acc7cSZhang Wei * Return - The number of descriptors allocated. 368173acc7cSZhang Wei */ 369173acc7cSZhang Wei static int fsl_dma_alloc_chan_resources(struct dma_chan *chan) 370173acc7cSZhang Wei { 371173acc7cSZhang Wei struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan); 372173acc7cSZhang Wei LIST_HEAD(tmp_list); 373173acc7cSZhang Wei 374173acc7cSZhang Wei /* We need the descriptor to be aligned to 32bytes 375173acc7cSZhang Wei * for meeting FSL DMA specification requirement. 376173acc7cSZhang Wei */ 377173acc7cSZhang Wei fsl_chan->desc_pool = dma_pool_create("fsl_dma_engine_desc_pool", 378173acc7cSZhang Wei fsl_chan->dev, sizeof(struct fsl_desc_sw), 379173acc7cSZhang Wei 32, 0); 380173acc7cSZhang Wei if (!fsl_chan->desc_pool) { 381173acc7cSZhang Wei dev_err(fsl_chan->dev, "No memory for channel %d " 382173acc7cSZhang Wei "descriptor dma pool.\n", fsl_chan->id); 383173acc7cSZhang Wei return 0; 384173acc7cSZhang Wei } 385173acc7cSZhang Wei 386173acc7cSZhang Wei return 1; 387173acc7cSZhang Wei } 388173acc7cSZhang Wei 389173acc7cSZhang Wei /** 390173acc7cSZhang Wei * fsl_dma_free_chan_resources - Free all resources of the channel. 391173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 392173acc7cSZhang Wei */ 393173acc7cSZhang Wei static void fsl_dma_free_chan_resources(struct dma_chan *chan) 394173acc7cSZhang Wei { 395173acc7cSZhang Wei struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan); 396173acc7cSZhang Wei struct fsl_desc_sw *desc, *_desc; 397173acc7cSZhang Wei unsigned long flags; 398173acc7cSZhang Wei 399173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "Free all channel resources.\n"); 400173acc7cSZhang Wei spin_lock_irqsave(&fsl_chan->desc_lock, flags); 401173acc7cSZhang Wei list_for_each_entry_safe(desc, _desc, &fsl_chan->ld_queue, node) { 402173acc7cSZhang Wei #ifdef FSL_DMA_LD_DEBUG 403173acc7cSZhang Wei dev_dbg(fsl_chan->dev, 404173acc7cSZhang Wei "LD %p will be released.\n", desc); 405173acc7cSZhang Wei #endif 406173acc7cSZhang Wei list_del(&desc->node); 407173acc7cSZhang Wei /* free link descriptor */ 408173acc7cSZhang Wei dma_pool_free(fsl_chan->desc_pool, desc, desc->async_tx.phys); 409173acc7cSZhang Wei } 410173acc7cSZhang Wei spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); 411173acc7cSZhang Wei dma_pool_destroy(fsl_chan->desc_pool); 412173acc7cSZhang Wei } 413173acc7cSZhang Wei 4142187c269SZhang Wei static struct dma_async_tx_descriptor * 4152187c269SZhang Wei fsl_dma_prep_interrupt(struct dma_chan *chan) 4162187c269SZhang Wei { 4172187c269SZhang Wei struct fsl_dma_chan *fsl_chan; 4182187c269SZhang Wei struct fsl_desc_sw *new; 4192187c269SZhang Wei 4202187c269SZhang Wei if (!chan) 4212187c269SZhang Wei return NULL; 4222187c269SZhang Wei 4232187c269SZhang Wei fsl_chan = to_fsl_chan(chan); 4242187c269SZhang Wei 4252187c269SZhang Wei new = fsl_dma_alloc_descriptor(fsl_chan); 4262187c269SZhang Wei if (!new) { 4272187c269SZhang Wei dev_err(fsl_chan->dev, "No free memory for link descriptor\n"); 4282187c269SZhang Wei return NULL; 4292187c269SZhang Wei } 4302187c269SZhang Wei 4312187c269SZhang Wei new->async_tx.cookie = -EBUSY; 4322187c269SZhang Wei new->async_tx.ack = 0; 4332187c269SZhang Wei 434f79abb62SZhang Wei /* Insert the link descriptor to the LD ring */ 435f79abb62SZhang Wei list_add_tail(&new->node, &new->async_tx.tx_list); 436f79abb62SZhang Wei 4372187c269SZhang Wei /* Set End-of-link to the last link descriptor of new list*/ 4382187c269SZhang Wei set_ld_eol(fsl_chan, new); 4392187c269SZhang Wei 4402187c269SZhang Wei return &new->async_tx; 4412187c269SZhang Wei } 4422187c269SZhang Wei 443173acc7cSZhang Wei static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy( 444173acc7cSZhang Wei struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src, 445173acc7cSZhang Wei size_t len, unsigned long flags) 446173acc7cSZhang Wei { 447173acc7cSZhang Wei struct fsl_dma_chan *fsl_chan; 448173acc7cSZhang Wei struct fsl_desc_sw *first = NULL, *prev = NULL, *new; 449173acc7cSZhang Wei size_t copy; 450173acc7cSZhang Wei LIST_HEAD(link_chain); 451173acc7cSZhang Wei 452173acc7cSZhang Wei if (!chan) 453173acc7cSZhang Wei return NULL; 454173acc7cSZhang Wei 455173acc7cSZhang Wei if (!len) 456173acc7cSZhang Wei return NULL; 457173acc7cSZhang Wei 458173acc7cSZhang Wei fsl_chan = to_fsl_chan(chan); 459173acc7cSZhang Wei 460173acc7cSZhang Wei do { 461173acc7cSZhang Wei 462173acc7cSZhang Wei /* Allocate the link descriptor from DMA pool */ 463173acc7cSZhang Wei new = fsl_dma_alloc_descriptor(fsl_chan); 464173acc7cSZhang Wei if (!new) { 465173acc7cSZhang Wei dev_err(fsl_chan->dev, 466173acc7cSZhang Wei "No free memory for link descriptor\n"); 467173acc7cSZhang Wei return NULL; 468173acc7cSZhang Wei } 469173acc7cSZhang Wei #ifdef FSL_DMA_LD_DEBUG 470173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "new link desc alloc %p\n", new); 471173acc7cSZhang Wei #endif 472173acc7cSZhang Wei 47356822843SZhang Wei copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT); 474173acc7cSZhang Wei 475173acc7cSZhang Wei set_desc_cnt(fsl_chan, &new->hw, copy); 476173acc7cSZhang Wei set_desc_src(fsl_chan, &new->hw, dma_src); 477173acc7cSZhang Wei set_desc_dest(fsl_chan, &new->hw, dma_dest); 478173acc7cSZhang Wei 479173acc7cSZhang Wei if (!first) 480173acc7cSZhang Wei first = new; 481173acc7cSZhang Wei else 482173acc7cSZhang Wei set_desc_next(fsl_chan, &prev->hw, new->async_tx.phys); 483173acc7cSZhang Wei 484173acc7cSZhang Wei new->async_tx.cookie = 0; 485173acc7cSZhang Wei new->async_tx.ack = 1; 486173acc7cSZhang Wei 487173acc7cSZhang Wei prev = new; 488173acc7cSZhang Wei len -= copy; 489173acc7cSZhang Wei dma_src += copy; 490173acc7cSZhang Wei dma_dest += copy; 491173acc7cSZhang Wei 492173acc7cSZhang Wei /* Insert the link descriptor to the LD ring */ 493173acc7cSZhang Wei list_add_tail(&new->node, &first->async_tx.tx_list); 494173acc7cSZhang Wei } while (len); 495173acc7cSZhang Wei 496173acc7cSZhang Wei new->async_tx.ack = 0; /* client is in control of this ack */ 497173acc7cSZhang Wei new->async_tx.cookie = -EBUSY; 498173acc7cSZhang Wei 499173acc7cSZhang Wei /* Set End-of-link to the last link descriptor of new list*/ 500173acc7cSZhang Wei set_ld_eol(fsl_chan, new); 501173acc7cSZhang Wei 502173acc7cSZhang Wei return first ? &first->async_tx : NULL; 503173acc7cSZhang Wei } 504173acc7cSZhang Wei 505173acc7cSZhang Wei /** 506173acc7cSZhang Wei * fsl_dma_update_completed_cookie - Update the completed cookie. 507173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 508173acc7cSZhang Wei */ 509173acc7cSZhang Wei static void fsl_dma_update_completed_cookie(struct fsl_dma_chan *fsl_chan) 510173acc7cSZhang Wei { 511173acc7cSZhang Wei struct fsl_desc_sw *cur_desc, *desc; 512173acc7cSZhang Wei dma_addr_t ld_phy; 513173acc7cSZhang Wei 514173acc7cSZhang Wei ld_phy = get_cdar(fsl_chan) & FSL_DMA_NLDA_MASK; 515173acc7cSZhang Wei 516173acc7cSZhang Wei if (ld_phy) { 517173acc7cSZhang Wei cur_desc = NULL; 518173acc7cSZhang Wei list_for_each_entry(desc, &fsl_chan->ld_queue, node) 519173acc7cSZhang Wei if (desc->async_tx.phys == ld_phy) { 520173acc7cSZhang Wei cur_desc = desc; 521173acc7cSZhang Wei break; 522173acc7cSZhang Wei } 523173acc7cSZhang Wei 524173acc7cSZhang Wei if (cur_desc && cur_desc->async_tx.cookie) { 525173acc7cSZhang Wei if (dma_is_idle(fsl_chan)) 526173acc7cSZhang Wei fsl_chan->completed_cookie = 527173acc7cSZhang Wei cur_desc->async_tx.cookie; 528173acc7cSZhang Wei else 529173acc7cSZhang Wei fsl_chan->completed_cookie = 530173acc7cSZhang Wei cur_desc->async_tx.cookie - 1; 531173acc7cSZhang Wei } 532173acc7cSZhang Wei } 533173acc7cSZhang Wei } 534173acc7cSZhang Wei 535173acc7cSZhang Wei /** 536173acc7cSZhang Wei * fsl_chan_ld_cleanup - Clean up link descriptors 537173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 538173acc7cSZhang Wei * 539173acc7cSZhang Wei * This function clean up the ld_queue of DMA channel. 540173acc7cSZhang Wei * If 'in_intr' is set, the function will move the link descriptor to 541173acc7cSZhang Wei * the recycle list. Otherwise, free it directly. 542173acc7cSZhang Wei */ 543173acc7cSZhang Wei static void fsl_chan_ld_cleanup(struct fsl_dma_chan *fsl_chan) 544173acc7cSZhang Wei { 545173acc7cSZhang Wei struct fsl_desc_sw *desc, *_desc; 546173acc7cSZhang Wei unsigned long flags; 547173acc7cSZhang Wei 548173acc7cSZhang Wei spin_lock_irqsave(&fsl_chan->desc_lock, flags); 549173acc7cSZhang Wei 550173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "chan completed_cookie = %d\n", 551173acc7cSZhang Wei fsl_chan->completed_cookie); 552173acc7cSZhang Wei list_for_each_entry_safe(desc, _desc, &fsl_chan->ld_queue, node) { 553173acc7cSZhang Wei dma_async_tx_callback callback; 554173acc7cSZhang Wei void *callback_param; 555173acc7cSZhang Wei 556173acc7cSZhang Wei if (dma_async_is_complete(desc->async_tx.cookie, 557173acc7cSZhang Wei fsl_chan->completed_cookie, fsl_chan->common.cookie) 558173acc7cSZhang Wei == DMA_IN_PROGRESS) 559173acc7cSZhang Wei break; 560173acc7cSZhang Wei 561173acc7cSZhang Wei callback = desc->async_tx.callback; 562173acc7cSZhang Wei callback_param = desc->async_tx.callback_param; 563173acc7cSZhang Wei 564173acc7cSZhang Wei /* Remove from ld_queue list */ 565173acc7cSZhang Wei list_del(&desc->node); 566173acc7cSZhang Wei 567173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "link descriptor %p will be recycle.\n", 568173acc7cSZhang Wei desc); 569173acc7cSZhang Wei dma_pool_free(fsl_chan->desc_pool, desc, desc->async_tx.phys); 570173acc7cSZhang Wei 571173acc7cSZhang Wei /* Run the link descriptor callback function */ 572173acc7cSZhang Wei if (callback) { 573173acc7cSZhang Wei spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); 574173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "link descriptor %p callback\n", 575173acc7cSZhang Wei desc); 576173acc7cSZhang Wei callback(callback_param); 577173acc7cSZhang Wei spin_lock_irqsave(&fsl_chan->desc_lock, flags); 578173acc7cSZhang Wei } 579173acc7cSZhang Wei } 580173acc7cSZhang Wei spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); 581173acc7cSZhang Wei } 582173acc7cSZhang Wei 583173acc7cSZhang Wei /** 584173acc7cSZhang Wei * fsl_chan_xfer_ld_queue - Transfer link descriptors in channel ld_queue. 585173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 586173acc7cSZhang Wei */ 587173acc7cSZhang Wei static void fsl_chan_xfer_ld_queue(struct fsl_dma_chan *fsl_chan) 588173acc7cSZhang Wei { 589173acc7cSZhang Wei struct list_head *ld_node; 590173acc7cSZhang Wei dma_addr_t next_dest_addr; 591173acc7cSZhang Wei unsigned long flags; 592173acc7cSZhang Wei 593173acc7cSZhang Wei if (!dma_is_idle(fsl_chan)) 594173acc7cSZhang Wei return; 595173acc7cSZhang Wei 596173acc7cSZhang Wei dma_halt(fsl_chan); 597173acc7cSZhang Wei 598173acc7cSZhang Wei /* If there are some link descriptors 599173acc7cSZhang Wei * not transfered in queue. We need to start it. 600173acc7cSZhang Wei */ 601173acc7cSZhang Wei spin_lock_irqsave(&fsl_chan->desc_lock, flags); 602173acc7cSZhang Wei 603173acc7cSZhang Wei /* Find the first un-transfer desciptor */ 604173acc7cSZhang Wei for (ld_node = fsl_chan->ld_queue.next; 605173acc7cSZhang Wei (ld_node != &fsl_chan->ld_queue) 606173acc7cSZhang Wei && (dma_async_is_complete( 607173acc7cSZhang Wei to_fsl_desc(ld_node)->async_tx.cookie, 608173acc7cSZhang Wei fsl_chan->completed_cookie, 609173acc7cSZhang Wei fsl_chan->common.cookie) == DMA_SUCCESS); 610173acc7cSZhang Wei ld_node = ld_node->next); 611173acc7cSZhang Wei 612173acc7cSZhang Wei spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); 613173acc7cSZhang Wei 614173acc7cSZhang Wei if (ld_node != &fsl_chan->ld_queue) { 615173acc7cSZhang Wei /* Get the ld start address from ld_queue */ 616173acc7cSZhang Wei next_dest_addr = to_fsl_desc(ld_node)->async_tx.phys; 61756822843SZhang Wei dev_dbg(fsl_chan->dev, "xfer LDs staring from %p\n", 61856822843SZhang Wei (void *)next_dest_addr); 619173acc7cSZhang Wei set_cdar(fsl_chan, next_dest_addr); 620173acc7cSZhang Wei dma_start(fsl_chan); 621173acc7cSZhang Wei } else { 622173acc7cSZhang Wei set_cdar(fsl_chan, 0); 623173acc7cSZhang Wei set_ndar(fsl_chan, 0); 624173acc7cSZhang Wei } 625173acc7cSZhang Wei } 626173acc7cSZhang Wei 627173acc7cSZhang Wei /** 628173acc7cSZhang Wei * fsl_dma_memcpy_issue_pending - Issue the DMA start command 629173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 630173acc7cSZhang Wei */ 631173acc7cSZhang Wei static void fsl_dma_memcpy_issue_pending(struct dma_chan *chan) 632173acc7cSZhang Wei { 633173acc7cSZhang Wei struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan); 634173acc7cSZhang Wei 635173acc7cSZhang Wei #ifdef FSL_DMA_LD_DEBUG 636173acc7cSZhang Wei struct fsl_desc_sw *ld; 637173acc7cSZhang Wei unsigned long flags; 638173acc7cSZhang Wei 639173acc7cSZhang Wei spin_lock_irqsave(&fsl_chan->desc_lock, flags); 640173acc7cSZhang Wei if (list_empty(&fsl_chan->ld_queue)) { 641173acc7cSZhang Wei spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); 642173acc7cSZhang Wei return; 643173acc7cSZhang Wei } 644173acc7cSZhang Wei 645173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "--memcpy issue--\n"); 646173acc7cSZhang Wei list_for_each_entry(ld, &fsl_chan->ld_queue, node) { 647173acc7cSZhang Wei int i; 648173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "Ch %d, LD %08x\n", 649173acc7cSZhang Wei fsl_chan->id, ld->async_tx.phys); 650173acc7cSZhang Wei for (i = 0; i < 8; i++) 651173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "LD offset %d: %08x\n", 652173acc7cSZhang Wei i, *(((u32 *)&ld->hw) + i)); 653173acc7cSZhang Wei } 654173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "----------------\n"); 655173acc7cSZhang Wei spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); 656173acc7cSZhang Wei #endif 657173acc7cSZhang Wei 658173acc7cSZhang Wei fsl_chan_xfer_ld_queue(fsl_chan); 659173acc7cSZhang Wei } 660173acc7cSZhang Wei 661173acc7cSZhang Wei static void fsl_dma_dependency_added(struct dma_chan *chan) 662173acc7cSZhang Wei { 663173acc7cSZhang Wei struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan); 664173acc7cSZhang Wei 665173acc7cSZhang Wei fsl_chan_ld_cleanup(fsl_chan); 666173acc7cSZhang Wei } 667173acc7cSZhang Wei 668173acc7cSZhang Wei /** 669173acc7cSZhang Wei * fsl_dma_is_complete - Determine the DMA status 670173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 671173acc7cSZhang Wei */ 672173acc7cSZhang Wei static enum dma_status fsl_dma_is_complete(struct dma_chan *chan, 673173acc7cSZhang Wei dma_cookie_t cookie, 674173acc7cSZhang Wei dma_cookie_t *done, 675173acc7cSZhang Wei dma_cookie_t *used) 676173acc7cSZhang Wei { 677173acc7cSZhang Wei struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan); 678173acc7cSZhang Wei dma_cookie_t last_used; 679173acc7cSZhang Wei dma_cookie_t last_complete; 680173acc7cSZhang Wei 681173acc7cSZhang Wei fsl_chan_ld_cleanup(fsl_chan); 682173acc7cSZhang Wei 683173acc7cSZhang Wei last_used = chan->cookie; 684173acc7cSZhang Wei last_complete = fsl_chan->completed_cookie; 685173acc7cSZhang Wei 686173acc7cSZhang Wei if (done) 687173acc7cSZhang Wei *done = last_complete; 688173acc7cSZhang Wei 689173acc7cSZhang Wei if (used) 690173acc7cSZhang Wei *used = last_used; 691173acc7cSZhang Wei 692173acc7cSZhang Wei return dma_async_is_complete(cookie, last_complete, last_used); 693173acc7cSZhang Wei } 694173acc7cSZhang Wei 695173acc7cSZhang Wei static irqreturn_t fsl_dma_chan_do_interrupt(int irq, void *data) 696173acc7cSZhang Wei { 697173acc7cSZhang Wei struct fsl_dma_chan *fsl_chan = (struct fsl_dma_chan *)data; 69856822843SZhang Wei u32 stat; 699173acc7cSZhang Wei 700173acc7cSZhang Wei stat = get_sr(fsl_chan); 701173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "event: channel %d, stat = 0x%x\n", 702173acc7cSZhang Wei fsl_chan->id, stat); 703173acc7cSZhang Wei set_sr(fsl_chan, stat); /* Clear the event register */ 704173acc7cSZhang Wei 705173acc7cSZhang Wei stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH); 706173acc7cSZhang Wei if (!stat) 707173acc7cSZhang Wei return IRQ_NONE; 708173acc7cSZhang Wei 709173acc7cSZhang Wei if (stat & FSL_DMA_SR_TE) 710173acc7cSZhang Wei dev_err(fsl_chan->dev, "Transfer Error!\n"); 711173acc7cSZhang Wei 712f79abb62SZhang Wei /* Programming Error 713f79abb62SZhang Wei * The DMA_INTERRUPT async_tx is a NULL transfer, which will 714f79abb62SZhang Wei * triger a PE interrupt. 715f79abb62SZhang Wei */ 716f79abb62SZhang Wei if (stat & FSL_DMA_SR_PE) { 717f79abb62SZhang Wei dev_dbg(fsl_chan->dev, "event: Programming Error INT\n"); 718f79abb62SZhang Wei if (get_bcr(fsl_chan) == 0) { 719f79abb62SZhang Wei /* BCR register is 0, this is a DMA_INTERRUPT async_tx. 720f79abb62SZhang Wei * Now, update the completed cookie, and continue the 721f79abb62SZhang Wei * next uncompleted transfer. 722f79abb62SZhang Wei */ 723f79abb62SZhang Wei fsl_dma_update_completed_cookie(fsl_chan); 724f79abb62SZhang Wei fsl_chan_xfer_ld_queue(fsl_chan); 725f79abb62SZhang Wei } 726f79abb62SZhang Wei stat &= ~FSL_DMA_SR_PE; 727f79abb62SZhang Wei } 728f79abb62SZhang Wei 729173acc7cSZhang Wei /* If the link descriptor segment transfer finishes, 730173acc7cSZhang Wei * we will recycle the used descriptor. 731173acc7cSZhang Wei */ 732173acc7cSZhang Wei if (stat & FSL_DMA_SR_EOSI) { 733173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "event: End-of-segments INT\n"); 73456822843SZhang Wei dev_dbg(fsl_chan->dev, "event: clndar %p, nlndar %p\n", 73556822843SZhang Wei (void *)get_cdar(fsl_chan), (void *)get_ndar(fsl_chan)); 736173acc7cSZhang Wei stat &= ~FSL_DMA_SR_EOSI; 7379c98718eSZhang Wei fsl_dma_update_completed_cookie(fsl_chan); 738173acc7cSZhang Wei } 739173acc7cSZhang Wei 740173acc7cSZhang Wei /* If it current transfer is the end-of-transfer, 741173acc7cSZhang Wei * we should clear the Channel Start bit for 742173acc7cSZhang Wei * prepare next transfer. 743173acc7cSZhang Wei */ 744173acc7cSZhang Wei if (stat & (FSL_DMA_SR_EOLNI | FSL_DMA_SR_EOCDI)) { 745173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "event: End-of-link INT\n"); 746173acc7cSZhang Wei stat &= ~FSL_DMA_SR_EOLNI; 747173acc7cSZhang Wei fsl_chan_xfer_ld_queue(fsl_chan); 748173acc7cSZhang Wei } 749173acc7cSZhang Wei 750173acc7cSZhang Wei if (stat) 751173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "event: unhandled sr 0x%02x\n", 752173acc7cSZhang Wei stat); 753173acc7cSZhang Wei 754173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "event: Exit\n"); 755173acc7cSZhang Wei tasklet_schedule(&fsl_chan->tasklet); 756173acc7cSZhang Wei return IRQ_HANDLED; 757173acc7cSZhang Wei } 758173acc7cSZhang Wei 759173acc7cSZhang Wei static irqreturn_t fsl_dma_do_interrupt(int irq, void *data) 760173acc7cSZhang Wei { 761173acc7cSZhang Wei struct fsl_dma_device *fdev = (struct fsl_dma_device *)data; 762173acc7cSZhang Wei u32 gsr; 763173acc7cSZhang Wei int ch_nr; 764173acc7cSZhang Wei 765173acc7cSZhang Wei gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->reg_base) 766173acc7cSZhang Wei : in_le32(fdev->reg_base); 767173acc7cSZhang Wei ch_nr = (32 - ffs(gsr)) / 8; 768173acc7cSZhang Wei 769173acc7cSZhang Wei return fdev->chan[ch_nr] ? fsl_dma_chan_do_interrupt(irq, 770173acc7cSZhang Wei fdev->chan[ch_nr]) : IRQ_NONE; 771173acc7cSZhang Wei } 772173acc7cSZhang Wei 773173acc7cSZhang Wei static void dma_do_tasklet(unsigned long data) 774173acc7cSZhang Wei { 775173acc7cSZhang Wei struct fsl_dma_chan *fsl_chan = (struct fsl_dma_chan *)data; 776173acc7cSZhang Wei fsl_chan_ld_cleanup(fsl_chan); 777173acc7cSZhang Wei } 778173acc7cSZhang Wei 77956822843SZhang Wei #ifdef FSL_DMA_CALLBACKTEST 780173acc7cSZhang Wei static void fsl_dma_callback_test(struct fsl_dma_chan *fsl_chan) 781173acc7cSZhang Wei { 782173acc7cSZhang Wei if (fsl_chan) 783173acc7cSZhang Wei dev_info(fsl_chan->dev, "selftest: callback is ok!\n"); 784173acc7cSZhang Wei } 78556822843SZhang Wei #endif 786173acc7cSZhang Wei 78756822843SZhang Wei #ifdef CONFIG_FSL_DMA_SELFTEST 788173acc7cSZhang Wei static int fsl_dma_self_test(struct fsl_dma_chan *fsl_chan) 789173acc7cSZhang Wei { 790173acc7cSZhang Wei struct dma_chan *chan; 791173acc7cSZhang Wei int err = 0; 792173acc7cSZhang Wei dma_addr_t dma_dest, dma_src; 793173acc7cSZhang Wei dma_cookie_t cookie; 794173acc7cSZhang Wei u8 *src, *dest; 795173acc7cSZhang Wei int i; 796173acc7cSZhang Wei size_t test_size; 797173acc7cSZhang Wei struct dma_async_tx_descriptor *tx1, *tx2, *tx3; 798173acc7cSZhang Wei 799173acc7cSZhang Wei test_size = 4096; 800173acc7cSZhang Wei 801173acc7cSZhang Wei src = kmalloc(test_size * 2, GFP_KERNEL); 802173acc7cSZhang Wei if (!src) { 803173acc7cSZhang Wei dev_err(fsl_chan->dev, 804173acc7cSZhang Wei "selftest: Cannot alloc memory for test!\n"); 805173acc7cSZhang Wei err = -ENOMEM; 806173acc7cSZhang Wei goto out; 807173acc7cSZhang Wei } 808173acc7cSZhang Wei 809173acc7cSZhang Wei dest = src + test_size; 810173acc7cSZhang Wei 811173acc7cSZhang Wei for (i = 0; i < test_size; i++) 812173acc7cSZhang Wei src[i] = (u8) i; 813173acc7cSZhang Wei 814173acc7cSZhang Wei chan = &fsl_chan->common; 815173acc7cSZhang Wei 816173acc7cSZhang Wei if (fsl_dma_alloc_chan_resources(chan) < 1) { 817173acc7cSZhang Wei dev_err(fsl_chan->dev, 818173acc7cSZhang Wei "selftest: Cannot alloc resources for DMA\n"); 819173acc7cSZhang Wei err = -ENODEV; 820173acc7cSZhang Wei goto out; 821173acc7cSZhang Wei } 822173acc7cSZhang Wei 823173acc7cSZhang Wei /* TX 1 */ 824173acc7cSZhang Wei dma_src = dma_map_single(fsl_chan->dev, src, test_size / 2, 825173acc7cSZhang Wei DMA_TO_DEVICE); 826173acc7cSZhang Wei dma_dest = dma_map_single(fsl_chan->dev, dest, test_size / 2, 827173acc7cSZhang Wei DMA_FROM_DEVICE); 828173acc7cSZhang Wei tx1 = fsl_dma_prep_memcpy(chan, dma_dest, dma_src, test_size / 2, 0); 829173acc7cSZhang Wei async_tx_ack(tx1); 830173acc7cSZhang Wei 831173acc7cSZhang Wei cookie = fsl_dma_tx_submit(tx1); 832173acc7cSZhang Wei fsl_dma_memcpy_issue_pending(chan); 833173acc7cSZhang Wei msleep(2); 834173acc7cSZhang Wei 835173acc7cSZhang Wei if (fsl_dma_is_complete(chan, cookie, NULL, NULL) != DMA_SUCCESS) { 836173acc7cSZhang Wei dev_err(fsl_chan->dev, "selftest: Time out!\n"); 837173acc7cSZhang Wei err = -ENODEV; 838173acc7cSZhang Wei goto out; 839173acc7cSZhang Wei } 840173acc7cSZhang Wei 841173acc7cSZhang Wei /* Test free and re-alloc channel resources */ 842173acc7cSZhang Wei fsl_dma_free_chan_resources(chan); 843173acc7cSZhang Wei 844173acc7cSZhang Wei if (fsl_dma_alloc_chan_resources(chan) < 1) { 845173acc7cSZhang Wei dev_err(fsl_chan->dev, 846173acc7cSZhang Wei "selftest: Cannot alloc resources for DMA\n"); 847173acc7cSZhang Wei err = -ENODEV; 848173acc7cSZhang Wei goto free_resources; 849173acc7cSZhang Wei } 850173acc7cSZhang Wei 851173acc7cSZhang Wei /* Continue to test 852173acc7cSZhang Wei * TX 2 853173acc7cSZhang Wei */ 854173acc7cSZhang Wei dma_src = dma_map_single(fsl_chan->dev, src + test_size / 2, 855173acc7cSZhang Wei test_size / 4, DMA_TO_DEVICE); 856173acc7cSZhang Wei dma_dest = dma_map_single(fsl_chan->dev, dest + test_size / 2, 857173acc7cSZhang Wei test_size / 4, DMA_FROM_DEVICE); 858173acc7cSZhang Wei tx2 = fsl_dma_prep_memcpy(chan, dma_dest, dma_src, test_size / 4, 0); 859173acc7cSZhang Wei async_tx_ack(tx2); 860173acc7cSZhang Wei 861173acc7cSZhang Wei /* TX 3 */ 862173acc7cSZhang Wei dma_src = dma_map_single(fsl_chan->dev, src + test_size * 3 / 4, 863173acc7cSZhang Wei test_size / 4, DMA_TO_DEVICE); 864173acc7cSZhang Wei dma_dest = dma_map_single(fsl_chan->dev, dest + test_size * 3 / 4, 865173acc7cSZhang Wei test_size / 4, DMA_FROM_DEVICE); 866173acc7cSZhang Wei tx3 = fsl_dma_prep_memcpy(chan, dma_dest, dma_src, test_size / 4, 0); 867173acc7cSZhang Wei async_tx_ack(tx3); 868173acc7cSZhang Wei 869f79abb62SZhang Wei /* Interrupt tx test */ 870f79abb62SZhang Wei tx1 = fsl_dma_prep_interrupt(chan); 871f79abb62SZhang Wei async_tx_ack(tx1); 872f79abb62SZhang Wei cookie = fsl_dma_tx_submit(tx1); 873f79abb62SZhang Wei 874173acc7cSZhang Wei /* Test exchanging the prepared tx sort */ 875173acc7cSZhang Wei cookie = fsl_dma_tx_submit(tx3); 876173acc7cSZhang Wei cookie = fsl_dma_tx_submit(tx2); 877173acc7cSZhang Wei 878173acc7cSZhang Wei #ifdef FSL_DMA_CALLBACKTEST 879173acc7cSZhang Wei if (dma_has_cap(DMA_INTERRUPT, ((struct fsl_dma_device *) 880173acc7cSZhang Wei dev_get_drvdata(fsl_chan->dev->parent))->common.cap_mask)) { 881173acc7cSZhang Wei tx3->callback = fsl_dma_callback_test; 882173acc7cSZhang Wei tx3->callback_param = fsl_chan; 883173acc7cSZhang Wei } 884173acc7cSZhang Wei #endif 885173acc7cSZhang Wei fsl_dma_memcpy_issue_pending(chan); 886173acc7cSZhang Wei msleep(2); 887173acc7cSZhang Wei 888173acc7cSZhang Wei if (fsl_dma_is_complete(chan, cookie, NULL, NULL) != DMA_SUCCESS) { 889173acc7cSZhang Wei dev_err(fsl_chan->dev, "selftest: Time out!\n"); 890173acc7cSZhang Wei err = -ENODEV; 891173acc7cSZhang Wei goto free_resources; 892173acc7cSZhang Wei } 893173acc7cSZhang Wei 894173acc7cSZhang Wei err = memcmp(src, dest, test_size); 895173acc7cSZhang Wei if (err) { 896173acc7cSZhang Wei for (i = 0; (*(src + i) == *(dest + i)) && (i < test_size); 897173acc7cSZhang Wei i++); 89856822843SZhang Wei dev_err(fsl_chan->dev, "selftest: Test failed, data %d/%ld is " 899173acc7cSZhang Wei "error! src 0x%x, dest 0x%x\n", 90056822843SZhang Wei i, (long)test_size, *(src + i), *(dest + i)); 901173acc7cSZhang Wei } 902173acc7cSZhang Wei 903173acc7cSZhang Wei free_resources: 904173acc7cSZhang Wei fsl_dma_free_chan_resources(chan); 905173acc7cSZhang Wei out: 906173acc7cSZhang Wei kfree(src); 907173acc7cSZhang Wei return err; 908173acc7cSZhang Wei } 90956822843SZhang Wei #endif 910173acc7cSZhang Wei 911173acc7cSZhang Wei static int __devinit of_fsl_dma_chan_probe(struct of_device *dev, 912173acc7cSZhang Wei const struct of_device_id *match) 913173acc7cSZhang Wei { 914173acc7cSZhang Wei struct fsl_dma_device *fdev; 915173acc7cSZhang Wei struct fsl_dma_chan *new_fsl_chan; 916173acc7cSZhang Wei int err; 917173acc7cSZhang Wei 918173acc7cSZhang Wei fdev = dev_get_drvdata(dev->dev.parent); 919173acc7cSZhang Wei BUG_ON(!fdev); 920173acc7cSZhang Wei 921173acc7cSZhang Wei /* alloc channel */ 922173acc7cSZhang Wei new_fsl_chan = kzalloc(sizeof(struct fsl_dma_chan), GFP_KERNEL); 923173acc7cSZhang Wei if (!new_fsl_chan) { 924173acc7cSZhang Wei dev_err(&dev->dev, "No free memory for allocating " 925173acc7cSZhang Wei "dma channels!\n"); 926173acc7cSZhang Wei err = -ENOMEM; 927173acc7cSZhang Wei goto err; 928173acc7cSZhang Wei } 929173acc7cSZhang Wei 930173acc7cSZhang Wei /* get dma channel register base */ 931173acc7cSZhang Wei err = of_address_to_resource(dev->node, 0, &new_fsl_chan->reg); 932173acc7cSZhang Wei if (err) { 933173acc7cSZhang Wei dev_err(&dev->dev, "Can't get %s property 'reg'\n", 934173acc7cSZhang Wei dev->node->full_name); 935173acc7cSZhang Wei goto err; 936173acc7cSZhang Wei } 937173acc7cSZhang Wei 938173acc7cSZhang Wei new_fsl_chan->feature = *(u32 *)match->data; 939173acc7cSZhang Wei 940173acc7cSZhang Wei if (!fdev->feature) 941173acc7cSZhang Wei fdev->feature = new_fsl_chan->feature; 942173acc7cSZhang Wei 943173acc7cSZhang Wei /* If the DMA device's feature is different than its channels', 944173acc7cSZhang Wei * report the bug. 945173acc7cSZhang Wei */ 946173acc7cSZhang Wei WARN_ON(fdev->feature != new_fsl_chan->feature); 947173acc7cSZhang Wei 948173acc7cSZhang Wei new_fsl_chan->dev = &dev->dev; 949173acc7cSZhang Wei new_fsl_chan->reg_base = ioremap(new_fsl_chan->reg.start, 950173acc7cSZhang Wei new_fsl_chan->reg.end - new_fsl_chan->reg.start + 1); 951173acc7cSZhang Wei 952173acc7cSZhang Wei new_fsl_chan->id = ((new_fsl_chan->reg.start - 0x100) & 0xfff) >> 7; 953173acc7cSZhang Wei if (new_fsl_chan->id > FSL_DMA_MAX_CHANS_PER_DEVICE) { 954173acc7cSZhang Wei dev_err(&dev->dev, "There is no %d channel!\n", 955173acc7cSZhang Wei new_fsl_chan->id); 956173acc7cSZhang Wei err = -EINVAL; 957173acc7cSZhang Wei goto err; 958173acc7cSZhang Wei } 959173acc7cSZhang Wei fdev->chan[new_fsl_chan->id] = new_fsl_chan; 960173acc7cSZhang Wei tasklet_init(&new_fsl_chan->tasklet, dma_do_tasklet, 961173acc7cSZhang Wei (unsigned long)new_fsl_chan); 962173acc7cSZhang Wei 963173acc7cSZhang Wei /* Init the channel */ 964173acc7cSZhang Wei dma_init(new_fsl_chan); 965173acc7cSZhang Wei 966173acc7cSZhang Wei /* Clear cdar registers */ 967173acc7cSZhang Wei set_cdar(new_fsl_chan, 0); 968173acc7cSZhang Wei 969173acc7cSZhang Wei switch (new_fsl_chan->feature & FSL_DMA_IP_MASK) { 970173acc7cSZhang Wei case FSL_DMA_IP_85XX: 971173acc7cSZhang Wei new_fsl_chan->toggle_ext_start = fsl_chan_toggle_ext_start; 972173acc7cSZhang Wei new_fsl_chan->toggle_ext_pause = fsl_chan_toggle_ext_pause; 973173acc7cSZhang Wei case FSL_DMA_IP_83XX: 974173acc7cSZhang Wei new_fsl_chan->set_src_loop_size = fsl_chan_set_src_loop_size; 975173acc7cSZhang Wei new_fsl_chan->set_dest_loop_size = fsl_chan_set_dest_loop_size; 976173acc7cSZhang Wei } 977173acc7cSZhang Wei 978173acc7cSZhang Wei spin_lock_init(&new_fsl_chan->desc_lock); 979173acc7cSZhang Wei INIT_LIST_HEAD(&new_fsl_chan->ld_queue); 980173acc7cSZhang Wei 981173acc7cSZhang Wei new_fsl_chan->common.device = &fdev->common; 982173acc7cSZhang Wei 983173acc7cSZhang Wei /* Add the channel to DMA device channel list */ 984173acc7cSZhang Wei list_add_tail(&new_fsl_chan->common.device_node, 985173acc7cSZhang Wei &fdev->common.channels); 986173acc7cSZhang Wei fdev->common.chancnt++; 987173acc7cSZhang Wei 988173acc7cSZhang Wei new_fsl_chan->irq = irq_of_parse_and_map(dev->node, 0); 989173acc7cSZhang Wei if (new_fsl_chan->irq != NO_IRQ) { 990173acc7cSZhang Wei err = request_irq(new_fsl_chan->irq, 991173acc7cSZhang Wei &fsl_dma_chan_do_interrupt, IRQF_SHARED, 992173acc7cSZhang Wei "fsldma-channel", new_fsl_chan); 993173acc7cSZhang Wei if (err) { 994173acc7cSZhang Wei dev_err(&dev->dev, "DMA channel %s request_irq error " 995173acc7cSZhang Wei "with return %d\n", dev->node->full_name, err); 996173acc7cSZhang Wei goto err; 997173acc7cSZhang Wei } 998173acc7cSZhang Wei } 999173acc7cSZhang Wei 1000173acc7cSZhang Wei #ifdef CONFIG_FSL_DMA_SELFTEST 1001173acc7cSZhang Wei err = fsl_dma_self_test(new_fsl_chan); 1002173acc7cSZhang Wei if (err) 1003173acc7cSZhang Wei goto err; 1004173acc7cSZhang Wei #endif 1005173acc7cSZhang Wei 1006173acc7cSZhang Wei dev_info(&dev->dev, "#%d (%s), irq %d\n", new_fsl_chan->id, 1007173acc7cSZhang Wei match->compatible, new_fsl_chan->irq); 1008173acc7cSZhang Wei 1009173acc7cSZhang Wei return 0; 1010173acc7cSZhang Wei err: 1011173acc7cSZhang Wei dma_halt(new_fsl_chan); 1012173acc7cSZhang Wei iounmap(new_fsl_chan->reg_base); 1013173acc7cSZhang Wei free_irq(new_fsl_chan->irq, new_fsl_chan); 1014173acc7cSZhang Wei list_del(&new_fsl_chan->common.device_node); 1015173acc7cSZhang Wei kfree(new_fsl_chan); 1016173acc7cSZhang Wei return err; 1017173acc7cSZhang Wei } 1018173acc7cSZhang Wei 1019173acc7cSZhang Wei const u32 mpc8540_dma_ip_feature = FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN; 1020173acc7cSZhang Wei const u32 mpc8349_dma_ip_feature = FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN; 1021173acc7cSZhang Wei 1022173acc7cSZhang Wei static struct of_device_id of_fsl_dma_chan_ids[] = { 1023173acc7cSZhang Wei { 1024173acc7cSZhang Wei .compatible = "fsl,mpc8540-dma-channel", 1025173acc7cSZhang Wei .data = (void *)&mpc8540_dma_ip_feature, 1026173acc7cSZhang Wei }, 1027173acc7cSZhang Wei { 1028173acc7cSZhang Wei .compatible = "fsl,mpc8349-dma-channel", 1029173acc7cSZhang Wei .data = (void *)&mpc8349_dma_ip_feature, 1030173acc7cSZhang Wei }, 1031173acc7cSZhang Wei {} 1032173acc7cSZhang Wei }; 1033173acc7cSZhang Wei 1034173acc7cSZhang Wei static struct of_platform_driver of_fsl_dma_chan_driver = { 1035173acc7cSZhang Wei .name = "of-fsl-dma-channel", 1036173acc7cSZhang Wei .match_table = of_fsl_dma_chan_ids, 1037173acc7cSZhang Wei .probe = of_fsl_dma_chan_probe, 1038173acc7cSZhang Wei }; 1039173acc7cSZhang Wei 1040173acc7cSZhang Wei static __init int of_fsl_dma_chan_init(void) 1041173acc7cSZhang Wei { 1042173acc7cSZhang Wei return of_register_platform_driver(&of_fsl_dma_chan_driver); 1043173acc7cSZhang Wei } 1044173acc7cSZhang Wei 1045173acc7cSZhang Wei static int __devinit of_fsl_dma_probe(struct of_device *dev, 1046173acc7cSZhang Wei const struct of_device_id *match) 1047173acc7cSZhang Wei { 1048173acc7cSZhang Wei int err; 1049173acc7cSZhang Wei unsigned int irq; 1050173acc7cSZhang Wei struct fsl_dma_device *fdev; 1051173acc7cSZhang Wei 1052173acc7cSZhang Wei fdev = kzalloc(sizeof(struct fsl_dma_device), GFP_KERNEL); 1053173acc7cSZhang Wei if (!fdev) { 1054173acc7cSZhang Wei dev_err(&dev->dev, "No enough memory for 'priv'\n"); 1055173acc7cSZhang Wei err = -ENOMEM; 1056173acc7cSZhang Wei goto err; 1057173acc7cSZhang Wei } 1058173acc7cSZhang Wei fdev->dev = &dev->dev; 1059173acc7cSZhang Wei INIT_LIST_HEAD(&fdev->common.channels); 1060173acc7cSZhang Wei 1061173acc7cSZhang Wei /* get DMA controller register base */ 1062173acc7cSZhang Wei err = of_address_to_resource(dev->node, 0, &fdev->reg); 1063173acc7cSZhang Wei if (err) { 1064173acc7cSZhang Wei dev_err(&dev->dev, "Can't get %s property 'reg'\n", 1065173acc7cSZhang Wei dev->node->full_name); 1066173acc7cSZhang Wei goto err; 1067173acc7cSZhang Wei } 1068173acc7cSZhang Wei 1069173acc7cSZhang Wei dev_info(&dev->dev, "Probe the Freescale DMA driver for %s " 107056822843SZhang Wei "controller at %p...\n", 107156822843SZhang Wei match->compatible, (void *)fdev->reg.start); 1072173acc7cSZhang Wei fdev->reg_base = ioremap(fdev->reg.start, fdev->reg.end 1073173acc7cSZhang Wei - fdev->reg.start + 1); 1074173acc7cSZhang Wei 1075173acc7cSZhang Wei dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask); 1076173acc7cSZhang Wei dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask); 1077173acc7cSZhang Wei fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources; 1078173acc7cSZhang Wei fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources; 10792187c269SZhang Wei fdev->common.device_prep_dma_interrupt = fsl_dma_prep_interrupt; 1080173acc7cSZhang Wei fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy; 1081173acc7cSZhang Wei fdev->common.device_is_tx_complete = fsl_dma_is_complete; 1082173acc7cSZhang Wei fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending; 1083173acc7cSZhang Wei fdev->common.device_dependency_added = fsl_dma_dependency_added; 1084173acc7cSZhang Wei fdev->common.dev = &dev->dev; 1085173acc7cSZhang Wei 1086173acc7cSZhang Wei irq = irq_of_parse_and_map(dev->node, 0); 1087173acc7cSZhang Wei if (irq != NO_IRQ) { 1088173acc7cSZhang Wei err = request_irq(irq, &fsl_dma_do_interrupt, IRQF_SHARED, 1089173acc7cSZhang Wei "fsldma-device", fdev); 1090173acc7cSZhang Wei if (err) { 1091173acc7cSZhang Wei dev_err(&dev->dev, "DMA device request_irq error " 1092173acc7cSZhang Wei "with return %d\n", err); 1093173acc7cSZhang Wei goto err; 1094173acc7cSZhang Wei } 1095173acc7cSZhang Wei } 1096173acc7cSZhang Wei 1097173acc7cSZhang Wei dev_set_drvdata(&(dev->dev), fdev); 1098173acc7cSZhang Wei of_platform_bus_probe(dev->node, of_fsl_dma_chan_ids, &dev->dev); 1099173acc7cSZhang Wei 1100173acc7cSZhang Wei dma_async_device_register(&fdev->common); 1101173acc7cSZhang Wei return 0; 1102173acc7cSZhang Wei 1103173acc7cSZhang Wei err: 1104173acc7cSZhang Wei iounmap(fdev->reg_base); 1105173acc7cSZhang Wei kfree(fdev); 1106173acc7cSZhang Wei return err; 1107173acc7cSZhang Wei } 1108173acc7cSZhang Wei 1109173acc7cSZhang Wei static struct of_device_id of_fsl_dma_ids[] = { 1110173acc7cSZhang Wei { .compatible = "fsl,mpc8540-dma", }, 1111173acc7cSZhang Wei { .compatible = "fsl,mpc8349-dma", }, 1112173acc7cSZhang Wei {} 1113173acc7cSZhang Wei }; 1114173acc7cSZhang Wei 1115173acc7cSZhang Wei static struct of_platform_driver of_fsl_dma_driver = { 1116173acc7cSZhang Wei .name = "of-fsl-dma", 1117173acc7cSZhang Wei .match_table = of_fsl_dma_ids, 1118173acc7cSZhang Wei .probe = of_fsl_dma_probe, 1119173acc7cSZhang Wei }; 1120173acc7cSZhang Wei 1121173acc7cSZhang Wei static __init int of_fsl_dma_init(void) 1122173acc7cSZhang Wei { 1123173acc7cSZhang Wei return of_register_platform_driver(&of_fsl_dma_driver); 1124173acc7cSZhang Wei } 1125173acc7cSZhang Wei 1126173acc7cSZhang Wei subsys_initcall(of_fsl_dma_chan_init); 1127173acc7cSZhang Wei subsys_initcall(of_fsl_dma_init); 1128