1173acc7cSZhang Wei /* 2173acc7cSZhang Wei * Freescale MPC85xx, MPC83xx DMA Engine support 3173acc7cSZhang Wei * 4173acc7cSZhang Wei * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved. 5173acc7cSZhang Wei * 6173acc7cSZhang Wei * Author: 7173acc7cSZhang Wei * Zhang Wei <wei.zhang@freescale.com>, Jul 2007 8173acc7cSZhang Wei * Ebony Zhu <ebony.zhu@freescale.com>, May 2007 9173acc7cSZhang Wei * 10173acc7cSZhang Wei * Description: 11173acc7cSZhang Wei * DMA engine driver for Freescale MPC8540 DMA controller, which is 12173acc7cSZhang Wei * also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc. 13173acc7cSZhang Wei * The support for MPC8349 DMA contorller is also added. 14173acc7cSZhang Wei * 15173acc7cSZhang Wei * This is free software; you can redistribute it and/or modify 16173acc7cSZhang Wei * it under the terms of the GNU General Public License as published by 17173acc7cSZhang Wei * the Free Software Foundation; either version 2 of the License, or 18173acc7cSZhang Wei * (at your option) any later version. 19173acc7cSZhang Wei * 20173acc7cSZhang Wei */ 21173acc7cSZhang Wei 22173acc7cSZhang Wei #include <linux/init.h> 23173acc7cSZhang Wei #include <linux/module.h> 24173acc7cSZhang Wei #include <linux/pci.h> 25173acc7cSZhang Wei #include <linux/interrupt.h> 26173acc7cSZhang Wei #include <linux/dmaengine.h> 27173acc7cSZhang Wei #include <linux/delay.h> 28173acc7cSZhang Wei #include <linux/dma-mapping.h> 29173acc7cSZhang Wei #include <linux/dmapool.h> 30173acc7cSZhang Wei #include <linux/of_platform.h> 31173acc7cSZhang Wei 32173acc7cSZhang Wei #include "fsldma.h" 33173acc7cSZhang Wei 34173acc7cSZhang Wei static void dma_init(struct fsl_dma_chan *fsl_chan) 35173acc7cSZhang Wei { 36173acc7cSZhang Wei /* Reset the channel */ 37173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 0, 32); 38173acc7cSZhang Wei 39173acc7cSZhang Wei switch (fsl_chan->feature & FSL_DMA_IP_MASK) { 40173acc7cSZhang Wei case FSL_DMA_IP_85XX: 41173acc7cSZhang Wei /* Set the channel to below modes: 42173acc7cSZhang Wei * EIE - Error interrupt enable 43173acc7cSZhang Wei * EOSIE - End of segments interrupt enable (basic mode) 44173acc7cSZhang Wei * EOLNIE - End of links interrupt enable 45173acc7cSZhang Wei */ 46173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, FSL_DMA_MR_EIE 47173acc7cSZhang Wei | FSL_DMA_MR_EOLNIE | FSL_DMA_MR_EOSIE, 32); 48173acc7cSZhang Wei break; 49173acc7cSZhang Wei case FSL_DMA_IP_83XX: 50173acc7cSZhang Wei /* Set the channel to below modes: 51173acc7cSZhang Wei * EOTIE - End-of-transfer interrupt enable 52173acc7cSZhang Wei */ 53173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, FSL_DMA_MR_EOTIE, 54173acc7cSZhang Wei 32); 55173acc7cSZhang Wei break; 56173acc7cSZhang Wei } 57173acc7cSZhang Wei 58173acc7cSZhang Wei } 59173acc7cSZhang Wei 6056822843SZhang Wei static void set_sr(struct fsl_dma_chan *fsl_chan, u32 val) 61173acc7cSZhang Wei { 62173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->sr, val, 32); 63173acc7cSZhang Wei } 64173acc7cSZhang Wei 6556822843SZhang Wei static u32 get_sr(struct fsl_dma_chan *fsl_chan) 66173acc7cSZhang Wei { 67173acc7cSZhang Wei return DMA_IN(fsl_chan, &fsl_chan->reg_base->sr, 32); 68173acc7cSZhang Wei } 69173acc7cSZhang Wei 70173acc7cSZhang Wei static void set_desc_cnt(struct fsl_dma_chan *fsl_chan, 71173acc7cSZhang Wei struct fsl_dma_ld_hw *hw, u32 count) 72173acc7cSZhang Wei { 73173acc7cSZhang Wei hw->count = CPU_TO_DMA(fsl_chan, count, 32); 74173acc7cSZhang Wei } 75173acc7cSZhang Wei 76173acc7cSZhang Wei static void set_desc_src(struct fsl_dma_chan *fsl_chan, 77173acc7cSZhang Wei struct fsl_dma_ld_hw *hw, dma_addr_t src) 78173acc7cSZhang Wei { 79173acc7cSZhang Wei u64 snoop_bits; 80173acc7cSZhang Wei 81173acc7cSZhang Wei snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) 82173acc7cSZhang Wei ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0; 83173acc7cSZhang Wei hw->src_addr = CPU_TO_DMA(fsl_chan, snoop_bits | src, 64); 84173acc7cSZhang Wei } 85173acc7cSZhang Wei 86173acc7cSZhang Wei static void set_desc_dest(struct fsl_dma_chan *fsl_chan, 87173acc7cSZhang Wei struct fsl_dma_ld_hw *hw, dma_addr_t dest) 88173acc7cSZhang Wei { 89173acc7cSZhang Wei u64 snoop_bits; 90173acc7cSZhang Wei 91173acc7cSZhang Wei snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) 92173acc7cSZhang Wei ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0; 93173acc7cSZhang Wei hw->dst_addr = CPU_TO_DMA(fsl_chan, snoop_bits | dest, 64); 94173acc7cSZhang Wei } 95173acc7cSZhang Wei 96173acc7cSZhang Wei static void set_desc_next(struct fsl_dma_chan *fsl_chan, 97173acc7cSZhang Wei struct fsl_dma_ld_hw *hw, dma_addr_t next) 98173acc7cSZhang Wei { 99173acc7cSZhang Wei u64 snoop_bits; 100173acc7cSZhang Wei 101173acc7cSZhang Wei snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) 102173acc7cSZhang Wei ? FSL_DMA_SNEN : 0; 103173acc7cSZhang Wei hw->next_ln_addr = CPU_TO_DMA(fsl_chan, snoop_bits | next, 64); 104173acc7cSZhang Wei } 105173acc7cSZhang Wei 106173acc7cSZhang Wei static void set_cdar(struct fsl_dma_chan *fsl_chan, dma_addr_t addr) 107173acc7cSZhang Wei { 108173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->cdar, addr | FSL_DMA_SNEN, 64); 109173acc7cSZhang Wei } 110173acc7cSZhang Wei 111173acc7cSZhang Wei static dma_addr_t get_cdar(struct fsl_dma_chan *fsl_chan) 112173acc7cSZhang Wei { 113173acc7cSZhang Wei return DMA_IN(fsl_chan, &fsl_chan->reg_base->cdar, 64) & ~FSL_DMA_SNEN; 114173acc7cSZhang Wei } 115173acc7cSZhang Wei 116173acc7cSZhang Wei static void set_ndar(struct fsl_dma_chan *fsl_chan, dma_addr_t addr) 117173acc7cSZhang Wei { 118173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->ndar, addr, 64); 119173acc7cSZhang Wei } 120173acc7cSZhang Wei 121173acc7cSZhang Wei static dma_addr_t get_ndar(struct fsl_dma_chan *fsl_chan) 122173acc7cSZhang Wei { 123173acc7cSZhang Wei return DMA_IN(fsl_chan, &fsl_chan->reg_base->ndar, 64); 124173acc7cSZhang Wei } 125173acc7cSZhang Wei 126f79abb62SZhang Wei static u32 get_bcr(struct fsl_dma_chan *fsl_chan) 127f79abb62SZhang Wei { 128f79abb62SZhang Wei return DMA_IN(fsl_chan, &fsl_chan->reg_base->bcr, 32); 129f79abb62SZhang Wei } 130f79abb62SZhang Wei 131173acc7cSZhang Wei static int dma_is_idle(struct fsl_dma_chan *fsl_chan) 132173acc7cSZhang Wei { 133173acc7cSZhang Wei u32 sr = get_sr(fsl_chan); 134173acc7cSZhang Wei return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH); 135173acc7cSZhang Wei } 136173acc7cSZhang Wei 137173acc7cSZhang Wei static void dma_start(struct fsl_dma_chan *fsl_chan) 138173acc7cSZhang Wei { 139173acc7cSZhang Wei u32 mr_set = 0;; 140173acc7cSZhang Wei 141173acc7cSZhang Wei if (fsl_chan->feature & FSL_DMA_CHAN_PAUSE_EXT) { 142173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->bcr, 0, 32); 143173acc7cSZhang Wei mr_set |= FSL_DMA_MR_EMP_EN; 144173acc7cSZhang Wei } else 145173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 146173acc7cSZhang Wei DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) 147173acc7cSZhang Wei & ~FSL_DMA_MR_EMP_EN, 32); 148173acc7cSZhang Wei 149173acc7cSZhang Wei if (fsl_chan->feature & FSL_DMA_CHAN_START_EXT) 150173acc7cSZhang Wei mr_set |= FSL_DMA_MR_EMS_EN; 151173acc7cSZhang Wei else 152173acc7cSZhang Wei mr_set |= FSL_DMA_MR_CS; 153173acc7cSZhang Wei 154173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 155173acc7cSZhang Wei DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) 156173acc7cSZhang Wei | mr_set, 32); 157173acc7cSZhang Wei } 158173acc7cSZhang Wei 159173acc7cSZhang Wei static void dma_halt(struct fsl_dma_chan *fsl_chan) 160173acc7cSZhang Wei { 161900325a6SDan Williams int i; 162900325a6SDan Williams 163173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 164173acc7cSZhang Wei DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) | FSL_DMA_MR_CA, 165173acc7cSZhang Wei 32); 166173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 167173acc7cSZhang Wei DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) & ~(FSL_DMA_MR_CS 168173acc7cSZhang Wei | FSL_DMA_MR_EMS_EN | FSL_DMA_MR_CA), 32); 169173acc7cSZhang Wei 170900325a6SDan Williams for (i = 0; i < 100; i++) { 171900325a6SDan Williams if (dma_is_idle(fsl_chan)) 172900325a6SDan Williams break; 173173acc7cSZhang Wei udelay(10); 174900325a6SDan Williams } 175173acc7cSZhang Wei if (i >= 100 && !dma_is_idle(fsl_chan)) 176173acc7cSZhang Wei dev_err(fsl_chan->dev, "DMA halt timeout!\n"); 177173acc7cSZhang Wei } 178173acc7cSZhang Wei 179173acc7cSZhang Wei static void set_ld_eol(struct fsl_dma_chan *fsl_chan, 180173acc7cSZhang Wei struct fsl_desc_sw *desc) 181173acc7cSZhang Wei { 182173acc7cSZhang Wei desc->hw.next_ln_addr = CPU_TO_DMA(fsl_chan, 183173acc7cSZhang Wei DMA_TO_CPU(fsl_chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL, 184173acc7cSZhang Wei 64); 185173acc7cSZhang Wei } 186173acc7cSZhang Wei 187173acc7cSZhang Wei static void append_ld_queue(struct fsl_dma_chan *fsl_chan, 188173acc7cSZhang Wei struct fsl_desc_sw *new_desc) 189173acc7cSZhang Wei { 190173acc7cSZhang Wei struct fsl_desc_sw *queue_tail = to_fsl_desc(fsl_chan->ld_queue.prev); 191173acc7cSZhang Wei 192173acc7cSZhang Wei if (list_empty(&fsl_chan->ld_queue)) 193173acc7cSZhang Wei return; 194173acc7cSZhang Wei 195173acc7cSZhang Wei /* Link to the new descriptor physical address and 196173acc7cSZhang Wei * Enable End-of-segment interrupt for 197173acc7cSZhang Wei * the last link descriptor. 198173acc7cSZhang Wei * (the previous node's next link descriptor) 199173acc7cSZhang Wei * 200173acc7cSZhang Wei * For FSL_DMA_IP_83xx, the snoop enable bit need be set. 201173acc7cSZhang Wei */ 202173acc7cSZhang Wei queue_tail->hw.next_ln_addr = CPU_TO_DMA(fsl_chan, 203173acc7cSZhang Wei new_desc->async_tx.phys | FSL_DMA_EOSIE | 204173acc7cSZhang Wei (((fsl_chan->feature & FSL_DMA_IP_MASK) 205173acc7cSZhang Wei == FSL_DMA_IP_83XX) ? FSL_DMA_SNEN : 0), 64); 206173acc7cSZhang Wei } 207173acc7cSZhang Wei 208173acc7cSZhang Wei /** 209173acc7cSZhang Wei * fsl_chan_set_src_loop_size - Set source address hold transfer size 210173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 211173acc7cSZhang Wei * @size : Address loop size, 0 for disable loop 212173acc7cSZhang Wei * 213173acc7cSZhang Wei * The set source address hold transfer size. The source 214173acc7cSZhang Wei * address hold or loop transfer size is when the DMA transfer 215173acc7cSZhang Wei * data from source address (SA), if the loop size is 4, the DMA will 216173acc7cSZhang Wei * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA, 217173acc7cSZhang Wei * SA + 1 ... and so on. 218173acc7cSZhang Wei */ 219173acc7cSZhang Wei static void fsl_chan_set_src_loop_size(struct fsl_dma_chan *fsl_chan, int size) 220173acc7cSZhang Wei { 221173acc7cSZhang Wei switch (size) { 222173acc7cSZhang Wei case 0: 223173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 224173acc7cSZhang Wei DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) & 225173acc7cSZhang Wei (~FSL_DMA_MR_SAHE), 32); 226173acc7cSZhang Wei break; 227173acc7cSZhang Wei case 1: 228173acc7cSZhang Wei case 2: 229173acc7cSZhang Wei case 4: 230173acc7cSZhang Wei case 8: 231173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 232173acc7cSZhang Wei DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) | 233173acc7cSZhang Wei FSL_DMA_MR_SAHE | (__ilog2(size) << 14), 234173acc7cSZhang Wei 32); 235173acc7cSZhang Wei break; 236173acc7cSZhang Wei } 237173acc7cSZhang Wei } 238173acc7cSZhang Wei 239173acc7cSZhang Wei /** 240173acc7cSZhang Wei * fsl_chan_set_dest_loop_size - Set destination address hold transfer size 241173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 242173acc7cSZhang Wei * @size : Address loop size, 0 for disable loop 243173acc7cSZhang Wei * 244173acc7cSZhang Wei * The set destination address hold transfer size. The destination 245173acc7cSZhang Wei * address hold or loop transfer size is when the DMA transfer 246173acc7cSZhang Wei * data to destination address (TA), if the loop size is 4, the DMA will 247173acc7cSZhang Wei * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA, 248173acc7cSZhang Wei * TA + 1 ... and so on. 249173acc7cSZhang Wei */ 250173acc7cSZhang Wei static void fsl_chan_set_dest_loop_size(struct fsl_dma_chan *fsl_chan, int size) 251173acc7cSZhang Wei { 252173acc7cSZhang Wei switch (size) { 253173acc7cSZhang Wei case 0: 254173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 255173acc7cSZhang Wei DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) & 256173acc7cSZhang Wei (~FSL_DMA_MR_DAHE), 32); 257173acc7cSZhang Wei break; 258173acc7cSZhang Wei case 1: 259173acc7cSZhang Wei case 2: 260173acc7cSZhang Wei case 4: 261173acc7cSZhang Wei case 8: 262173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 263173acc7cSZhang Wei DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) | 264173acc7cSZhang Wei FSL_DMA_MR_DAHE | (__ilog2(size) << 16), 265173acc7cSZhang Wei 32); 266173acc7cSZhang Wei break; 267173acc7cSZhang Wei } 268173acc7cSZhang Wei } 269173acc7cSZhang Wei 270173acc7cSZhang Wei /** 271173acc7cSZhang Wei * fsl_chan_toggle_ext_pause - Toggle channel external pause status 272173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 273173acc7cSZhang Wei * @size : Pause control size, 0 for disable external pause control. 274173acc7cSZhang Wei * The maximum is 1024. 275173acc7cSZhang Wei * 276173acc7cSZhang Wei * The Freescale DMA channel can be controlled by the external 277173acc7cSZhang Wei * signal DREQ#. The pause control size is how many bytes are allowed 278173acc7cSZhang Wei * to transfer before pausing the channel, after which a new assertion 279173acc7cSZhang Wei * of DREQ# resumes channel operation. 280173acc7cSZhang Wei */ 281173acc7cSZhang Wei static void fsl_chan_toggle_ext_pause(struct fsl_dma_chan *fsl_chan, int size) 282173acc7cSZhang Wei { 283173acc7cSZhang Wei if (size > 1024) 284173acc7cSZhang Wei return; 285173acc7cSZhang Wei 286173acc7cSZhang Wei if (size) { 287173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 288173acc7cSZhang Wei DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) 289173acc7cSZhang Wei | ((__ilog2(size) << 24) & 0x0f000000), 290173acc7cSZhang Wei 32); 291173acc7cSZhang Wei fsl_chan->feature |= FSL_DMA_CHAN_PAUSE_EXT; 292173acc7cSZhang Wei } else 293173acc7cSZhang Wei fsl_chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT; 294173acc7cSZhang Wei } 295173acc7cSZhang Wei 296173acc7cSZhang Wei /** 297173acc7cSZhang Wei * fsl_chan_toggle_ext_start - Toggle channel external start status 298173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 299173acc7cSZhang Wei * @enable : 0 is disabled, 1 is enabled. 300173acc7cSZhang Wei * 301173acc7cSZhang Wei * If enable the external start, the channel can be started by an 302173acc7cSZhang Wei * external DMA start pin. So the dma_start() does not start the 303173acc7cSZhang Wei * transfer immediately. The DMA channel will wait for the 304173acc7cSZhang Wei * control pin asserted. 305173acc7cSZhang Wei */ 306173acc7cSZhang Wei static void fsl_chan_toggle_ext_start(struct fsl_dma_chan *fsl_chan, int enable) 307173acc7cSZhang Wei { 308173acc7cSZhang Wei if (enable) 309173acc7cSZhang Wei fsl_chan->feature |= FSL_DMA_CHAN_START_EXT; 310173acc7cSZhang Wei else 311173acc7cSZhang Wei fsl_chan->feature &= ~FSL_DMA_CHAN_START_EXT; 312173acc7cSZhang Wei } 313173acc7cSZhang Wei 314173acc7cSZhang Wei static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx) 315173acc7cSZhang Wei { 316173acc7cSZhang Wei struct fsl_desc_sw *desc = tx_to_fsl_desc(tx); 317173acc7cSZhang Wei struct fsl_dma_chan *fsl_chan = to_fsl_chan(tx->chan); 318173acc7cSZhang Wei unsigned long flags; 319173acc7cSZhang Wei dma_cookie_t cookie; 320173acc7cSZhang Wei 321173acc7cSZhang Wei /* cookie increment and adding to ld_queue must be atomic */ 322173acc7cSZhang Wei spin_lock_irqsave(&fsl_chan->desc_lock, flags); 323173acc7cSZhang Wei 324173acc7cSZhang Wei cookie = fsl_chan->common.cookie; 325173acc7cSZhang Wei cookie++; 326173acc7cSZhang Wei if (cookie < 0) 327173acc7cSZhang Wei cookie = 1; 328173acc7cSZhang Wei desc->async_tx.cookie = cookie; 329173acc7cSZhang Wei fsl_chan->common.cookie = desc->async_tx.cookie; 330173acc7cSZhang Wei 331173acc7cSZhang Wei append_ld_queue(fsl_chan, desc); 332173acc7cSZhang Wei list_splice_init(&desc->async_tx.tx_list, fsl_chan->ld_queue.prev); 333173acc7cSZhang Wei 334173acc7cSZhang Wei spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); 335173acc7cSZhang Wei 336173acc7cSZhang Wei return cookie; 337173acc7cSZhang Wei } 338173acc7cSZhang Wei 339173acc7cSZhang Wei /** 340173acc7cSZhang Wei * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool. 341173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 342173acc7cSZhang Wei * 343173acc7cSZhang Wei * Return - The descriptor allocated. NULL for failed. 344173acc7cSZhang Wei */ 345173acc7cSZhang Wei static struct fsl_desc_sw *fsl_dma_alloc_descriptor( 346173acc7cSZhang Wei struct fsl_dma_chan *fsl_chan) 347173acc7cSZhang Wei { 348173acc7cSZhang Wei dma_addr_t pdesc; 349173acc7cSZhang Wei struct fsl_desc_sw *desc_sw; 350173acc7cSZhang Wei 351173acc7cSZhang Wei desc_sw = dma_pool_alloc(fsl_chan->desc_pool, GFP_ATOMIC, &pdesc); 352173acc7cSZhang Wei if (desc_sw) { 353173acc7cSZhang Wei memset(desc_sw, 0, sizeof(struct fsl_desc_sw)); 354173acc7cSZhang Wei dma_async_tx_descriptor_init(&desc_sw->async_tx, 355173acc7cSZhang Wei &fsl_chan->common); 356173acc7cSZhang Wei desc_sw->async_tx.tx_submit = fsl_dma_tx_submit; 357173acc7cSZhang Wei desc_sw->async_tx.phys = pdesc; 358173acc7cSZhang Wei } 359173acc7cSZhang Wei 360173acc7cSZhang Wei return desc_sw; 361173acc7cSZhang Wei } 362173acc7cSZhang Wei 363173acc7cSZhang Wei 364173acc7cSZhang Wei /** 365173acc7cSZhang Wei * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel. 366173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 367173acc7cSZhang Wei * 368173acc7cSZhang Wei * This function will create a dma pool for descriptor allocation. 369173acc7cSZhang Wei * 370173acc7cSZhang Wei * Return - The number of descriptors allocated. 371173acc7cSZhang Wei */ 372aa1e6f1aSDan Williams static int fsl_dma_alloc_chan_resources(struct dma_chan *chan) 373173acc7cSZhang Wei { 374173acc7cSZhang Wei struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan); 37577cd62e8STimur Tabi 37677cd62e8STimur Tabi /* Has this channel already been allocated? */ 37777cd62e8STimur Tabi if (fsl_chan->desc_pool) 37877cd62e8STimur Tabi return 1; 379173acc7cSZhang Wei 380173acc7cSZhang Wei /* We need the descriptor to be aligned to 32bytes 381173acc7cSZhang Wei * for meeting FSL DMA specification requirement. 382173acc7cSZhang Wei */ 383173acc7cSZhang Wei fsl_chan->desc_pool = dma_pool_create("fsl_dma_engine_desc_pool", 384173acc7cSZhang Wei fsl_chan->dev, sizeof(struct fsl_desc_sw), 385173acc7cSZhang Wei 32, 0); 386173acc7cSZhang Wei if (!fsl_chan->desc_pool) { 387173acc7cSZhang Wei dev_err(fsl_chan->dev, "No memory for channel %d " 388173acc7cSZhang Wei "descriptor dma pool.\n", fsl_chan->id); 389173acc7cSZhang Wei return 0; 390173acc7cSZhang Wei } 391173acc7cSZhang Wei 392173acc7cSZhang Wei return 1; 393173acc7cSZhang Wei } 394173acc7cSZhang Wei 395173acc7cSZhang Wei /** 396173acc7cSZhang Wei * fsl_dma_free_chan_resources - Free all resources of the channel. 397173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 398173acc7cSZhang Wei */ 399173acc7cSZhang Wei static void fsl_dma_free_chan_resources(struct dma_chan *chan) 400173acc7cSZhang Wei { 401173acc7cSZhang Wei struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan); 402173acc7cSZhang Wei struct fsl_desc_sw *desc, *_desc; 403173acc7cSZhang Wei unsigned long flags; 404173acc7cSZhang Wei 405173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "Free all channel resources.\n"); 406173acc7cSZhang Wei spin_lock_irqsave(&fsl_chan->desc_lock, flags); 407173acc7cSZhang Wei list_for_each_entry_safe(desc, _desc, &fsl_chan->ld_queue, node) { 408173acc7cSZhang Wei #ifdef FSL_DMA_LD_DEBUG 409173acc7cSZhang Wei dev_dbg(fsl_chan->dev, 410173acc7cSZhang Wei "LD %p will be released.\n", desc); 411173acc7cSZhang Wei #endif 412173acc7cSZhang Wei list_del(&desc->node); 413173acc7cSZhang Wei /* free link descriptor */ 414173acc7cSZhang Wei dma_pool_free(fsl_chan->desc_pool, desc, desc->async_tx.phys); 415173acc7cSZhang Wei } 416173acc7cSZhang Wei spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); 417173acc7cSZhang Wei dma_pool_destroy(fsl_chan->desc_pool); 41877cd62e8STimur Tabi 41977cd62e8STimur Tabi fsl_chan->desc_pool = NULL; 420173acc7cSZhang Wei } 421173acc7cSZhang Wei 4222187c269SZhang Wei static struct dma_async_tx_descriptor * 423636bdeaaSDan Williams fsl_dma_prep_interrupt(struct dma_chan *chan, unsigned long flags) 4242187c269SZhang Wei { 4252187c269SZhang Wei struct fsl_dma_chan *fsl_chan; 4262187c269SZhang Wei struct fsl_desc_sw *new; 4272187c269SZhang Wei 4282187c269SZhang Wei if (!chan) 4292187c269SZhang Wei return NULL; 4302187c269SZhang Wei 4312187c269SZhang Wei fsl_chan = to_fsl_chan(chan); 4322187c269SZhang Wei 4332187c269SZhang Wei new = fsl_dma_alloc_descriptor(fsl_chan); 4342187c269SZhang Wei if (!new) { 4352187c269SZhang Wei dev_err(fsl_chan->dev, "No free memory for link descriptor\n"); 4362187c269SZhang Wei return NULL; 4372187c269SZhang Wei } 4382187c269SZhang Wei 4392187c269SZhang Wei new->async_tx.cookie = -EBUSY; 440636bdeaaSDan Williams new->async_tx.flags = flags; 4412187c269SZhang Wei 442f79abb62SZhang Wei /* Insert the link descriptor to the LD ring */ 443f79abb62SZhang Wei list_add_tail(&new->node, &new->async_tx.tx_list); 444f79abb62SZhang Wei 4452187c269SZhang Wei /* Set End-of-link to the last link descriptor of new list*/ 4462187c269SZhang Wei set_ld_eol(fsl_chan, new); 4472187c269SZhang Wei 4482187c269SZhang Wei return &new->async_tx; 4492187c269SZhang Wei } 4502187c269SZhang Wei 451173acc7cSZhang Wei static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy( 452173acc7cSZhang Wei struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src, 453173acc7cSZhang Wei size_t len, unsigned long flags) 454173acc7cSZhang Wei { 455173acc7cSZhang Wei struct fsl_dma_chan *fsl_chan; 456173acc7cSZhang Wei struct fsl_desc_sw *first = NULL, *prev = NULL, *new; 457173acc7cSZhang Wei size_t copy; 458173acc7cSZhang Wei LIST_HEAD(link_chain); 459173acc7cSZhang Wei 460173acc7cSZhang Wei if (!chan) 461173acc7cSZhang Wei return NULL; 462173acc7cSZhang Wei 463173acc7cSZhang Wei if (!len) 464173acc7cSZhang Wei return NULL; 465173acc7cSZhang Wei 466173acc7cSZhang Wei fsl_chan = to_fsl_chan(chan); 467173acc7cSZhang Wei 468173acc7cSZhang Wei do { 469173acc7cSZhang Wei 470173acc7cSZhang Wei /* Allocate the link descriptor from DMA pool */ 471173acc7cSZhang Wei new = fsl_dma_alloc_descriptor(fsl_chan); 472173acc7cSZhang Wei if (!new) { 473173acc7cSZhang Wei dev_err(fsl_chan->dev, 474173acc7cSZhang Wei "No free memory for link descriptor\n"); 475173acc7cSZhang Wei return NULL; 476173acc7cSZhang Wei } 477173acc7cSZhang Wei #ifdef FSL_DMA_LD_DEBUG 478173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "new link desc alloc %p\n", new); 479173acc7cSZhang Wei #endif 480173acc7cSZhang Wei 48156822843SZhang Wei copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT); 482173acc7cSZhang Wei 483173acc7cSZhang Wei set_desc_cnt(fsl_chan, &new->hw, copy); 484173acc7cSZhang Wei set_desc_src(fsl_chan, &new->hw, dma_src); 485173acc7cSZhang Wei set_desc_dest(fsl_chan, &new->hw, dma_dest); 486173acc7cSZhang Wei 487173acc7cSZhang Wei if (!first) 488173acc7cSZhang Wei first = new; 489173acc7cSZhang Wei else 490173acc7cSZhang Wei set_desc_next(fsl_chan, &prev->hw, new->async_tx.phys); 491173acc7cSZhang Wei 492173acc7cSZhang Wei new->async_tx.cookie = 0; 493636bdeaaSDan Williams async_tx_ack(&new->async_tx); 494173acc7cSZhang Wei 495173acc7cSZhang Wei prev = new; 496173acc7cSZhang Wei len -= copy; 497173acc7cSZhang Wei dma_src += copy; 498173acc7cSZhang Wei dma_dest += copy; 499173acc7cSZhang Wei 500173acc7cSZhang Wei /* Insert the link descriptor to the LD ring */ 501173acc7cSZhang Wei list_add_tail(&new->node, &first->async_tx.tx_list); 502173acc7cSZhang Wei } while (len); 503173acc7cSZhang Wei 504636bdeaaSDan Williams new->async_tx.flags = flags; /* client is in control of this ack */ 505173acc7cSZhang Wei new->async_tx.cookie = -EBUSY; 506173acc7cSZhang Wei 507173acc7cSZhang Wei /* Set End-of-link to the last link descriptor of new list*/ 508173acc7cSZhang Wei set_ld_eol(fsl_chan, new); 509173acc7cSZhang Wei 510173acc7cSZhang Wei return first ? &first->async_tx : NULL; 511173acc7cSZhang Wei } 512173acc7cSZhang Wei 513173acc7cSZhang Wei /** 514173acc7cSZhang Wei * fsl_dma_update_completed_cookie - Update the completed cookie. 515173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 516173acc7cSZhang Wei */ 517173acc7cSZhang Wei static void fsl_dma_update_completed_cookie(struct fsl_dma_chan *fsl_chan) 518173acc7cSZhang Wei { 519173acc7cSZhang Wei struct fsl_desc_sw *cur_desc, *desc; 520173acc7cSZhang Wei dma_addr_t ld_phy; 521173acc7cSZhang Wei 522173acc7cSZhang Wei ld_phy = get_cdar(fsl_chan) & FSL_DMA_NLDA_MASK; 523173acc7cSZhang Wei 524173acc7cSZhang Wei if (ld_phy) { 525173acc7cSZhang Wei cur_desc = NULL; 526173acc7cSZhang Wei list_for_each_entry(desc, &fsl_chan->ld_queue, node) 527173acc7cSZhang Wei if (desc->async_tx.phys == ld_phy) { 528173acc7cSZhang Wei cur_desc = desc; 529173acc7cSZhang Wei break; 530173acc7cSZhang Wei } 531173acc7cSZhang Wei 532173acc7cSZhang Wei if (cur_desc && cur_desc->async_tx.cookie) { 533173acc7cSZhang Wei if (dma_is_idle(fsl_chan)) 534173acc7cSZhang Wei fsl_chan->completed_cookie = 535173acc7cSZhang Wei cur_desc->async_tx.cookie; 536173acc7cSZhang Wei else 537173acc7cSZhang Wei fsl_chan->completed_cookie = 538173acc7cSZhang Wei cur_desc->async_tx.cookie - 1; 539173acc7cSZhang Wei } 540173acc7cSZhang Wei } 541173acc7cSZhang Wei } 542173acc7cSZhang Wei 543173acc7cSZhang Wei /** 544173acc7cSZhang Wei * fsl_chan_ld_cleanup - Clean up link descriptors 545173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 546173acc7cSZhang Wei * 547173acc7cSZhang Wei * This function clean up the ld_queue of DMA channel. 548173acc7cSZhang Wei * If 'in_intr' is set, the function will move the link descriptor to 549173acc7cSZhang Wei * the recycle list. Otherwise, free it directly. 550173acc7cSZhang Wei */ 551173acc7cSZhang Wei static void fsl_chan_ld_cleanup(struct fsl_dma_chan *fsl_chan) 552173acc7cSZhang Wei { 553173acc7cSZhang Wei struct fsl_desc_sw *desc, *_desc; 554173acc7cSZhang Wei unsigned long flags; 555173acc7cSZhang Wei 556173acc7cSZhang Wei spin_lock_irqsave(&fsl_chan->desc_lock, flags); 557173acc7cSZhang Wei 558173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "chan completed_cookie = %d\n", 559173acc7cSZhang Wei fsl_chan->completed_cookie); 560173acc7cSZhang Wei list_for_each_entry_safe(desc, _desc, &fsl_chan->ld_queue, node) { 561173acc7cSZhang Wei dma_async_tx_callback callback; 562173acc7cSZhang Wei void *callback_param; 563173acc7cSZhang Wei 564173acc7cSZhang Wei if (dma_async_is_complete(desc->async_tx.cookie, 565173acc7cSZhang Wei fsl_chan->completed_cookie, fsl_chan->common.cookie) 566173acc7cSZhang Wei == DMA_IN_PROGRESS) 567173acc7cSZhang Wei break; 568173acc7cSZhang Wei 569173acc7cSZhang Wei callback = desc->async_tx.callback; 570173acc7cSZhang Wei callback_param = desc->async_tx.callback_param; 571173acc7cSZhang Wei 572173acc7cSZhang Wei /* Remove from ld_queue list */ 573173acc7cSZhang Wei list_del(&desc->node); 574173acc7cSZhang Wei 575173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "link descriptor %p will be recycle.\n", 576173acc7cSZhang Wei desc); 577173acc7cSZhang Wei dma_pool_free(fsl_chan->desc_pool, desc, desc->async_tx.phys); 578173acc7cSZhang Wei 579173acc7cSZhang Wei /* Run the link descriptor callback function */ 580173acc7cSZhang Wei if (callback) { 581173acc7cSZhang Wei spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); 582173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "link descriptor %p callback\n", 583173acc7cSZhang Wei desc); 584173acc7cSZhang Wei callback(callback_param); 585173acc7cSZhang Wei spin_lock_irqsave(&fsl_chan->desc_lock, flags); 586173acc7cSZhang Wei } 587173acc7cSZhang Wei } 588173acc7cSZhang Wei spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); 589173acc7cSZhang Wei } 590173acc7cSZhang Wei 591173acc7cSZhang Wei /** 592173acc7cSZhang Wei * fsl_chan_xfer_ld_queue - Transfer link descriptors in channel ld_queue. 593173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 594173acc7cSZhang Wei */ 595173acc7cSZhang Wei static void fsl_chan_xfer_ld_queue(struct fsl_dma_chan *fsl_chan) 596173acc7cSZhang Wei { 597173acc7cSZhang Wei struct list_head *ld_node; 598173acc7cSZhang Wei dma_addr_t next_dest_addr; 599173acc7cSZhang Wei unsigned long flags; 600173acc7cSZhang Wei 601173acc7cSZhang Wei if (!dma_is_idle(fsl_chan)) 602173acc7cSZhang Wei return; 603173acc7cSZhang Wei 604173acc7cSZhang Wei dma_halt(fsl_chan); 605173acc7cSZhang Wei 606173acc7cSZhang Wei /* If there are some link descriptors 607173acc7cSZhang Wei * not transfered in queue. We need to start it. 608173acc7cSZhang Wei */ 609173acc7cSZhang Wei spin_lock_irqsave(&fsl_chan->desc_lock, flags); 610173acc7cSZhang Wei 611173acc7cSZhang Wei /* Find the first un-transfer desciptor */ 612173acc7cSZhang Wei for (ld_node = fsl_chan->ld_queue.next; 613173acc7cSZhang Wei (ld_node != &fsl_chan->ld_queue) 614173acc7cSZhang Wei && (dma_async_is_complete( 615173acc7cSZhang Wei to_fsl_desc(ld_node)->async_tx.cookie, 616173acc7cSZhang Wei fsl_chan->completed_cookie, 617173acc7cSZhang Wei fsl_chan->common.cookie) == DMA_SUCCESS); 618173acc7cSZhang Wei ld_node = ld_node->next); 619173acc7cSZhang Wei 620173acc7cSZhang Wei spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); 621173acc7cSZhang Wei 622173acc7cSZhang Wei if (ld_node != &fsl_chan->ld_queue) { 623173acc7cSZhang Wei /* Get the ld start address from ld_queue */ 624173acc7cSZhang Wei next_dest_addr = to_fsl_desc(ld_node)->async_tx.phys; 62556822843SZhang Wei dev_dbg(fsl_chan->dev, "xfer LDs staring from %p\n", 62656822843SZhang Wei (void *)next_dest_addr); 627173acc7cSZhang Wei set_cdar(fsl_chan, next_dest_addr); 628173acc7cSZhang Wei dma_start(fsl_chan); 629173acc7cSZhang Wei } else { 630173acc7cSZhang Wei set_cdar(fsl_chan, 0); 631173acc7cSZhang Wei set_ndar(fsl_chan, 0); 632173acc7cSZhang Wei } 633173acc7cSZhang Wei } 634173acc7cSZhang Wei 635173acc7cSZhang Wei /** 636173acc7cSZhang Wei * fsl_dma_memcpy_issue_pending - Issue the DMA start command 637173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 638173acc7cSZhang Wei */ 639173acc7cSZhang Wei static void fsl_dma_memcpy_issue_pending(struct dma_chan *chan) 640173acc7cSZhang Wei { 641173acc7cSZhang Wei struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan); 642173acc7cSZhang Wei 643173acc7cSZhang Wei #ifdef FSL_DMA_LD_DEBUG 644173acc7cSZhang Wei struct fsl_desc_sw *ld; 645173acc7cSZhang Wei unsigned long flags; 646173acc7cSZhang Wei 647173acc7cSZhang Wei spin_lock_irqsave(&fsl_chan->desc_lock, flags); 648173acc7cSZhang Wei if (list_empty(&fsl_chan->ld_queue)) { 649173acc7cSZhang Wei spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); 650173acc7cSZhang Wei return; 651173acc7cSZhang Wei } 652173acc7cSZhang Wei 653173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "--memcpy issue--\n"); 654173acc7cSZhang Wei list_for_each_entry(ld, &fsl_chan->ld_queue, node) { 655173acc7cSZhang Wei int i; 656173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "Ch %d, LD %08x\n", 657173acc7cSZhang Wei fsl_chan->id, ld->async_tx.phys); 658173acc7cSZhang Wei for (i = 0; i < 8; i++) 659173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "LD offset %d: %08x\n", 660173acc7cSZhang Wei i, *(((u32 *)&ld->hw) + i)); 661173acc7cSZhang Wei } 662173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "----------------\n"); 663173acc7cSZhang Wei spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); 664173acc7cSZhang Wei #endif 665173acc7cSZhang Wei 666173acc7cSZhang Wei fsl_chan_xfer_ld_queue(fsl_chan); 667173acc7cSZhang Wei } 668173acc7cSZhang Wei 669173acc7cSZhang Wei /** 670173acc7cSZhang Wei * fsl_dma_is_complete - Determine the DMA status 671173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 672173acc7cSZhang Wei */ 673173acc7cSZhang Wei static enum dma_status fsl_dma_is_complete(struct dma_chan *chan, 674173acc7cSZhang Wei dma_cookie_t cookie, 675173acc7cSZhang Wei dma_cookie_t *done, 676173acc7cSZhang Wei dma_cookie_t *used) 677173acc7cSZhang Wei { 678173acc7cSZhang Wei struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan); 679173acc7cSZhang Wei dma_cookie_t last_used; 680173acc7cSZhang Wei dma_cookie_t last_complete; 681173acc7cSZhang Wei 682173acc7cSZhang Wei fsl_chan_ld_cleanup(fsl_chan); 683173acc7cSZhang Wei 684173acc7cSZhang Wei last_used = chan->cookie; 685173acc7cSZhang Wei last_complete = fsl_chan->completed_cookie; 686173acc7cSZhang Wei 687173acc7cSZhang Wei if (done) 688173acc7cSZhang Wei *done = last_complete; 689173acc7cSZhang Wei 690173acc7cSZhang Wei if (used) 691173acc7cSZhang Wei *used = last_used; 692173acc7cSZhang Wei 693173acc7cSZhang Wei return dma_async_is_complete(cookie, last_complete, last_used); 694173acc7cSZhang Wei } 695173acc7cSZhang Wei 696173acc7cSZhang Wei static irqreturn_t fsl_dma_chan_do_interrupt(int irq, void *data) 697173acc7cSZhang Wei { 698173acc7cSZhang Wei struct fsl_dma_chan *fsl_chan = (struct fsl_dma_chan *)data; 69956822843SZhang Wei u32 stat; 7001c62979eSZhang Wei int update_cookie = 0; 7011c62979eSZhang Wei int xfer_ld_q = 0; 702173acc7cSZhang Wei 703173acc7cSZhang Wei stat = get_sr(fsl_chan); 704173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "event: channel %d, stat = 0x%x\n", 705173acc7cSZhang Wei fsl_chan->id, stat); 706173acc7cSZhang Wei set_sr(fsl_chan, stat); /* Clear the event register */ 707173acc7cSZhang Wei 708173acc7cSZhang Wei stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH); 709173acc7cSZhang Wei if (!stat) 710173acc7cSZhang Wei return IRQ_NONE; 711173acc7cSZhang Wei 712173acc7cSZhang Wei if (stat & FSL_DMA_SR_TE) 713173acc7cSZhang Wei dev_err(fsl_chan->dev, "Transfer Error!\n"); 714173acc7cSZhang Wei 715f79abb62SZhang Wei /* Programming Error 716f79abb62SZhang Wei * The DMA_INTERRUPT async_tx is a NULL transfer, which will 717f79abb62SZhang Wei * triger a PE interrupt. 718f79abb62SZhang Wei */ 719f79abb62SZhang Wei if (stat & FSL_DMA_SR_PE) { 720f79abb62SZhang Wei dev_dbg(fsl_chan->dev, "event: Programming Error INT\n"); 721f79abb62SZhang Wei if (get_bcr(fsl_chan) == 0) { 722f79abb62SZhang Wei /* BCR register is 0, this is a DMA_INTERRUPT async_tx. 723f79abb62SZhang Wei * Now, update the completed cookie, and continue the 724f79abb62SZhang Wei * next uncompleted transfer. 725f79abb62SZhang Wei */ 7261c62979eSZhang Wei update_cookie = 1; 7271c62979eSZhang Wei xfer_ld_q = 1; 728f79abb62SZhang Wei } 729f79abb62SZhang Wei stat &= ~FSL_DMA_SR_PE; 730f79abb62SZhang Wei } 731f79abb62SZhang Wei 732173acc7cSZhang Wei /* If the link descriptor segment transfer finishes, 733173acc7cSZhang Wei * we will recycle the used descriptor. 734173acc7cSZhang Wei */ 735173acc7cSZhang Wei if (stat & FSL_DMA_SR_EOSI) { 736173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "event: End-of-segments INT\n"); 73756822843SZhang Wei dev_dbg(fsl_chan->dev, "event: clndar %p, nlndar %p\n", 73856822843SZhang Wei (void *)get_cdar(fsl_chan), (void *)get_ndar(fsl_chan)); 739173acc7cSZhang Wei stat &= ~FSL_DMA_SR_EOSI; 7401c62979eSZhang Wei update_cookie = 1; 7411c62979eSZhang Wei } 7421c62979eSZhang Wei 7431c62979eSZhang Wei /* For MPC8349, EOCDI event need to update cookie 7441c62979eSZhang Wei * and start the next transfer if it exist. 7451c62979eSZhang Wei */ 7461c62979eSZhang Wei if (stat & FSL_DMA_SR_EOCDI) { 7471c62979eSZhang Wei dev_dbg(fsl_chan->dev, "event: End-of-Chain link INT\n"); 7481c62979eSZhang Wei stat &= ~FSL_DMA_SR_EOCDI; 7491c62979eSZhang Wei update_cookie = 1; 7501c62979eSZhang Wei xfer_ld_q = 1; 751173acc7cSZhang Wei } 752173acc7cSZhang Wei 753173acc7cSZhang Wei /* If it current transfer is the end-of-transfer, 754173acc7cSZhang Wei * we should clear the Channel Start bit for 755173acc7cSZhang Wei * prepare next transfer. 756173acc7cSZhang Wei */ 7571c62979eSZhang Wei if (stat & FSL_DMA_SR_EOLNI) { 758173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "event: End-of-link INT\n"); 759173acc7cSZhang Wei stat &= ~FSL_DMA_SR_EOLNI; 7601c62979eSZhang Wei xfer_ld_q = 1; 761173acc7cSZhang Wei } 762173acc7cSZhang Wei 7631c62979eSZhang Wei if (update_cookie) 7641c62979eSZhang Wei fsl_dma_update_completed_cookie(fsl_chan); 7651c62979eSZhang Wei if (xfer_ld_q) 7661c62979eSZhang Wei fsl_chan_xfer_ld_queue(fsl_chan); 767173acc7cSZhang Wei if (stat) 768173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "event: unhandled sr 0x%02x\n", 769173acc7cSZhang Wei stat); 770173acc7cSZhang Wei 771173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "event: Exit\n"); 772173acc7cSZhang Wei tasklet_schedule(&fsl_chan->tasklet); 773173acc7cSZhang Wei return IRQ_HANDLED; 774173acc7cSZhang Wei } 775173acc7cSZhang Wei 776173acc7cSZhang Wei static irqreturn_t fsl_dma_do_interrupt(int irq, void *data) 777173acc7cSZhang Wei { 778173acc7cSZhang Wei struct fsl_dma_device *fdev = (struct fsl_dma_device *)data; 779173acc7cSZhang Wei u32 gsr; 780173acc7cSZhang Wei int ch_nr; 781173acc7cSZhang Wei 782173acc7cSZhang Wei gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->reg_base) 783173acc7cSZhang Wei : in_le32(fdev->reg_base); 784173acc7cSZhang Wei ch_nr = (32 - ffs(gsr)) / 8; 785173acc7cSZhang Wei 786173acc7cSZhang Wei return fdev->chan[ch_nr] ? fsl_dma_chan_do_interrupt(irq, 787173acc7cSZhang Wei fdev->chan[ch_nr]) : IRQ_NONE; 788173acc7cSZhang Wei } 789173acc7cSZhang Wei 790173acc7cSZhang Wei static void dma_do_tasklet(unsigned long data) 791173acc7cSZhang Wei { 792173acc7cSZhang Wei struct fsl_dma_chan *fsl_chan = (struct fsl_dma_chan *)data; 793173acc7cSZhang Wei fsl_chan_ld_cleanup(fsl_chan); 794173acc7cSZhang Wei } 795173acc7cSZhang Wei 79677cd62e8STimur Tabi static int __devinit fsl_dma_chan_probe(struct fsl_dma_device *fdev, 79777cd62e8STimur Tabi struct device_node *node, u32 feature, const char *compatible) 798173acc7cSZhang Wei { 799173acc7cSZhang Wei struct fsl_dma_chan *new_fsl_chan; 800173acc7cSZhang Wei int err; 801173acc7cSZhang Wei 802173acc7cSZhang Wei /* alloc channel */ 803173acc7cSZhang Wei new_fsl_chan = kzalloc(sizeof(struct fsl_dma_chan), GFP_KERNEL); 804173acc7cSZhang Wei if (!new_fsl_chan) { 80577cd62e8STimur Tabi dev_err(fdev->dev, "No free memory for allocating " 806173acc7cSZhang Wei "dma channels!\n"); 80751ee87f2SLi Yang return -ENOMEM; 808173acc7cSZhang Wei } 809173acc7cSZhang Wei 810173acc7cSZhang Wei /* get dma channel register base */ 81177cd62e8STimur Tabi err = of_address_to_resource(node, 0, &new_fsl_chan->reg); 812173acc7cSZhang Wei if (err) { 81377cd62e8STimur Tabi dev_err(fdev->dev, "Can't get %s property 'reg'\n", 81477cd62e8STimur Tabi node->full_name); 81551ee87f2SLi Yang goto err_no_reg; 816173acc7cSZhang Wei } 817173acc7cSZhang Wei 81877cd62e8STimur Tabi new_fsl_chan->feature = feature; 819173acc7cSZhang Wei 820173acc7cSZhang Wei if (!fdev->feature) 821173acc7cSZhang Wei fdev->feature = new_fsl_chan->feature; 822173acc7cSZhang Wei 823173acc7cSZhang Wei /* If the DMA device's feature is different than its channels', 824173acc7cSZhang Wei * report the bug. 825173acc7cSZhang Wei */ 826173acc7cSZhang Wei WARN_ON(fdev->feature != new_fsl_chan->feature); 827173acc7cSZhang Wei 8286527de6dSDan Williams new_fsl_chan->dev = fdev->dev; 829173acc7cSZhang Wei new_fsl_chan->reg_base = ioremap(new_fsl_chan->reg.start, 830173acc7cSZhang Wei new_fsl_chan->reg.end - new_fsl_chan->reg.start + 1); 831173acc7cSZhang Wei 832173acc7cSZhang Wei new_fsl_chan->id = ((new_fsl_chan->reg.start - 0x100) & 0xfff) >> 7; 833f47edc6dSRoel Kluin if (new_fsl_chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) { 83477cd62e8STimur Tabi dev_err(fdev->dev, "There is no %d channel!\n", 835173acc7cSZhang Wei new_fsl_chan->id); 836173acc7cSZhang Wei err = -EINVAL; 83751ee87f2SLi Yang goto err_no_chan; 838173acc7cSZhang Wei } 839173acc7cSZhang Wei fdev->chan[new_fsl_chan->id] = new_fsl_chan; 840173acc7cSZhang Wei tasklet_init(&new_fsl_chan->tasklet, dma_do_tasklet, 841173acc7cSZhang Wei (unsigned long)new_fsl_chan); 842173acc7cSZhang Wei 843173acc7cSZhang Wei /* Init the channel */ 844173acc7cSZhang Wei dma_init(new_fsl_chan); 845173acc7cSZhang Wei 846173acc7cSZhang Wei /* Clear cdar registers */ 847173acc7cSZhang Wei set_cdar(new_fsl_chan, 0); 848173acc7cSZhang Wei 849173acc7cSZhang Wei switch (new_fsl_chan->feature & FSL_DMA_IP_MASK) { 850173acc7cSZhang Wei case FSL_DMA_IP_85XX: 851173acc7cSZhang Wei new_fsl_chan->toggle_ext_start = fsl_chan_toggle_ext_start; 852173acc7cSZhang Wei new_fsl_chan->toggle_ext_pause = fsl_chan_toggle_ext_pause; 853173acc7cSZhang Wei case FSL_DMA_IP_83XX: 854173acc7cSZhang Wei new_fsl_chan->set_src_loop_size = fsl_chan_set_src_loop_size; 855173acc7cSZhang Wei new_fsl_chan->set_dest_loop_size = fsl_chan_set_dest_loop_size; 856173acc7cSZhang Wei } 857173acc7cSZhang Wei 858173acc7cSZhang Wei spin_lock_init(&new_fsl_chan->desc_lock); 859173acc7cSZhang Wei INIT_LIST_HEAD(&new_fsl_chan->ld_queue); 860173acc7cSZhang Wei 861173acc7cSZhang Wei new_fsl_chan->common.device = &fdev->common; 862173acc7cSZhang Wei 863173acc7cSZhang Wei /* Add the channel to DMA device channel list */ 864173acc7cSZhang Wei list_add_tail(&new_fsl_chan->common.device_node, 865173acc7cSZhang Wei &fdev->common.channels); 866173acc7cSZhang Wei fdev->common.chancnt++; 867173acc7cSZhang Wei 86877cd62e8STimur Tabi new_fsl_chan->irq = irq_of_parse_and_map(node, 0); 869173acc7cSZhang Wei if (new_fsl_chan->irq != NO_IRQ) { 870173acc7cSZhang Wei err = request_irq(new_fsl_chan->irq, 871173acc7cSZhang Wei &fsl_dma_chan_do_interrupt, IRQF_SHARED, 872173acc7cSZhang Wei "fsldma-channel", new_fsl_chan); 873173acc7cSZhang Wei if (err) { 87477cd62e8STimur Tabi dev_err(fdev->dev, "DMA channel %s request_irq error " 87577cd62e8STimur Tabi "with return %d\n", node->full_name, err); 87651ee87f2SLi Yang goto err_no_irq; 877173acc7cSZhang Wei } 878173acc7cSZhang Wei } 879173acc7cSZhang Wei 88077cd62e8STimur Tabi dev_info(fdev->dev, "#%d (%s), irq %d\n", new_fsl_chan->id, 881169d5f66SPeter Korsgaard compatible, 882169d5f66SPeter Korsgaard new_fsl_chan->irq != NO_IRQ ? new_fsl_chan->irq : fdev->irq); 883173acc7cSZhang Wei 884173acc7cSZhang Wei return 0; 88551ee87f2SLi Yang 88651ee87f2SLi Yang err_no_irq: 887173acc7cSZhang Wei list_del(&new_fsl_chan->common.device_node); 88851ee87f2SLi Yang err_no_chan: 88951ee87f2SLi Yang iounmap(new_fsl_chan->reg_base); 89051ee87f2SLi Yang err_no_reg: 891173acc7cSZhang Wei kfree(new_fsl_chan); 892173acc7cSZhang Wei return err; 893173acc7cSZhang Wei } 894173acc7cSZhang Wei 89577cd62e8STimur Tabi static void fsl_dma_chan_remove(struct fsl_dma_chan *fchan) 896173acc7cSZhang Wei { 8976782dfe4SPeter Korsgaard if (fchan->irq != NO_IRQ) 89877cd62e8STimur Tabi free_irq(fchan->irq, fchan); 89977cd62e8STimur Tabi list_del(&fchan->common.device_node); 90077cd62e8STimur Tabi iounmap(fchan->reg_base); 90177cd62e8STimur Tabi kfree(fchan); 902173acc7cSZhang Wei } 903173acc7cSZhang Wei 904173acc7cSZhang Wei static int __devinit of_fsl_dma_probe(struct of_device *dev, 905173acc7cSZhang Wei const struct of_device_id *match) 906173acc7cSZhang Wei { 907173acc7cSZhang Wei int err; 908173acc7cSZhang Wei struct fsl_dma_device *fdev; 90977cd62e8STimur Tabi struct device_node *child; 910173acc7cSZhang Wei 911173acc7cSZhang Wei fdev = kzalloc(sizeof(struct fsl_dma_device), GFP_KERNEL); 912173acc7cSZhang Wei if (!fdev) { 913173acc7cSZhang Wei dev_err(&dev->dev, "No enough memory for 'priv'\n"); 91451ee87f2SLi Yang return -ENOMEM; 915173acc7cSZhang Wei } 916173acc7cSZhang Wei fdev->dev = &dev->dev; 917173acc7cSZhang Wei INIT_LIST_HEAD(&fdev->common.channels); 918173acc7cSZhang Wei 919173acc7cSZhang Wei /* get DMA controller register base */ 920173acc7cSZhang Wei err = of_address_to_resource(dev->node, 0, &fdev->reg); 921173acc7cSZhang Wei if (err) { 922173acc7cSZhang Wei dev_err(&dev->dev, "Can't get %s property 'reg'\n", 923173acc7cSZhang Wei dev->node->full_name); 92451ee87f2SLi Yang goto err_no_reg; 925173acc7cSZhang Wei } 926173acc7cSZhang Wei 927173acc7cSZhang Wei dev_info(&dev->dev, "Probe the Freescale DMA driver for %s " 92856822843SZhang Wei "controller at %p...\n", 92956822843SZhang Wei match->compatible, (void *)fdev->reg.start); 930173acc7cSZhang Wei fdev->reg_base = ioremap(fdev->reg.start, fdev->reg.end 931173acc7cSZhang Wei - fdev->reg.start + 1); 932173acc7cSZhang Wei 933173acc7cSZhang Wei dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask); 934173acc7cSZhang Wei dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask); 935173acc7cSZhang Wei fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources; 936173acc7cSZhang Wei fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources; 9372187c269SZhang Wei fdev->common.device_prep_dma_interrupt = fsl_dma_prep_interrupt; 938173acc7cSZhang Wei fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy; 939173acc7cSZhang Wei fdev->common.device_is_tx_complete = fsl_dma_is_complete; 940173acc7cSZhang Wei fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending; 941173acc7cSZhang Wei fdev->common.dev = &dev->dev; 942173acc7cSZhang Wei 94377cd62e8STimur Tabi fdev->irq = irq_of_parse_and_map(dev->node, 0); 94477cd62e8STimur Tabi if (fdev->irq != NO_IRQ) { 94577cd62e8STimur Tabi err = request_irq(fdev->irq, &fsl_dma_do_interrupt, IRQF_SHARED, 946173acc7cSZhang Wei "fsldma-device", fdev); 947173acc7cSZhang Wei if (err) { 948173acc7cSZhang Wei dev_err(&dev->dev, "DMA device request_irq error " 949173acc7cSZhang Wei "with return %d\n", err); 950173acc7cSZhang Wei goto err; 951173acc7cSZhang Wei } 952173acc7cSZhang Wei } 953173acc7cSZhang Wei 954173acc7cSZhang Wei dev_set_drvdata(&(dev->dev), fdev); 95577cd62e8STimur Tabi 95677cd62e8STimur Tabi /* We cannot use of_platform_bus_probe() because there is no 95777cd62e8STimur Tabi * of_platform_bus_remove. Instead, we manually instantiate every DMA 95877cd62e8STimur Tabi * channel object. 95977cd62e8STimur Tabi */ 96077cd62e8STimur Tabi for_each_child_of_node(dev->node, child) { 96177cd62e8STimur Tabi if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) 96277cd62e8STimur Tabi fsl_dma_chan_probe(fdev, child, 96377cd62e8STimur Tabi FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN, 96477cd62e8STimur Tabi "fsl,eloplus-dma-channel"); 96577cd62e8STimur Tabi if (of_device_is_compatible(child, "fsl,elo-dma-channel")) 96677cd62e8STimur Tabi fsl_dma_chan_probe(fdev, child, 96777cd62e8STimur Tabi FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN, 96877cd62e8STimur Tabi "fsl,elo-dma-channel"); 96977cd62e8STimur Tabi } 970173acc7cSZhang Wei 971173acc7cSZhang Wei dma_async_device_register(&fdev->common); 972173acc7cSZhang Wei return 0; 973173acc7cSZhang Wei 974173acc7cSZhang Wei err: 975173acc7cSZhang Wei iounmap(fdev->reg_base); 97651ee87f2SLi Yang err_no_reg: 977173acc7cSZhang Wei kfree(fdev); 978173acc7cSZhang Wei return err; 979173acc7cSZhang Wei } 980173acc7cSZhang Wei 98177cd62e8STimur Tabi static int of_fsl_dma_remove(struct of_device *of_dev) 98277cd62e8STimur Tabi { 98377cd62e8STimur Tabi struct fsl_dma_device *fdev; 98477cd62e8STimur Tabi unsigned int i; 98577cd62e8STimur Tabi 98677cd62e8STimur Tabi fdev = dev_get_drvdata(&of_dev->dev); 98777cd62e8STimur Tabi 98877cd62e8STimur Tabi dma_async_device_unregister(&fdev->common); 98977cd62e8STimur Tabi 99077cd62e8STimur Tabi for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) 99177cd62e8STimur Tabi if (fdev->chan[i]) 99277cd62e8STimur Tabi fsl_dma_chan_remove(fdev->chan[i]); 99377cd62e8STimur Tabi 99477cd62e8STimur Tabi if (fdev->irq != NO_IRQ) 99577cd62e8STimur Tabi free_irq(fdev->irq, fdev); 99677cd62e8STimur Tabi 99777cd62e8STimur Tabi iounmap(fdev->reg_base); 99877cd62e8STimur Tabi 99977cd62e8STimur Tabi kfree(fdev); 100077cd62e8STimur Tabi dev_set_drvdata(&of_dev->dev, NULL); 100177cd62e8STimur Tabi 100277cd62e8STimur Tabi return 0; 100377cd62e8STimur Tabi } 100477cd62e8STimur Tabi 1005173acc7cSZhang Wei static struct of_device_id of_fsl_dma_ids[] = { 1006049c9d45SKumar Gala { .compatible = "fsl,eloplus-dma", }, 1007049c9d45SKumar Gala { .compatible = "fsl,elo-dma", }, 1008173acc7cSZhang Wei {} 1009173acc7cSZhang Wei }; 1010173acc7cSZhang Wei 1011173acc7cSZhang Wei static struct of_platform_driver of_fsl_dma_driver = { 101277cd62e8STimur Tabi .name = "fsl-elo-dma", 1013173acc7cSZhang Wei .match_table = of_fsl_dma_ids, 1014173acc7cSZhang Wei .probe = of_fsl_dma_probe, 101577cd62e8STimur Tabi .remove = of_fsl_dma_remove, 1016173acc7cSZhang Wei }; 1017173acc7cSZhang Wei 1018173acc7cSZhang Wei static __init int of_fsl_dma_init(void) 1019173acc7cSZhang Wei { 102077cd62e8STimur Tabi int ret; 102177cd62e8STimur Tabi 102277cd62e8STimur Tabi pr_info("Freescale Elo / Elo Plus DMA driver\n"); 102377cd62e8STimur Tabi 102477cd62e8STimur Tabi ret = of_register_platform_driver(&of_fsl_dma_driver); 102577cd62e8STimur Tabi if (ret) 102677cd62e8STimur Tabi pr_err("fsldma: failed to register platform driver\n"); 102777cd62e8STimur Tabi 102877cd62e8STimur Tabi return ret; 1029173acc7cSZhang Wei } 1030173acc7cSZhang Wei 103177cd62e8STimur Tabi static void __exit of_fsl_dma_exit(void) 103277cd62e8STimur Tabi { 103377cd62e8STimur Tabi of_unregister_platform_driver(&of_fsl_dma_driver); 103477cd62e8STimur Tabi } 103577cd62e8STimur Tabi 1036173acc7cSZhang Wei subsys_initcall(of_fsl_dma_init); 103777cd62e8STimur Tabi module_exit(of_fsl_dma_exit); 103877cd62e8STimur Tabi 103977cd62e8STimur Tabi MODULE_DESCRIPTION("Freescale Elo / Elo Plus DMA driver"); 104077cd62e8STimur Tabi MODULE_LICENSE("GPL"); 1041