1173acc7cSZhang Wei /* 2173acc7cSZhang Wei * Freescale MPC85xx, MPC83xx DMA Engine support 3173acc7cSZhang Wei * 4173acc7cSZhang Wei * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved. 5173acc7cSZhang Wei * 6173acc7cSZhang Wei * Author: 7173acc7cSZhang Wei * Zhang Wei <wei.zhang@freescale.com>, Jul 2007 8173acc7cSZhang Wei * Ebony Zhu <ebony.zhu@freescale.com>, May 2007 9173acc7cSZhang Wei * 10173acc7cSZhang Wei * Description: 11173acc7cSZhang Wei * DMA engine driver for Freescale MPC8540 DMA controller, which is 12173acc7cSZhang Wei * also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc. 13173acc7cSZhang Wei * The support for MPC8349 DMA contorller is also added. 14173acc7cSZhang Wei * 15a7aea373SIra W. Snyder * This driver instructs the DMA controller to issue the PCI Read Multiple 16a7aea373SIra W. Snyder * command for PCI read operations, instead of using the default PCI Read Line 17a7aea373SIra W. Snyder * command. Please be aware that this setting may result in read pre-fetching 18a7aea373SIra W. Snyder * on some platforms. 19a7aea373SIra W. Snyder * 20173acc7cSZhang Wei * This is free software; you can redistribute it and/or modify 21173acc7cSZhang Wei * it under the terms of the GNU General Public License as published by 22173acc7cSZhang Wei * the Free Software Foundation; either version 2 of the License, or 23173acc7cSZhang Wei * (at your option) any later version. 24173acc7cSZhang Wei * 25173acc7cSZhang Wei */ 26173acc7cSZhang Wei 27173acc7cSZhang Wei #include <linux/init.h> 28173acc7cSZhang Wei #include <linux/module.h> 29173acc7cSZhang Wei #include <linux/pci.h> 30173acc7cSZhang Wei #include <linux/interrupt.h> 31173acc7cSZhang Wei #include <linux/dmaengine.h> 32173acc7cSZhang Wei #include <linux/delay.h> 33173acc7cSZhang Wei #include <linux/dma-mapping.h> 34173acc7cSZhang Wei #include <linux/dmapool.h> 35173acc7cSZhang Wei #include <linux/of_platform.h> 36173acc7cSZhang Wei 37173acc7cSZhang Wei #include "fsldma.h" 38173acc7cSZhang Wei 39173acc7cSZhang Wei static void dma_init(struct fsl_dma_chan *fsl_chan) 40173acc7cSZhang Wei { 41173acc7cSZhang Wei /* Reset the channel */ 42173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 0, 32); 43173acc7cSZhang Wei 44173acc7cSZhang Wei switch (fsl_chan->feature & FSL_DMA_IP_MASK) { 45173acc7cSZhang Wei case FSL_DMA_IP_85XX: 46173acc7cSZhang Wei /* Set the channel to below modes: 47173acc7cSZhang Wei * EIE - Error interrupt enable 48173acc7cSZhang Wei * EOSIE - End of segments interrupt enable (basic mode) 49173acc7cSZhang Wei * EOLNIE - End of links interrupt enable 50173acc7cSZhang Wei */ 51173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, FSL_DMA_MR_EIE 52173acc7cSZhang Wei | FSL_DMA_MR_EOLNIE | FSL_DMA_MR_EOSIE, 32); 53173acc7cSZhang Wei break; 54173acc7cSZhang Wei case FSL_DMA_IP_83XX: 55173acc7cSZhang Wei /* Set the channel to below modes: 56173acc7cSZhang Wei * EOTIE - End-of-transfer interrupt enable 57a7aea373SIra W. Snyder * PRC_RM - PCI read multiple 58173acc7cSZhang Wei */ 59a7aea373SIra W. Snyder DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, FSL_DMA_MR_EOTIE 60a7aea373SIra W. Snyder | FSL_DMA_MR_PRC_RM, 32); 61173acc7cSZhang Wei break; 62173acc7cSZhang Wei } 63173acc7cSZhang Wei 64173acc7cSZhang Wei } 65173acc7cSZhang Wei 6656822843SZhang Wei static void set_sr(struct fsl_dma_chan *fsl_chan, u32 val) 67173acc7cSZhang Wei { 68173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->sr, val, 32); 69173acc7cSZhang Wei } 70173acc7cSZhang Wei 7156822843SZhang Wei static u32 get_sr(struct fsl_dma_chan *fsl_chan) 72173acc7cSZhang Wei { 73173acc7cSZhang Wei return DMA_IN(fsl_chan, &fsl_chan->reg_base->sr, 32); 74173acc7cSZhang Wei } 75173acc7cSZhang Wei 76173acc7cSZhang Wei static void set_desc_cnt(struct fsl_dma_chan *fsl_chan, 77173acc7cSZhang Wei struct fsl_dma_ld_hw *hw, u32 count) 78173acc7cSZhang Wei { 79173acc7cSZhang Wei hw->count = CPU_TO_DMA(fsl_chan, count, 32); 80173acc7cSZhang Wei } 81173acc7cSZhang Wei 82173acc7cSZhang Wei static void set_desc_src(struct fsl_dma_chan *fsl_chan, 83173acc7cSZhang Wei struct fsl_dma_ld_hw *hw, dma_addr_t src) 84173acc7cSZhang Wei { 85173acc7cSZhang Wei u64 snoop_bits; 86173acc7cSZhang Wei 87173acc7cSZhang Wei snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) 88173acc7cSZhang Wei ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0; 89173acc7cSZhang Wei hw->src_addr = CPU_TO_DMA(fsl_chan, snoop_bits | src, 64); 90173acc7cSZhang Wei } 91173acc7cSZhang Wei 92173acc7cSZhang Wei static void set_desc_dest(struct fsl_dma_chan *fsl_chan, 93173acc7cSZhang Wei struct fsl_dma_ld_hw *hw, dma_addr_t dest) 94173acc7cSZhang Wei { 95173acc7cSZhang Wei u64 snoop_bits; 96173acc7cSZhang Wei 97173acc7cSZhang Wei snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) 98173acc7cSZhang Wei ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0; 99173acc7cSZhang Wei hw->dst_addr = CPU_TO_DMA(fsl_chan, snoop_bits | dest, 64); 100173acc7cSZhang Wei } 101173acc7cSZhang Wei 102173acc7cSZhang Wei static void set_desc_next(struct fsl_dma_chan *fsl_chan, 103173acc7cSZhang Wei struct fsl_dma_ld_hw *hw, dma_addr_t next) 104173acc7cSZhang Wei { 105173acc7cSZhang Wei u64 snoop_bits; 106173acc7cSZhang Wei 107173acc7cSZhang Wei snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) 108173acc7cSZhang Wei ? FSL_DMA_SNEN : 0; 109173acc7cSZhang Wei hw->next_ln_addr = CPU_TO_DMA(fsl_chan, snoop_bits | next, 64); 110173acc7cSZhang Wei } 111173acc7cSZhang Wei 112173acc7cSZhang Wei static void set_cdar(struct fsl_dma_chan *fsl_chan, dma_addr_t addr) 113173acc7cSZhang Wei { 114173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->cdar, addr | FSL_DMA_SNEN, 64); 115173acc7cSZhang Wei } 116173acc7cSZhang Wei 117173acc7cSZhang Wei static dma_addr_t get_cdar(struct fsl_dma_chan *fsl_chan) 118173acc7cSZhang Wei { 119173acc7cSZhang Wei return DMA_IN(fsl_chan, &fsl_chan->reg_base->cdar, 64) & ~FSL_DMA_SNEN; 120173acc7cSZhang Wei } 121173acc7cSZhang Wei 122173acc7cSZhang Wei static void set_ndar(struct fsl_dma_chan *fsl_chan, dma_addr_t addr) 123173acc7cSZhang Wei { 124173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->ndar, addr, 64); 125173acc7cSZhang Wei } 126173acc7cSZhang Wei 127173acc7cSZhang Wei static dma_addr_t get_ndar(struct fsl_dma_chan *fsl_chan) 128173acc7cSZhang Wei { 129173acc7cSZhang Wei return DMA_IN(fsl_chan, &fsl_chan->reg_base->ndar, 64); 130173acc7cSZhang Wei } 131173acc7cSZhang Wei 132f79abb62SZhang Wei static u32 get_bcr(struct fsl_dma_chan *fsl_chan) 133f79abb62SZhang Wei { 134f79abb62SZhang Wei return DMA_IN(fsl_chan, &fsl_chan->reg_base->bcr, 32); 135f79abb62SZhang Wei } 136f79abb62SZhang Wei 137173acc7cSZhang Wei static int dma_is_idle(struct fsl_dma_chan *fsl_chan) 138173acc7cSZhang Wei { 139173acc7cSZhang Wei u32 sr = get_sr(fsl_chan); 140173acc7cSZhang Wei return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH); 141173acc7cSZhang Wei } 142173acc7cSZhang Wei 143173acc7cSZhang Wei static void dma_start(struct fsl_dma_chan *fsl_chan) 144173acc7cSZhang Wei { 145e3d43304SJoe Perches u32 mr_set = 0; 146173acc7cSZhang Wei 147173acc7cSZhang Wei if (fsl_chan->feature & FSL_DMA_CHAN_PAUSE_EXT) { 148173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->bcr, 0, 32); 149173acc7cSZhang Wei mr_set |= FSL_DMA_MR_EMP_EN; 15043a1a3edSIra Snyder } else if ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) { 151173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 152173acc7cSZhang Wei DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) 153173acc7cSZhang Wei & ~FSL_DMA_MR_EMP_EN, 32); 15443a1a3edSIra Snyder } 155173acc7cSZhang Wei 156173acc7cSZhang Wei if (fsl_chan->feature & FSL_DMA_CHAN_START_EXT) 157173acc7cSZhang Wei mr_set |= FSL_DMA_MR_EMS_EN; 158173acc7cSZhang Wei else 159173acc7cSZhang Wei mr_set |= FSL_DMA_MR_CS; 160173acc7cSZhang Wei 161173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 162173acc7cSZhang Wei DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) 163173acc7cSZhang Wei | mr_set, 32); 164173acc7cSZhang Wei } 165173acc7cSZhang Wei 166173acc7cSZhang Wei static void dma_halt(struct fsl_dma_chan *fsl_chan) 167173acc7cSZhang Wei { 168900325a6SDan Williams int i; 169900325a6SDan Williams 170173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 171173acc7cSZhang Wei DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) | FSL_DMA_MR_CA, 172173acc7cSZhang Wei 32); 173173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 174173acc7cSZhang Wei DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) & ~(FSL_DMA_MR_CS 175173acc7cSZhang Wei | FSL_DMA_MR_EMS_EN | FSL_DMA_MR_CA), 32); 176173acc7cSZhang Wei 177900325a6SDan Williams for (i = 0; i < 100; i++) { 178900325a6SDan Williams if (dma_is_idle(fsl_chan)) 179900325a6SDan Williams break; 180173acc7cSZhang Wei udelay(10); 181900325a6SDan Williams } 182173acc7cSZhang Wei if (i >= 100 && !dma_is_idle(fsl_chan)) 183173acc7cSZhang Wei dev_err(fsl_chan->dev, "DMA halt timeout!\n"); 184173acc7cSZhang Wei } 185173acc7cSZhang Wei 186173acc7cSZhang Wei static void set_ld_eol(struct fsl_dma_chan *fsl_chan, 187173acc7cSZhang Wei struct fsl_desc_sw *desc) 188173acc7cSZhang Wei { 189776c8943SIra Snyder u64 snoop_bits; 190776c8943SIra Snyder 191776c8943SIra Snyder snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) 192776c8943SIra Snyder ? FSL_DMA_SNEN : 0; 193776c8943SIra Snyder 194173acc7cSZhang Wei desc->hw.next_ln_addr = CPU_TO_DMA(fsl_chan, 195776c8943SIra Snyder DMA_TO_CPU(fsl_chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL 196776c8943SIra Snyder | snoop_bits, 64); 197173acc7cSZhang Wei } 198173acc7cSZhang Wei 199173acc7cSZhang Wei static void append_ld_queue(struct fsl_dma_chan *fsl_chan, 200173acc7cSZhang Wei struct fsl_desc_sw *new_desc) 201173acc7cSZhang Wei { 202173acc7cSZhang Wei struct fsl_desc_sw *queue_tail = to_fsl_desc(fsl_chan->ld_queue.prev); 203173acc7cSZhang Wei 204173acc7cSZhang Wei if (list_empty(&fsl_chan->ld_queue)) 205173acc7cSZhang Wei return; 206173acc7cSZhang Wei 207173acc7cSZhang Wei /* Link to the new descriptor physical address and 208173acc7cSZhang Wei * Enable End-of-segment interrupt for 209173acc7cSZhang Wei * the last link descriptor. 210173acc7cSZhang Wei * (the previous node's next link descriptor) 211173acc7cSZhang Wei * 212173acc7cSZhang Wei * For FSL_DMA_IP_83xx, the snoop enable bit need be set. 213173acc7cSZhang Wei */ 214173acc7cSZhang Wei queue_tail->hw.next_ln_addr = CPU_TO_DMA(fsl_chan, 215173acc7cSZhang Wei new_desc->async_tx.phys | FSL_DMA_EOSIE | 216173acc7cSZhang Wei (((fsl_chan->feature & FSL_DMA_IP_MASK) 217173acc7cSZhang Wei == FSL_DMA_IP_83XX) ? FSL_DMA_SNEN : 0), 64); 218173acc7cSZhang Wei } 219173acc7cSZhang Wei 220173acc7cSZhang Wei /** 221173acc7cSZhang Wei * fsl_chan_set_src_loop_size - Set source address hold transfer size 222173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 223173acc7cSZhang Wei * @size : Address loop size, 0 for disable loop 224173acc7cSZhang Wei * 225173acc7cSZhang Wei * The set source address hold transfer size. The source 226173acc7cSZhang Wei * address hold or loop transfer size is when the DMA transfer 227173acc7cSZhang Wei * data from source address (SA), if the loop size is 4, the DMA will 228173acc7cSZhang Wei * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA, 229173acc7cSZhang Wei * SA + 1 ... and so on. 230173acc7cSZhang Wei */ 231173acc7cSZhang Wei static void fsl_chan_set_src_loop_size(struct fsl_dma_chan *fsl_chan, int size) 232173acc7cSZhang Wei { 233173acc7cSZhang Wei switch (size) { 234173acc7cSZhang Wei case 0: 235173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 236173acc7cSZhang Wei DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) & 237173acc7cSZhang Wei (~FSL_DMA_MR_SAHE), 32); 238173acc7cSZhang Wei break; 239173acc7cSZhang Wei case 1: 240173acc7cSZhang Wei case 2: 241173acc7cSZhang Wei case 4: 242173acc7cSZhang Wei case 8: 243173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 244173acc7cSZhang Wei DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) | 245173acc7cSZhang Wei FSL_DMA_MR_SAHE | (__ilog2(size) << 14), 246173acc7cSZhang Wei 32); 247173acc7cSZhang Wei break; 248173acc7cSZhang Wei } 249173acc7cSZhang Wei } 250173acc7cSZhang Wei 251173acc7cSZhang Wei /** 252173acc7cSZhang Wei * fsl_chan_set_dest_loop_size - Set destination address hold transfer size 253173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 254173acc7cSZhang Wei * @size : Address loop size, 0 for disable loop 255173acc7cSZhang Wei * 256173acc7cSZhang Wei * The set destination address hold transfer size. The destination 257173acc7cSZhang Wei * address hold or loop transfer size is when the DMA transfer 258173acc7cSZhang Wei * data to destination address (TA), if the loop size is 4, the DMA will 259173acc7cSZhang Wei * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA, 260173acc7cSZhang Wei * TA + 1 ... and so on. 261173acc7cSZhang Wei */ 262173acc7cSZhang Wei static void fsl_chan_set_dest_loop_size(struct fsl_dma_chan *fsl_chan, int size) 263173acc7cSZhang Wei { 264173acc7cSZhang Wei switch (size) { 265173acc7cSZhang Wei case 0: 266173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 267173acc7cSZhang Wei DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) & 268173acc7cSZhang Wei (~FSL_DMA_MR_DAHE), 32); 269173acc7cSZhang Wei break; 270173acc7cSZhang Wei case 1: 271173acc7cSZhang Wei case 2: 272173acc7cSZhang Wei case 4: 273173acc7cSZhang Wei case 8: 274173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 275173acc7cSZhang Wei DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) | 276173acc7cSZhang Wei FSL_DMA_MR_DAHE | (__ilog2(size) << 16), 277173acc7cSZhang Wei 32); 278173acc7cSZhang Wei break; 279173acc7cSZhang Wei } 280173acc7cSZhang Wei } 281173acc7cSZhang Wei 282173acc7cSZhang Wei /** 283173acc7cSZhang Wei * fsl_chan_toggle_ext_pause - Toggle channel external pause status 284173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 285173acc7cSZhang Wei * @size : Pause control size, 0 for disable external pause control. 286173acc7cSZhang Wei * The maximum is 1024. 287173acc7cSZhang Wei * 288173acc7cSZhang Wei * The Freescale DMA channel can be controlled by the external 289173acc7cSZhang Wei * signal DREQ#. The pause control size is how many bytes are allowed 290173acc7cSZhang Wei * to transfer before pausing the channel, after which a new assertion 291173acc7cSZhang Wei * of DREQ# resumes channel operation. 292173acc7cSZhang Wei */ 293173acc7cSZhang Wei static void fsl_chan_toggle_ext_pause(struct fsl_dma_chan *fsl_chan, int size) 294173acc7cSZhang Wei { 295173acc7cSZhang Wei if (size > 1024) 296173acc7cSZhang Wei return; 297173acc7cSZhang Wei 298173acc7cSZhang Wei if (size) { 299173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 300173acc7cSZhang Wei DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) 301173acc7cSZhang Wei | ((__ilog2(size) << 24) & 0x0f000000), 302173acc7cSZhang Wei 32); 303173acc7cSZhang Wei fsl_chan->feature |= FSL_DMA_CHAN_PAUSE_EXT; 304173acc7cSZhang Wei } else 305173acc7cSZhang Wei fsl_chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT; 306173acc7cSZhang Wei } 307173acc7cSZhang Wei 308173acc7cSZhang Wei /** 309173acc7cSZhang Wei * fsl_chan_toggle_ext_start - Toggle channel external start status 310173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 311173acc7cSZhang Wei * @enable : 0 is disabled, 1 is enabled. 312173acc7cSZhang Wei * 313173acc7cSZhang Wei * If enable the external start, the channel can be started by an 314173acc7cSZhang Wei * external DMA start pin. So the dma_start() does not start the 315173acc7cSZhang Wei * transfer immediately. The DMA channel will wait for the 316173acc7cSZhang Wei * control pin asserted. 317173acc7cSZhang Wei */ 318173acc7cSZhang Wei static void fsl_chan_toggle_ext_start(struct fsl_dma_chan *fsl_chan, int enable) 319173acc7cSZhang Wei { 320173acc7cSZhang Wei if (enable) 321173acc7cSZhang Wei fsl_chan->feature |= FSL_DMA_CHAN_START_EXT; 322173acc7cSZhang Wei else 323173acc7cSZhang Wei fsl_chan->feature &= ~FSL_DMA_CHAN_START_EXT; 324173acc7cSZhang Wei } 325173acc7cSZhang Wei 326173acc7cSZhang Wei static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx) 327173acc7cSZhang Wei { 328173acc7cSZhang Wei struct fsl_dma_chan *fsl_chan = to_fsl_chan(tx->chan); 329eda34234SDan Williams struct fsl_desc_sw *desc = tx_to_fsl_desc(tx); 330eda34234SDan Williams struct fsl_desc_sw *child; 331173acc7cSZhang Wei unsigned long flags; 332173acc7cSZhang Wei dma_cookie_t cookie; 333173acc7cSZhang Wei 334173acc7cSZhang Wei /* cookie increment and adding to ld_queue must be atomic */ 335173acc7cSZhang Wei spin_lock_irqsave(&fsl_chan->desc_lock, flags); 336173acc7cSZhang Wei 337173acc7cSZhang Wei cookie = fsl_chan->common.cookie; 338eda34234SDan Williams list_for_each_entry(child, &desc->tx_list, node) { 339173acc7cSZhang Wei cookie++; 340173acc7cSZhang Wei if (cookie < 0) 341173acc7cSZhang Wei cookie = 1; 342173acc7cSZhang Wei 343bcfb7465SIra Snyder desc->async_tx.cookie = cookie; 344bcfb7465SIra Snyder } 345bcfb7465SIra Snyder 346bcfb7465SIra Snyder fsl_chan->common.cookie = cookie; 347eda34234SDan Williams append_ld_queue(fsl_chan, desc); 348eda34234SDan Williams list_splice_init(&desc->tx_list, fsl_chan->ld_queue.prev); 349173acc7cSZhang Wei 350173acc7cSZhang Wei spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); 351173acc7cSZhang Wei 352173acc7cSZhang Wei return cookie; 353173acc7cSZhang Wei } 354173acc7cSZhang Wei 355173acc7cSZhang Wei /** 356173acc7cSZhang Wei * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool. 357173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 358173acc7cSZhang Wei * 359173acc7cSZhang Wei * Return - The descriptor allocated. NULL for failed. 360173acc7cSZhang Wei */ 361173acc7cSZhang Wei static struct fsl_desc_sw *fsl_dma_alloc_descriptor( 362173acc7cSZhang Wei struct fsl_dma_chan *fsl_chan) 363173acc7cSZhang Wei { 364173acc7cSZhang Wei dma_addr_t pdesc; 365173acc7cSZhang Wei struct fsl_desc_sw *desc_sw; 366173acc7cSZhang Wei 367173acc7cSZhang Wei desc_sw = dma_pool_alloc(fsl_chan->desc_pool, GFP_ATOMIC, &pdesc); 368173acc7cSZhang Wei if (desc_sw) { 369173acc7cSZhang Wei memset(desc_sw, 0, sizeof(struct fsl_desc_sw)); 370eda34234SDan Williams INIT_LIST_HEAD(&desc_sw->tx_list); 371173acc7cSZhang Wei dma_async_tx_descriptor_init(&desc_sw->async_tx, 372173acc7cSZhang Wei &fsl_chan->common); 373173acc7cSZhang Wei desc_sw->async_tx.tx_submit = fsl_dma_tx_submit; 374173acc7cSZhang Wei desc_sw->async_tx.phys = pdesc; 375173acc7cSZhang Wei } 376173acc7cSZhang Wei 377173acc7cSZhang Wei return desc_sw; 378173acc7cSZhang Wei } 379173acc7cSZhang Wei 380173acc7cSZhang Wei 381173acc7cSZhang Wei /** 382173acc7cSZhang Wei * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel. 383173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 384173acc7cSZhang Wei * 385173acc7cSZhang Wei * This function will create a dma pool for descriptor allocation. 386173acc7cSZhang Wei * 387173acc7cSZhang Wei * Return - The number of descriptors allocated. 388173acc7cSZhang Wei */ 389aa1e6f1aSDan Williams static int fsl_dma_alloc_chan_resources(struct dma_chan *chan) 390173acc7cSZhang Wei { 391173acc7cSZhang Wei struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan); 39277cd62e8STimur Tabi 39377cd62e8STimur Tabi /* Has this channel already been allocated? */ 39477cd62e8STimur Tabi if (fsl_chan->desc_pool) 39577cd62e8STimur Tabi return 1; 396173acc7cSZhang Wei 397173acc7cSZhang Wei /* We need the descriptor to be aligned to 32bytes 398173acc7cSZhang Wei * for meeting FSL DMA specification requirement. 399173acc7cSZhang Wei */ 400173acc7cSZhang Wei fsl_chan->desc_pool = dma_pool_create("fsl_dma_engine_desc_pool", 401173acc7cSZhang Wei fsl_chan->dev, sizeof(struct fsl_desc_sw), 402173acc7cSZhang Wei 32, 0); 403173acc7cSZhang Wei if (!fsl_chan->desc_pool) { 404173acc7cSZhang Wei dev_err(fsl_chan->dev, "No memory for channel %d " 405173acc7cSZhang Wei "descriptor dma pool.\n", fsl_chan->id); 406173acc7cSZhang Wei return 0; 407173acc7cSZhang Wei } 408173acc7cSZhang Wei 409173acc7cSZhang Wei return 1; 410173acc7cSZhang Wei } 411173acc7cSZhang Wei 412173acc7cSZhang Wei /** 413173acc7cSZhang Wei * fsl_dma_free_chan_resources - Free all resources of the channel. 414173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 415173acc7cSZhang Wei */ 416173acc7cSZhang Wei static void fsl_dma_free_chan_resources(struct dma_chan *chan) 417173acc7cSZhang Wei { 418173acc7cSZhang Wei struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan); 419173acc7cSZhang Wei struct fsl_desc_sw *desc, *_desc; 420173acc7cSZhang Wei unsigned long flags; 421173acc7cSZhang Wei 422173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "Free all channel resources.\n"); 423173acc7cSZhang Wei spin_lock_irqsave(&fsl_chan->desc_lock, flags); 424173acc7cSZhang Wei list_for_each_entry_safe(desc, _desc, &fsl_chan->ld_queue, node) { 425173acc7cSZhang Wei #ifdef FSL_DMA_LD_DEBUG 426173acc7cSZhang Wei dev_dbg(fsl_chan->dev, 427173acc7cSZhang Wei "LD %p will be released.\n", desc); 428173acc7cSZhang Wei #endif 429173acc7cSZhang Wei list_del(&desc->node); 430173acc7cSZhang Wei /* free link descriptor */ 431173acc7cSZhang Wei dma_pool_free(fsl_chan->desc_pool, desc, desc->async_tx.phys); 432173acc7cSZhang Wei } 433173acc7cSZhang Wei spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); 434173acc7cSZhang Wei dma_pool_destroy(fsl_chan->desc_pool); 43577cd62e8STimur Tabi 43677cd62e8STimur Tabi fsl_chan->desc_pool = NULL; 437173acc7cSZhang Wei } 438173acc7cSZhang Wei 4392187c269SZhang Wei static struct dma_async_tx_descriptor * 440636bdeaaSDan Williams fsl_dma_prep_interrupt(struct dma_chan *chan, unsigned long flags) 4412187c269SZhang Wei { 4422187c269SZhang Wei struct fsl_dma_chan *fsl_chan; 4432187c269SZhang Wei struct fsl_desc_sw *new; 4442187c269SZhang Wei 4452187c269SZhang Wei if (!chan) 4462187c269SZhang Wei return NULL; 4472187c269SZhang Wei 4482187c269SZhang Wei fsl_chan = to_fsl_chan(chan); 4492187c269SZhang Wei 4502187c269SZhang Wei new = fsl_dma_alloc_descriptor(fsl_chan); 4512187c269SZhang Wei if (!new) { 4522187c269SZhang Wei dev_err(fsl_chan->dev, "No free memory for link descriptor\n"); 4532187c269SZhang Wei return NULL; 4542187c269SZhang Wei } 4552187c269SZhang Wei 4562187c269SZhang Wei new->async_tx.cookie = -EBUSY; 457636bdeaaSDan Williams new->async_tx.flags = flags; 4582187c269SZhang Wei 459f79abb62SZhang Wei /* Insert the link descriptor to the LD ring */ 460eda34234SDan Williams list_add_tail(&new->node, &new->tx_list); 461f79abb62SZhang Wei 4622187c269SZhang Wei /* Set End-of-link to the last link descriptor of new list*/ 4632187c269SZhang Wei set_ld_eol(fsl_chan, new); 4642187c269SZhang Wei 4652187c269SZhang Wei return &new->async_tx; 4662187c269SZhang Wei } 4672187c269SZhang Wei 468173acc7cSZhang Wei static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy( 469173acc7cSZhang Wei struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src, 470173acc7cSZhang Wei size_t len, unsigned long flags) 471173acc7cSZhang Wei { 472173acc7cSZhang Wei struct fsl_dma_chan *fsl_chan; 473173acc7cSZhang Wei struct fsl_desc_sw *first = NULL, *prev = NULL, *new; 4742e077f8eSIra Snyder struct list_head *list; 475173acc7cSZhang Wei size_t copy; 476173acc7cSZhang Wei 477173acc7cSZhang Wei if (!chan) 478173acc7cSZhang Wei return NULL; 479173acc7cSZhang Wei 480173acc7cSZhang Wei if (!len) 481173acc7cSZhang Wei return NULL; 482173acc7cSZhang Wei 483173acc7cSZhang Wei fsl_chan = to_fsl_chan(chan); 484173acc7cSZhang Wei 485173acc7cSZhang Wei do { 486173acc7cSZhang Wei 487173acc7cSZhang Wei /* Allocate the link descriptor from DMA pool */ 488173acc7cSZhang Wei new = fsl_dma_alloc_descriptor(fsl_chan); 489173acc7cSZhang Wei if (!new) { 490173acc7cSZhang Wei dev_err(fsl_chan->dev, 491173acc7cSZhang Wei "No free memory for link descriptor\n"); 4922e077f8eSIra Snyder goto fail; 493173acc7cSZhang Wei } 494173acc7cSZhang Wei #ifdef FSL_DMA_LD_DEBUG 495173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "new link desc alloc %p\n", new); 496173acc7cSZhang Wei #endif 497173acc7cSZhang Wei 49856822843SZhang Wei copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT); 499173acc7cSZhang Wei 500173acc7cSZhang Wei set_desc_cnt(fsl_chan, &new->hw, copy); 501173acc7cSZhang Wei set_desc_src(fsl_chan, &new->hw, dma_src); 502173acc7cSZhang Wei set_desc_dest(fsl_chan, &new->hw, dma_dest); 503173acc7cSZhang Wei 504173acc7cSZhang Wei if (!first) 505173acc7cSZhang Wei first = new; 506173acc7cSZhang Wei else 507173acc7cSZhang Wei set_desc_next(fsl_chan, &prev->hw, new->async_tx.phys); 508173acc7cSZhang Wei 509173acc7cSZhang Wei new->async_tx.cookie = 0; 510636bdeaaSDan Williams async_tx_ack(&new->async_tx); 511173acc7cSZhang Wei 512173acc7cSZhang Wei prev = new; 513173acc7cSZhang Wei len -= copy; 514173acc7cSZhang Wei dma_src += copy; 515173acc7cSZhang Wei dma_dest += copy; 516173acc7cSZhang Wei 517173acc7cSZhang Wei /* Insert the link descriptor to the LD ring */ 518eda34234SDan Williams list_add_tail(&new->node, &first->tx_list); 519173acc7cSZhang Wei } while (len); 520173acc7cSZhang Wei 521636bdeaaSDan Williams new->async_tx.flags = flags; /* client is in control of this ack */ 522173acc7cSZhang Wei new->async_tx.cookie = -EBUSY; 523173acc7cSZhang Wei 524173acc7cSZhang Wei /* Set End-of-link to the last link descriptor of new list*/ 525173acc7cSZhang Wei set_ld_eol(fsl_chan, new); 526173acc7cSZhang Wei 5272e077f8eSIra Snyder return &first->async_tx; 5282e077f8eSIra Snyder 5292e077f8eSIra Snyder fail: 5302e077f8eSIra Snyder if (!first) 5312e077f8eSIra Snyder return NULL; 5322e077f8eSIra Snyder 533eda34234SDan Williams list = &first->tx_list; 5342e077f8eSIra Snyder list_for_each_entry_safe_reverse(new, prev, list, node) { 5352e077f8eSIra Snyder list_del(&new->node); 5362e077f8eSIra Snyder dma_pool_free(fsl_chan->desc_pool, new, new->async_tx.phys); 5372e077f8eSIra Snyder } 5382e077f8eSIra Snyder 5392e077f8eSIra Snyder return NULL; 540173acc7cSZhang Wei } 541173acc7cSZhang Wei 542173acc7cSZhang Wei /** 543173acc7cSZhang Wei * fsl_dma_update_completed_cookie - Update the completed cookie. 544173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 545173acc7cSZhang Wei */ 546173acc7cSZhang Wei static void fsl_dma_update_completed_cookie(struct fsl_dma_chan *fsl_chan) 547173acc7cSZhang Wei { 548173acc7cSZhang Wei struct fsl_desc_sw *cur_desc, *desc; 549173acc7cSZhang Wei dma_addr_t ld_phy; 550173acc7cSZhang Wei 551173acc7cSZhang Wei ld_phy = get_cdar(fsl_chan) & FSL_DMA_NLDA_MASK; 552173acc7cSZhang Wei 553173acc7cSZhang Wei if (ld_phy) { 554173acc7cSZhang Wei cur_desc = NULL; 555173acc7cSZhang Wei list_for_each_entry(desc, &fsl_chan->ld_queue, node) 556173acc7cSZhang Wei if (desc->async_tx.phys == ld_phy) { 557173acc7cSZhang Wei cur_desc = desc; 558173acc7cSZhang Wei break; 559173acc7cSZhang Wei } 560173acc7cSZhang Wei 561173acc7cSZhang Wei if (cur_desc && cur_desc->async_tx.cookie) { 562173acc7cSZhang Wei if (dma_is_idle(fsl_chan)) 563173acc7cSZhang Wei fsl_chan->completed_cookie = 564173acc7cSZhang Wei cur_desc->async_tx.cookie; 565173acc7cSZhang Wei else 566173acc7cSZhang Wei fsl_chan->completed_cookie = 567173acc7cSZhang Wei cur_desc->async_tx.cookie - 1; 568173acc7cSZhang Wei } 569173acc7cSZhang Wei } 570173acc7cSZhang Wei } 571173acc7cSZhang Wei 572173acc7cSZhang Wei /** 573173acc7cSZhang Wei * fsl_chan_ld_cleanup - Clean up link descriptors 574173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 575173acc7cSZhang Wei * 576173acc7cSZhang Wei * This function clean up the ld_queue of DMA channel. 577173acc7cSZhang Wei * If 'in_intr' is set, the function will move the link descriptor to 578173acc7cSZhang Wei * the recycle list. Otherwise, free it directly. 579173acc7cSZhang Wei */ 580173acc7cSZhang Wei static void fsl_chan_ld_cleanup(struct fsl_dma_chan *fsl_chan) 581173acc7cSZhang Wei { 582173acc7cSZhang Wei struct fsl_desc_sw *desc, *_desc; 583173acc7cSZhang Wei unsigned long flags; 584173acc7cSZhang Wei 585173acc7cSZhang Wei spin_lock_irqsave(&fsl_chan->desc_lock, flags); 586173acc7cSZhang Wei 587173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "chan completed_cookie = %d\n", 588173acc7cSZhang Wei fsl_chan->completed_cookie); 589173acc7cSZhang Wei list_for_each_entry_safe(desc, _desc, &fsl_chan->ld_queue, node) { 590173acc7cSZhang Wei dma_async_tx_callback callback; 591173acc7cSZhang Wei void *callback_param; 592173acc7cSZhang Wei 593173acc7cSZhang Wei if (dma_async_is_complete(desc->async_tx.cookie, 594173acc7cSZhang Wei fsl_chan->completed_cookie, fsl_chan->common.cookie) 595173acc7cSZhang Wei == DMA_IN_PROGRESS) 596173acc7cSZhang Wei break; 597173acc7cSZhang Wei 598173acc7cSZhang Wei callback = desc->async_tx.callback; 599173acc7cSZhang Wei callback_param = desc->async_tx.callback_param; 600173acc7cSZhang Wei 601173acc7cSZhang Wei /* Remove from ld_queue list */ 602173acc7cSZhang Wei list_del(&desc->node); 603173acc7cSZhang Wei 604173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "link descriptor %p will be recycle.\n", 605173acc7cSZhang Wei desc); 606173acc7cSZhang Wei dma_pool_free(fsl_chan->desc_pool, desc, desc->async_tx.phys); 607173acc7cSZhang Wei 608173acc7cSZhang Wei /* Run the link descriptor callback function */ 609173acc7cSZhang Wei if (callback) { 610173acc7cSZhang Wei spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); 611173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "link descriptor %p callback\n", 612173acc7cSZhang Wei desc); 613173acc7cSZhang Wei callback(callback_param); 614173acc7cSZhang Wei spin_lock_irqsave(&fsl_chan->desc_lock, flags); 615173acc7cSZhang Wei } 616173acc7cSZhang Wei } 617173acc7cSZhang Wei spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); 618173acc7cSZhang Wei } 619173acc7cSZhang Wei 620173acc7cSZhang Wei /** 621173acc7cSZhang Wei * fsl_chan_xfer_ld_queue - Transfer link descriptors in channel ld_queue. 622173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 623173acc7cSZhang Wei */ 624173acc7cSZhang Wei static void fsl_chan_xfer_ld_queue(struct fsl_dma_chan *fsl_chan) 625173acc7cSZhang Wei { 626173acc7cSZhang Wei struct list_head *ld_node; 627173acc7cSZhang Wei dma_addr_t next_dest_addr; 628173acc7cSZhang Wei unsigned long flags; 629173acc7cSZhang Wei 630138ef018SIra Snyder spin_lock_irqsave(&fsl_chan->desc_lock, flags); 631138ef018SIra Snyder 632173acc7cSZhang Wei if (!dma_is_idle(fsl_chan)) 633138ef018SIra Snyder goto out_unlock; 634173acc7cSZhang Wei 635173acc7cSZhang Wei dma_halt(fsl_chan); 636173acc7cSZhang Wei 637173acc7cSZhang Wei /* If there are some link descriptors 638173acc7cSZhang Wei * not transfered in queue. We need to start it. 639173acc7cSZhang Wei */ 640173acc7cSZhang Wei 641173acc7cSZhang Wei /* Find the first un-transfer desciptor */ 642173acc7cSZhang Wei for (ld_node = fsl_chan->ld_queue.next; 643173acc7cSZhang Wei (ld_node != &fsl_chan->ld_queue) 644173acc7cSZhang Wei && (dma_async_is_complete( 645173acc7cSZhang Wei to_fsl_desc(ld_node)->async_tx.cookie, 646173acc7cSZhang Wei fsl_chan->completed_cookie, 647173acc7cSZhang Wei fsl_chan->common.cookie) == DMA_SUCCESS); 648173acc7cSZhang Wei ld_node = ld_node->next); 649173acc7cSZhang Wei 650173acc7cSZhang Wei if (ld_node != &fsl_chan->ld_queue) { 651173acc7cSZhang Wei /* Get the ld start address from ld_queue */ 652173acc7cSZhang Wei next_dest_addr = to_fsl_desc(ld_node)->async_tx.phys; 653b787f2e2SKumar Gala dev_dbg(fsl_chan->dev, "xfer LDs staring from 0x%llx\n", 654b787f2e2SKumar Gala (unsigned long long)next_dest_addr); 655173acc7cSZhang Wei set_cdar(fsl_chan, next_dest_addr); 656173acc7cSZhang Wei dma_start(fsl_chan); 657173acc7cSZhang Wei } else { 658173acc7cSZhang Wei set_cdar(fsl_chan, 0); 659173acc7cSZhang Wei set_ndar(fsl_chan, 0); 660173acc7cSZhang Wei } 661138ef018SIra Snyder 662138ef018SIra Snyder out_unlock: 663138ef018SIra Snyder spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); 664173acc7cSZhang Wei } 665173acc7cSZhang Wei 666173acc7cSZhang Wei /** 667173acc7cSZhang Wei * fsl_dma_memcpy_issue_pending - Issue the DMA start command 668173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 669173acc7cSZhang Wei */ 670173acc7cSZhang Wei static void fsl_dma_memcpy_issue_pending(struct dma_chan *chan) 671173acc7cSZhang Wei { 672173acc7cSZhang Wei struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan); 673173acc7cSZhang Wei 674173acc7cSZhang Wei #ifdef FSL_DMA_LD_DEBUG 675173acc7cSZhang Wei struct fsl_desc_sw *ld; 676173acc7cSZhang Wei unsigned long flags; 677173acc7cSZhang Wei 678173acc7cSZhang Wei spin_lock_irqsave(&fsl_chan->desc_lock, flags); 679173acc7cSZhang Wei if (list_empty(&fsl_chan->ld_queue)) { 680173acc7cSZhang Wei spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); 681173acc7cSZhang Wei return; 682173acc7cSZhang Wei } 683173acc7cSZhang Wei 684173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "--memcpy issue--\n"); 685173acc7cSZhang Wei list_for_each_entry(ld, &fsl_chan->ld_queue, node) { 686173acc7cSZhang Wei int i; 687173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "Ch %d, LD %08x\n", 688173acc7cSZhang Wei fsl_chan->id, ld->async_tx.phys); 689173acc7cSZhang Wei for (i = 0; i < 8; i++) 690173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "LD offset %d: %08x\n", 691173acc7cSZhang Wei i, *(((u32 *)&ld->hw) + i)); 692173acc7cSZhang Wei } 693173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "----------------\n"); 694173acc7cSZhang Wei spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); 695173acc7cSZhang Wei #endif 696173acc7cSZhang Wei 697173acc7cSZhang Wei fsl_chan_xfer_ld_queue(fsl_chan); 698173acc7cSZhang Wei } 699173acc7cSZhang Wei 700173acc7cSZhang Wei /** 701173acc7cSZhang Wei * fsl_dma_is_complete - Determine the DMA status 702173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 703173acc7cSZhang Wei */ 704173acc7cSZhang Wei static enum dma_status fsl_dma_is_complete(struct dma_chan *chan, 705173acc7cSZhang Wei dma_cookie_t cookie, 706173acc7cSZhang Wei dma_cookie_t *done, 707173acc7cSZhang Wei dma_cookie_t *used) 708173acc7cSZhang Wei { 709173acc7cSZhang Wei struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan); 710173acc7cSZhang Wei dma_cookie_t last_used; 711173acc7cSZhang Wei dma_cookie_t last_complete; 712173acc7cSZhang Wei 713173acc7cSZhang Wei fsl_chan_ld_cleanup(fsl_chan); 714173acc7cSZhang Wei 715173acc7cSZhang Wei last_used = chan->cookie; 716173acc7cSZhang Wei last_complete = fsl_chan->completed_cookie; 717173acc7cSZhang Wei 718173acc7cSZhang Wei if (done) 719173acc7cSZhang Wei *done = last_complete; 720173acc7cSZhang Wei 721173acc7cSZhang Wei if (used) 722173acc7cSZhang Wei *used = last_used; 723173acc7cSZhang Wei 724173acc7cSZhang Wei return dma_async_is_complete(cookie, last_complete, last_used); 725173acc7cSZhang Wei } 726173acc7cSZhang Wei 727173acc7cSZhang Wei static irqreturn_t fsl_dma_chan_do_interrupt(int irq, void *data) 728173acc7cSZhang Wei { 729173acc7cSZhang Wei struct fsl_dma_chan *fsl_chan = (struct fsl_dma_chan *)data; 73056822843SZhang Wei u32 stat; 7311c62979eSZhang Wei int update_cookie = 0; 7321c62979eSZhang Wei int xfer_ld_q = 0; 733173acc7cSZhang Wei 734173acc7cSZhang Wei stat = get_sr(fsl_chan); 735173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "event: channel %d, stat = 0x%x\n", 736173acc7cSZhang Wei fsl_chan->id, stat); 737173acc7cSZhang Wei set_sr(fsl_chan, stat); /* Clear the event register */ 738173acc7cSZhang Wei 739173acc7cSZhang Wei stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH); 740173acc7cSZhang Wei if (!stat) 741173acc7cSZhang Wei return IRQ_NONE; 742173acc7cSZhang Wei 743173acc7cSZhang Wei if (stat & FSL_DMA_SR_TE) 744173acc7cSZhang Wei dev_err(fsl_chan->dev, "Transfer Error!\n"); 745173acc7cSZhang Wei 746f79abb62SZhang Wei /* Programming Error 747f79abb62SZhang Wei * The DMA_INTERRUPT async_tx is a NULL transfer, which will 748f79abb62SZhang Wei * triger a PE interrupt. 749f79abb62SZhang Wei */ 750f79abb62SZhang Wei if (stat & FSL_DMA_SR_PE) { 751f79abb62SZhang Wei dev_dbg(fsl_chan->dev, "event: Programming Error INT\n"); 752f79abb62SZhang Wei if (get_bcr(fsl_chan) == 0) { 753f79abb62SZhang Wei /* BCR register is 0, this is a DMA_INTERRUPT async_tx. 754f79abb62SZhang Wei * Now, update the completed cookie, and continue the 755f79abb62SZhang Wei * next uncompleted transfer. 756f79abb62SZhang Wei */ 7571c62979eSZhang Wei update_cookie = 1; 7581c62979eSZhang Wei xfer_ld_q = 1; 759f79abb62SZhang Wei } 760f79abb62SZhang Wei stat &= ~FSL_DMA_SR_PE; 761f79abb62SZhang Wei } 762f79abb62SZhang Wei 763173acc7cSZhang Wei /* If the link descriptor segment transfer finishes, 764173acc7cSZhang Wei * we will recycle the used descriptor. 765173acc7cSZhang Wei */ 766173acc7cSZhang Wei if (stat & FSL_DMA_SR_EOSI) { 767173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "event: End-of-segments INT\n"); 768b787f2e2SKumar Gala dev_dbg(fsl_chan->dev, "event: clndar 0x%llx, nlndar 0x%llx\n", 769b787f2e2SKumar Gala (unsigned long long)get_cdar(fsl_chan), 770b787f2e2SKumar Gala (unsigned long long)get_ndar(fsl_chan)); 771173acc7cSZhang Wei stat &= ~FSL_DMA_SR_EOSI; 7721c62979eSZhang Wei update_cookie = 1; 7731c62979eSZhang Wei } 7741c62979eSZhang Wei 7751c62979eSZhang Wei /* For MPC8349, EOCDI event need to update cookie 7761c62979eSZhang Wei * and start the next transfer if it exist. 7771c62979eSZhang Wei */ 7781c62979eSZhang Wei if (stat & FSL_DMA_SR_EOCDI) { 7791c62979eSZhang Wei dev_dbg(fsl_chan->dev, "event: End-of-Chain link INT\n"); 7801c62979eSZhang Wei stat &= ~FSL_DMA_SR_EOCDI; 7811c62979eSZhang Wei update_cookie = 1; 7821c62979eSZhang Wei xfer_ld_q = 1; 783173acc7cSZhang Wei } 784173acc7cSZhang Wei 785173acc7cSZhang Wei /* If it current transfer is the end-of-transfer, 786173acc7cSZhang Wei * we should clear the Channel Start bit for 787173acc7cSZhang Wei * prepare next transfer. 788173acc7cSZhang Wei */ 7891c62979eSZhang Wei if (stat & FSL_DMA_SR_EOLNI) { 790173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "event: End-of-link INT\n"); 791173acc7cSZhang Wei stat &= ~FSL_DMA_SR_EOLNI; 7921c62979eSZhang Wei xfer_ld_q = 1; 793173acc7cSZhang Wei } 794173acc7cSZhang Wei 7951c62979eSZhang Wei if (update_cookie) 7961c62979eSZhang Wei fsl_dma_update_completed_cookie(fsl_chan); 7971c62979eSZhang Wei if (xfer_ld_q) 7981c62979eSZhang Wei fsl_chan_xfer_ld_queue(fsl_chan); 799173acc7cSZhang Wei if (stat) 800173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "event: unhandled sr 0x%02x\n", 801173acc7cSZhang Wei stat); 802173acc7cSZhang Wei 803173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "event: Exit\n"); 804173acc7cSZhang Wei tasklet_schedule(&fsl_chan->tasklet); 805173acc7cSZhang Wei return IRQ_HANDLED; 806173acc7cSZhang Wei } 807173acc7cSZhang Wei 808173acc7cSZhang Wei static irqreturn_t fsl_dma_do_interrupt(int irq, void *data) 809173acc7cSZhang Wei { 810173acc7cSZhang Wei struct fsl_dma_device *fdev = (struct fsl_dma_device *)data; 811173acc7cSZhang Wei u32 gsr; 812173acc7cSZhang Wei int ch_nr; 813173acc7cSZhang Wei 814173acc7cSZhang Wei gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->reg_base) 815173acc7cSZhang Wei : in_le32(fdev->reg_base); 816173acc7cSZhang Wei ch_nr = (32 - ffs(gsr)) / 8; 817173acc7cSZhang Wei 818173acc7cSZhang Wei return fdev->chan[ch_nr] ? fsl_dma_chan_do_interrupt(irq, 819173acc7cSZhang Wei fdev->chan[ch_nr]) : IRQ_NONE; 820173acc7cSZhang Wei } 821173acc7cSZhang Wei 822173acc7cSZhang Wei static void dma_do_tasklet(unsigned long data) 823173acc7cSZhang Wei { 824173acc7cSZhang Wei struct fsl_dma_chan *fsl_chan = (struct fsl_dma_chan *)data; 825173acc7cSZhang Wei fsl_chan_ld_cleanup(fsl_chan); 826173acc7cSZhang Wei } 827173acc7cSZhang Wei 82877cd62e8STimur Tabi static int __devinit fsl_dma_chan_probe(struct fsl_dma_device *fdev, 82977cd62e8STimur Tabi struct device_node *node, u32 feature, const char *compatible) 830173acc7cSZhang Wei { 831173acc7cSZhang Wei struct fsl_dma_chan *new_fsl_chan; 832173acc7cSZhang Wei int err; 833173acc7cSZhang Wei 834173acc7cSZhang Wei /* alloc channel */ 835173acc7cSZhang Wei new_fsl_chan = kzalloc(sizeof(struct fsl_dma_chan), GFP_KERNEL); 836173acc7cSZhang Wei if (!new_fsl_chan) { 83777cd62e8STimur Tabi dev_err(fdev->dev, "No free memory for allocating " 838173acc7cSZhang Wei "dma channels!\n"); 83951ee87f2SLi Yang return -ENOMEM; 840173acc7cSZhang Wei } 841173acc7cSZhang Wei 842173acc7cSZhang Wei /* get dma channel register base */ 84377cd62e8STimur Tabi err = of_address_to_resource(node, 0, &new_fsl_chan->reg); 844173acc7cSZhang Wei if (err) { 84577cd62e8STimur Tabi dev_err(fdev->dev, "Can't get %s property 'reg'\n", 84677cd62e8STimur Tabi node->full_name); 84751ee87f2SLi Yang goto err_no_reg; 848173acc7cSZhang Wei } 849173acc7cSZhang Wei 85077cd62e8STimur Tabi new_fsl_chan->feature = feature; 851173acc7cSZhang Wei 852173acc7cSZhang Wei if (!fdev->feature) 853173acc7cSZhang Wei fdev->feature = new_fsl_chan->feature; 854173acc7cSZhang Wei 855173acc7cSZhang Wei /* If the DMA device's feature is different than its channels', 856173acc7cSZhang Wei * report the bug. 857173acc7cSZhang Wei */ 858173acc7cSZhang Wei WARN_ON(fdev->feature != new_fsl_chan->feature); 859173acc7cSZhang Wei 8606527de6dSDan Williams new_fsl_chan->dev = fdev->dev; 861173acc7cSZhang Wei new_fsl_chan->reg_base = ioremap(new_fsl_chan->reg.start, 862173acc7cSZhang Wei new_fsl_chan->reg.end - new_fsl_chan->reg.start + 1); 863173acc7cSZhang Wei 864173acc7cSZhang Wei new_fsl_chan->id = ((new_fsl_chan->reg.start - 0x100) & 0xfff) >> 7; 865f47edc6dSRoel Kluin if (new_fsl_chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) { 86677cd62e8STimur Tabi dev_err(fdev->dev, "There is no %d channel!\n", 867173acc7cSZhang Wei new_fsl_chan->id); 868173acc7cSZhang Wei err = -EINVAL; 86951ee87f2SLi Yang goto err_no_chan; 870173acc7cSZhang Wei } 871173acc7cSZhang Wei fdev->chan[new_fsl_chan->id] = new_fsl_chan; 872173acc7cSZhang Wei tasklet_init(&new_fsl_chan->tasklet, dma_do_tasklet, 873173acc7cSZhang Wei (unsigned long)new_fsl_chan); 874173acc7cSZhang Wei 875173acc7cSZhang Wei /* Init the channel */ 876173acc7cSZhang Wei dma_init(new_fsl_chan); 877173acc7cSZhang Wei 878173acc7cSZhang Wei /* Clear cdar registers */ 879173acc7cSZhang Wei set_cdar(new_fsl_chan, 0); 880173acc7cSZhang Wei 881173acc7cSZhang Wei switch (new_fsl_chan->feature & FSL_DMA_IP_MASK) { 882173acc7cSZhang Wei case FSL_DMA_IP_85XX: 883173acc7cSZhang Wei new_fsl_chan->toggle_ext_pause = fsl_chan_toggle_ext_pause; 884173acc7cSZhang Wei case FSL_DMA_IP_83XX: 885be30b226SIra Snyder new_fsl_chan->toggle_ext_start = fsl_chan_toggle_ext_start; 886173acc7cSZhang Wei new_fsl_chan->set_src_loop_size = fsl_chan_set_src_loop_size; 887173acc7cSZhang Wei new_fsl_chan->set_dest_loop_size = fsl_chan_set_dest_loop_size; 888173acc7cSZhang Wei } 889173acc7cSZhang Wei 890173acc7cSZhang Wei spin_lock_init(&new_fsl_chan->desc_lock); 891173acc7cSZhang Wei INIT_LIST_HEAD(&new_fsl_chan->ld_queue); 892173acc7cSZhang Wei 893173acc7cSZhang Wei new_fsl_chan->common.device = &fdev->common; 894173acc7cSZhang Wei 895173acc7cSZhang Wei /* Add the channel to DMA device channel list */ 896173acc7cSZhang Wei list_add_tail(&new_fsl_chan->common.device_node, 897173acc7cSZhang Wei &fdev->common.channels); 898173acc7cSZhang Wei fdev->common.chancnt++; 899173acc7cSZhang Wei 90077cd62e8STimur Tabi new_fsl_chan->irq = irq_of_parse_and_map(node, 0); 901173acc7cSZhang Wei if (new_fsl_chan->irq != NO_IRQ) { 902173acc7cSZhang Wei err = request_irq(new_fsl_chan->irq, 903173acc7cSZhang Wei &fsl_dma_chan_do_interrupt, IRQF_SHARED, 904173acc7cSZhang Wei "fsldma-channel", new_fsl_chan); 905173acc7cSZhang Wei if (err) { 90677cd62e8STimur Tabi dev_err(fdev->dev, "DMA channel %s request_irq error " 90777cd62e8STimur Tabi "with return %d\n", node->full_name, err); 90851ee87f2SLi Yang goto err_no_irq; 909173acc7cSZhang Wei } 910173acc7cSZhang Wei } 911173acc7cSZhang Wei 91277cd62e8STimur Tabi dev_info(fdev->dev, "#%d (%s), irq %d\n", new_fsl_chan->id, 913169d5f66SPeter Korsgaard compatible, 914169d5f66SPeter Korsgaard new_fsl_chan->irq != NO_IRQ ? new_fsl_chan->irq : fdev->irq); 915173acc7cSZhang Wei 916173acc7cSZhang Wei return 0; 91751ee87f2SLi Yang 91851ee87f2SLi Yang err_no_irq: 919173acc7cSZhang Wei list_del(&new_fsl_chan->common.device_node); 92051ee87f2SLi Yang err_no_chan: 92151ee87f2SLi Yang iounmap(new_fsl_chan->reg_base); 92251ee87f2SLi Yang err_no_reg: 923173acc7cSZhang Wei kfree(new_fsl_chan); 924173acc7cSZhang Wei return err; 925173acc7cSZhang Wei } 926173acc7cSZhang Wei 92777cd62e8STimur Tabi static void fsl_dma_chan_remove(struct fsl_dma_chan *fchan) 928173acc7cSZhang Wei { 9296782dfe4SPeter Korsgaard if (fchan->irq != NO_IRQ) 93077cd62e8STimur Tabi free_irq(fchan->irq, fchan); 93177cd62e8STimur Tabi list_del(&fchan->common.device_node); 93277cd62e8STimur Tabi iounmap(fchan->reg_base); 93377cd62e8STimur Tabi kfree(fchan); 934173acc7cSZhang Wei } 935173acc7cSZhang Wei 936173acc7cSZhang Wei static int __devinit of_fsl_dma_probe(struct of_device *dev, 937173acc7cSZhang Wei const struct of_device_id *match) 938173acc7cSZhang Wei { 939173acc7cSZhang Wei int err; 940173acc7cSZhang Wei struct fsl_dma_device *fdev; 94177cd62e8STimur Tabi struct device_node *child; 942173acc7cSZhang Wei 943173acc7cSZhang Wei fdev = kzalloc(sizeof(struct fsl_dma_device), GFP_KERNEL); 944173acc7cSZhang Wei if (!fdev) { 945173acc7cSZhang Wei dev_err(&dev->dev, "No enough memory for 'priv'\n"); 94651ee87f2SLi Yang return -ENOMEM; 947173acc7cSZhang Wei } 948173acc7cSZhang Wei fdev->dev = &dev->dev; 949173acc7cSZhang Wei INIT_LIST_HEAD(&fdev->common.channels); 950173acc7cSZhang Wei 951173acc7cSZhang Wei /* get DMA controller register base */ 952173acc7cSZhang Wei err = of_address_to_resource(dev->node, 0, &fdev->reg); 953173acc7cSZhang Wei if (err) { 954173acc7cSZhang Wei dev_err(&dev->dev, "Can't get %s property 'reg'\n", 955173acc7cSZhang Wei dev->node->full_name); 95651ee87f2SLi Yang goto err_no_reg; 957173acc7cSZhang Wei } 958173acc7cSZhang Wei 959173acc7cSZhang Wei dev_info(&dev->dev, "Probe the Freescale DMA driver for %s " 960b787f2e2SKumar Gala "controller at 0x%llx...\n", 961b787f2e2SKumar Gala match->compatible, (unsigned long long)fdev->reg.start); 962173acc7cSZhang Wei fdev->reg_base = ioremap(fdev->reg.start, fdev->reg.end 963173acc7cSZhang Wei - fdev->reg.start + 1); 964173acc7cSZhang Wei 965173acc7cSZhang Wei dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask); 966173acc7cSZhang Wei dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask); 967173acc7cSZhang Wei fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources; 968173acc7cSZhang Wei fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources; 9692187c269SZhang Wei fdev->common.device_prep_dma_interrupt = fsl_dma_prep_interrupt; 970173acc7cSZhang Wei fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy; 971173acc7cSZhang Wei fdev->common.device_is_tx_complete = fsl_dma_is_complete; 972173acc7cSZhang Wei fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending; 973173acc7cSZhang Wei fdev->common.dev = &dev->dev; 974173acc7cSZhang Wei 97577cd62e8STimur Tabi fdev->irq = irq_of_parse_and_map(dev->node, 0); 97677cd62e8STimur Tabi if (fdev->irq != NO_IRQ) { 97777cd62e8STimur Tabi err = request_irq(fdev->irq, &fsl_dma_do_interrupt, IRQF_SHARED, 978173acc7cSZhang Wei "fsldma-device", fdev); 979173acc7cSZhang Wei if (err) { 980173acc7cSZhang Wei dev_err(&dev->dev, "DMA device request_irq error " 981173acc7cSZhang Wei "with return %d\n", err); 982173acc7cSZhang Wei goto err; 983173acc7cSZhang Wei } 984173acc7cSZhang Wei } 985173acc7cSZhang Wei 986173acc7cSZhang Wei dev_set_drvdata(&(dev->dev), fdev); 98777cd62e8STimur Tabi 98877cd62e8STimur Tabi /* We cannot use of_platform_bus_probe() because there is no 98977cd62e8STimur Tabi * of_platform_bus_remove. Instead, we manually instantiate every DMA 99077cd62e8STimur Tabi * channel object. 99177cd62e8STimur Tabi */ 99277cd62e8STimur Tabi for_each_child_of_node(dev->node, child) { 99377cd62e8STimur Tabi if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) 99477cd62e8STimur Tabi fsl_dma_chan_probe(fdev, child, 99577cd62e8STimur Tabi FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN, 99677cd62e8STimur Tabi "fsl,eloplus-dma-channel"); 99777cd62e8STimur Tabi if (of_device_is_compatible(child, "fsl,elo-dma-channel")) 99877cd62e8STimur Tabi fsl_dma_chan_probe(fdev, child, 99977cd62e8STimur Tabi FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN, 100077cd62e8STimur Tabi "fsl,elo-dma-channel"); 100177cd62e8STimur Tabi } 1002173acc7cSZhang Wei 1003173acc7cSZhang Wei dma_async_device_register(&fdev->common); 1004173acc7cSZhang Wei return 0; 1005173acc7cSZhang Wei 1006173acc7cSZhang Wei err: 1007173acc7cSZhang Wei iounmap(fdev->reg_base); 100851ee87f2SLi Yang err_no_reg: 1009173acc7cSZhang Wei kfree(fdev); 1010173acc7cSZhang Wei return err; 1011173acc7cSZhang Wei } 1012173acc7cSZhang Wei 101377cd62e8STimur Tabi static int of_fsl_dma_remove(struct of_device *of_dev) 101477cd62e8STimur Tabi { 101577cd62e8STimur Tabi struct fsl_dma_device *fdev; 101677cd62e8STimur Tabi unsigned int i; 101777cd62e8STimur Tabi 101877cd62e8STimur Tabi fdev = dev_get_drvdata(&of_dev->dev); 101977cd62e8STimur Tabi 102077cd62e8STimur Tabi dma_async_device_unregister(&fdev->common); 102177cd62e8STimur Tabi 102277cd62e8STimur Tabi for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) 102377cd62e8STimur Tabi if (fdev->chan[i]) 102477cd62e8STimur Tabi fsl_dma_chan_remove(fdev->chan[i]); 102577cd62e8STimur Tabi 102677cd62e8STimur Tabi if (fdev->irq != NO_IRQ) 102777cd62e8STimur Tabi free_irq(fdev->irq, fdev); 102877cd62e8STimur Tabi 102977cd62e8STimur Tabi iounmap(fdev->reg_base); 103077cd62e8STimur Tabi 103177cd62e8STimur Tabi kfree(fdev); 103277cd62e8STimur Tabi dev_set_drvdata(&of_dev->dev, NULL); 103377cd62e8STimur Tabi 103477cd62e8STimur Tabi return 0; 103577cd62e8STimur Tabi } 103677cd62e8STimur Tabi 1037173acc7cSZhang Wei static struct of_device_id of_fsl_dma_ids[] = { 1038049c9d45SKumar Gala { .compatible = "fsl,eloplus-dma", }, 1039049c9d45SKumar Gala { .compatible = "fsl,elo-dma", }, 1040173acc7cSZhang Wei {} 1041173acc7cSZhang Wei }; 1042173acc7cSZhang Wei 1043173acc7cSZhang Wei static struct of_platform_driver of_fsl_dma_driver = { 104477cd62e8STimur Tabi .name = "fsl-elo-dma", 1045173acc7cSZhang Wei .match_table = of_fsl_dma_ids, 1046173acc7cSZhang Wei .probe = of_fsl_dma_probe, 104777cd62e8STimur Tabi .remove = of_fsl_dma_remove, 1048173acc7cSZhang Wei }; 1049173acc7cSZhang Wei 1050173acc7cSZhang Wei static __init int of_fsl_dma_init(void) 1051173acc7cSZhang Wei { 105277cd62e8STimur Tabi int ret; 105377cd62e8STimur Tabi 105477cd62e8STimur Tabi pr_info("Freescale Elo / Elo Plus DMA driver\n"); 105577cd62e8STimur Tabi 105677cd62e8STimur Tabi ret = of_register_platform_driver(&of_fsl_dma_driver); 105777cd62e8STimur Tabi if (ret) 105877cd62e8STimur Tabi pr_err("fsldma: failed to register platform driver\n"); 105977cd62e8STimur Tabi 106077cd62e8STimur Tabi return ret; 1061173acc7cSZhang Wei } 1062173acc7cSZhang Wei 106377cd62e8STimur Tabi static void __exit of_fsl_dma_exit(void) 106477cd62e8STimur Tabi { 106577cd62e8STimur Tabi of_unregister_platform_driver(&of_fsl_dma_driver); 106677cd62e8STimur Tabi } 106777cd62e8STimur Tabi 1068173acc7cSZhang Wei subsys_initcall(of_fsl_dma_init); 106977cd62e8STimur Tabi module_exit(of_fsl_dma_exit); 107077cd62e8STimur Tabi 107177cd62e8STimur Tabi MODULE_DESCRIPTION("Freescale Elo / Elo Plus DMA driver"); 107277cd62e8STimur Tabi MODULE_LICENSE("GPL"); 1073