1173acc7cSZhang Wei /* 2173acc7cSZhang Wei * Freescale MPC85xx, MPC83xx DMA Engine support 3173acc7cSZhang Wei * 4e2c8e425SLi Yang * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved. 5173acc7cSZhang Wei * 6173acc7cSZhang Wei * Author: 7173acc7cSZhang Wei * Zhang Wei <wei.zhang@freescale.com>, Jul 2007 8173acc7cSZhang Wei * Ebony Zhu <ebony.zhu@freescale.com>, May 2007 9173acc7cSZhang Wei * 10173acc7cSZhang Wei * Description: 11173acc7cSZhang Wei * DMA engine driver for Freescale MPC8540 DMA controller, which is 12173acc7cSZhang Wei * also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc. 13c2e07b3aSStefan Weil * The support for MPC8349 DMA controller is also added. 14173acc7cSZhang Wei * 15a7aea373SIra W. Snyder * This driver instructs the DMA controller to issue the PCI Read Multiple 16a7aea373SIra W. Snyder * command for PCI read operations, instead of using the default PCI Read Line 17a7aea373SIra W. Snyder * command. Please be aware that this setting may result in read pre-fetching 18a7aea373SIra W. Snyder * on some platforms. 19a7aea373SIra W. Snyder * 20173acc7cSZhang Wei * This is free software; you can redistribute it and/or modify 21173acc7cSZhang Wei * it under the terms of the GNU General Public License as published by 22173acc7cSZhang Wei * the Free Software Foundation; either version 2 of the License, or 23173acc7cSZhang Wei * (at your option) any later version. 24173acc7cSZhang Wei * 25173acc7cSZhang Wei */ 26173acc7cSZhang Wei 27173acc7cSZhang Wei #include <linux/init.h> 28173acc7cSZhang Wei #include <linux/module.h> 29173acc7cSZhang Wei #include <linux/pci.h> 305a0e3ad6STejun Heo #include <linux/slab.h> 31173acc7cSZhang Wei #include <linux/interrupt.h> 32173acc7cSZhang Wei #include <linux/dmaengine.h> 33173acc7cSZhang Wei #include <linux/delay.h> 34173acc7cSZhang Wei #include <linux/dma-mapping.h> 35173acc7cSZhang Wei #include <linux/dmapool.h> 36173acc7cSZhang Wei #include <linux/of_platform.h> 37173acc7cSZhang Wei 38d2ebfb33SRussell King - ARM Linux #include "dmaengine.h" 39173acc7cSZhang Wei #include "fsldma.h" 40173acc7cSZhang Wei 41b158471eSIra Snyder #define chan_dbg(chan, fmt, arg...) \ 42b158471eSIra Snyder dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg) 43b158471eSIra Snyder #define chan_err(chan, fmt, arg...) \ 44b158471eSIra Snyder dev_err(chan->dev, "%s: " fmt, chan->name, ##arg) 45c1433041SIra Snyder 46b158471eSIra Snyder static const char msg_ld_oom[] = "No free memory for link descriptor"; 47173acc7cSZhang Wei 48e8bd84dfSIra Snyder /* 49e8bd84dfSIra Snyder * Register Helpers 50173acc7cSZhang Wei */ 51173acc7cSZhang Wei 52a1c03319SIra Snyder static void set_sr(struct fsldma_chan *chan, u32 val) 53173acc7cSZhang Wei { 54a1c03319SIra Snyder DMA_OUT(chan, &chan->regs->sr, val, 32); 55173acc7cSZhang Wei } 56173acc7cSZhang Wei 57a1c03319SIra Snyder static u32 get_sr(struct fsldma_chan *chan) 58173acc7cSZhang Wei { 59a1c03319SIra Snyder return DMA_IN(chan, &chan->regs->sr, 32); 60173acc7cSZhang Wei } 61173acc7cSZhang Wei 62a1c03319SIra Snyder static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr) 63173acc7cSZhang Wei { 64a1c03319SIra Snyder DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64); 65173acc7cSZhang Wei } 66173acc7cSZhang Wei 67a1c03319SIra Snyder static dma_addr_t get_cdar(struct fsldma_chan *chan) 68173acc7cSZhang Wei { 69a1c03319SIra Snyder return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN; 70173acc7cSZhang Wei } 71173acc7cSZhang Wei 72a1c03319SIra Snyder static u32 get_bcr(struct fsldma_chan *chan) 73f79abb62SZhang Wei { 74a1c03319SIra Snyder return DMA_IN(chan, &chan->regs->bcr, 32); 75f79abb62SZhang Wei } 76f79abb62SZhang Wei 77e8bd84dfSIra Snyder /* 78e8bd84dfSIra Snyder * Descriptor Helpers 79e8bd84dfSIra Snyder */ 80e8bd84dfSIra Snyder 81173acc7cSZhang Wei static void set_desc_cnt(struct fsldma_chan *chan, 82173acc7cSZhang Wei struct fsl_dma_ld_hw *hw, u32 count) 83173acc7cSZhang Wei { 84173acc7cSZhang Wei hw->count = CPU_TO_DMA(chan, count, 32); 85173acc7cSZhang Wei } 86173acc7cSZhang Wei 879c4d1e7bSIra Snyder static u32 get_desc_cnt(struct fsldma_chan *chan, struct fsl_desc_sw *desc) 88173acc7cSZhang Wei { 899c4d1e7bSIra Snyder return DMA_TO_CPU(chan, desc->hw.count, 32); 9043a1a3edSIra Snyder } 91173acc7cSZhang Wei 92173acc7cSZhang Wei static void set_desc_src(struct fsldma_chan *chan, 93173acc7cSZhang Wei struct fsl_dma_ld_hw *hw, dma_addr_t src) 94173acc7cSZhang Wei { 95173acc7cSZhang Wei u64 snoop_bits; 96900325a6SDan Williams 97173acc7cSZhang Wei snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) 98173acc7cSZhang Wei ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0; 99173acc7cSZhang Wei hw->src_addr = CPU_TO_DMA(chan, snoop_bits | src, 64); 100900325a6SDan Williams } 101272ca655SIra Snyder 1029c4d1e7bSIra Snyder static dma_addr_t get_desc_src(struct fsldma_chan *chan, 103173acc7cSZhang Wei struct fsl_desc_sw *desc) 104173acc7cSZhang Wei { 105776c8943SIra Snyder u64 snoop_bits; 106776c8943SIra Snyder 1079c4d1e7bSIra Snyder snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) 1089c4d1e7bSIra Snyder ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0; 1099c4d1e7bSIra Snyder return DMA_TO_CPU(chan, desc->hw.src_addr, 64) & ~snoop_bits; 1109c4d1e7bSIra Snyder } 1119c4d1e7bSIra Snyder 112173acc7cSZhang Wei static void set_desc_dst(struct fsldma_chan *chan, 113173acc7cSZhang Wei struct fsl_dma_ld_hw *hw, dma_addr_t dst) 114173acc7cSZhang Wei { 115173acc7cSZhang Wei u64 snoop_bits; 116173acc7cSZhang Wei 117173acc7cSZhang Wei snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) 118173acc7cSZhang Wei ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0; 119173acc7cSZhang Wei hw->dst_addr = CPU_TO_DMA(chan, snoop_bits | dst, 64); 120173acc7cSZhang Wei } 121173acc7cSZhang Wei 1229c4d1e7bSIra Snyder static dma_addr_t get_desc_dst(struct fsldma_chan *chan, 1239c4d1e7bSIra Snyder struct fsl_desc_sw *desc) 1249c4d1e7bSIra Snyder { 1259c4d1e7bSIra Snyder u64 snoop_bits; 1269c4d1e7bSIra Snyder 1279c4d1e7bSIra Snyder snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) 1289c4d1e7bSIra Snyder ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0; 1299c4d1e7bSIra Snyder return DMA_TO_CPU(chan, desc->hw.dst_addr, 64) & ~snoop_bits; 1309c4d1e7bSIra Snyder } 1319c4d1e7bSIra Snyder 132173acc7cSZhang Wei static void set_desc_next(struct fsldma_chan *chan, 133173acc7cSZhang Wei struct fsl_dma_ld_hw *hw, dma_addr_t next) 134173acc7cSZhang Wei { 135173acc7cSZhang Wei u64 snoop_bits; 136173acc7cSZhang Wei 137173acc7cSZhang Wei snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) 138173acc7cSZhang Wei ? FSL_DMA_SNEN : 0; 139173acc7cSZhang Wei hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64); 140173acc7cSZhang Wei } 141173acc7cSZhang Wei 14231f4306cSIra Snyder static void set_ld_eol(struct fsldma_chan *chan, struct fsl_desc_sw *desc) 143173acc7cSZhang Wei { 144e8bd84dfSIra Snyder u64 snoop_bits; 145e8bd84dfSIra Snyder 146a1c03319SIra Snyder snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) 147776c8943SIra Snyder ? FSL_DMA_SNEN : 0; 148776c8943SIra Snyder 149a1c03319SIra Snyder desc->hw.next_ln_addr = CPU_TO_DMA(chan, 150a1c03319SIra Snyder DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL 151776c8943SIra Snyder | snoop_bits, 64); 152173acc7cSZhang Wei } 153173acc7cSZhang Wei 154e8bd84dfSIra Snyder /* 155e8bd84dfSIra Snyder * DMA Engine Hardware Control Helpers 156e8bd84dfSIra Snyder */ 157173acc7cSZhang Wei 158e8bd84dfSIra Snyder static void dma_init(struct fsldma_chan *chan) 159173acc7cSZhang Wei { 160e8bd84dfSIra Snyder /* Reset the channel */ 161e8bd84dfSIra Snyder DMA_OUT(chan, &chan->regs->mr, 0, 32); 162173acc7cSZhang Wei 163e8bd84dfSIra Snyder switch (chan->feature & FSL_DMA_IP_MASK) { 164e8bd84dfSIra Snyder case FSL_DMA_IP_85XX: 165e8bd84dfSIra Snyder /* Set the channel to below modes: 166e8bd84dfSIra Snyder * EIE - Error interrupt enable 167e8bd84dfSIra Snyder * EOLNIE - End of links interrupt enable 168e8bd84dfSIra Snyder * BWC - Bandwidth sharing among channels 169e8bd84dfSIra Snyder */ 170e8bd84dfSIra Snyder DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_BWC 171f04cd407SIra Snyder | FSL_DMA_MR_EIE | FSL_DMA_MR_EOLNIE, 32); 172e8bd84dfSIra Snyder break; 173e8bd84dfSIra Snyder case FSL_DMA_IP_83XX: 174e8bd84dfSIra Snyder /* Set the channel to below modes: 175e8bd84dfSIra Snyder * EOTIE - End-of-transfer interrupt enable 176e8bd84dfSIra Snyder * PRC_RM - PCI read multiple 177e8bd84dfSIra Snyder */ 178e8bd84dfSIra Snyder DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EOTIE 179e8bd84dfSIra Snyder | FSL_DMA_MR_PRC_RM, 32); 180e8bd84dfSIra Snyder break; 181e8bd84dfSIra Snyder } 182173acc7cSZhang Wei } 183173acc7cSZhang Wei 184173acc7cSZhang Wei static int dma_is_idle(struct fsldma_chan *chan) 185173acc7cSZhang Wei { 186173acc7cSZhang Wei u32 sr = get_sr(chan); 187173acc7cSZhang Wei return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH); 188173acc7cSZhang Wei } 189173acc7cSZhang Wei 190f04cd407SIra Snyder /* 191f04cd407SIra Snyder * Start the DMA controller 192f04cd407SIra Snyder * 193f04cd407SIra Snyder * Preconditions: 194f04cd407SIra Snyder * - the CDAR register must point to the start descriptor 195f04cd407SIra Snyder * - the MRn[CS] bit must be cleared 196f04cd407SIra Snyder */ 197173acc7cSZhang Wei static void dma_start(struct fsldma_chan *chan) 198173acc7cSZhang Wei { 199173acc7cSZhang Wei u32 mode; 200173acc7cSZhang Wei 201173acc7cSZhang Wei mode = DMA_IN(chan, &chan->regs->mr, 32); 202173acc7cSZhang Wei 203173acc7cSZhang Wei if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) { 204173acc7cSZhang Wei DMA_OUT(chan, &chan->regs->bcr, 0, 32); 205173acc7cSZhang Wei mode |= FSL_DMA_MR_EMP_EN; 206173acc7cSZhang Wei } else { 207173acc7cSZhang Wei mode &= ~FSL_DMA_MR_EMP_EN; 208173acc7cSZhang Wei } 209173acc7cSZhang Wei 210f04cd407SIra Snyder if (chan->feature & FSL_DMA_CHAN_START_EXT) { 211173acc7cSZhang Wei mode |= FSL_DMA_MR_EMS_EN; 212f04cd407SIra Snyder } else { 213f04cd407SIra Snyder mode &= ~FSL_DMA_MR_EMS_EN; 214173acc7cSZhang Wei mode |= FSL_DMA_MR_CS; 215f04cd407SIra Snyder } 216173acc7cSZhang Wei 217173acc7cSZhang Wei DMA_OUT(chan, &chan->regs->mr, mode, 32); 218173acc7cSZhang Wei } 219173acc7cSZhang Wei 220173acc7cSZhang Wei static void dma_halt(struct fsldma_chan *chan) 221173acc7cSZhang Wei { 222173acc7cSZhang Wei u32 mode; 223173acc7cSZhang Wei int i; 224173acc7cSZhang Wei 225a00ae34aSIra Snyder /* read the mode register */ 226173acc7cSZhang Wei mode = DMA_IN(chan, &chan->regs->mr, 32); 227a00ae34aSIra Snyder 228a00ae34aSIra Snyder /* 229a00ae34aSIra Snyder * The 85xx controller supports channel abort, which will stop 230a00ae34aSIra Snyder * the current transfer. On 83xx, this bit is the transfer error 231a00ae34aSIra Snyder * mask bit, which should not be changed. 232a00ae34aSIra Snyder */ 233a00ae34aSIra Snyder if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) { 234173acc7cSZhang Wei mode |= FSL_DMA_MR_CA; 235173acc7cSZhang Wei DMA_OUT(chan, &chan->regs->mr, mode, 32); 236173acc7cSZhang Wei 237a00ae34aSIra Snyder mode &= ~FSL_DMA_MR_CA; 238a00ae34aSIra Snyder } 239a00ae34aSIra Snyder 240a00ae34aSIra Snyder /* stop the DMA controller */ 241a00ae34aSIra Snyder mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN); 242173acc7cSZhang Wei DMA_OUT(chan, &chan->regs->mr, mode, 32); 243173acc7cSZhang Wei 244a00ae34aSIra Snyder /* wait for the DMA controller to become idle */ 245173acc7cSZhang Wei for (i = 0; i < 100; i++) { 246173acc7cSZhang Wei if (dma_is_idle(chan)) 247173acc7cSZhang Wei return; 248173acc7cSZhang Wei 249173acc7cSZhang Wei udelay(10); 250173acc7cSZhang Wei } 251173acc7cSZhang Wei 252173acc7cSZhang Wei if (!dma_is_idle(chan)) 253b158471eSIra Snyder chan_err(chan, "DMA halt timeout!\n"); 254173acc7cSZhang Wei } 255173acc7cSZhang Wei 256173acc7cSZhang Wei /** 257173acc7cSZhang Wei * fsl_chan_set_src_loop_size - Set source address hold transfer size 258a1c03319SIra Snyder * @chan : Freescale DMA channel 259173acc7cSZhang Wei * @size : Address loop size, 0 for disable loop 260173acc7cSZhang Wei * 261173acc7cSZhang Wei * The set source address hold transfer size. The source 262173acc7cSZhang Wei * address hold or loop transfer size is when the DMA transfer 263173acc7cSZhang Wei * data from source address (SA), if the loop size is 4, the DMA will 264173acc7cSZhang Wei * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA, 265173acc7cSZhang Wei * SA + 1 ... and so on. 266173acc7cSZhang Wei */ 267a1c03319SIra Snyder static void fsl_chan_set_src_loop_size(struct fsldma_chan *chan, int size) 268173acc7cSZhang Wei { 269272ca655SIra Snyder u32 mode; 270272ca655SIra Snyder 271a1c03319SIra Snyder mode = DMA_IN(chan, &chan->regs->mr, 32); 272272ca655SIra Snyder 273173acc7cSZhang Wei switch (size) { 274173acc7cSZhang Wei case 0: 275272ca655SIra Snyder mode &= ~FSL_DMA_MR_SAHE; 276173acc7cSZhang Wei break; 277173acc7cSZhang Wei case 1: 278173acc7cSZhang Wei case 2: 279173acc7cSZhang Wei case 4: 280173acc7cSZhang Wei case 8: 281272ca655SIra Snyder mode |= FSL_DMA_MR_SAHE | (__ilog2(size) << 14); 282173acc7cSZhang Wei break; 283173acc7cSZhang Wei } 284272ca655SIra Snyder 285a1c03319SIra Snyder DMA_OUT(chan, &chan->regs->mr, mode, 32); 286173acc7cSZhang Wei } 287173acc7cSZhang Wei 288173acc7cSZhang Wei /** 289738f5f7eSIra Snyder * fsl_chan_set_dst_loop_size - Set destination address hold transfer size 290a1c03319SIra Snyder * @chan : Freescale DMA channel 291173acc7cSZhang Wei * @size : Address loop size, 0 for disable loop 292173acc7cSZhang Wei * 293173acc7cSZhang Wei * The set destination address hold transfer size. The destination 294173acc7cSZhang Wei * address hold or loop transfer size is when the DMA transfer 295173acc7cSZhang Wei * data to destination address (TA), if the loop size is 4, the DMA will 296173acc7cSZhang Wei * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA, 297173acc7cSZhang Wei * TA + 1 ... and so on. 298173acc7cSZhang Wei */ 299a1c03319SIra Snyder static void fsl_chan_set_dst_loop_size(struct fsldma_chan *chan, int size) 300173acc7cSZhang Wei { 301272ca655SIra Snyder u32 mode; 302272ca655SIra Snyder 303a1c03319SIra Snyder mode = DMA_IN(chan, &chan->regs->mr, 32); 304272ca655SIra Snyder 305173acc7cSZhang Wei switch (size) { 306173acc7cSZhang Wei case 0: 307272ca655SIra Snyder mode &= ~FSL_DMA_MR_DAHE; 308173acc7cSZhang Wei break; 309173acc7cSZhang Wei case 1: 310173acc7cSZhang Wei case 2: 311173acc7cSZhang Wei case 4: 312173acc7cSZhang Wei case 8: 313272ca655SIra Snyder mode |= FSL_DMA_MR_DAHE | (__ilog2(size) << 16); 314173acc7cSZhang Wei break; 315173acc7cSZhang Wei } 316272ca655SIra Snyder 317a1c03319SIra Snyder DMA_OUT(chan, &chan->regs->mr, mode, 32); 318173acc7cSZhang Wei } 319173acc7cSZhang Wei 320173acc7cSZhang Wei /** 321e6c7ecb6SIra Snyder * fsl_chan_set_request_count - Set DMA Request Count for external control 322a1c03319SIra Snyder * @chan : Freescale DMA channel 323e6c7ecb6SIra Snyder * @size : Number of bytes to transfer in a single request 324173acc7cSZhang Wei * 325e6c7ecb6SIra Snyder * The Freescale DMA channel can be controlled by the external signal DREQ#. 326e6c7ecb6SIra Snyder * The DMA request count is how many bytes are allowed to transfer before 327e6c7ecb6SIra Snyder * pausing the channel, after which a new assertion of DREQ# resumes channel 328e6c7ecb6SIra Snyder * operation. 329e6c7ecb6SIra Snyder * 330e6c7ecb6SIra Snyder * A size of 0 disables external pause control. The maximum size is 1024. 331173acc7cSZhang Wei */ 332a1c03319SIra Snyder static void fsl_chan_set_request_count(struct fsldma_chan *chan, int size) 333173acc7cSZhang Wei { 334272ca655SIra Snyder u32 mode; 335272ca655SIra Snyder 336e6c7ecb6SIra Snyder BUG_ON(size > 1024); 337272ca655SIra Snyder 338a1c03319SIra Snyder mode = DMA_IN(chan, &chan->regs->mr, 32); 339272ca655SIra Snyder mode |= (__ilog2(size) << 24) & 0x0f000000; 340272ca655SIra Snyder 341a1c03319SIra Snyder DMA_OUT(chan, &chan->regs->mr, mode, 32); 342e6c7ecb6SIra Snyder } 343e6c7ecb6SIra Snyder 344e6c7ecb6SIra Snyder /** 345e6c7ecb6SIra Snyder * fsl_chan_toggle_ext_pause - Toggle channel external pause status 346a1c03319SIra Snyder * @chan : Freescale DMA channel 347e6c7ecb6SIra Snyder * @enable : 0 is disabled, 1 is enabled. 348e6c7ecb6SIra Snyder * 349e6c7ecb6SIra Snyder * The Freescale DMA channel can be controlled by the external signal DREQ#. 350e6c7ecb6SIra Snyder * The DMA Request Count feature should be used in addition to this feature 351e6c7ecb6SIra Snyder * to set the number of bytes to transfer before pausing the channel. 352e6c7ecb6SIra Snyder */ 353a1c03319SIra Snyder static void fsl_chan_toggle_ext_pause(struct fsldma_chan *chan, int enable) 354e6c7ecb6SIra Snyder { 355e6c7ecb6SIra Snyder if (enable) 356a1c03319SIra Snyder chan->feature |= FSL_DMA_CHAN_PAUSE_EXT; 357e6c7ecb6SIra Snyder else 358a1c03319SIra Snyder chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT; 359173acc7cSZhang Wei } 360173acc7cSZhang Wei 361173acc7cSZhang Wei /** 362173acc7cSZhang Wei * fsl_chan_toggle_ext_start - Toggle channel external start status 363a1c03319SIra Snyder * @chan : Freescale DMA channel 364173acc7cSZhang Wei * @enable : 0 is disabled, 1 is enabled. 365173acc7cSZhang Wei * 366173acc7cSZhang Wei * If enable the external start, the channel can be started by an 367173acc7cSZhang Wei * external DMA start pin. So the dma_start() does not start the 368173acc7cSZhang Wei * transfer immediately. The DMA channel will wait for the 369173acc7cSZhang Wei * control pin asserted. 370173acc7cSZhang Wei */ 371a1c03319SIra Snyder static void fsl_chan_toggle_ext_start(struct fsldma_chan *chan, int enable) 372173acc7cSZhang Wei { 373173acc7cSZhang Wei if (enable) 374a1c03319SIra Snyder chan->feature |= FSL_DMA_CHAN_START_EXT; 375173acc7cSZhang Wei else 376a1c03319SIra Snyder chan->feature &= ~FSL_DMA_CHAN_START_EXT; 377173acc7cSZhang Wei } 378173acc7cSZhang Wei 37931f4306cSIra Snyder static void append_ld_queue(struct fsldma_chan *chan, struct fsl_desc_sw *desc) 3809c3a50b7SIra Snyder { 3819c3a50b7SIra Snyder struct fsl_desc_sw *tail = to_fsl_desc(chan->ld_pending.prev); 3829c3a50b7SIra Snyder 3839c3a50b7SIra Snyder if (list_empty(&chan->ld_pending)) 3849c3a50b7SIra Snyder goto out_splice; 3859c3a50b7SIra Snyder 3869c3a50b7SIra Snyder /* 3879c3a50b7SIra Snyder * Add the hardware descriptor to the chain of hardware descriptors 3889c3a50b7SIra Snyder * that already exists in memory. 3899c3a50b7SIra Snyder * 3909c3a50b7SIra Snyder * This will un-set the EOL bit of the existing transaction, and the 3919c3a50b7SIra Snyder * last link in this transaction will become the EOL descriptor. 3929c3a50b7SIra Snyder */ 3939c3a50b7SIra Snyder set_desc_next(chan, &tail->hw, desc->async_tx.phys); 3949c3a50b7SIra Snyder 3959c3a50b7SIra Snyder /* 3969c3a50b7SIra Snyder * Add the software descriptor and all children to the list 3979c3a50b7SIra Snyder * of pending transactions 3989c3a50b7SIra Snyder */ 3999c3a50b7SIra Snyder out_splice: 4009c3a50b7SIra Snyder list_splice_tail_init(&desc->tx_list, &chan->ld_pending); 4019c3a50b7SIra Snyder } 4029c3a50b7SIra Snyder 403173acc7cSZhang Wei static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx) 404173acc7cSZhang Wei { 405a1c03319SIra Snyder struct fsldma_chan *chan = to_fsl_chan(tx->chan); 406eda34234SDan Williams struct fsl_desc_sw *desc = tx_to_fsl_desc(tx); 407eda34234SDan Williams struct fsl_desc_sw *child; 408173acc7cSZhang Wei unsigned long flags; 409173acc7cSZhang Wei dma_cookie_t cookie; 410173acc7cSZhang Wei 411a1c03319SIra Snyder spin_lock_irqsave(&chan->desc_lock, flags); 412173acc7cSZhang Wei 4139c3a50b7SIra Snyder /* 4149c3a50b7SIra Snyder * assign cookies to all of the software descriptors 4159c3a50b7SIra Snyder * that make up this transaction 4169c3a50b7SIra Snyder */ 417eda34234SDan Williams list_for_each_entry(child, &desc->tx_list, node) { 418884485e1SRussell King - ARM Linux cookie = dma_cookie_assign(&child->async_tx); 419bcfb7465SIra Snyder } 420bcfb7465SIra Snyder 4219c3a50b7SIra Snyder /* put this transaction onto the tail of the pending queue */ 422a1c03319SIra Snyder append_ld_queue(chan, desc); 423173acc7cSZhang Wei 424a1c03319SIra Snyder spin_unlock_irqrestore(&chan->desc_lock, flags); 425173acc7cSZhang Wei 426173acc7cSZhang Wei return cookie; 427173acc7cSZhang Wei } 428173acc7cSZhang Wei 429173acc7cSZhang Wei /** 430173acc7cSZhang Wei * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool. 431a1c03319SIra Snyder * @chan : Freescale DMA channel 432173acc7cSZhang Wei * 433173acc7cSZhang Wei * Return - The descriptor allocated. NULL for failed. 434173acc7cSZhang Wei */ 43531f4306cSIra Snyder static struct fsl_desc_sw *fsl_dma_alloc_descriptor(struct fsldma_chan *chan) 436173acc7cSZhang Wei { 4379c3a50b7SIra Snyder struct fsl_desc_sw *desc; 438173acc7cSZhang Wei dma_addr_t pdesc; 439173acc7cSZhang Wei 4409c3a50b7SIra Snyder desc = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc); 4419c3a50b7SIra Snyder if (!desc) { 442b158471eSIra Snyder chan_dbg(chan, "out of memory for link descriptor\n"); 4439c3a50b7SIra Snyder return NULL; 444173acc7cSZhang Wei } 445173acc7cSZhang Wei 4469c3a50b7SIra Snyder memset(desc, 0, sizeof(*desc)); 4479c3a50b7SIra Snyder INIT_LIST_HEAD(&desc->tx_list); 4489c3a50b7SIra Snyder dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); 4499c3a50b7SIra Snyder desc->async_tx.tx_submit = fsl_dma_tx_submit; 4509c3a50b7SIra Snyder desc->async_tx.phys = pdesc; 4519c3a50b7SIra Snyder 4520ab09c36SIra Snyder #ifdef FSL_DMA_LD_DEBUG 4530ab09c36SIra Snyder chan_dbg(chan, "LD %p allocated\n", desc); 4540ab09c36SIra Snyder #endif 4550ab09c36SIra Snyder 4569c3a50b7SIra Snyder return desc; 457173acc7cSZhang Wei } 458173acc7cSZhang Wei 459173acc7cSZhang Wei /** 460173acc7cSZhang Wei * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel. 461a1c03319SIra Snyder * @chan : Freescale DMA channel 462173acc7cSZhang Wei * 463173acc7cSZhang Wei * This function will create a dma pool for descriptor allocation. 464173acc7cSZhang Wei * 465173acc7cSZhang Wei * Return - The number of descriptors allocated. 466173acc7cSZhang Wei */ 467a1c03319SIra Snyder static int fsl_dma_alloc_chan_resources(struct dma_chan *dchan) 468173acc7cSZhang Wei { 469a1c03319SIra Snyder struct fsldma_chan *chan = to_fsl_chan(dchan); 47077cd62e8STimur Tabi 47177cd62e8STimur Tabi /* Has this channel already been allocated? */ 472a1c03319SIra Snyder if (chan->desc_pool) 47377cd62e8STimur Tabi return 1; 474173acc7cSZhang Wei 4759c3a50b7SIra Snyder /* 4769c3a50b7SIra Snyder * We need the descriptor to be aligned to 32bytes 477173acc7cSZhang Wei * for meeting FSL DMA specification requirement. 478173acc7cSZhang Wei */ 479b158471eSIra Snyder chan->desc_pool = dma_pool_create(chan->name, chan->dev, 4809c3a50b7SIra Snyder sizeof(struct fsl_desc_sw), 4819c3a50b7SIra Snyder __alignof__(struct fsl_desc_sw), 0); 482a1c03319SIra Snyder if (!chan->desc_pool) { 483b158471eSIra Snyder chan_err(chan, "unable to allocate descriptor pool\n"); 4849c3a50b7SIra Snyder return -ENOMEM; 485173acc7cSZhang Wei } 486173acc7cSZhang Wei 4879c3a50b7SIra Snyder /* there is at least one descriptor free to be allocated */ 488173acc7cSZhang Wei return 1; 489173acc7cSZhang Wei } 490173acc7cSZhang Wei 491173acc7cSZhang Wei /** 4929c3a50b7SIra Snyder * fsldma_free_desc_list - Free all descriptors in a queue 4939c3a50b7SIra Snyder * @chan: Freescae DMA channel 4949c3a50b7SIra Snyder * @list: the list to free 4959c3a50b7SIra Snyder * 4969c3a50b7SIra Snyder * LOCKING: must hold chan->desc_lock 4979c3a50b7SIra Snyder */ 4989c3a50b7SIra Snyder static void fsldma_free_desc_list(struct fsldma_chan *chan, 4999c3a50b7SIra Snyder struct list_head *list) 5009c3a50b7SIra Snyder { 5019c3a50b7SIra Snyder struct fsl_desc_sw *desc, *_desc; 5029c3a50b7SIra Snyder 5039c3a50b7SIra Snyder list_for_each_entry_safe(desc, _desc, list, node) { 5049c3a50b7SIra Snyder list_del(&desc->node); 5050ab09c36SIra Snyder #ifdef FSL_DMA_LD_DEBUG 5060ab09c36SIra Snyder chan_dbg(chan, "LD %p free\n", desc); 5070ab09c36SIra Snyder #endif 5089c3a50b7SIra Snyder dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); 5099c3a50b7SIra Snyder } 5109c3a50b7SIra Snyder } 5119c3a50b7SIra Snyder 5129c3a50b7SIra Snyder static void fsldma_free_desc_list_reverse(struct fsldma_chan *chan, 5139c3a50b7SIra Snyder struct list_head *list) 5149c3a50b7SIra Snyder { 5159c3a50b7SIra Snyder struct fsl_desc_sw *desc, *_desc; 5169c3a50b7SIra Snyder 5179c3a50b7SIra Snyder list_for_each_entry_safe_reverse(desc, _desc, list, node) { 5189c3a50b7SIra Snyder list_del(&desc->node); 5190ab09c36SIra Snyder #ifdef FSL_DMA_LD_DEBUG 5200ab09c36SIra Snyder chan_dbg(chan, "LD %p free\n", desc); 5210ab09c36SIra Snyder #endif 5229c3a50b7SIra Snyder dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); 5239c3a50b7SIra Snyder } 5249c3a50b7SIra Snyder } 5259c3a50b7SIra Snyder 5269c3a50b7SIra Snyder /** 527173acc7cSZhang Wei * fsl_dma_free_chan_resources - Free all resources of the channel. 528a1c03319SIra Snyder * @chan : Freescale DMA channel 529173acc7cSZhang Wei */ 530a1c03319SIra Snyder static void fsl_dma_free_chan_resources(struct dma_chan *dchan) 531173acc7cSZhang Wei { 532a1c03319SIra Snyder struct fsldma_chan *chan = to_fsl_chan(dchan); 533173acc7cSZhang Wei unsigned long flags; 534173acc7cSZhang Wei 535b158471eSIra Snyder chan_dbg(chan, "free all channel resources\n"); 536a1c03319SIra Snyder spin_lock_irqsave(&chan->desc_lock, flags); 5379c3a50b7SIra Snyder fsldma_free_desc_list(chan, &chan->ld_pending); 5389c3a50b7SIra Snyder fsldma_free_desc_list(chan, &chan->ld_running); 539a1c03319SIra Snyder spin_unlock_irqrestore(&chan->desc_lock, flags); 54077cd62e8STimur Tabi 5419c3a50b7SIra Snyder dma_pool_destroy(chan->desc_pool); 542a1c03319SIra Snyder chan->desc_pool = NULL; 543173acc7cSZhang Wei } 544173acc7cSZhang Wei 5452187c269SZhang Wei static struct dma_async_tx_descriptor * 546a1c03319SIra Snyder fsl_dma_prep_interrupt(struct dma_chan *dchan, unsigned long flags) 5472187c269SZhang Wei { 548a1c03319SIra Snyder struct fsldma_chan *chan; 5492187c269SZhang Wei struct fsl_desc_sw *new; 5502187c269SZhang Wei 551a1c03319SIra Snyder if (!dchan) 5522187c269SZhang Wei return NULL; 5532187c269SZhang Wei 554a1c03319SIra Snyder chan = to_fsl_chan(dchan); 5552187c269SZhang Wei 556a1c03319SIra Snyder new = fsl_dma_alloc_descriptor(chan); 5572187c269SZhang Wei if (!new) { 558b158471eSIra Snyder chan_err(chan, "%s\n", msg_ld_oom); 5592187c269SZhang Wei return NULL; 5602187c269SZhang Wei } 5612187c269SZhang Wei 5622187c269SZhang Wei new->async_tx.cookie = -EBUSY; 563636bdeaaSDan Williams new->async_tx.flags = flags; 5642187c269SZhang Wei 565f79abb62SZhang Wei /* Insert the link descriptor to the LD ring */ 566eda34234SDan Williams list_add_tail(&new->node, &new->tx_list); 567f79abb62SZhang Wei 5682187c269SZhang Wei /* Set End-of-link to the last link descriptor of new list */ 569a1c03319SIra Snyder set_ld_eol(chan, new); 5702187c269SZhang Wei 5712187c269SZhang Wei return &new->async_tx; 5722187c269SZhang Wei } 5732187c269SZhang Wei 57431f4306cSIra Snyder static struct dma_async_tx_descriptor * 57531f4306cSIra Snyder fsl_dma_prep_memcpy(struct dma_chan *dchan, 57631f4306cSIra Snyder dma_addr_t dma_dst, dma_addr_t dma_src, 577173acc7cSZhang Wei size_t len, unsigned long flags) 578173acc7cSZhang Wei { 579a1c03319SIra Snyder struct fsldma_chan *chan; 580173acc7cSZhang Wei struct fsl_desc_sw *first = NULL, *prev = NULL, *new; 581173acc7cSZhang Wei size_t copy; 582173acc7cSZhang Wei 583a1c03319SIra Snyder if (!dchan) 584173acc7cSZhang Wei return NULL; 585173acc7cSZhang Wei 586173acc7cSZhang Wei if (!len) 587173acc7cSZhang Wei return NULL; 588173acc7cSZhang Wei 589a1c03319SIra Snyder chan = to_fsl_chan(dchan); 590173acc7cSZhang Wei 591173acc7cSZhang Wei do { 592173acc7cSZhang Wei 593173acc7cSZhang Wei /* Allocate the link descriptor from DMA pool */ 594a1c03319SIra Snyder new = fsl_dma_alloc_descriptor(chan); 595173acc7cSZhang Wei if (!new) { 596b158471eSIra Snyder chan_err(chan, "%s\n", msg_ld_oom); 5972e077f8eSIra Snyder goto fail; 598173acc7cSZhang Wei } 599173acc7cSZhang Wei 60056822843SZhang Wei copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT); 601173acc7cSZhang Wei 602a1c03319SIra Snyder set_desc_cnt(chan, &new->hw, copy); 603a1c03319SIra Snyder set_desc_src(chan, &new->hw, dma_src); 604a1c03319SIra Snyder set_desc_dst(chan, &new->hw, dma_dst); 605173acc7cSZhang Wei 606173acc7cSZhang Wei if (!first) 607173acc7cSZhang Wei first = new; 608173acc7cSZhang Wei else 609a1c03319SIra Snyder set_desc_next(chan, &prev->hw, new->async_tx.phys); 610173acc7cSZhang Wei 611173acc7cSZhang Wei new->async_tx.cookie = 0; 612636bdeaaSDan Williams async_tx_ack(&new->async_tx); 613173acc7cSZhang Wei 614173acc7cSZhang Wei prev = new; 615173acc7cSZhang Wei len -= copy; 616173acc7cSZhang Wei dma_src += copy; 617738f5f7eSIra Snyder dma_dst += copy; 618173acc7cSZhang Wei 619173acc7cSZhang Wei /* Insert the link descriptor to the LD ring */ 620eda34234SDan Williams list_add_tail(&new->node, &first->tx_list); 621173acc7cSZhang Wei } while (len); 622173acc7cSZhang Wei 623636bdeaaSDan Williams new->async_tx.flags = flags; /* client is in control of this ack */ 624173acc7cSZhang Wei new->async_tx.cookie = -EBUSY; 625173acc7cSZhang Wei 626173acc7cSZhang Wei /* Set End-of-link to the last link descriptor of new list */ 627a1c03319SIra Snyder set_ld_eol(chan, new); 628173acc7cSZhang Wei 6292e077f8eSIra Snyder return &first->async_tx; 6302e077f8eSIra Snyder 6312e077f8eSIra Snyder fail: 6322e077f8eSIra Snyder if (!first) 6332e077f8eSIra Snyder return NULL; 6342e077f8eSIra Snyder 6359c3a50b7SIra Snyder fsldma_free_desc_list_reverse(chan, &first->tx_list); 6362e077f8eSIra Snyder return NULL; 637173acc7cSZhang Wei } 638173acc7cSZhang Wei 639c1433041SIra Snyder static struct dma_async_tx_descriptor *fsl_dma_prep_sg(struct dma_chan *dchan, 640c1433041SIra Snyder struct scatterlist *dst_sg, unsigned int dst_nents, 641c1433041SIra Snyder struct scatterlist *src_sg, unsigned int src_nents, 642c1433041SIra Snyder unsigned long flags) 643c1433041SIra Snyder { 644c1433041SIra Snyder struct fsl_desc_sw *first = NULL, *prev = NULL, *new = NULL; 645c1433041SIra Snyder struct fsldma_chan *chan = to_fsl_chan(dchan); 646c1433041SIra Snyder size_t dst_avail, src_avail; 647c1433041SIra Snyder dma_addr_t dst, src; 648c1433041SIra Snyder size_t len; 649c1433041SIra Snyder 650c1433041SIra Snyder /* basic sanity checks */ 651c1433041SIra Snyder if (dst_nents == 0 || src_nents == 0) 652c1433041SIra Snyder return NULL; 653c1433041SIra Snyder 654c1433041SIra Snyder if (dst_sg == NULL || src_sg == NULL) 655c1433041SIra Snyder return NULL; 656c1433041SIra Snyder 657c1433041SIra Snyder /* 658c1433041SIra Snyder * TODO: should we check that both scatterlists have the same 659c1433041SIra Snyder * TODO: number of bytes in total? Is that really an error? 660c1433041SIra Snyder */ 661c1433041SIra Snyder 662c1433041SIra Snyder /* get prepared for the loop */ 663c1433041SIra Snyder dst_avail = sg_dma_len(dst_sg); 664c1433041SIra Snyder src_avail = sg_dma_len(src_sg); 665c1433041SIra Snyder 666c1433041SIra Snyder /* run until we are out of scatterlist entries */ 667c1433041SIra Snyder while (true) { 668c1433041SIra Snyder 669c1433041SIra Snyder /* create the largest transaction possible */ 670c1433041SIra Snyder len = min_t(size_t, src_avail, dst_avail); 671c1433041SIra Snyder len = min_t(size_t, len, FSL_DMA_BCR_MAX_CNT); 672c1433041SIra Snyder if (len == 0) 673c1433041SIra Snyder goto fetch; 674c1433041SIra Snyder 675c1433041SIra Snyder dst = sg_dma_address(dst_sg) + sg_dma_len(dst_sg) - dst_avail; 676c1433041SIra Snyder src = sg_dma_address(src_sg) + sg_dma_len(src_sg) - src_avail; 677c1433041SIra Snyder 678c1433041SIra Snyder /* allocate and populate the descriptor */ 679c1433041SIra Snyder new = fsl_dma_alloc_descriptor(chan); 680c1433041SIra Snyder if (!new) { 681b158471eSIra Snyder chan_err(chan, "%s\n", msg_ld_oom); 682c1433041SIra Snyder goto fail; 683c1433041SIra Snyder } 684c1433041SIra Snyder 685c1433041SIra Snyder set_desc_cnt(chan, &new->hw, len); 686c1433041SIra Snyder set_desc_src(chan, &new->hw, src); 687c1433041SIra Snyder set_desc_dst(chan, &new->hw, dst); 688c1433041SIra Snyder 689c1433041SIra Snyder if (!first) 690c1433041SIra Snyder first = new; 691c1433041SIra Snyder else 692c1433041SIra Snyder set_desc_next(chan, &prev->hw, new->async_tx.phys); 693c1433041SIra Snyder 694c1433041SIra Snyder new->async_tx.cookie = 0; 695c1433041SIra Snyder async_tx_ack(&new->async_tx); 696c1433041SIra Snyder prev = new; 697c1433041SIra Snyder 698c1433041SIra Snyder /* Insert the link descriptor to the LD ring */ 699c1433041SIra Snyder list_add_tail(&new->node, &first->tx_list); 700c1433041SIra Snyder 701c1433041SIra Snyder /* update metadata */ 702c1433041SIra Snyder dst_avail -= len; 703c1433041SIra Snyder src_avail -= len; 704c1433041SIra Snyder 705c1433041SIra Snyder fetch: 706c1433041SIra Snyder /* fetch the next dst scatterlist entry */ 707c1433041SIra Snyder if (dst_avail == 0) { 708c1433041SIra Snyder 709c1433041SIra Snyder /* no more entries: we're done */ 710c1433041SIra Snyder if (dst_nents == 0) 711c1433041SIra Snyder break; 712c1433041SIra Snyder 713c1433041SIra Snyder /* fetch the next entry: if there are no more: done */ 714c1433041SIra Snyder dst_sg = sg_next(dst_sg); 715c1433041SIra Snyder if (dst_sg == NULL) 716c1433041SIra Snyder break; 717c1433041SIra Snyder 718c1433041SIra Snyder dst_nents--; 719c1433041SIra Snyder dst_avail = sg_dma_len(dst_sg); 720c1433041SIra Snyder } 721c1433041SIra Snyder 722c1433041SIra Snyder /* fetch the next src scatterlist entry */ 723c1433041SIra Snyder if (src_avail == 0) { 724c1433041SIra Snyder 725c1433041SIra Snyder /* no more entries: we're done */ 726c1433041SIra Snyder if (src_nents == 0) 727c1433041SIra Snyder break; 728c1433041SIra Snyder 729c1433041SIra Snyder /* fetch the next entry: if there are no more: done */ 730c1433041SIra Snyder src_sg = sg_next(src_sg); 731c1433041SIra Snyder if (src_sg == NULL) 732c1433041SIra Snyder break; 733c1433041SIra Snyder 734c1433041SIra Snyder src_nents--; 735c1433041SIra Snyder src_avail = sg_dma_len(src_sg); 736c1433041SIra Snyder } 737c1433041SIra Snyder } 738c1433041SIra Snyder 739c1433041SIra Snyder new->async_tx.flags = flags; /* client is in control of this ack */ 740c1433041SIra Snyder new->async_tx.cookie = -EBUSY; 741c1433041SIra Snyder 742c1433041SIra Snyder /* Set End-of-link to the last link descriptor of new list */ 743c1433041SIra Snyder set_ld_eol(chan, new); 744c1433041SIra Snyder 745c1433041SIra Snyder return &first->async_tx; 746c1433041SIra Snyder 747c1433041SIra Snyder fail: 748c1433041SIra Snyder if (!first) 749c1433041SIra Snyder return NULL; 750c1433041SIra Snyder 751c1433041SIra Snyder fsldma_free_desc_list_reverse(chan, &first->tx_list); 752c1433041SIra Snyder return NULL; 753c1433041SIra Snyder } 754c1433041SIra Snyder 755173acc7cSZhang Wei /** 756bbea0b6eSIra Snyder * fsl_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction 757bbea0b6eSIra Snyder * @chan: DMA channel 758bbea0b6eSIra Snyder * @sgl: scatterlist to transfer to/from 759bbea0b6eSIra Snyder * @sg_len: number of entries in @scatterlist 760bbea0b6eSIra Snyder * @direction: DMA direction 761bbea0b6eSIra Snyder * @flags: DMAEngine flags 762185ecb5fSAlexandre Bounine * @context: transaction context (ignored) 763bbea0b6eSIra Snyder * 764bbea0b6eSIra Snyder * Prepare a set of descriptors for a DMA_SLAVE transaction. Following the 765bbea0b6eSIra Snyder * DMA_SLAVE API, this gets the device-specific information from the 766bbea0b6eSIra Snyder * chan->private variable. 767bbea0b6eSIra Snyder */ 768bbea0b6eSIra Snyder static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg( 769a1c03319SIra Snyder struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len, 770185ecb5fSAlexandre Bounine enum dma_transfer_direction direction, unsigned long flags, 771185ecb5fSAlexandre Bounine void *context) 772bbea0b6eSIra Snyder { 773bbea0b6eSIra Snyder /* 774968f19aeSIra Snyder * This operation is not supported on the Freescale DMA controller 775bbea0b6eSIra Snyder * 776968f19aeSIra Snyder * However, we need to provide the function pointer to allow the 777968f19aeSIra Snyder * device_control() method to work. 778bbea0b6eSIra Snyder */ 779bbea0b6eSIra Snyder return NULL; 780bbea0b6eSIra Snyder } 781bbea0b6eSIra Snyder 782c3635c78SLinus Walleij static int fsl_dma_device_control(struct dma_chan *dchan, 78305827630SLinus Walleij enum dma_ctrl_cmd cmd, unsigned long arg) 784bbea0b6eSIra Snyder { 785968f19aeSIra Snyder struct dma_slave_config *config; 786a1c03319SIra Snyder struct fsldma_chan *chan; 787bbea0b6eSIra Snyder unsigned long flags; 788968f19aeSIra Snyder int size; 789c3635c78SLinus Walleij 790a1c03319SIra Snyder if (!dchan) 791c3635c78SLinus Walleij return -EINVAL; 792bbea0b6eSIra Snyder 793a1c03319SIra Snyder chan = to_fsl_chan(dchan); 794bbea0b6eSIra Snyder 795968f19aeSIra Snyder switch (cmd) { 796968f19aeSIra Snyder case DMA_TERMINATE_ALL: 797f04cd407SIra Snyder spin_lock_irqsave(&chan->desc_lock, flags); 798f04cd407SIra Snyder 799bbea0b6eSIra Snyder /* Halt the DMA engine */ 800a1c03319SIra Snyder dma_halt(chan); 801bbea0b6eSIra Snyder 802bbea0b6eSIra Snyder /* Remove and free all of the descriptors in the LD queue */ 8039c3a50b7SIra Snyder fsldma_free_desc_list(chan, &chan->ld_pending); 8049c3a50b7SIra Snyder fsldma_free_desc_list(chan, &chan->ld_running); 805f04cd407SIra Snyder chan->idle = true; 806bbea0b6eSIra Snyder 807a1c03319SIra Snyder spin_unlock_irqrestore(&chan->desc_lock, flags); 808968f19aeSIra Snyder return 0; 809968f19aeSIra Snyder 810968f19aeSIra Snyder case DMA_SLAVE_CONFIG: 811968f19aeSIra Snyder config = (struct dma_slave_config *)arg; 812968f19aeSIra Snyder 813968f19aeSIra Snyder /* make sure the channel supports setting burst size */ 814968f19aeSIra Snyder if (!chan->set_request_count) 815968f19aeSIra Snyder return -ENXIO; 816968f19aeSIra Snyder 817968f19aeSIra Snyder /* we set the controller burst size depending on direction */ 818db8196dfSVinod Koul if (config->direction == DMA_MEM_TO_DEV) 819968f19aeSIra Snyder size = config->dst_addr_width * config->dst_maxburst; 820968f19aeSIra Snyder else 821968f19aeSIra Snyder size = config->src_addr_width * config->src_maxburst; 822968f19aeSIra Snyder 823968f19aeSIra Snyder chan->set_request_count(chan, size); 824968f19aeSIra Snyder return 0; 825968f19aeSIra Snyder 826968f19aeSIra Snyder case FSLDMA_EXTERNAL_START: 827968f19aeSIra Snyder 828968f19aeSIra Snyder /* make sure the channel supports external start */ 829968f19aeSIra Snyder if (!chan->toggle_ext_start) 830968f19aeSIra Snyder return -ENXIO; 831968f19aeSIra Snyder 832968f19aeSIra Snyder chan->toggle_ext_start(chan, arg); 833968f19aeSIra Snyder return 0; 834968f19aeSIra Snyder 835968f19aeSIra Snyder default: 836968f19aeSIra Snyder return -ENXIO; 837968f19aeSIra Snyder } 838c3635c78SLinus Walleij 839c3635c78SLinus Walleij return 0; 840bbea0b6eSIra Snyder } 841bbea0b6eSIra Snyder 842bbea0b6eSIra Snyder /** 8439c4d1e7bSIra Snyder * fsldma_cleanup_descriptor - cleanup and free a single link descriptor 844a1c03319SIra Snyder * @chan: Freescale DMA channel 8459c4d1e7bSIra Snyder * @desc: descriptor to cleanup and free 8469c3a50b7SIra Snyder * 8479c4d1e7bSIra Snyder * This function is used on a descriptor which has been executed by the DMA 8489c4d1e7bSIra Snyder * controller. It will run any callbacks, submit any dependencies, and then 8499c4d1e7bSIra Snyder * free the descriptor. 850173acc7cSZhang Wei */ 8519c4d1e7bSIra Snyder static void fsldma_cleanup_descriptor(struct fsldma_chan *chan, 8529c3a50b7SIra Snyder struct fsl_desc_sw *desc) 8539c3a50b7SIra Snyder { 8549c4d1e7bSIra Snyder struct dma_async_tx_descriptor *txd = &desc->async_tx; 8559c4d1e7bSIra Snyder struct device *dev = chan->common.device->dev; 8569c4d1e7bSIra Snyder dma_addr_t src = get_desc_src(chan, desc); 8579c4d1e7bSIra Snyder dma_addr_t dst = get_desc_dst(chan, desc); 8589c4d1e7bSIra Snyder u32 len = get_desc_cnt(chan, desc); 859173acc7cSZhang Wei 860173acc7cSZhang Wei /* Run the link descriptor callback function */ 8619c4d1e7bSIra Snyder if (txd->callback) { 8629c4d1e7bSIra Snyder #ifdef FSL_DMA_LD_DEBUG 8639c4d1e7bSIra Snyder chan_dbg(chan, "LD %p callback\n", desc); 8649c4d1e7bSIra Snyder #endif 8659c4d1e7bSIra Snyder txd->callback(txd->callback_param); 866173acc7cSZhang Wei } 8679c3a50b7SIra Snyder 8689c4d1e7bSIra Snyder /* Run any dependencies */ 8699c4d1e7bSIra Snyder dma_run_dependencies(txd); 8709c4d1e7bSIra Snyder 8719c4d1e7bSIra Snyder /* Unmap the dst buffer, if requested */ 8729c4d1e7bSIra Snyder if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) { 8739c4d1e7bSIra Snyder if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE) 8749c4d1e7bSIra Snyder dma_unmap_single(dev, dst, len, DMA_FROM_DEVICE); 8759c4d1e7bSIra Snyder else 8769c4d1e7bSIra Snyder dma_unmap_page(dev, dst, len, DMA_FROM_DEVICE); 877173acc7cSZhang Wei } 8789c3a50b7SIra Snyder 8799c4d1e7bSIra Snyder /* Unmap the src buffer, if requested */ 8809c4d1e7bSIra Snyder if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) { 8819c4d1e7bSIra Snyder if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE) 8829c4d1e7bSIra Snyder dma_unmap_single(dev, src, len, DMA_TO_DEVICE); 8839c4d1e7bSIra Snyder else 8849c4d1e7bSIra Snyder dma_unmap_page(dev, src, len, DMA_TO_DEVICE); 8859c4d1e7bSIra Snyder } 8869c4d1e7bSIra Snyder 8879c4d1e7bSIra Snyder #ifdef FSL_DMA_LD_DEBUG 8889c4d1e7bSIra Snyder chan_dbg(chan, "LD %p free\n", desc); 8899c4d1e7bSIra Snyder #endif 8909c4d1e7bSIra Snyder dma_pool_free(chan->desc_pool, desc, txd->phys); 891173acc7cSZhang Wei } 892173acc7cSZhang Wei 893173acc7cSZhang Wei /** 8949c3a50b7SIra Snyder * fsl_chan_xfer_ld_queue - transfer any pending transactions 895a1c03319SIra Snyder * @chan : Freescale DMA channel 8969c3a50b7SIra Snyder * 897f04cd407SIra Snyder * HARDWARE STATE: idle 898dc8d4091SIra Snyder * LOCKING: must hold chan->desc_lock 899173acc7cSZhang Wei */ 900a1c03319SIra Snyder static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan) 901173acc7cSZhang Wei { 9029c3a50b7SIra Snyder struct fsl_desc_sw *desc; 903138ef018SIra Snyder 9049c3a50b7SIra Snyder /* 9059c3a50b7SIra Snyder * If the list of pending descriptors is empty, then we 9069c3a50b7SIra Snyder * don't need to do any work at all 9079c3a50b7SIra Snyder */ 9089c3a50b7SIra Snyder if (list_empty(&chan->ld_pending)) { 909b158471eSIra Snyder chan_dbg(chan, "no pending LDs\n"); 910dc8d4091SIra Snyder return; 9119c3a50b7SIra Snyder } 912173acc7cSZhang Wei 9139c3a50b7SIra Snyder /* 914f04cd407SIra Snyder * The DMA controller is not idle, which means that the interrupt 915f04cd407SIra Snyder * handler will start any queued transactions when it runs after 916f04cd407SIra Snyder * this transaction finishes 9179c3a50b7SIra Snyder */ 918f04cd407SIra Snyder if (!chan->idle) { 919b158471eSIra Snyder chan_dbg(chan, "DMA controller still busy\n"); 920dc8d4091SIra Snyder return; 9219c3a50b7SIra Snyder } 9229c3a50b7SIra Snyder 9239c3a50b7SIra Snyder /* 9249c3a50b7SIra Snyder * If there are some link descriptors which have not been 9259c3a50b7SIra Snyder * transferred, we need to start the controller 926173acc7cSZhang Wei */ 927173acc7cSZhang Wei 9289c3a50b7SIra Snyder /* 9299c3a50b7SIra Snyder * Move all elements from the queue of pending transactions 9309c3a50b7SIra Snyder * onto the list of running transactions 9319c3a50b7SIra Snyder */ 932f04cd407SIra Snyder chan_dbg(chan, "idle, starting controller\n"); 9339c3a50b7SIra Snyder desc = list_first_entry(&chan->ld_pending, struct fsl_desc_sw, node); 9349c3a50b7SIra Snyder list_splice_tail_init(&chan->ld_pending, &chan->ld_running); 935173acc7cSZhang Wei 9369c3a50b7SIra Snyder /* 937f04cd407SIra Snyder * The 85xx DMA controller doesn't clear the channel start bit 938f04cd407SIra Snyder * automatically at the end of a transfer. Therefore we must clear 939f04cd407SIra Snyder * it in software before starting the transfer. 940f04cd407SIra Snyder */ 941f04cd407SIra Snyder if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) { 942f04cd407SIra Snyder u32 mode; 943f04cd407SIra Snyder 944f04cd407SIra Snyder mode = DMA_IN(chan, &chan->regs->mr, 32); 945f04cd407SIra Snyder mode &= ~FSL_DMA_MR_CS; 946f04cd407SIra Snyder DMA_OUT(chan, &chan->regs->mr, mode, 32); 947f04cd407SIra Snyder } 948f04cd407SIra Snyder 949f04cd407SIra Snyder /* 9509c3a50b7SIra Snyder * Program the descriptor's address into the DMA controller, 9519c3a50b7SIra Snyder * then start the DMA transaction 9529c3a50b7SIra Snyder */ 9539c3a50b7SIra Snyder set_cdar(chan, desc->async_tx.phys); 954f04cd407SIra Snyder get_cdar(chan); 955138ef018SIra Snyder 956173acc7cSZhang Wei dma_start(chan); 957f04cd407SIra Snyder chan->idle = false; 958173acc7cSZhang Wei } 959173acc7cSZhang Wei 960173acc7cSZhang Wei /** 961173acc7cSZhang Wei * fsl_dma_memcpy_issue_pending - Issue the DMA start command 962a1c03319SIra Snyder * @chan : Freescale DMA channel 963173acc7cSZhang Wei */ 964a1c03319SIra Snyder static void fsl_dma_memcpy_issue_pending(struct dma_chan *dchan) 965173acc7cSZhang Wei { 966a1c03319SIra Snyder struct fsldma_chan *chan = to_fsl_chan(dchan); 967dc8d4091SIra Snyder unsigned long flags; 968dc8d4091SIra Snyder 969dc8d4091SIra Snyder spin_lock_irqsave(&chan->desc_lock, flags); 970a1c03319SIra Snyder fsl_chan_xfer_ld_queue(chan); 971dc8d4091SIra Snyder spin_unlock_irqrestore(&chan->desc_lock, flags); 972173acc7cSZhang Wei } 973173acc7cSZhang Wei 974173acc7cSZhang Wei /** 97507934481SLinus Walleij * fsl_tx_status - Determine the DMA status 976a1c03319SIra Snyder * @chan : Freescale DMA channel 977173acc7cSZhang Wei */ 97807934481SLinus Walleij static enum dma_status fsl_tx_status(struct dma_chan *dchan, 979173acc7cSZhang Wei dma_cookie_t cookie, 98007934481SLinus Walleij struct dma_tx_state *txstate) 981173acc7cSZhang Wei { 982a1c03319SIra Snyder struct fsldma_chan *chan = to_fsl_chan(dchan); 98396a2af41SRussell King - ARM Linux enum dma_status ret; 984f04cd407SIra Snyder unsigned long flags; 985173acc7cSZhang Wei 986f04cd407SIra Snyder spin_lock_irqsave(&chan->desc_lock, flags); 98796a2af41SRussell King - ARM Linux ret = dma_cookie_status(dchan, cookie, txstate); 988f04cd407SIra Snyder spin_unlock_irqrestore(&chan->desc_lock, flags); 989173acc7cSZhang Wei 99096a2af41SRussell King - ARM Linux return ret; 991173acc7cSZhang Wei } 992173acc7cSZhang Wei 993d3f620b2SIra Snyder /*----------------------------------------------------------------------------*/ 994d3f620b2SIra Snyder /* Interrupt Handling */ 995d3f620b2SIra Snyder /*----------------------------------------------------------------------------*/ 996d3f620b2SIra Snyder 997e7a29151SIra Snyder static irqreturn_t fsldma_chan_irq(int irq, void *data) 998173acc7cSZhang Wei { 999a1c03319SIra Snyder struct fsldma_chan *chan = data; 1000a1c03319SIra Snyder u32 stat; 1001173acc7cSZhang Wei 10029c3a50b7SIra Snyder /* save and clear the status register */ 1003a1c03319SIra Snyder stat = get_sr(chan); 10049c3a50b7SIra Snyder set_sr(chan, stat); 1005b158471eSIra Snyder chan_dbg(chan, "irq: stat = 0x%x\n", stat); 1006173acc7cSZhang Wei 1007f04cd407SIra Snyder /* check that this was really our device */ 1008173acc7cSZhang Wei stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH); 1009173acc7cSZhang Wei if (!stat) 1010173acc7cSZhang Wei return IRQ_NONE; 1011173acc7cSZhang Wei 1012173acc7cSZhang Wei if (stat & FSL_DMA_SR_TE) 1013b158471eSIra Snyder chan_err(chan, "Transfer Error!\n"); 1014173acc7cSZhang Wei 10159c3a50b7SIra Snyder /* 10169c3a50b7SIra Snyder * Programming Error 1017f79abb62SZhang Wei * The DMA_INTERRUPT async_tx is a NULL transfer, which will 1018d73111c6SMasanari Iida * trigger a PE interrupt. 1019f79abb62SZhang Wei */ 1020f79abb62SZhang Wei if (stat & FSL_DMA_SR_PE) { 1021b158471eSIra Snyder chan_dbg(chan, "irq: Programming Error INT\n"); 1022f79abb62SZhang Wei stat &= ~FSL_DMA_SR_PE; 1023f04cd407SIra Snyder if (get_bcr(chan) != 0) 1024f04cd407SIra Snyder chan_err(chan, "Programming Error!\n"); 10251c62979eSZhang Wei } 10261c62979eSZhang Wei 10279c3a50b7SIra Snyder /* 10289c3a50b7SIra Snyder * For MPC8349, EOCDI event need to update cookie 10291c62979eSZhang Wei * and start the next transfer if it exist. 10301c62979eSZhang Wei */ 10311c62979eSZhang Wei if (stat & FSL_DMA_SR_EOCDI) { 1032b158471eSIra Snyder chan_dbg(chan, "irq: End-of-Chain link INT\n"); 10331c62979eSZhang Wei stat &= ~FSL_DMA_SR_EOCDI; 1034173acc7cSZhang Wei } 1035173acc7cSZhang Wei 10369c3a50b7SIra Snyder /* 10379c3a50b7SIra Snyder * If it current transfer is the end-of-transfer, 1038173acc7cSZhang Wei * we should clear the Channel Start bit for 1039173acc7cSZhang Wei * prepare next transfer. 1040173acc7cSZhang Wei */ 10411c62979eSZhang Wei if (stat & FSL_DMA_SR_EOLNI) { 1042b158471eSIra Snyder chan_dbg(chan, "irq: End-of-link INT\n"); 1043173acc7cSZhang Wei stat &= ~FSL_DMA_SR_EOLNI; 1044173acc7cSZhang Wei } 1045173acc7cSZhang Wei 1046f04cd407SIra Snyder /* check that the DMA controller is really idle */ 1047f04cd407SIra Snyder if (!dma_is_idle(chan)) 1048f04cd407SIra Snyder chan_err(chan, "irq: controller not idle!\n"); 1049173acc7cSZhang Wei 1050f04cd407SIra Snyder /* check that we handled all of the bits */ 1051f04cd407SIra Snyder if (stat) 1052f04cd407SIra Snyder chan_err(chan, "irq: unhandled sr 0x%08x\n", stat); 1053f04cd407SIra Snyder 1054f04cd407SIra Snyder /* 1055f04cd407SIra Snyder * Schedule the tasklet to handle all cleanup of the current 1056f04cd407SIra Snyder * transaction. It will start a new transaction if there is 1057f04cd407SIra Snyder * one pending. 1058f04cd407SIra Snyder */ 1059a1c03319SIra Snyder tasklet_schedule(&chan->tasklet); 1060f04cd407SIra Snyder chan_dbg(chan, "irq: Exit\n"); 1061173acc7cSZhang Wei return IRQ_HANDLED; 1062173acc7cSZhang Wei } 1063173acc7cSZhang Wei 1064173acc7cSZhang Wei static void dma_do_tasklet(unsigned long data) 1065173acc7cSZhang Wei { 1066a1c03319SIra Snyder struct fsldma_chan *chan = (struct fsldma_chan *)data; 1067dc8d4091SIra Snyder struct fsl_desc_sw *desc, *_desc; 1068dc8d4091SIra Snyder LIST_HEAD(ld_cleanup); 1069f04cd407SIra Snyder unsigned long flags; 1070f04cd407SIra Snyder 1071f04cd407SIra Snyder chan_dbg(chan, "tasklet entry\n"); 1072f04cd407SIra Snyder 1073f04cd407SIra Snyder spin_lock_irqsave(&chan->desc_lock, flags); 1074dc8d4091SIra Snyder 1075dc8d4091SIra Snyder /* update the cookie if we have some descriptors to cleanup */ 1076dc8d4091SIra Snyder if (!list_empty(&chan->ld_running)) { 1077dc8d4091SIra Snyder dma_cookie_t cookie; 1078dc8d4091SIra Snyder 1079dc8d4091SIra Snyder desc = to_fsl_desc(chan->ld_running.prev); 1080dc8d4091SIra Snyder cookie = desc->async_tx.cookie; 1081f7fbce07SRussell King - ARM Linux dma_cookie_complete(&desc->async_tx); 1082dc8d4091SIra Snyder 1083dc8d4091SIra Snyder chan_dbg(chan, "completed_cookie=%d\n", cookie); 1084dc8d4091SIra Snyder } 1085dc8d4091SIra Snyder 1086dc8d4091SIra Snyder /* 1087dc8d4091SIra Snyder * move the descriptors to a temporary list so we can drop the lock 1088dc8d4091SIra Snyder * during the entire cleanup operation 1089dc8d4091SIra Snyder */ 1090dc8d4091SIra Snyder list_splice_tail_init(&chan->ld_running, &ld_cleanup); 1091dc8d4091SIra Snyder 1092dc8d4091SIra Snyder /* the hardware is now idle and ready for more */ 1093f04cd407SIra Snyder chan->idle = true; 1094dc8d4091SIra Snyder 1095dc8d4091SIra Snyder /* 1096dc8d4091SIra Snyder * Start any pending transactions automatically 1097dc8d4091SIra Snyder * 1098dc8d4091SIra Snyder * In the ideal case, we keep the DMA controller busy while we go 1099dc8d4091SIra Snyder * ahead and free the descriptors below. 1100dc8d4091SIra Snyder */ 1101dc8d4091SIra Snyder fsl_chan_xfer_ld_queue(chan); 1102f04cd407SIra Snyder spin_unlock_irqrestore(&chan->desc_lock, flags); 1103f04cd407SIra Snyder 1104dc8d4091SIra Snyder /* Run the callback for each descriptor, in order */ 1105dc8d4091SIra Snyder list_for_each_entry_safe(desc, _desc, &ld_cleanup, node) { 1106dc8d4091SIra Snyder 1107dc8d4091SIra Snyder /* Remove from the list of transactions */ 1108dc8d4091SIra Snyder list_del(&desc->node); 1109dc8d4091SIra Snyder 1110dc8d4091SIra Snyder /* Run all cleanup for this descriptor */ 1111dc8d4091SIra Snyder fsldma_cleanup_descriptor(chan, desc); 1112dc8d4091SIra Snyder } 1113dc8d4091SIra Snyder 1114f04cd407SIra Snyder chan_dbg(chan, "tasklet exit\n"); 1115173acc7cSZhang Wei } 1116173acc7cSZhang Wei 1117d3f620b2SIra Snyder static irqreturn_t fsldma_ctrl_irq(int irq, void *data) 1118d3f620b2SIra Snyder { 1119d3f620b2SIra Snyder struct fsldma_device *fdev = data; 1120d3f620b2SIra Snyder struct fsldma_chan *chan; 1121d3f620b2SIra Snyder unsigned int handled = 0; 1122d3f620b2SIra Snyder u32 gsr, mask; 1123d3f620b2SIra Snyder int i; 1124d3f620b2SIra Snyder 1125d3f620b2SIra Snyder gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->regs) 1126d3f620b2SIra Snyder : in_le32(fdev->regs); 1127d3f620b2SIra Snyder mask = 0xff000000; 1128d3f620b2SIra Snyder dev_dbg(fdev->dev, "IRQ: gsr 0x%.8x\n", gsr); 1129d3f620b2SIra Snyder 1130d3f620b2SIra Snyder for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { 1131d3f620b2SIra Snyder chan = fdev->chan[i]; 1132d3f620b2SIra Snyder if (!chan) 1133d3f620b2SIra Snyder continue; 1134d3f620b2SIra Snyder 1135d3f620b2SIra Snyder if (gsr & mask) { 1136d3f620b2SIra Snyder dev_dbg(fdev->dev, "IRQ: chan %d\n", chan->id); 1137d3f620b2SIra Snyder fsldma_chan_irq(irq, chan); 1138d3f620b2SIra Snyder handled++; 1139d3f620b2SIra Snyder } 1140d3f620b2SIra Snyder 1141d3f620b2SIra Snyder gsr &= ~mask; 1142d3f620b2SIra Snyder mask >>= 8; 1143d3f620b2SIra Snyder } 1144d3f620b2SIra Snyder 1145d3f620b2SIra Snyder return IRQ_RETVAL(handled); 1146d3f620b2SIra Snyder } 1147d3f620b2SIra Snyder 1148d3f620b2SIra Snyder static void fsldma_free_irqs(struct fsldma_device *fdev) 1149d3f620b2SIra Snyder { 1150d3f620b2SIra Snyder struct fsldma_chan *chan; 1151d3f620b2SIra Snyder int i; 1152d3f620b2SIra Snyder 1153d3f620b2SIra Snyder if (fdev->irq != NO_IRQ) { 1154d3f620b2SIra Snyder dev_dbg(fdev->dev, "free per-controller IRQ\n"); 1155d3f620b2SIra Snyder free_irq(fdev->irq, fdev); 1156d3f620b2SIra Snyder return; 1157d3f620b2SIra Snyder } 1158d3f620b2SIra Snyder 1159d3f620b2SIra Snyder for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { 1160d3f620b2SIra Snyder chan = fdev->chan[i]; 1161d3f620b2SIra Snyder if (chan && chan->irq != NO_IRQ) { 1162b158471eSIra Snyder chan_dbg(chan, "free per-channel IRQ\n"); 1163d3f620b2SIra Snyder free_irq(chan->irq, chan); 1164d3f620b2SIra Snyder } 1165d3f620b2SIra Snyder } 1166d3f620b2SIra Snyder } 1167d3f620b2SIra Snyder 1168d3f620b2SIra Snyder static int fsldma_request_irqs(struct fsldma_device *fdev) 1169d3f620b2SIra Snyder { 1170d3f620b2SIra Snyder struct fsldma_chan *chan; 1171d3f620b2SIra Snyder int ret; 1172d3f620b2SIra Snyder int i; 1173d3f620b2SIra Snyder 1174d3f620b2SIra Snyder /* if we have a per-controller IRQ, use that */ 1175d3f620b2SIra Snyder if (fdev->irq != NO_IRQ) { 1176d3f620b2SIra Snyder dev_dbg(fdev->dev, "request per-controller IRQ\n"); 1177d3f620b2SIra Snyder ret = request_irq(fdev->irq, fsldma_ctrl_irq, IRQF_SHARED, 1178d3f620b2SIra Snyder "fsldma-controller", fdev); 1179d3f620b2SIra Snyder return ret; 1180d3f620b2SIra Snyder } 1181d3f620b2SIra Snyder 1182d3f620b2SIra Snyder /* no per-controller IRQ, use the per-channel IRQs */ 1183d3f620b2SIra Snyder for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { 1184d3f620b2SIra Snyder chan = fdev->chan[i]; 1185d3f620b2SIra Snyder if (!chan) 1186d3f620b2SIra Snyder continue; 1187d3f620b2SIra Snyder 1188d3f620b2SIra Snyder if (chan->irq == NO_IRQ) { 1189b158471eSIra Snyder chan_err(chan, "interrupts property missing in device tree\n"); 1190d3f620b2SIra Snyder ret = -ENODEV; 1191d3f620b2SIra Snyder goto out_unwind; 1192d3f620b2SIra Snyder } 1193d3f620b2SIra Snyder 1194b158471eSIra Snyder chan_dbg(chan, "request per-channel IRQ\n"); 1195d3f620b2SIra Snyder ret = request_irq(chan->irq, fsldma_chan_irq, IRQF_SHARED, 1196d3f620b2SIra Snyder "fsldma-chan", chan); 1197d3f620b2SIra Snyder if (ret) { 1198b158471eSIra Snyder chan_err(chan, "unable to request per-channel IRQ\n"); 1199d3f620b2SIra Snyder goto out_unwind; 1200d3f620b2SIra Snyder } 1201d3f620b2SIra Snyder } 1202d3f620b2SIra Snyder 1203d3f620b2SIra Snyder return 0; 1204d3f620b2SIra Snyder 1205d3f620b2SIra Snyder out_unwind: 1206d3f620b2SIra Snyder for (/* none */; i >= 0; i--) { 1207d3f620b2SIra Snyder chan = fdev->chan[i]; 1208d3f620b2SIra Snyder if (!chan) 1209d3f620b2SIra Snyder continue; 1210d3f620b2SIra Snyder 1211d3f620b2SIra Snyder if (chan->irq == NO_IRQ) 1212d3f620b2SIra Snyder continue; 1213d3f620b2SIra Snyder 1214d3f620b2SIra Snyder free_irq(chan->irq, chan); 1215d3f620b2SIra Snyder } 1216d3f620b2SIra Snyder 1217d3f620b2SIra Snyder return ret; 1218d3f620b2SIra Snyder } 1219d3f620b2SIra Snyder 1220a4f56d4bSIra Snyder /*----------------------------------------------------------------------------*/ 1221a4f56d4bSIra Snyder /* OpenFirmware Subsystem */ 1222a4f56d4bSIra Snyder /*----------------------------------------------------------------------------*/ 1223a4f56d4bSIra Snyder 1224463a1f8bSBill Pemberton static int fsl_dma_chan_probe(struct fsldma_device *fdev, 122577cd62e8STimur Tabi struct device_node *node, u32 feature, const char *compatible) 1226173acc7cSZhang Wei { 1227a1c03319SIra Snyder struct fsldma_chan *chan; 12284ce0e953SIra Snyder struct resource res; 1229173acc7cSZhang Wei int err; 1230173acc7cSZhang Wei 1231173acc7cSZhang Wei /* alloc channel */ 1232a1c03319SIra Snyder chan = kzalloc(sizeof(*chan), GFP_KERNEL); 1233a1c03319SIra Snyder if (!chan) { 1234e7a29151SIra Snyder dev_err(fdev->dev, "no free memory for DMA channels!\n"); 1235e7a29151SIra Snyder err = -ENOMEM; 1236e7a29151SIra Snyder goto out_return; 1237173acc7cSZhang Wei } 1238173acc7cSZhang Wei 1239e7a29151SIra Snyder /* ioremap registers for use */ 1240a1c03319SIra Snyder chan->regs = of_iomap(node, 0); 1241a1c03319SIra Snyder if (!chan->regs) { 1242e7a29151SIra Snyder dev_err(fdev->dev, "unable to ioremap registers\n"); 1243e7a29151SIra Snyder err = -ENOMEM; 1244a1c03319SIra Snyder goto out_free_chan; 1245e7a29151SIra Snyder } 1246e7a29151SIra Snyder 12474ce0e953SIra Snyder err = of_address_to_resource(node, 0, &res); 1248173acc7cSZhang Wei if (err) { 1249e7a29151SIra Snyder dev_err(fdev->dev, "unable to find 'reg' property\n"); 1250e7a29151SIra Snyder goto out_iounmap_regs; 1251173acc7cSZhang Wei } 1252173acc7cSZhang Wei 1253a1c03319SIra Snyder chan->feature = feature; 1254173acc7cSZhang Wei if (!fdev->feature) 1255a1c03319SIra Snyder fdev->feature = chan->feature; 1256173acc7cSZhang Wei 1257e7a29151SIra Snyder /* 1258e7a29151SIra Snyder * If the DMA device's feature is different than the feature 1259e7a29151SIra Snyder * of its channels, report the bug 1260173acc7cSZhang Wei */ 1261a1c03319SIra Snyder WARN_ON(fdev->feature != chan->feature); 1262173acc7cSZhang Wei 1263a1c03319SIra Snyder chan->dev = fdev->dev; 1264a1c03319SIra Snyder chan->id = ((res.start - 0x100) & 0xfff) >> 7; 1265a1c03319SIra Snyder if (chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) { 1266e7a29151SIra Snyder dev_err(fdev->dev, "too many channels for device\n"); 1267173acc7cSZhang Wei err = -EINVAL; 1268e7a29151SIra Snyder goto out_iounmap_regs; 1269173acc7cSZhang Wei } 1270173acc7cSZhang Wei 1271a1c03319SIra Snyder fdev->chan[chan->id] = chan; 1272a1c03319SIra Snyder tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan); 1273b158471eSIra Snyder snprintf(chan->name, sizeof(chan->name), "chan%d", chan->id); 1274e7a29151SIra Snyder 1275e7a29151SIra Snyder /* Initialize the channel */ 1276a1c03319SIra Snyder dma_init(chan); 1277173acc7cSZhang Wei 1278173acc7cSZhang Wei /* Clear cdar registers */ 1279a1c03319SIra Snyder set_cdar(chan, 0); 1280173acc7cSZhang Wei 1281a1c03319SIra Snyder switch (chan->feature & FSL_DMA_IP_MASK) { 1282173acc7cSZhang Wei case FSL_DMA_IP_85XX: 1283a1c03319SIra Snyder chan->toggle_ext_pause = fsl_chan_toggle_ext_pause; 1284173acc7cSZhang Wei case FSL_DMA_IP_83XX: 1285a1c03319SIra Snyder chan->toggle_ext_start = fsl_chan_toggle_ext_start; 1286a1c03319SIra Snyder chan->set_src_loop_size = fsl_chan_set_src_loop_size; 1287a1c03319SIra Snyder chan->set_dst_loop_size = fsl_chan_set_dst_loop_size; 1288a1c03319SIra Snyder chan->set_request_count = fsl_chan_set_request_count; 1289173acc7cSZhang Wei } 1290173acc7cSZhang Wei 1291a1c03319SIra Snyder spin_lock_init(&chan->desc_lock); 12929c3a50b7SIra Snyder INIT_LIST_HEAD(&chan->ld_pending); 12939c3a50b7SIra Snyder INIT_LIST_HEAD(&chan->ld_running); 1294f04cd407SIra Snyder chan->idle = true; 1295173acc7cSZhang Wei 1296a1c03319SIra Snyder chan->common.device = &fdev->common; 12978ac69546SRussell King - ARM Linux dma_cookie_init(&chan->common); 1298173acc7cSZhang Wei 1299d3f620b2SIra Snyder /* find the IRQ line, if it exists in the device tree */ 1300a1c03319SIra Snyder chan->irq = irq_of_parse_and_map(node, 0); 1301d3f620b2SIra Snyder 1302173acc7cSZhang Wei /* Add the channel to DMA device channel list */ 1303a1c03319SIra Snyder list_add_tail(&chan->common.device_node, &fdev->common.channels); 1304173acc7cSZhang Wei fdev->common.chancnt++; 1305173acc7cSZhang Wei 1306a1c03319SIra Snyder dev_info(fdev->dev, "#%d (%s), irq %d\n", chan->id, compatible, 1307a1c03319SIra Snyder chan->irq != NO_IRQ ? chan->irq : fdev->irq); 1308173acc7cSZhang Wei 1309173acc7cSZhang Wei return 0; 131051ee87f2SLi Yang 1311e7a29151SIra Snyder out_iounmap_regs: 1312a1c03319SIra Snyder iounmap(chan->regs); 1313a1c03319SIra Snyder out_free_chan: 1314a1c03319SIra Snyder kfree(chan); 1315e7a29151SIra Snyder out_return: 1316173acc7cSZhang Wei return err; 1317173acc7cSZhang Wei } 1318173acc7cSZhang Wei 1319a1c03319SIra Snyder static void fsl_dma_chan_remove(struct fsldma_chan *chan) 1320173acc7cSZhang Wei { 1321a1c03319SIra Snyder irq_dispose_mapping(chan->irq); 1322a1c03319SIra Snyder list_del(&chan->common.device_node); 1323a1c03319SIra Snyder iounmap(chan->regs); 1324a1c03319SIra Snyder kfree(chan); 1325173acc7cSZhang Wei } 1326173acc7cSZhang Wei 1327463a1f8bSBill Pemberton static int fsldma_of_probe(struct platform_device *op) 1328173acc7cSZhang Wei { 1329a4f56d4bSIra Snyder struct fsldma_device *fdev; 133077cd62e8STimur Tabi struct device_node *child; 1331e7a29151SIra Snyder int err; 1332173acc7cSZhang Wei 1333a4f56d4bSIra Snyder fdev = kzalloc(sizeof(*fdev), GFP_KERNEL); 1334173acc7cSZhang Wei if (!fdev) { 1335e7a29151SIra Snyder dev_err(&op->dev, "No enough memory for 'priv'\n"); 1336e7a29151SIra Snyder err = -ENOMEM; 1337e7a29151SIra Snyder goto out_return; 1338173acc7cSZhang Wei } 1339e7a29151SIra Snyder 1340e7a29151SIra Snyder fdev->dev = &op->dev; 1341173acc7cSZhang Wei INIT_LIST_HEAD(&fdev->common.channels); 1342173acc7cSZhang Wei 1343e7a29151SIra Snyder /* ioremap the registers for use */ 134461c7a080SGrant Likely fdev->regs = of_iomap(op->dev.of_node, 0); 1345e7a29151SIra Snyder if (!fdev->regs) { 1346e7a29151SIra Snyder dev_err(&op->dev, "unable to ioremap registers\n"); 1347e7a29151SIra Snyder err = -ENOMEM; 1348e7a29151SIra Snyder goto out_free_fdev; 1349173acc7cSZhang Wei } 1350173acc7cSZhang Wei 1351d3f620b2SIra Snyder /* map the channel IRQ if it exists, but don't hookup the handler yet */ 135261c7a080SGrant Likely fdev->irq = irq_of_parse_and_map(op->dev.of_node, 0); 1353d3f620b2SIra Snyder 1354173acc7cSZhang Wei dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask); 1355173acc7cSZhang Wei dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask); 1356c1433041SIra Snyder dma_cap_set(DMA_SG, fdev->common.cap_mask); 1357bbea0b6eSIra Snyder dma_cap_set(DMA_SLAVE, fdev->common.cap_mask); 1358173acc7cSZhang Wei fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources; 1359173acc7cSZhang Wei fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources; 13602187c269SZhang Wei fdev->common.device_prep_dma_interrupt = fsl_dma_prep_interrupt; 1361173acc7cSZhang Wei fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy; 1362c1433041SIra Snyder fdev->common.device_prep_dma_sg = fsl_dma_prep_sg; 136307934481SLinus Walleij fdev->common.device_tx_status = fsl_tx_status; 1364173acc7cSZhang Wei fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending; 1365bbea0b6eSIra Snyder fdev->common.device_prep_slave_sg = fsl_dma_prep_slave_sg; 1366c3635c78SLinus Walleij fdev->common.device_control = fsl_dma_device_control; 1367e7a29151SIra Snyder fdev->common.dev = &op->dev; 1368173acc7cSZhang Wei 1369e2c8e425SLi Yang dma_set_mask(&(op->dev), DMA_BIT_MASK(36)); 1370e2c8e425SLi Yang 1371e7a29151SIra Snyder dev_set_drvdata(&op->dev, fdev); 137277cd62e8STimur Tabi 1373e7a29151SIra Snyder /* 1374e7a29151SIra Snyder * We cannot use of_platform_bus_probe() because there is no 1375e7a29151SIra Snyder * of_platform_bus_remove(). Instead, we manually instantiate every DMA 137677cd62e8STimur Tabi * channel object. 137777cd62e8STimur Tabi */ 137861c7a080SGrant Likely for_each_child_of_node(op->dev.of_node, child) { 1379e7a29151SIra Snyder if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) { 138077cd62e8STimur Tabi fsl_dma_chan_probe(fdev, child, 138177cd62e8STimur Tabi FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN, 138277cd62e8STimur Tabi "fsl,eloplus-dma-channel"); 1383e7a29151SIra Snyder } 1384e7a29151SIra Snyder 1385e7a29151SIra Snyder if (of_device_is_compatible(child, "fsl,elo-dma-channel")) { 138677cd62e8STimur Tabi fsl_dma_chan_probe(fdev, child, 138777cd62e8STimur Tabi FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN, 138877cd62e8STimur Tabi "fsl,elo-dma-channel"); 138977cd62e8STimur Tabi } 1390e7a29151SIra Snyder } 1391173acc7cSZhang Wei 1392d3f620b2SIra Snyder /* 1393d3f620b2SIra Snyder * Hookup the IRQ handler(s) 1394d3f620b2SIra Snyder * 1395d3f620b2SIra Snyder * If we have a per-controller interrupt, we prefer that to the 1396d3f620b2SIra Snyder * per-channel interrupts to reduce the number of shared interrupt 1397d3f620b2SIra Snyder * handlers on the same IRQ line 1398d3f620b2SIra Snyder */ 1399d3f620b2SIra Snyder err = fsldma_request_irqs(fdev); 1400d3f620b2SIra Snyder if (err) { 1401d3f620b2SIra Snyder dev_err(fdev->dev, "unable to request IRQs\n"); 1402d3f620b2SIra Snyder goto out_free_fdev; 1403d3f620b2SIra Snyder } 1404d3f620b2SIra Snyder 1405173acc7cSZhang Wei dma_async_device_register(&fdev->common); 1406173acc7cSZhang Wei return 0; 1407173acc7cSZhang Wei 1408e7a29151SIra Snyder out_free_fdev: 1409d3f620b2SIra Snyder irq_dispose_mapping(fdev->irq); 1410173acc7cSZhang Wei kfree(fdev); 1411e7a29151SIra Snyder out_return: 1412173acc7cSZhang Wei return err; 1413173acc7cSZhang Wei } 1414173acc7cSZhang Wei 14152dc11581SGrant Likely static int fsldma_of_remove(struct platform_device *op) 141677cd62e8STimur Tabi { 1417a4f56d4bSIra Snyder struct fsldma_device *fdev; 141877cd62e8STimur Tabi unsigned int i; 141977cd62e8STimur Tabi 1420e7a29151SIra Snyder fdev = dev_get_drvdata(&op->dev); 142177cd62e8STimur Tabi dma_async_device_unregister(&fdev->common); 142277cd62e8STimur Tabi 1423d3f620b2SIra Snyder fsldma_free_irqs(fdev); 1424d3f620b2SIra Snyder 1425e7a29151SIra Snyder for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { 142677cd62e8STimur Tabi if (fdev->chan[i]) 142777cd62e8STimur Tabi fsl_dma_chan_remove(fdev->chan[i]); 1428e7a29151SIra Snyder } 142977cd62e8STimur Tabi 1430e7a29151SIra Snyder iounmap(fdev->regs); 1431e7a29151SIra Snyder dev_set_drvdata(&op->dev, NULL); 143277cd62e8STimur Tabi kfree(fdev); 143377cd62e8STimur Tabi 143477cd62e8STimur Tabi return 0; 143577cd62e8STimur Tabi } 143677cd62e8STimur Tabi 14374b1cf1faSMárton Németh static const struct of_device_id fsldma_of_ids[] = { 1438049c9d45SKumar Gala { .compatible = "fsl,eloplus-dma", }, 1439049c9d45SKumar Gala { .compatible = "fsl,elo-dma", }, 1440173acc7cSZhang Wei {} 1441173acc7cSZhang Wei }; 1442173acc7cSZhang Wei 14438faa7cf8SIra W. Snyder static struct platform_driver fsldma_of_driver = { 14444018294bSGrant Likely .driver = { 144577cd62e8STimur Tabi .name = "fsl-elo-dma", 14464018294bSGrant Likely .owner = THIS_MODULE, 14474018294bSGrant Likely .of_match_table = fsldma_of_ids, 14484018294bSGrant Likely }, 1449a4f56d4bSIra Snyder .probe = fsldma_of_probe, 1450a4f56d4bSIra Snyder .remove = fsldma_of_remove, 1451173acc7cSZhang Wei }; 1452173acc7cSZhang Wei 1453a4f56d4bSIra Snyder /*----------------------------------------------------------------------------*/ 1454a4f56d4bSIra Snyder /* Module Init / Exit */ 1455a4f56d4bSIra Snyder /*----------------------------------------------------------------------------*/ 1456a4f56d4bSIra Snyder 1457a4f56d4bSIra Snyder static __init int fsldma_init(void) 1458173acc7cSZhang Wei { 145977cd62e8STimur Tabi pr_info("Freescale Elo / Elo Plus DMA driver\n"); 146000006124SGrant Likely return platform_driver_register(&fsldma_of_driver); 1461173acc7cSZhang Wei } 1462173acc7cSZhang Wei 1463a4f56d4bSIra Snyder static void __exit fsldma_exit(void) 146477cd62e8STimur Tabi { 146500006124SGrant Likely platform_driver_unregister(&fsldma_of_driver); 146677cd62e8STimur Tabi } 146777cd62e8STimur Tabi 1468a4f56d4bSIra Snyder subsys_initcall(fsldma_init); 1469a4f56d4bSIra Snyder module_exit(fsldma_exit); 147077cd62e8STimur Tabi 147177cd62e8STimur Tabi MODULE_DESCRIPTION("Freescale Elo / Elo Plus DMA driver"); 147277cd62e8STimur Tabi MODULE_LICENSE("GPL"); 1473