1173acc7cSZhang Wei /* 2173acc7cSZhang Wei * Freescale MPC85xx, MPC83xx DMA Engine support 3173acc7cSZhang Wei * 4173acc7cSZhang Wei * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved. 5173acc7cSZhang Wei * 6173acc7cSZhang Wei * Author: 7173acc7cSZhang Wei * Zhang Wei <wei.zhang@freescale.com>, Jul 2007 8173acc7cSZhang Wei * Ebony Zhu <ebony.zhu@freescale.com>, May 2007 9173acc7cSZhang Wei * 10173acc7cSZhang Wei * Description: 11173acc7cSZhang Wei * DMA engine driver for Freescale MPC8540 DMA controller, which is 12173acc7cSZhang Wei * also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc. 13173acc7cSZhang Wei * The support for MPC8349 DMA contorller is also added. 14173acc7cSZhang Wei * 15a7aea373SIra W. Snyder * This driver instructs the DMA controller to issue the PCI Read Multiple 16a7aea373SIra W. Snyder * command for PCI read operations, instead of using the default PCI Read Line 17a7aea373SIra W. Snyder * command. Please be aware that this setting may result in read pre-fetching 18a7aea373SIra W. Snyder * on some platforms. 19a7aea373SIra W. Snyder * 20173acc7cSZhang Wei * This is free software; you can redistribute it and/or modify 21173acc7cSZhang Wei * it under the terms of the GNU General Public License as published by 22173acc7cSZhang Wei * the Free Software Foundation; either version 2 of the License, or 23173acc7cSZhang Wei * (at your option) any later version. 24173acc7cSZhang Wei * 25173acc7cSZhang Wei */ 26173acc7cSZhang Wei 27173acc7cSZhang Wei #include <linux/init.h> 28173acc7cSZhang Wei #include <linux/module.h> 29173acc7cSZhang Wei #include <linux/pci.h> 305a0e3ad6STejun Heo #include <linux/slab.h> 31173acc7cSZhang Wei #include <linux/interrupt.h> 32173acc7cSZhang Wei #include <linux/dmaengine.h> 33173acc7cSZhang Wei #include <linux/delay.h> 34173acc7cSZhang Wei #include <linux/dma-mapping.h> 35173acc7cSZhang Wei #include <linux/dmapool.h> 36173acc7cSZhang Wei #include <linux/of_platform.h> 37173acc7cSZhang Wei 38bbea0b6eSIra Snyder #include <asm/fsldma.h> 39173acc7cSZhang Wei #include "fsldma.h" 40173acc7cSZhang Wei 41a1c03319SIra Snyder static void dma_init(struct fsldma_chan *chan) 42173acc7cSZhang Wei { 43173acc7cSZhang Wei /* Reset the channel */ 44a1c03319SIra Snyder DMA_OUT(chan, &chan->regs->mr, 0, 32); 45173acc7cSZhang Wei 46a1c03319SIra Snyder switch (chan->feature & FSL_DMA_IP_MASK) { 47173acc7cSZhang Wei case FSL_DMA_IP_85XX: 48173acc7cSZhang Wei /* Set the channel to below modes: 49173acc7cSZhang Wei * EIE - Error interrupt enable 50173acc7cSZhang Wei * EOSIE - End of segments interrupt enable (basic mode) 51173acc7cSZhang Wei * EOLNIE - End of links interrupt enable 52173acc7cSZhang Wei */ 53a1c03319SIra Snyder DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EIE 54173acc7cSZhang Wei | FSL_DMA_MR_EOLNIE | FSL_DMA_MR_EOSIE, 32); 55173acc7cSZhang Wei break; 56173acc7cSZhang Wei case FSL_DMA_IP_83XX: 57173acc7cSZhang Wei /* Set the channel to below modes: 58173acc7cSZhang Wei * EOTIE - End-of-transfer interrupt enable 59a7aea373SIra W. Snyder * PRC_RM - PCI read multiple 60173acc7cSZhang Wei */ 61a1c03319SIra Snyder DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EOTIE 62a7aea373SIra W. Snyder | FSL_DMA_MR_PRC_RM, 32); 63173acc7cSZhang Wei break; 64173acc7cSZhang Wei } 65173acc7cSZhang Wei } 66173acc7cSZhang Wei 67a1c03319SIra Snyder static void set_sr(struct fsldma_chan *chan, u32 val) 68173acc7cSZhang Wei { 69a1c03319SIra Snyder DMA_OUT(chan, &chan->regs->sr, val, 32); 70173acc7cSZhang Wei } 71173acc7cSZhang Wei 72a1c03319SIra Snyder static u32 get_sr(struct fsldma_chan *chan) 73173acc7cSZhang Wei { 74a1c03319SIra Snyder return DMA_IN(chan, &chan->regs->sr, 32); 75173acc7cSZhang Wei } 76173acc7cSZhang Wei 77a1c03319SIra Snyder static void set_desc_cnt(struct fsldma_chan *chan, 78173acc7cSZhang Wei struct fsl_dma_ld_hw *hw, u32 count) 79173acc7cSZhang Wei { 80a1c03319SIra Snyder hw->count = CPU_TO_DMA(chan, count, 32); 81173acc7cSZhang Wei } 82173acc7cSZhang Wei 83a1c03319SIra Snyder static void set_desc_src(struct fsldma_chan *chan, 84173acc7cSZhang Wei struct fsl_dma_ld_hw *hw, dma_addr_t src) 85173acc7cSZhang Wei { 86173acc7cSZhang Wei u64 snoop_bits; 87173acc7cSZhang Wei 88a1c03319SIra Snyder snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) 89173acc7cSZhang Wei ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0; 90a1c03319SIra Snyder hw->src_addr = CPU_TO_DMA(chan, snoop_bits | src, 64); 91173acc7cSZhang Wei } 92173acc7cSZhang Wei 93a1c03319SIra Snyder static void set_desc_dst(struct fsldma_chan *chan, 94738f5f7eSIra Snyder struct fsl_dma_ld_hw *hw, dma_addr_t dst) 95173acc7cSZhang Wei { 96173acc7cSZhang Wei u64 snoop_bits; 97173acc7cSZhang Wei 98a1c03319SIra Snyder snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) 99173acc7cSZhang Wei ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0; 100a1c03319SIra Snyder hw->dst_addr = CPU_TO_DMA(chan, snoop_bits | dst, 64); 101173acc7cSZhang Wei } 102173acc7cSZhang Wei 103a1c03319SIra Snyder static void set_desc_next(struct fsldma_chan *chan, 104173acc7cSZhang Wei struct fsl_dma_ld_hw *hw, dma_addr_t next) 105173acc7cSZhang Wei { 106173acc7cSZhang Wei u64 snoop_bits; 107173acc7cSZhang Wei 108a1c03319SIra Snyder snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) 109173acc7cSZhang Wei ? FSL_DMA_SNEN : 0; 110a1c03319SIra Snyder hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64); 111173acc7cSZhang Wei } 112173acc7cSZhang Wei 113a1c03319SIra Snyder static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr) 114173acc7cSZhang Wei { 115a1c03319SIra Snyder DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64); 116173acc7cSZhang Wei } 117173acc7cSZhang Wei 118a1c03319SIra Snyder static dma_addr_t get_cdar(struct fsldma_chan *chan) 119173acc7cSZhang Wei { 120a1c03319SIra Snyder return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN; 121173acc7cSZhang Wei } 122173acc7cSZhang Wei 123a1c03319SIra Snyder static dma_addr_t get_ndar(struct fsldma_chan *chan) 124173acc7cSZhang Wei { 125a1c03319SIra Snyder return DMA_IN(chan, &chan->regs->ndar, 64); 126173acc7cSZhang Wei } 127173acc7cSZhang Wei 128a1c03319SIra Snyder static u32 get_bcr(struct fsldma_chan *chan) 129f79abb62SZhang Wei { 130a1c03319SIra Snyder return DMA_IN(chan, &chan->regs->bcr, 32); 131f79abb62SZhang Wei } 132f79abb62SZhang Wei 133a1c03319SIra Snyder static int dma_is_idle(struct fsldma_chan *chan) 134173acc7cSZhang Wei { 135a1c03319SIra Snyder u32 sr = get_sr(chan); 136173acc7cSZhang Wei return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH); 137173acc7cSZhang Wei } 138173acc7cSZhang Wei 139a1c03319SIra Snyder static void dma_start(struct fsldma_chan *chan) 140173acc7cSZhang Wei { 141272ca655SIra Snyder u32 mode; 142173acc7cSZhang Wei 143a1c03319SIra Snyder mode = DMA_IN(chan, &chan->regs->mr, 32); 144272ca655SIra Snyder 145a1c03319SIra Snyder if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) { 146a1c03319SIra Snyder if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) { 147a1c03319SIra Snyder DMA_OUT(chan, &chan->regs->bcr, 0, 32); 148272ca655SIra Snyder mode |= FSL_DMA_MR_EMP_EN; 149272ca655SIra Snyder } else { 150272ca655SIra Snyder mode &= ~FSL_DMA_MR_EMP_EN; 151272ca655SIra Snyder } 15243a1a3edSIra Snyder } 153173acc7cSZhang Wei 154a1c03319SIra Snyder if (chan->feature & FSL_DMA_CHAN_START_EXT) 155272ca655SIra Snyder mode |= FSL_DMA_MR_EMS_EN; 156173acc7cSZhang Wei else 157272ca655SIra Snyder mode |= FSL_DMA_MR_CS; 158173acc7cSZhang Wei 159a1c03319SIra Snyder DMA_OUT(chan, &chan->regs->mr, mode, 32); 160173acc7cSZhang Wei } 161173acc7cSZhang Wei 162a1c03319SIra Snyder static void dma_halt(struct fsldma_chan *chan) 163173acc7cSZhang Wei { 164272ca655SIra Snyder u32 mode; 165900325a6SDan Williams int i; 166900325a6SDan Williams 167a1c03319SIra Snyder mode = DMA_IN(chan, &chan->regs->mr, 32); 168272ca655SIra Snyder mode |= FSL_DMA_MR_CA; 169a1c03319SIra Snyder DMA_OUT(chan, &chan->regs->mr, mode, 32); 170272ca655SIra Snyder 171272ca655SIra Snyder mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN | FSL_DMA_MR_CA); 172a1c03319SIra Snyder DMA_OUT(chan, &chan->regs->mr, mode, 32); 173173acc7cSZhang Wei 174900325a6SDan Williams for (i = 0; i < 100; i++) { 175a1c03319SIra Snyder if (dma_is_idle(chan)) 1769c3a50b7SIra Snyder return; 1779c3a50b7SIra Snyder 178173acc7cSZhang Wei udelay(10); 179900325a6SDan Williams } 180272ca655SIra Snyder 1819c3a50b7SIra Snyder if (!dma_is_idle(chan)) 182a1c03319SIra Snyder dev_err(chan->dev, "DMA halt timeout!\n"); 183173acc7cSZhang Wei } 184173acc7cSZhang Wei 185a1c03319SIra Snyder static void set_ld_eol(struct fsldma_chan *chan, 186173acc7cSZhang Wei struct fsl_desc_sw *desc) 187173acc7cSZhang Wei { 188776c8943SIra Snyder u64 snoop_bits; 189776c8943SIra Snyder 190a1c03319SIra Snyder snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) 191776c8943SIra Snyder ? FSL_DMA_SNEN : 0; 192776c8943SIra Snyder 193a1c03319SIra Snyder desc->hw.next_ln_addr = CPU_TO_DMA(chan, 194a1c03319SIra Snyder DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL 195776c8943SIra Snyder | snoop_bits, 64); 196173acc7cSZhang Wei } 197173acc7cSZhang Wei 198173acc7cSZhang Wei /** 199173acc7cSZhang Wei * fsl_chan_set_src_loop_size - Set source address hold transfer size 200a1c03319SIra Snyder * @chan : Freescale DMA channel 201173acc7cSZhang Wei * @size : Address loop size, 0 for disable loop 202173acc7cSZhang Wei * 203173acc7cSZhang Wei * The set source address hold transfer size. The source 204173acc7cSZhang Wei * address hold or loop transfer size is when the DMA transfer 205173acc7cSZhang Wei * data from source address (SA), if the loop size is 4, the DMA will 206173acc7cSZhang Wei * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA, 207173acc7cSZhang Wei * SA + 1 ... and so on. 208173acc7cSZhang Wei */ 209a1c03319SIra Snyder static void fsl_chan_set_src_loop_size(struct fsldma_chan *chan, int size) 210173acc7cSZhang Wei { 211272ca655SIra Snyder u32 mode; 212272ca655SIra Snyder 213a1c03319SIra Snyder mode = DMA_IN(chan, &chan->regs->mr, 32); 214272ca655SIra Snyder 215173acc7cSZhang Wei switch (size) { 216173acc7cSZhang Wei case 0: 217272ca655SIra Snyder mode &= ~FSL_DMA_MR_SAHE; 218173acc7cSZhang Wei break; 219173acc7cSZhang Wei case 1: 220173acc7cSZhang Wei case 2: 221173acc7cSZhang Wei case 4: 222173acc7cSZhang Wei case 8: 223272ca655SIra Snyder mode |= FSL_DMA_MR_SAHE | (__ilog2(size) << 14); 224173acc7cSZhang Wei break; 225173acc7cSZhang Wei } 226272ca655SIra Snyder 227a1c03319SIra Snyder DMA_OUT(chan, &chan->regs->mr, mode, 32); 228173acc7cSZhang Wei } 229173acc7cSZhang Wei 230173acc7cSZhang Wei /** 231738f5f7eSIra Snyder * fsl_chan_set_dst_loop_size - Set destination address hold transfer size 232a1c03319SIra Snyder * @chan : Freescale DMA channel 233173acc7cSZhang Wei * @size : Address loop size, 0 for disable loop 234173acc7cSZhang Wei * 235173acc7cSZhang Wei * The set destination address hold transfer size. The destination 236173acc7cSZhang Wei * address hold or loop transfer size is when the DMA transfer 237173acc7cSZhang Wei * data to destination address (TA), if the loop size is 4, the DMA will 238173acc7cSZhang Wei * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA, 239173acc7cSZhang Wei * TA + 1 ... and so on. 240173acc7cSZhang Wei */ 241a1c03319SIra Snyder static void fsl_chan_set_dst_loop_size(struct fsldma_chan *chan, int size) 242173acc7cSZhang Wei { 243272ca655SIra Snyder u32 mode; 244272ca655SIra Snyder 245a1c03319SIra Snyder mode = DMA_IN(chan, &chan->regs->mr, 32); 246272ca655SIra Snyder 247173acc7cSZhang Wei switch (size) { 248173acc7cSZhang Wei case 0: 249272ca655SIra Snyder mode &= ~FSL_DMA_MR_DAHE; 250173acc7cSZhang Wei break; 251173acc7cSZhang Wei case 1: 252173acc7cSZhang Wei case 2: 253173acc7cSZhang Wei case 4: 254173acc7cSZhang Wei case 8: 255272ca655SIra Snyder mode |= FSL_DMA_MR_DAHE | (__ilog2(size) << 16); 256173acc7cSZhang Wei break; 257173acc7cSZhang Wei } 258272ca655SIra Snyder 259a1c03319SIra Snyder DMA_OUT(chan, &chan->regs->mr, mode, 32); 260173acc7cSZhang Wei } 261173acc7cSZhang Wei 262173acc7cSZhang Wei /** 263e6c7ecb6SIra Snyder * fsl_chan_set_request_count - Set DMA Request Count for external control 264a1c03319SIra Snyder * @chan : Freescale DMA channel 265e6c7ecb6SIra Snyder * @size : Number of bytes to transfer in a single request 266173acc7cSZhang Wei * 267e6c7ecb6SIra Snyder * The Freescale DMA channel can be controlled by the external signal DREQ#. 268e6c7ecb6SIra Snyder * The DMA request count is how many bytes are allowed to transfer before 269e6c7ecb6SIra Snyder * pausing the channel, after which a new assertion of DREQ# resumes channel 270e6c7ecb6SIra Snyder * operation. 271e6c7ecb6SIra Snyder * 272e6c7ecb6SIra Snyder * A size of 0 disables external pause control. The maximum size is 1024. 273173acc7cSZhang Wei */ 274a1c03319SIra Snyder static void fsl_chan_set_request_count(struct fsldma_chan *chan, int size) 275173acc7cSZhang Wei { 276272ca655SIra Snyder u32 mode; 277272ca655SIra Snyder 278e6c7ecb6SIra Snyder BUG_ON(size > 1024); 279272ca655SIra Snyder 280a1c03319SIra Snyder mode = DMA_IN(chan, &chan->regs->mr, 32); 281272ca655SIra Snyder mode |= (__ilog2(size) << 24) & 0x0f000000; 282272ca655SIra Snyder 283a1c03319SIra Snyder DMA_OUT(chan, &chan->regs->mr, mode, 32); 284e6c7ecb6SIra Snyder } 285e6c7ecb6SIra Snyder 286e6c7ecb6SIra Snyder /** 287e6c7ecb6SIra Snyder * fsl_chan_toggle_ext_pause - Toggle channel external pause status 288a1c03319SIra Snyder * @chan : Freescale DMA channel 289e6c7ecb6SIra Snyder * @enable : 0 is disabled, 1 is enabled. 290e6c7ecb6SIra Snyder * 291e6c7ecb6SIra Snyder * The Freescale DMA channel can be controlled by the external signal DREQ#. 292e6c7ecb6SIra Snyder * The DMA Request Count feature should be used in addition to this feature 293e6c7ecb6SIra Snyder * to set the number of bytes to transfer before pausing the channel. 294e6c7ecb6SIra Snyder */ 295a1c03319SIra Snyder static void fsl_chan_toggle_ext_pause(struct fsldma_chan *chan, int enable) 296e6c7ecb6SIra Snyder { 297e6c7ecb6SIra Snyder if (enable) 298a1c03319SIra Snyder chan->feature |= FSL_DMA_CHAN_PAUSE_EXT; 299e6c7ecb6SIra Snyder else 300a1c03319SIra Snyder chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT; 301173acc7cSZhang Wei } 302173acc7cSZhang Wei 303173acc7cSZhang Wei /** 304173acc7cSZhang Wei * fsl_chan_toggle_ext_start - Toggle channel external start status 305a1c03319SIra Snyder * @chan : Freescale DMA channel 306173acc7cSZhang Wei * @enable : 0 is disabled, 1 is enabled. 307173acc7cSZhang Wei * 308173acc7cSZhang Wei * If enable the external start, the channel can be started by an 309173acc7cSZhang Wei * external DMA start pin. So the dma_start() does not start the 310173acc7cSZhang Wei * transfer immediately. The DMA channel will wait for the 311173acc7cSZhang Wei * control pin asserted. 312173acc7cSZhang Wei */ 313a1c03319SIra Snyder static void fsl_chan_toggle_ext_start(struct fsldma_chan *chan, int enable) 314173acc7cSZhang Wei { 315173acc7cSZhang Wei if (enable) 316a1c03319SIra Snyder chan->feature |= FSL_DMA_CHAN_START_EXT; 317173acc7cSZhang Wei else 318a1c03319SIra Snyder chan->feature &= ~FSL_DMA_CHAN_START_EXT; 319173acc7cSZhang Wei } 320173acc7cSZhang Wei 3219c3a50b7SIra Snyder static void append_ld_queue(struct fsldma_chan *chan, 3229c3a50b7SIra Snyder struct fsl_desc_sw *desc) 3239c3a50b7SIra Snyder { 3249c3a50b7SIra Snyder struct fsl_desc_sw *tail = to_fsl_desc(chan->ld_pending.prev); 3259c3a50b7SIra Snyder 3269c3a50b7SIra Snyder if (list_empty(&chan->ld_pending)) 3279c3a50b7SIra Snyder goto out_splice; 3289c3a50b7SIra Snyder 3299c3a50b7SIra Snyder /* 3309c3a50b7SIra Snyder * Add the hardware descriptor to the chain of hardware descriptors 3319c3a50b7SIra Snyder * that already exists in memory. 3329c3a50b7SIra Snyder * 3339c3a50b7SIra Snyder * This will un-set the EOL bit of the existing transaction, and the 3349c3a50b7SIra Snyder * last link in this transaction will become the EOL descriptor. 3359c3a50b7SIra Snyder */ 3369c3a50b7SIra Snyder set_desc_next(chan, &tail->hw, desc->async_tx.phys); 3379c3a50b7SIra Snyder 3389c3a50b7SIra Snyder /* 3399c3a50b7SIra Snyder * Add the software descriptor and all children to the list 3409c3a50b7SIra Snyder * of pending transactions 3419c3a50b7SIra Snyder */ 3429c3a50b7SIra Snyder out_splice: 3439c3a50b7SIra Snyder list_splice_tail_init(&desc->tx_list, &chan->ld_pending); 3449c3a50b7SIra Snyder } 3459c3a50b7SIra Snyder 346173acc7cSZhang Wei static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx) 347173acc7cSZhang Wei { 348a1c03319SIra Snyder struct fsldma_chan *chan = to_fsl_chan(tx->chan); 349eda34234SDan Williams struct fsl_desc_sw *desc = tx_to_fsl_desc(tx); 350eda34234SDan Williams struct fsl_desc_sw *child; 351173acc7cSZhang Wei unsigned long flags; 352173acc7cSZhang Wei dma_cookie_t cookie; 353173acc7cSZhang Wei 354a1c03319SIra Snyder spin_lock_irqsave(&chan->desc_lock, flags); 355173acc7cSZhang Wei 3569c3a50b7SIra Snyder /* 3579c3a50b7SIra Snyder * assign cookies to all of the software descriptors 3589c3a50b7SIra Snyder * that make up this transaction 3599c3a50b7SIra Snyder */ 360a1c03319SIra Snyder cookie = chan->common.cookie; 361eda34234SDan Williams list_for_each_entry(child, &desc->tx_list, node) { 362173acc7cSZhang Wei cookie++; 363173acc7cSZhang Wei if (cookie < 0) 364173acc7cSZhang Wei cookie = 1; 365173acc7cSZhang Wei 3666ca3a7a9SSteven J. Magnani child->async_tx.cookie = cookie; 367bcfb7465SIra Snyder } 368bcfb7465SIra Snyder 369a1c03319SIra Snyder chan->common.cookie = cookie; 3709c3a50b7SIra Snyder 3719c3a50b7SIra Snyder /* put this transaction onto the tail of the pending queue */ 372a1c03319SIra Snyder append_ld_queue(chan, desc); 373173acc7cSZhang Wei 374a1c03319SIra Snyder spin_unlock_irqrestore(&chan->desc_lock, flags); 375173acc7cSZhang Wei 376173acc7cSZhang Wei return cookie; 377173acc7cSZhang Wei } 378173acc7cSZhang Wei 379173acc7cSZhang Wei /** 380173acc7cSZhang Wei * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool. 381a1c03319SIra Snyder * @chan : Freescale DMA channel 382173acc7cSZhang Wei * 383173acc7cSZhang Wei * Return - The descriptor allocated. NULL for failed. 384173acc7cSZhang Wei */ 385173acc7cSZhang Wei static struct fsl_desc_sw *fsl_dma_alloc_descriptor( 386a1c03319SIra Snyder struct fsldma_chan *chan) 387173acc7cSZhang Wei { 3889c3a50b7SIra Snyder struct fsl_desc_sw *desc; 389173acc7cSZhang Wei dma_addr_t pdesc; 390173acc7cSZhang Wei 3919c3a50b7SIra Snyder desc = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc); 3929c3a50b7SIra Snyder if (!desc) { 3939c3a50b7SIra Snyder dev_dbg(chan->dev, "out of memory for link desc\n"); 3949c3a50b7SIra Snyder return NULL; 395173acc7cSZhang Wei } 396173acc7cSZhang Wei 3979c3a50b7SIra Snyder memset(desc, 0, sizeof(*desc)); 3989c3a50b7SIra Snyder INIT_LIST_HEAD(&desc->tx_list); 3999c3a50b7SIra Snyder dma_async_tx_descriptor_init(&desc->async_tx, &chan->common); 4009c3a50b7SIra Snyder desc->async_tx.tx_submit = fsl_dma_tx_submit; 4019c3a50b7SIra Snyder desc->async_tx.phys = pdesc; 4029c3a50b7SIra Snyder 4039c3a50b7SIra Snyder return desc; 404173acc7cSZhang Wei } 405173acc7cSZhang Wei 406173acc7cSZhang Wei 407173acc7cSZhang Wei /** 408173acc7cSZhang Wei * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel. 409a1c03319SIra Snyder * @chan : Freescale DMA channel 410173acc7cSZhang Wei * 411173acc7cSZhang Wei * This function will create a dma pool for descriptor allocation. 412173acc7cSZhang Wei * 413173acc7cSZhang Wei * Return - The number of descriptors allocated. 414173acc7cSZhang Wei */ 415a1c03319SIra Snyder static int fsl_dma_alloc_chan_resources(struct dma_chan *dchan) 416173acc7cSZhang Wei { 417a1c03319SIra Snyder struct fsldma_chan *chan = to_fsl_chan(dchan); 41877cd62e8STimur Tabi 41977cd62e8STimur Tabi /* Has this channel already been allocated? */ 420a1c03319SIra Snyder if (chan->desc_pool) 42177cd62e8STimur Tabi return 1; 422173acc7cSZhang Wei 4239c3a50b7SIra Snyder /* 4249c3a50b7SIra Snyder * We need the descriptor to be aligned to 32bytes 425173acc7cSZhang Wei * for meeting FSL DMA specification requirement. 426173acc7cSZhang Wei */ 427a1c03319SIra Snyder chan->desc_pool = dma_pool_create("fsl_dma_engine_desc_pool", 4289c3a50b7SIra Snyder chan->dev, 4299c3a50b7SIra Snyder sizeof(struct fsl_desc_sw), 4309c3a50b7SIra Snyder __alignof__(struct fsl_desc_sw), 0); 431a1c03319SIra Snyder if (!chan->desc_pool) { 4329c3a50b7SIra Snyder dev_err(chan->dev, "unable to allocate channel %d " 4339c3a50b7SIra Snyder "descriptor pool\n", chan->id); 4349c3a50b7SIra Snyder return -ENOMEM; 435173acc7cSZhang Wei } 436173acc7cSZhang Wei 4379c3a50b7SIra Snyder /* there is at least one descriptor free to be allocated */ 438173acc7cSZhang Wei return 1; 439173acc7cSZhang Wei } 440173acc7cSZhang Wei 441173acc7cSZhang Wei /** 4429c3a50b7SIra Snyder * fsldma_free_desc_list - Free all descriptors in a queue 4439c3a50b7SIra Snyder * @chan: Freescae DMA channel 4449c3a50b7SIra Snyder * @list: the list to free 4459c3a50b7SIra Snyder * 4469c3a50b7SIra Snyder * LOCKING: must hold chan->desc_lock 4479c3a50b7SIra Snyder */ 4489c3a50b7SIra Snyder static void fsldma_free_desc_list(struct fsldma_chan *chan, 4499c3a50b7SIra Snyder struct list_head *list) 4509c3a50b7SIra Snyder { 4519c3a50b7SIra Snyder struct fsl_desc_sw *desc, *_desc; 4529c3a50b7SIra Snyder 4539c3a50b7SIra Snyder list_for_each_entry_safe(desc, _desc, list, node) { 4549c3a50b7SIra Snyder list_del(&desc->node); 4559c3a50b7SIra Snyder dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); 4569c3a50b7SIra Snyder } 4579c3a50b7SIra Snyder } 4589c3a50b7SIra Snyder 4599c3a50b7SIra Snyder static void fsldma_free_desc_list_reverse(struct fsldma_chan *chan, 4609c3a50b7SIra Snyder struct list_head *list) 4619c3a50b7SIra Snyder { 4629c3a50b7SIra Snyder struct fsl_desc_sw *desc, *_desc; 4639c3a50b7SIra Snyder 4649c3a50b7SIra Snyder list_for_each_entry_safe_reverse(desc, _desc, list, node) { 4659c3a50b7SIra Snyder list_del(&desc->node); 4669c3a50b7SIra Snyder dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); 4679c3a50b7SIra Snyder } 4689c3a50b7SIra Snyder } 4699c3a50b7SIra Snyder 4709c3a50b7SIra Snyder /** 471173acc7cSZhang Wei * fsl_dma_free_chan_resources - Free all resources of the channel. 472a1c03319SIra Snyder * @chan : Freescale DMA channel 473173acc7cSZhang Wei */ 474a1c03319SIra Snyder static void fsl_dma_free_chan_resources(struct dma_chan *dchan) 475173acc7cSZhang Wei { 476a1c03319SIra Snyder struct fsldma_chan *chan = to_fsl_chan(dchan); 477173acc7cSZhang Wei unsigned long flags; 478173acc7cSZhang Wei 479a1c03319SIra Snyder dev_dbg(chan->dev, "Free all channel resources.\n"); 480a1c03319SIra Snyder spin_lock_irqsave(&chan->desc_lock, flags); 4819c3a50b7SIra Snyder fsldma_free_desc_list(chan, &chan->ld_pending); 4829c3a50b7SIra Snyder fsldma_free_desc_list(chan, &chan->ld_running); 483a1c03319SIra Snyder spin_unlock_irqrestore(&chan->desc_lock, flags); 48477cd62e8STimur Tabi 4859c3a50b7SIra Snyder dma_pool_destroy(chan->desc_pool); 486a1c03319SIra Snyder chan->desc_pool = NULL; 487173acc7cSZhang Wei } 488173acc7cSZhang Wei 4892187c269SZhang Wei static struct dma_async_tx_descriptor * 490a1c03319SIra Snyder fsl_dma_prep_interrupt(struct dma_chan *dchan, unsigned long flags) 4912187c269SZhang Wei { 492a1c03319SIra Snyder struct fsldma_chan *chan; 4932187c269SZhang Wei struct fsl_desc_sw *new; 4942187c269SZhang Wei 495a1c03319SIra Snyder if (!dchan) 4962187c269SZhang Wei return NULL; 4972187c269SZhang Wei 498a1c03319SIra Snyder chan = to_fsl_chan(dchan); 4992187c269SZhang Wei 500a1c03319SIra Snyder new = fsl_dma_alloc_descriptor(chan); 5012187c269SZhang Wei if (!new) { 502a1c03319SIra Snyder dev_err(chan->dev, "No free memory for link descriptor\n"); 5032187c269SZhang Wei return NULL; 5042187c269SZhang Wei } 5052187c269SZhang Wei 5062187c269SZhang Wei new->async_tx.cookie = -EBUSY; 507636bdeaaSDan Williams new->async_tx.flags = flags; 5082187c269SZhang Wei 509f79abb62SZhang Wei /* Insert the link descriptor to the LD ring */ 510eda34234SDan Williams list_add_tail(&new->node, &new->tx_list); 511f79abb62SZhang Wei 5122187c269SZhang Wei /* Set End-of-link to the last link descriptor of new list*/ 513a1c03319SIra Snyder set_ld_eol(chan, new); 5142187c269SZhang Wei 5152187c269SZhang Wei return &new->async_tx; 5162187c269SZhang Wei } 5172187c269SZhang Wei 518173acc7cSZhang Wei static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy( 519a1c03319SIra Snyder struct dma_chan *dchan, dma_addr_t dma_dst, dma_addr_t dma_src, 520173acc7cSZhang Wei size_t len, unsigned long flags) 521173acc7cSZhang Wei { 522a1c03319SIra Snyder struct fsldma_chan *chan; 523173acc7cSZhang Wei struct fsl_desc_sw *first = NULL, *prev = NULL, *new; 524173acc7cSZhang Wei size_t copy; 525173acc7cSZhang Wei 526a1c03319SIra Snyder if (!dchan) 527173acc7cSZhang Wei return NULL; 528173acc7cSZhang Wei 529173acc7cSZhang Wei if (!len) 530173acc7cSZhang Wei return NULL; 531173acc7cSZhang Wei 532a1c03319SIra Snyder chan = to_fsl_chan(dchan); 533173acc7cSZhang Wei 534173acc7cSZhang Wei do { 535173acc7cSZhang Wei 536173acc7cSZhang Wei /* Allocate the link descriptor from DMA pool */ 537a1c03319SIra Snyder new = fsl_dma_alloc_descriptor(chan); 538173acc7cSZhang Wei if (!new) { 539a1c03319SIra Snyder dev_err(chan->dev, 540173acc7cSZhang Wei "No free memory for link descriptor\n"); 5412e077f8eSIra Snyder goto fail; 542173acc7cSZhang Wei } 543173acc7cSZhang Wei #ifdef FSL_DMA_LD_DEBUG 544a1c03319SIra Snyder dev_dbg(chan->dev, "new link desc alloc %p\n", new); 545173acc7cSZhang Wei #endif 546173acc7cSZhang Wei 54756822843SZhang Wei copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT); 548173acc7cSZhang Wei 549a1c03319SIra Snyder set_desc_cnt(chan, &new->hw, copy); 550a1c03319SIra Snyder set_desc_src(chan, &new->hw, dma_src); 551a1c03319SIra Snyder set_desc_dst(chan, &new->hw, dma_dst); 552173acc7cSZhang Wei 553173acc7cSZhang Wei if (!first) 554173acc7cSZhang Wei first = new; 555173acc7cSZhang Wei else 556a1c03319SIra Snyder set_desc_next(chan, &prev->hw, new->async_tx.phys); 557173acc7cSZhang Wei 558173acc7cSZhang Wei new->async_tx.cookie = 0; 559636bdeaaSDan Williams async_tx_ack(&new->async_tx); 560173acc7cSZhang Wei 561173acc7cSZhang Wei prev = new; 562173acc7cSZhang Wei len -= copy; 563173acc7cSZhang Wei dma_src += copy; 564738f5f7eSIra Snyder dma_dst += copy; 565173acc7cSZhang Wei 566173acc7cSZhang Wei /* Insert the link descriptor to the LD ring */ 567eda34234SDan Williams list_add_tail(&new->node, &first->tx_list); 568173acc7cSZhang Wei } while (len); 569173acc7cSZhang Wei 570636bdeaaSDan Williams new->async_tx.flags = flags; /* client is in control of this ack */ 571173acc7cSZhang Wei new->async_tx.cookie = -EBUSY; 572173acc7cSZhang Wei 573173acc7cSZhang Wei /* Set End-of-link to the last link descriptor of new list*/ 574a1c03319SIra Snyder set_ld_eol(chan, new); 575173acc7cSZhang Wei 5762e077f8eSIra Snyder return &first->async_tx; 5772e077f8eSIra Snyder 5782e077f8eSIra Snyder fail: 5792e077f8eSIra Snyder if (!first) 5802e077f8eSIra Snyder return NULL; 5812e077f8eSIra Snyder 5829c3a50b7SIra Snyder fsldma_free_desc_list_reverse(chan, &first->tx_list); 5832e077f8eSIra Snyder return NULL; 584173acc7cSZhang Wei } 585173acc7cSZhang Wei 586173acc7cSZhang Wei /** 587bbea0b6eSIra Snyder * fsl_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction 588bbea0b6eSIra Snyder * @chan: DMA channel 589bbea0b6eSIra Snyder * @sgl: scatterlist to transfer to/from 590bbea0b6eSIra Snyder * @sg_len: number of entries in @scatterlist 591bbea0b6eSIra Snyder * @direction: DMA direction 592bbea0b6eSIra Snyder * @flags: DMAEngine flags 593bbea0b6eSIra Snyder * 594bbea0b6eSIra Snyder * Prepare a set of descriptors for a DMA_SLAVE transaction. Following the 595bbea0b6eSIra Snyder * DMA_SLAVE API, this gets the device-specific information from the 596bbea0b6eSIra Snyder * chan->private variable. 597bbea0b6eSIra Snyder */ 598bbea0b6eSIra Snyder static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg( 599a1c03319SIra Snyder struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len, 600bbea0b6eSIra Snyder enum dma_data_direction direction, unsigned long flags) 601bbea0b6eSIra Snyder { 602a1c03319SIra Snyder struct fsldma_chan *chan; 603bbea0b6eSIra Snyder struct fsl_desc_sw *first = NULL, *prev = NULL, *new = NULL; 604bbea0b6eSIra Snyder struct fsl_dma_slave *slave; 605bbea0b6eSIra Snyder size_t copy; 606bbea0b6eSIra Snyder 607bbea0b6eSIra Snyder int i; 608bbea0b6eSIra Snyder struct scatterlist *sg; 609bbea0b6eSIra Snyder size_t sg_used; 610bbea0b6eSIra Snyder size_t hw_used; 611bbea0b6eSIra Snyder struct fsl_dma_hw_addr *hw; 612bbea0b6eSIra Snyder dma_addr_t dma_dst, dma_src; 613bbea0b6eSIra Snyder 614a1c03319SIra Snyder if (!dchan) 615bbea0b6eSIra Snyder return NULL; 616bbea0b6eSIra Snyder 617a1c03319SIra Snyder if (!dchan->private) 618bbea0b6eSIra Snyder return NULL; 619bbea0b6eSIra Snyder 620a1c03319SIra Snyder chan = to_fsl_chan(dchan); 621a1c03319SIra Snyder slave = dchan->private; 622bbea0b6eSIra Snyder 623bbea0b6eSIra Snyder if (list_empty(&slave->addresses)) 624bbea0b6eSIra Snyder return NULL; 625bbea0b6eSIra Snyder 626bbea0b6eSIra Snyder hw = list_first_entry(&slave->addresses, struct fsl_dma_hw_addr, entry); 627bbea0b6eSIra Snyder hw_used = 0; 628bbea0b6eSIra Snyder 629bbea0b6eSIra Snyder /* 630bbea0b6eSIra Snyder * Build the hardware transaction to copy from the scatterlist to 631bbea0b6eSIra Snyder * the hardware, or from the hardware to the scatterlist 632bbea0b6eSIra Snyder * 633bbea0b6eSIra Snyder * If you are copying from the hardware to the scatterlist and it 634bbea0b6eSIra Snyder * takes two hardware entries to fill an entire page, then both 635bbea0b6eSIra Snyder * hardware entries will be coalesced into the same page 636bbea0b6eSIra Snyder * 637bbea0b6eSIra Snyder * If you are copying from the scatterlist to the hardware and a 638bbea0b6eSIra Snyder * single page can fill two hardware entries, then the data will 639bbea0b6eSIra Snyder * be read out of the page into the first hardware entry, and so on 640bbea0b6eSIra Snyder */ 641bbea0b6eSIra Snyder for_each_sg(sgl, sg, sg_len, i) { 642bbea0b6eSIra Snyder sg_used = 0; 643bbea0b6eSIra Snyder 644bbea0b6eSIra Snyder /* Loop until the entire scatterlist entry is used */ 645bbea0b6eSIra Snyder while (sg_used < sg_dma_len(sg)) { 646bbea0b6eSIra Snyder 647bbea0b6eSIra Snyder /* 648bbea0b6eSIra Snyder * If we've used up the current hardware address/length 649bbea0b6eSIra Snyder * pair, we need to load a new one 650bbea0b6eSIra Snyder * 651bbea0b6eSIra Snyder * This is done in a while loop so that descriptors with 652bbea0b6eSIra Snyder * length == 0 will be skipped 653bbea0b6eSIra Snyder */ 654bbea0b6eSIra Snyder while (hw_used >= hw->length) { 655bbea0b6eSIra Snyder 656bbea0b6eSIra Snyder /* 657bbea0b6eSIra Snyder * If the current hardware entry is the last 658bbea0b6eSIra Snyder * entry in the list, we're finished 659bbea0b6eSIra Snyder */ 660bbea0b6eSIra Snyder if (list_is_last(&hw->entry, &slave->addresses)) 661bbea0b6eSIra Snyder goto finished; 662bbea0b6eSIra Snyder 663bbea0b6eSIra Snyder /* Get the next hardware address/length pair */ 664bbea0b6eSIra Snyder hw = list_entry(hw->entry.next, 665bbea0b6eSIra Snyder struct fsl_dma_hw_addr, entry); 666bbea0b6eSIra Snyder hw_used = 0; 667bbea0b6eSIra Snyder } 668bbea0b6eSIra Snyder 669bbea0b6eSIra Snyder /* Allocate the link descriptor from DMA pool */ 670a1c03319SIra Snyder new = fsl_dma_alloc_descriptor(chan); 671bbea0b6eSIra Snyder if (!new) { 672a1c03319SIra Snyder dev_err(chan->dev, "No free memory for " 673bbea0b6eSIra Snyder "link descriptor\n"); 674bbea0b6eSIra Snyder goto fail; 675bbea0b6eSIra Snyder } 676bbea0b6eSIra Snyder #ifdef FSL_DMA_LD_DEBUG 677a1c03319SIra Snyder dev_dbg(chan->dev, "new link desc alloc %p\n", new); 678bbea0b6eSIra Snyder #endif 679bbea0b6eSIra Snyder 680bbea0b6eSIra Snyder /* 681bbea0b6eSIra Snyder * Calculate the maximum number of bytes to transfer, 682bbea0b6eSIra Snyder * making sure it is less than the DMA controller limit 683bbea0b6eSIra Snyder */ 684bbea0b6eSIra Snyder copy = min_t(size_t, sg_dma_len(sg) - sg_used, 685bbea0b6eSIra Snyder hw->length - hw_used); 686bbea0b6eSIra Snyder copy = min_t(size_t, copy, FSL_DMA_BCR_MAX_CNT); 687bbea0b6eSIra Snyder 688bbea0b6eSIra Snyder /* 689bbea0b6eSIra Snyder * DMA_FROM_DEVICE 690bbea0b6eSIra Snyder * from the hardware to the scatterlist 691bbea0b6eSIra Snyder * 692bbea0b6eSIra Snyder * DMA_TO_DEVICE 693bbea0b6eSIra Snyder * from the scatterlist to the hardware 694bbea0b6eSIra Snyder */ 695bbea0b6eSIra Snyder if (direction == DMA_FROM_DEVICE) { 696bbea0b6eSIra Snyder dma_src = hw->address + hw_used; 697bbea0b6eSIra Snyder dma_dst = sg_dma_address(sg) + sg_used; 698bbea0b6eSIra Snyder } else { 699bbea0b6eSIra Snyder dma_src = sg_dma_address(sg) + sg_used; 700bbea0b6eSIra Snyder dma_dst = hw->address + hw_used; 701bbea0b6eSIra Snyder } 702bbea0b6eSIra Snyder 703bbea0b6eSIra Snyder /* Fill in the descriptor */ 704a1c03319SIra Snyder set_desc_cnt(chan, &new->hw, copy); 705a1c03319SIra Snyder set_desc_src(chan, &new->hw, dma_src); 706a1c03319SIra Snyder set_desc_dst(chan, &new->hw, dma_dst); 707bbea0b6eSIra Snyder 708bbea0b6eSIra Snyder /* 709bbea0b6eSIra Snyder * If this is not the first descriptor, chain the 710bbea0b6eSIra Snyder * current descriptor after the previous descriptor 711bbea0b6eSIra Snyder */ 712bbea0b6eSIra Snyder if (!first) { 713bbea0b6eSIra Snyder first = new; 714bbea0b6eSIra Snyder } else { 715a1c03319SIra Snyder set_desc_next(chan, &prev->hw, 716bbea0b6eSIra Snyder new->async_tx.phys); 717bbea0b6eSIra Snyder } 718bbea0b6eSIra Snyder 719bbea0b6eSIra Snyder new->async_tx.cookie = 0; 720bbea0b6eSIra Snyder async_tx_ack(&new->async_tx); 721bbea0b6eSIra Snyder 722bbea0b6eSIra Snyder prev = new; 723bbea0b6eSIra Snyder sg_used += copy; 724bbea0b6eSIra Snyder hw_used += copy; 725bbea0b6eSIra Snyder 726bbea0b6eSIra Snyder /* Insert the link descriptor into the LD ring */ 727bbea0b6eSIra Snyder list_add_tail(&new->node, &first->tx_list); 728bbea0b6eSIra Snyder } 729bbea0b6eSIra Snyder } 730bbea0b6eSIra Snyder 731bbea0b6eSIra Snyder finished: 732bbea0b6eSIra Snyder 733bbea0b6eSIra Snyder /* All of the hardware address/length pairs had length == 0 */ 734bbea0b6eSIra Snyder if (!first || !new) 735bbea0b6eSIra Snyder return NULL; 736bbea0b6eSIra Snyder 737bbea0b6eSIra Snyder new->async_tx.flags = flags; 738bbea0b6eSIra Snyder new->async_tx.cookie = -EBUSY; 739bbea0b6eSIra Snyder 740bbea0b6eSIra Snyder /* Set End-of-link to the last link descriptor of new list */ 741a1c03319SIra Snyder set_ld_eol(chan, new); 742bbea0b6eSIra Snyder 743bbea0b6eSIra Snyder /* Enable extra controller features */ 744a1c03319SIra Snyder if (chan->set_src_loop_size) 745a1c03319SIra Snyder chan->set_src_loop_size(chan, slave->src_loop_size); 746bbea0b6eSIra Snyder 747a1c03319SIra Snyder if (chan->set_dst_loop_size) 748a1c03319SIra Snyder chan->set_dst_loop_size(chan, slave->dst_loop_size); 749bbea0b6eSIra Snyder 750a1c03319SIra Snyder if (chan->toggle_ext_start) 751a1c03319SIra Snyder chan->toggle_ext_start(chan, slave->external_start); 752bbea0b6eSIra Snyder 753a1c03319SIra Snyder if (chan->toggle_ext_pause) 754a1c03319SIra Snyder chan->toggle_ext_pause(chan, slave->external_pause); 755bbea0b6eSIra Snyder 756a1c03319SIra Snyder if (chan->set_request_count) 757a1c03319SIra Snyder chan->set_request_count(chan, slave->request_count); 758bbea0b6eSIra Snyder 759bbea0b6eSIra Snyder return &first->async_tx; 760bbea0b6eSIra Snyder 761bbea0b6eSIra Snyder fail: 762bbea0b6eSIra Snyder /* If first was not set, then we failed to allocate the very first 763bbea0b6eSIra Snyder * descriptor, and we're done */ 764bbea0b6eSIra Snyder if (!first) 765bbea0b6eSIra Snyder return NULL; 766bbea0b6eSIra Snyder 767bbea0b6eSIra Snyder /* 768bbea0b6eSIra Snyder * First is set, so all of the descriptors we allocated have been added 769bbea0b6eSIra Snyder * to first->tx_list, INCLUDING "first" itself. Therefore we 770bbea0b6eSIra Snyder * must traverse the list backwards freeing each descriptor in turn 771bbea0b6eSIra Snyder * 772bbea0b6eSIra Snyder * We're re-using variables for the loop, oh well 773bbea0b6eSIra Snyder */ 7749c3a50b7SIra Snyder fsldma_free_desc_list_reverse(chan, &first->tx_list); 775bbea0b6eSIra Snyder return NULL; 776bbea0b6eSIra Snyder } 777bbea0b6eSIra Snyder 778a1c03319SIra Snyder static void fsl_dma_device_terminate_all(struct dma_chan *dchan) 779bbea0b6eSIra Snyder { 780a1c03319SIra Snyder struct fsldma_chan *chan; 781bbea0b6eSIra Snyder unsigned long flags; 782bbea0b6eSIra Snyder 783a1c03319SIra Snyder if (!dchan) 784bbea0b6eSIra Snyder return; 785bbea0b6eSIra Snyder 786a1c03319SIra Snyder chan = to_fsl_chan(dchan); 787bbea0b6eSIra Snyder 788bbea0b6eSIra Snyder /* Halt the DMA engine */ 789a1c03319SIra Snyder dma_halt(chan); 790bbea0b6eSIra Snyder 791a1c03319SIra Snyder spin_lock_irqsave(&chan->desc_lock, flags); 792bbea0b6eSIra Snyder 793bbea0b6eSIra Snyder /* Remove and free all of the descriptors in the LD queue */ 7949c3a50b7SIra Snyder fsldma_free_desc_list(chan, &chan->ld_pending); 7959c3a50b7SIra Snyder fsldma_free_desc_list(chan, &chan->ld_running); 796bbea0b6eSIra Snyder 797a1c03319SIra Snyder spin_unlock_irqrestore(&chan->desc_lock, flags); 798bbea0b6eSIra Snyder } 799bbea0b6eSIra Snyder 800bbea0b6eSIra Snyder /** 801173acc7cSZhang Wei * fsl_dma_update_completed_cookie - Update the completed cookie. 802a1c03319SIra Snyder * @chan : Freescale DMA channel 8039c3a50b7SIra Snyder * 8049c3a50b7SIra Snyder * CONTEXT: hardirq 805173acc7cSZhang Wei */ 806a1c03319SIra Snyder static void fsl_dma_update_completed_cookie(struct fsldma_chan *chan) 807173acc7cSZhang Wei { 8089c3a50b7SIra Snyder struct fsl_desc_sw *desc; 8099c3a50b7SIra Snyder unsigned long flags; 8109c3a50b7SIra Snyder dma_cookie_t cookie; 811173acc7cSZhang Wei 8129c3a50b7SIra Snyder spin_lock_irqsave(&chan->desc_lock, flags); 813173acc7cSZhang Wei 8149c3a50b7SIra Snyder if (list_empty(&chan->ld_running)) { 8159c3a50b7SIra Snyder dev_dbg(chan->dev, "no running descriptors\n"); 8169c3a50b7SIra Snyder goto out_unlock; 817173acc7cSZhang Wei } 818173acc7cSZhang Wei 8199c3a50b7SIra Snyder /* Get the last descriptor, update the cookie to that */ 8209c3a50b7SIra Snyder desc = to_fsl_desc(chan->ld_running.prev); 821a1c03319SIra Snyder if (dma_is_idle(chan)) 8229c3a50b7SIra Snyder cookie = desc->async_tx.cookie; 82376bd061fSSteven J. Magnani else { 8249c3a50b7SIra Snyder cookie = desc->async_tx.cookie - 1; 82576bd061fSSteven J. Magnani if (unlikely(cookie < DMA_MIN_COOKIE)) 82676bd061fSSteven J. Magnani cookie = DMA_MAX_COOKIE; 82776bd061fSSteven J. Magnani } 8289c3a50b7SIra Snyder 8299c3a50b7SIra Snyder chan->completed_cookie = cookie; 8309c3a50b7SIra Snyder 8319c3a50b7SIra Snyder out_unlock: 8329c3a50b7SIra Snyder spin_unlock_irqrestore(&chan->desc_lock, flags); 833173acc7cSZhang Wei } 8349c3a50b7SIra Snyder 8359c3a50b7SIra Snyder /** 8369c3a50b7SIra Snyder * fsldma_desc_status - Check the status of a descriptor 8379c3a50b7SIra Snyder * @chan: Freescale DMA channel 8389c3a50b7SIra Snyder * @desc: DMA SW descriptor 8399c3a50b7SIra Snyder * 8409c3a50b7SIra Snyder * This function will return the status of the given descriptor 8419c3a50b7SIra Snyder */ 8429c3a50b7SIra Snyder static enum dma_status fsldma_desc_status(struct fsldma_chan *chan, 8439c3a50b7SIra Snyder struct fsl_desc_sw *desc) 8449c3a50b7SIra Snyder { 8459c3a50b7SIra Snyder return dma_async_is_complete(desc->async_tx.cookie, 8469c3a50b7SIra Snyder chan->completed_cookie, 8479c3a50b7SIra Snyder chan->common.cookie); 848173acc7cSZhang Wei } 849173acc7cSZhang Wei 850173acc7cSZhang Wei /** 851173acc7cSZhang Wei * fsl_chan_ld_cleanup - Clean up link descriptors 852a1c03319SIra Snyder * @chan : Freescale DMA channel 853173acc7cSZhang Wei * 854173acc7cSZhang Wei * This function clean up the ld_queue of DMA channel. 855173acc7cSZhang Wei */ 856a1c03319SIra Snyder static void fsl_chan_ld_cleanup(struct fsldma_chan *chan) 857173acc7cSZhang Wei { 858173acc7cSZhang Wei struct fsl_desc_sw *desc, *_desc; 859173acc7cSZhang Wei unsigned long flags; 860173acc7cSZhang Wei 861a1c03319SIra Snyder spin_lock_irqsave(&chan->desc_lock, flags); 862173acc7cSZhang Wei 8639c3a50b7SIra Snyder dev_dbg(chan->dev, "chan completed_cookie = %d\n", chan->completed_cookie); 8649c3a50b7SIra Snyder list_for_each_entry_safe(desc, _desc, &chan->ld_running, node) { 865173acc7cSZhang Wei dma_async_tx_callback callback; 866173acc7cSZhang Wei void *callback_param; 867173acc7cSZhang Wei 8689c3a50b7SIra Snyder if (fsldma_desc_status(chan, desc) == DMA_IN_PROGRESS) 869173acc7cSZhang Wei break; 870173acc7cSZhang Wei 8719c3a50b7SIra Snyder /* Remove from the list of running transactions */ 872173acc7cSZhang Wei list_del(&desc->node); 873173acc7cSZhang Wei 874173acc7cSZhang Wei /* Run the link descriptor callback function */ 8759c3a50b7SIra Snyder callback = desc->async_tx.callback; 8769c3a50b7SIra Snyder callback_param = desc->async_tx.callback_param; 877173acc7cSZhang Wei if (callback) { 878a1c03319SIra Snyder spin_unlock_irqrestore(&chan->desc_lock, flags); 8799c3a50b7SIra Snyder dev_dbg(chan->dev, "LD %p callback\n", desc); 880173acc7cSZhang Wei callback(callback_param); 881a1c03319SIra Snyder spin_lock_irqsave(&chan->desc_lock, flags); 882173acc7cSZhang Wei } 8839c3a50b7SIra Snyder 8849c3a50b7SIra Snyder /* Run any dependencies, then free the descriptor */ 8859c3a50b7SIra Snyder dma_run_dependencies(&desc->async_tx); 8869c3a50b7SIra Snyder dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys); 887173acc7cSZhang Wei } 8889c3a50b7SIra Snyder 889a1c03319SIra Snyder spin_unlock_irqrestore(&chan->desc_lock, flags); 890173acc7cSZhang Wei } 891173acc7cSZhang Wei 892173acc7cSZhang Wei /** 8939c3a50b7SIra Snyder * fsl_chan_xfer_ld_queue - transfer any pending transactions 894a1c03319SIra Snyder * @chan : Freescale DMA channel 8959c3a50b7SIra Snyder * 8969c3a50b7SIra Snyder * This will make sure that any pending transactions will be run. 8979c3a50b7SIra Snyder * If the DMA controller is idle, it will be started. Otherwise, 8989c3a50b7SIra Snyder * the DMA controller's interrupt handler will start any pending 8999c3a50b7SIra Snyder * transactions when it becomes idle. 900173acc7cSZhang Wei */ 901a1c03319SIra Snyder static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan) 902173acc7cSZhang Wei { 9039c3a50b7SIra Snyder struct fsl_desc_sw *desc; 904173acc7cSZhang Wei unsigned long flags; 905173acc7cSZhang Wei 906a1c03319SIra Snyder spin_lock_irqsave(&chan->desc_lock, flags); 907138ef018SIra Snyder 9089c3a50b7SIra Snyder /* 9099c3a50b7SIra Snyder * If the list of pending descriptors is empty, then we 9109c3a50b7SIra Snyder * don't need to do any work at all 9119c3a50b7SIra Snyder */ 9129c3a50b7SIra Snyder if (list_empty(&chan->ld_pending)) { 9139c3a50b7SIra Snyder dev_dbg(chan->dev, "no pending LDs\n"); 914138ef018SIra Snyder goto out_unlock; 9159c3a50b7SIra Snyder } 916173acc7cSZhang Wei 9179c3a50b7SIra Snyder /* 9189c3a50b7SIra Snyder * The DMA controller is not idle, which means the interrupt 9199c3a50b7SIra Snyder * handler will start any queued transactions when it runs 9209c3a50b7SIra Snyder * at the end of the current transaction 9219c3a50b7SIra Snyder */ 9229c3a50b7SIra Snyder if (!dma_is_idle(chan)) { 9239c3a50b7SIra Snyder dev_dbg(chan->dev, "DMA controller still busy\n"); 9249c3a50b7SIra Snyder goto out_unlock; 9259c3a50b7SIra Snyder } 9269c3a50b7SIra Snyder 9279c3a50b7SIra Snyder /* 9289c3a50b7SIra Snyder * TODO: 9299c3a50b7SIra Snyder * make sure the dma_halt() function really un-wedges the 9309c3a50b7SIra Snyder * controller as much as possible 9319c3a50b7SIra Snyder */ 932a1c03319SIra Snyder dma_halt(chan); 933173acc7cSZhang Wei 9349c3a50b7SIra Snyder /* 9359c3a50b7SIra Snyder * If there are some link descriptors which have not been 9369c3a50b7SIra Snyder * transferred, we need to start the controller 937173acc7cSZhang Wei */ 938173acc7cSZhang Wei 9399c3a50b7SIra Snyder /* 9409c3a50b7SIra Snyder * Move all elements from the queue of pending transactions 9419c3a50b7SIra Snyder * onto the list of running transactions 9429c3a50b7SIra Snyder */ 9439c3a50b7SIra Snyder desc = list_first_entry(&chan->ld_pending, struct fsl_desc_sw, node); 9449c3a50b7SIra Snyder list_splice_tail_init(&chan->ld_pending, &chan->ld_running); 945173acc7cSZhang Wei 9469c3a50b7SIra Snyder /* 9479c3a50b7SIra Snyder * Program the descriptor's address into the DMA controller, 9489c3a50b7SIra Snyder * then start the DMA transaction 9499c3a50b7SIra Snyder */ 9509c3a50b7SIra Snyder set_cdar(chan, desc->async_tx.phys); 951a1c03319SIra Snyder dma_start(chan); 952138ef018SIra Snyder 953138ef018SIra Snyder out_unlock: 954a1c03319SIra Snyder spin_unlock_irqrestore(&chan->desc_lock, flags); 955173acc7cSZhang Wei } 956173acc7cSZhang Wei 957173acc7cSZhang Wei /** 958173acc7cSZhang Wei * fsl_dma_memcpy_issue_pending - Issue the DMA start command 959a1c03319SIra Snyder * @chan : Freescale DMA channel 960173acc7cSZhang Wei */ 961a1c03319SIra Snyder static void fsl_dma_memcpy_issue_pending(struct dma_chan *dchan) 962173acc7cSZhang Wei { 963a1c03319SIra Snyder struct fsldma_chan *chan = to_fsl_chan(dchan); 964a1c03319SIra Snyder fsl_chan_xfer_ld_queue(chan); 965173acc7cSZhang Wei } 966173acc7cSZhang Wei 967173acc7cSZhang Wei /** 968173acc7cSZhang Wei * fsl_dma_is_complete - Determine the DMA status 969a1c03319SIra Snyder * @chan : Freescale DMA channel 970173acc7cSZhang Wei */ 971a1c03319SIra Snyder static enum dma_status fsl_dma_is_complete(struct dma_chan *dchan, 972173acc7cSZhang Wei dma_cookie_t cookie, 973173acc7cSZhang Wei dma_cookie_t *done, 974173acc7cSZhang Wei dma_cookie_t *used) 975173acc7cSZhang Wei { 976a1c03319SIra Snyder struct fsldma_chan *chan = to_fsl_chan(dchan); 977173acc7cSZhang Wei dma_cookie_t last_used; 978173acc7cSZhang Wei dma_cookie_t last_complete; 979173acc7cSZhang Wei 980a1c03319SIra Snyder fsl_chan_ld_cleanup(chan); 981173acc7cSZhang Wei 982a1c03319SIra Snyder last_used = dchan->cookie; 983a1c03319SIra Snyder last_complete = chan->completed_cookie; 984173acc7cSZhang Wei 985173acc7cSZhang Wei if (done) 986173acc7cSZhang Wei *done = last_complete; 987173acc7cSZhang Wei 988173acc7cSZhang Wei if (used) 989173acc7cSZhang Wei *used = last_used; 990173acc7cSZhang Wei 991173acc7cSZhang Wei return dma_async_is_complete(cookie, last_complete, last_used); 992173acc7cSZhang Wei } 993173acc7cSZhang Wei 994d3f620b2SIra Snyder /*----------------------------------------------------------------------------*/ 995d3f620b2SIra Snyder /* Interrupt Handling */ 996d3f620b2SIra Snyder /*----------------------------------------------------------------------------*/ 997d3f620b2SIra Snyder 998e7a29151SIra Snyder static irqreturn_t fsldma_chan_irq(int irq, void *data) 999173acc7cSZhang Wei { 1000a1c03319SIra Snyder struct fsldma_chan *chan = data; 10011c62979eSZhang Wei int update_cookie = 0; 10021c62979eSZhang Wei int xfer_ld_q = 0; 1003a1c03319SIra Snyder u32 stat; 1004173acc7cSZhang Wei 10059c3a50b7SIra Snyder /* save and clear the status register */ 1006a1c03319SIra Snyder stat = get_sr(chan); 10079c3a50b7SIra Snyder set_sr(chan, stat); 10089c3a50b7SIra Snyder dev_dbg(chan->dev, "irq: channel %d, stat = 0x%x\n", chan->id, stat); 1009173acc7cSZhang Wei 1010173acc7cSZhang Wei stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH); 1011173acc7cSZhang Wei if (!stat) 1012173acc7cSZhang Wei return IRQ_NONE; 1013173acc7cSZhang Wei 1014173acc7cSZhang Wei if (stat & FSL_DMA_SR_TE) 1015a1c03319SIra Snyder dev_err(chan->dev, "Transfer Error!\n"); 1016173acc7cSZhang Wei 10179c3a50b7SIra Snyder /* 10189c3a50b7SIra Snyder * Programming Error 1019f79abb62SZhang Wei * The DMA_INTERRUPT async_tx is a NULL transfer, which will 1020f79abb62SZhang Wei * triger a PE interrupt. 1021f79abb62SZhang Wei */ 1022f79abb62SZhang Wei if (stat & FSL_DMA_SR_PE) { 10239c3a50b7SIra Snyder dev_dbg(chan->dev, "irq: Programming Error INT\n"); 1024a1c03319SIra Snyder if (get_bcr(chan) == 0) { 1025f79abb62SZhang Wei /* BCR register is 0, this is a DMA_INTERRUPT async_tx. 1026f79abb62SZhang Wei * Now, update the completed cookie, and continue the 1027f79abb62SZhang Wei * next uncompleted transfer. 1028f79abb62SZhang Wei */ 10291c62979eSZhang Wei update_cookie = 1; 10301c62979eSZhang Wei xfer_ld_q = 1; 1031f79abb62SZhang Wei } 1032f79abb62SZhang Wei stat &= ~FSL_DMA_SR_PE; 1033f79abb62SZhang Wei } 1034f79abb62SZhang Wei 10359c3a50b7SIra Snyder /* 10369c3a50b7SIra Snyder * If the link descriptor segment transfer finishes, 1037173acc7cSZhang Wei * we will recycle the used descriptor. 1038173acc7cSZhang Wei */ 1039173acc7cSZhang Wei if (stat & FSL_DMA_SR_EOSI) { 10409c3a50b7SIra Snyder dev_dbg(chan->dev, "irq: End-of-segments INT\n"); 10419c3a50b7SIra Snyder dev_dbg(chan->dev, "irq: clndar 0x%llx, nlndar 0x%llx\n", 1042a1c03319SIra Snyder (unsigned long long)get_cdar(chan), 1043a1c03319SIra Snyder (unsigned long long)get_ndar(chan)); 1044173acc7cSZhang Wei stat &= ~FSL_DMA_SR_EOSI; 10451c62979eSZhang Wei update_cookie = 1; 10461c62979eSZhang Wei } 10471c62979eSZhang Wei 10489c3a50b7SIra Snyder /* 10499c3a50b7SIra Snyder * For MPC8349, EOCDI event need to update cookie 10501c62979eSZhang Wei * and start the next transfer if it exist. 10511c62979eSZhang Wei */ 10521c62979eSZhang Wei if (stat & FSL_DMA_SR_EOCDI) { 10539c3a50b7SIra Snyder dev_dbg(chan->dev, "irq: End-of-Chain link INT\n"); 10541c62979eSZhang Wei stat &= ~FSL_DMA_SR_EOCDI; 10551c62979eSZhang Wei update_cookie = 1; 10561c62979eSZhang Wei xfer_ld_q = 1; 1057173acc7cSZhang Wei } 1058173acc7cSZhang Wei 10599c3a50b7SIra Snyder /* 10609c3a50b7SIra Snyder * If it current transfer is the end-of-transfer, 1061173acc7cSZhang Wei * we should clear the Channel Start bit for 1062173acc7cSZhang Wei * prepare next transfer. 1063173acc7cSZhang Wei */ 10641c62979eSZhang Wei if (stat & FSL_DMA_SR_EOLNI) { 10659c3a50b7SIra Snyder dev_dbg(chan->dev, "irq: End-of-link INT\n"); 1066173acc7cSZhang Wei stat &= ~FSL_DMA_SR_EOLNI; 10671c62979eSZhang Wei xfer_ld_q = 1; 1068173acc7cSZhang Wei } 1069173acc7cSZhang Wei 10701c62979eSZhang Wei if (update_cookie) 1071a1c03319SIra Snyder fsl_dma_update_completed_cookie(chan); 10721c62979eSZhang Wei if (xfer_ld_q) 1073a1c03319SIra Snyder fsl_chan_xfer_ld_queue(chan); 1074173acc7cSZhang Wei if (stat) 10759c3a50b7SIra Snyder dev_dbg(chan->dev, "irq: unhandled sr 0x%02x\n", stat); 1076173acc7cSZhang Wei 10779c3a50b7SIra Snyder dev_dbg(chan->dev, "irq: Exit\n"); 1078a1c03319SIra Snyder tasklet_schedule(&chan->tasklet); 1079173acc7cSZhang Wei return IRQ_HANDLED; 1080173acc7cSZhang Wei } 1081173acc7cSZhang Wei 1082173acc7cSZhang Wei static void dma_do_tasklet(unsigned long data) 1083173acc7cSZhang Wei { 1084a1c03319SIra Snyder struct fsldma_chan *chan = (struct fsldma_chan *)data; 1085a1c03319SIra Snyder fsl_chan_ld_cleanup(chan); 1086173acc7cSZhang Wei } 1087173acc7cSZhang Wei 1088d3f620b2SIra Snyder static irqreturn_t fsldma_ctrl_irq(int irq, void *data) 1089d3f620b2SIra Snyder { 1090d3f620b2SIra Snyder struct fsldma_device *fdev = data; 1091d3f620b2SIra Snyder struct fsldma_chan *chan; 1092d3f620b2SIra Snyder unsigned int handled = 0; 1093d3f620b2SIra Snyder u32 gsr, mask; 1094d3f620b2SIra Snyder int i; 1095d3f620b2SIra Snyder 1096d3f620b2SIra Snyder gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->regs) 1097d3f620b2SIra Snyder : in_le32(fdev->regs); 1098d3f620b2SIra Snyder mask = 0xff000000; 1099d3f620b2SIra Snyder dev_dbg(fdev->dev, "IRQ: gsr 0x%.8x\n", gsr); 1100d3f620b2SIra Snyder 1101d3f620b2SIra Snyder for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { 1102d3f620b2SIra Snyder chan = fdev->chan[i]; 1103d3f620b2SIra Snyder if (!chan) 1104d3f620b2SIra Snyder continue; 1105d3f620b2SIra Snyder 1106d3f620b2SIra Snyder if (gsr & mask) { 1107d3f620b2SIra Snyder dev_dbg(fdev->dev, "IRQ: chan %d\n", chan->id); 1108d3f620b2SIra Snyder fsldma_chan_irq(irq, chan); 1109d3f620b2SIra Snyder handled++; 1110d3f620b2SIra Snyder } 1111d3f620b2SIra Snyder 1112d3f620b2SIra Snyder gsr &= ~mask; 1113d3f620b2SIra Snyder mask >>= 8; 1114d3f620b2SIra Snyder } 1115d3f620b2SIra Snyder 1116d3f620b2SIra Snyder return IRQ_RETVAL(handled); 1117d3f620b2SIra Snyder } 1118d3f620b2SIra Snyder 1119d3f620b2SIra Snyder static void fsldma_free_irqs(struct fsldma_device *fdev) 1120d3f620b2SIra Snyder { 1121d3f620b2SIra Snyder struct fsldma_chan *chan; 1122d3f620b2SIra Snyder int i; 1123d3f620b2SIra Snyder 1124d3f620b2SIra Snyder if (fdev->irq != NO_IRQ) { 1125d3f620b2SIra Snyder dev_dbg(fdev->dev, "free per-controller IRQ\n"); 1126d3f620b2SIra Snyder free_irq(fdev->irq, fdev); 1127d3f620b2SIra Snyder return; 1128d3f620b2SIra Snyder } 1129d3f620b2SIra Snyder 1130d3f620b2SIra Snyder for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { 1131d3f620b2SIra Snyder chan = fdev->chan[i]; 1132d3f620b2SIra Snyder if (chan && chan->irq != NO_IRQ) { 1133d3f620b2SIra Snyder dev_dbg(fdev->dev, "free channel %d IRQ\n", chan->id); 1134d3f620b2SIra Snyder free_irq(chan->irq, chan); 1135d3f620b2SIra Snyder } 1136d3f620b2SIra Snyder } 1137d3f620b2SIra Snyder } 1138d3f620b2SIra Snyder 1139d3f620b2SIra Snyder static int fsldma_request_irqs(struct fsldma_device *fdev) 1140d3f620b2SIra Snyder { 1141d3f620b2SIra Snyder struct fsldma_chan *chan; 1142d3f620b2SIra Snyder int ret; 1143d3f620b2SIra Snyder int i; 1144d3f620b2SIra Snyder 1145d3f620b2SIra Snyder /* if we have a per-controller IRQ, use that */ 1146d3f620b2SIra Snyder if (fdev->irq != NO_IRQ) { 1147d3f620b2SIra Snyder dev_dbg(fdev->dev, "request per-controller IRQ\n"); 1148d3f620b2SIra Snyder ret = request_irq(fdev->irq, fsldma_ctrl_irq, IRQF_SHARED, 1149d3f620b2SIra Snyder "fsldma-controller", fdev); 1150d3f620b2SIra Snyder return ret; 1151d3f620b2SIra Snyder } 1152d3f620b2SIra Snyder 1153d3f620b2SIra Snyder /* no per-controller IRQ, use the per-channel IRQs */ 1154d3f620b2SIra Snyder for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { 1155d3f620b2SIra Snyder chan = fdev->chan[i]; 1156d3f620b2SIra Snyder if (!chan) 1157d3f620b2SIra Snyder continue; 1158d3f620b2SIra Snyder 1159d3f620b2SIra Snyder if (chan->irq == NO_IRQ) { 1160d3f620b2SIra Snyder dev_err(fdev->dev, "no interrupts property defined for " 1161d3f620b2SIra Snyder "DMA channel %d. Please fix your " 1162d3f620b2SIra Snyder "device tree\n", chan->id); 1163d3f620b2SIra Snyder ret = -ENODEV; 1164d3f620b2SIra Snyder goto out_unwind; 1165d3f620b2SIra Snyder } 1166d3f620b2SIra Snyder 1167d3f620b2SIra Snyder dev_dbg(fdev->dev, "request channel %d IRQ\n", chan->id); 1168d3f620b2SIra Snyder ret = request_irq(chan->irq, fsldma_chan_irq, IRQF_SHARED, 1169d3f620b2SIra Snyder "fsldma-chan", chan); 1170d3f620b2SIra Snyder if (ret) { 1171d3f620b2SIra Snyder dev_err(fdev->dev, "unable to request IRQ for DMA " 1172d3f620b2SIra Snyder "channel %d\n", chan->id); 1173d3f620b2SIra Snyder goto out_unwind; 1174d3f620b2SIra Snyder } 1175d3f620b2SIra Snyder } 1176d3f620b2SIra Snyder 1177d3f620b2SIra Snyder return 0; 1178d3f620b2SIra Snyder 1179d3f620b2SIra Snyder out_unwind: 1180d3f620b2SIra Snyder for (/* none */; i >= 0; i--) { 1181d3f620b2SIra Snyder chan = fdev->chan[i]; 1182d3f620b2SIra Snyder if (!chan) 1183d3f620b2SIra Snyder continue; 1184d3f620b2SIra Snyder 1185d3f620b2SIra Snyder if (chan->irq == NO_IRQ) 1186d3f620b2SIra Snyder continue; 1187d3f620b2SIra Snyder 1188d3f620b2SIra Snyder free_irq(chan->irq, chan); 1189d3f620b2SIra Snyder } 1190d3f620b2SIra Snyder 1191d3f620b2SIra Snyder return ret; 1192d3f620b2SIra Snyder } 1193d3f620b2SIra Snyder 1194a4f56d4bSIra Snyder /*----------------------------------------------------------------------------*/ 1195a4f56d4bSIra Snyder /* OpenFirmware Subsystem */ 1196a4f56d4bSIra Snyder /*----------------------------------------------------------------------------*/ 1197a4f56d4bSIra Snyder 1198a4f56d4bSIra Snyder static int __devinit fsl_dma_chan_probe(struct fsldma_device *fdev, 119977cd62e8STimur Tabi struct device_node *node, u32 feature, const char *compatible) 1200173acc7cSZhang Wei { 1201a1c03319SIra Snyder struct fsldma_chan *chan; 12024ce0e953SIra Snyder struct resource res; 1203173acc7cSZhang Wei int err; 1204173acc7cSZhang Wei 1205173acc7cSZhang Wei /* alloc channel */ 1206a1c03319SIra Snyder chan = kzalloc(sizeof(*chan), GFP_KERNEL); 1207a1c03319SIra Snyder if (!chan) { 1208e7a29151SIra Snyder dev_err(fdev->dev, "no free memory for DMA channels!\n"); 1209e7a29151SIra Snyder err = -ENOMEM; 1210e7a29151SIra Snyder goto out_return; 1211173acc7cSZhang Wei } 1212173acc7cSZhang Wei 1213e7a29151SIra Snyder /* ioremap registers for use */ 1214a1c03319SIra Snyder chan->regs = of_iomap(node, 0); 1215a1c03319SIra Snyder if (!chan->regs) { 1216e7a29151SIra Snyder dev_err(fdev->dev, "unable to ioremap registers\n"); 1217e7a29151SIra Snyder err = -ENOMEM; 1218a1c03319SIra Snyder goto out_free_chan; 1219e7a29151SIra Snyder } 1220e7a29151SIra Snyder 12214ce0e953SIra Snyder err = of_address_to_resource(node, 0, &res); 1222173acc7cSZhang Wei if (err) { 1223e7a29151SIra Snyder dev_err(fdev->dev, "unable to find 'reg' property\n"); 1224e7a29151SIra Snyder goto out_iounmap_regs; 1225173acc7cSZhang Wei } 1226173acc7cSZhang Wei 1227a1c03319SIra Snyder chan->feature = feature; 1228173acc7cSZhang Wei if (!fdev->feature) 1229a1c03319SIra Snyder fdev->feature = chan->feature; 1230173acc7cSZhang Wei 1231e7a29151SIra Snyder /* 1232e7a29151SIra Snyder * If the DMA device's feature is different than the feature 1233e7a29151SIra Snyder * of its channels, report the bug 1234173acc7cSZhang Wei */ 1235a1c03319SIra Snyder WARN_ON(fdev->feature != chan->feature); 1236173acc7cSZhang Wei 1237a1c03319SIra Snyder chan->dev = fdev->dev; 1238a1c03319SIra Snyder chan->id = ((res.start - 0x100) & 0xfff) >> 7; 1239a1c03319SIra Snyder if (chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) { 1240e7a29151SIra Snyder dev_err(fdev->dev, "too many channels for device\n"); 1241173acc7cSZhang Wei err = -EINVAL; 1242e7a29151SIra Snyder goto out_iounmap_regs; 1243173acc7cSZhang Wei } 1244173acc7cSZhang Wei 1245a1c03319SIra Snyder fdev->chan[chan->id] = chan; 1246a1c03319SIra Snyder tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan); 1247e7a29151SIra Snyder 1248e7a29151SIra Snyder /* Initialize the channel */ 1249a1c03319SIra Snyder dma_init(chan); 1250173acc7cSZhang Wei 1251173acc7cSZhang Wei /* Clear cdar registers */ 1252a1c03319SIra Snyder set_cdar(chan, 0); 1253173acc7cSZhang Wei 1254a1c03319SIra Snyder switch (chan->feature & FSL_DMA_IP_MASK) { 1255173acc7cSZhang Wei case FSL_DMA_IP_85XX: 1256a1c03319SIra Snyder chan->toggle_ext_pause = fsl_chan_toggle_ext_pause; 1257173acc7cSZhang Wei case FSL_DMA_IP_83XX: 1258a1c03319SIra Snyder chan->toggle_ext_start = fsl_chan_toggle_ext_start; 1259a1c03319SIra Snyder chan->set_src_loop_size = fsl_chan_set_src_loop_size; 1260a1c03319SIra Snyder chan->set_dst_loop_size = fsl_chan_set_dst_loop_size; 1261a1c03319SIra Snyder chan->set_request_count = fsl_chan_set_request_count; 1262173acc7cSZhang Wei } 1263173acc7cSZhang Wei 1264a1c03319SIra Snyder spin_lock_init(&chan->desc_lock); 12659c3a50b7SIra Snyder INIT_LIST_HEAD(&chan->ld_pending); 12669c3a50b7SIra Snyder INIT_LIST_HEAD(&chan->ld_running); 1267173acc7cSZhang Wei 1268a1c03319SIra Snyder chan->common.device = &fdev->common; 1269173acc7cSZhang Wei 1270d3f620b2SIra Snyder /* find the IRQ line, if it exists in the device tree */ 1271a1c03319SIra Snyder chan->irq = irq_of_parse_and_map(node, 0); 1272d3f620b2SIra Snyder 1273173acc7cSZhang Wei /* Add the channel to DMA device channel list */ 1274a1c03319SIra Snyder list_add_tail(&chan->common.device_node, &fdev->common.channels); 1275173acc7cSZhang Wei fdev->common.chancnt++; 1276173acc7cSZhang Wei 1277a1c03319SIra Snyder dev_info(fdev->dev, "#%d (%s), irq %d\n", chan->id, compatible, 1278a1c03319SIra Snyder chan->irq != NO_IRQ ? chan->irq : fdev->irq); 1279173acc7cSZhang Wei 1280173acc7cSZhang Wei return 0; 128151ee87f2SLi Yang 1282e7a29151SIra Snyder out_iounmap_regs: 1283a1c03319SIra Snyder iounmap(chan->regs); 1284a1c03319SIra Snyder out_free_chan: 1285a1c03319SIra Snyder kfree(chan); 1286e7a29151SIra Snyder out_return: 1287173acc7cSZhang Wei return err; 1288173acc7cSZhang Wei } 1289173acc7cSZhang Wei 1290a1c03319SIra Snyder static void fsl_dma_chan_remove(struct fsldma_chan *chan) 1291173acc7cSZhang Wei { 1292a1c03319SIra Snyder irq_dispose_mapping(chan->irq); 1293a1c03319SIra Snyder list_del(&chan->common.device_node); 1294a1c03319SIra Snyder iounmap(chan->regs); 1295a1c03319SIra Snyder kfree(chan); 1296173acc7cSZhang Wei } 1297173acc7cSZhang Wei 1298e7a29151SIra Snyder static int __devinit fsldma_of_probe(struct of_device *op, 1299173acc7cSZhang Wei const struct of_device_id *match) 1300173acc7cSZhang Wei { 1301a4f56d4bSIra Snyder struct fsldma_device *fdev; 130277cd62e8STimur Tabi struct device_node *child; 1303e7a29151SIra Snyder int err; 1304173acc7cSZhang Wei 1305a4f56d4bSIra Snyder fdev = kzalloc(sizeof(*fdev), GFP_KERNEL); 1306173acc7cSZhang Wei if (!fdev) { 1307e7a29151SIra Snyder dev_err(&op->dev, "No enough memory for 'priv'\n"); 1308e7a29151SIra Snyder err = -ENOMEM; 1309e7a29151SIra Snyder goto out_return; 1310173acc7cSZhang Wei } 1311e7a29151SIra Snyder 1312e7a29151SIra Snyder fdev->dev = &op->dev; 1313173acc7cSZhang Wei INIT_LIST_HEAD(&fdev->common.channels); 1314173acc7cSZhang Wei 1315e7a29151SIra Snyder /* ioremap the registers for use */ 131661c7a080SGrant Likely fdev->regs = of_iomap(op->dev.of_node, 0); 1317e7a29151SIra Snyder if (!fdev->regs) { 1318e7a29151SIra Snyder dev_err(&op->dev, "unable to ioremap registers\n"); 1319e7a29151SIra Snyder err = -ENOMEM; 1320e7a29151SIra Snyder goto out_free_fdev; 1321173acc7cSZhang Wei } 1322173acc7cSZhang Wei 1323d3f620b2SIra Snyder /* map the channel IRQ if it exists, but don't hookup the handler yet */ 132461c7a080SGrant Likely fdev->irq = irq_of_parse_and_map(op->dev.of_node, 0); 1325d3f620b2SIra Snyder 1326173acc7cSZhang Wei dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask); 1327173acc7cSZhang Wei dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask); 1328bbea0b6eSIra Snyder dma_cap_set(DMA_SLAVE, fdev->common.cap_mask); 1329173acc7cSZhang Wei fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources; 1330173acc7cSZhang Wei fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources; 13312187c269SZhang Wei fdev->common.device_prep_dma_interrupt = fsl_dma_prep_interrupt; 1332173acc7cSZhang Wei fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy; 1333173acc7cSZhang Wei fdev->common.device_is_tx_complete = fsl_dma_is_complete; 1334173acc7cSZhang Wei fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending; 1335bbea0b6eSIra Snyder fdev->common.device_prep_slave_sg = fsl_dma_prep_slave_sg; 1336bbea0b6eSIra Snyder fdev->common.device_terminate_all = fsl_dma_device_terminate_all; 1337e7a29151SIra Snyder fdev->common.dev = &op->dev; 1338173acc7cSZhang Wei 1339e7a29151SIra Snyder dev_set_drvdata(&op->dev, fdev); 134077cd62e8STimur Tabi 1341e7a29151SIra Snyder /* 1342e7a29151SIra Snyder * We cannot use of_platform_bus_probe() because there is no 1343e7a29151SIra Snyder * of_platform_bus_remove(). Instead, we manually instantiate every DMA 134477cd62e8STimur Tabi * channel object. 134577cd62e8STimur Tabi */ 134661c7a080SGrant Likely for_each_child_of_node(op->dev.of_node, child) { 1347e7a29151SIra Snyder if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) { 134877cd62e8STimur Tabi fsl_dma_chan_probe(fdev, child, 134977cd62e8STimur Tabi FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN, 135077cd62e8STimur Tabi "fsl,eloplus-dma-channel"); 1351e7a29151SIra Snyder } 1352e7a29151SIra Snyder 1353e7a29151SIra Snyder if (of_device_is_compatible(child, "fsl,elo-dma-channel")) { 135477cd62e8STimur Tabi fsl_dma_chan_probe(fdev, child, 135577cd62e8STimur Tabi FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN, 135677cd62e8STimur Tabi "fsl,elo-dma-channel"); 135777cd62e8STimur Tabi } 1358e7a29151SIra Snyder } 1359173acc7cSZhang Wei 1360d3f620b2SIra Snyder /* 1361d3f620b2SIra Snyder * Hookup the IRQ handler(s) 1362d3f620b2SIra Snyder * 1363d3f620b2SIra Snyder * If we have a per-controller interrupt, we prefer that to the 1364d3f620b2SIra Snyder * per-channel interrupts to reduce the number of shared interrupt 1365d3f620b2SIra Snyder * handlers on the same IRQ line 1366d3f620b2SIra Snyder */ 1367d3f620b2SIra Snyder err = fsldma_request_irqs(fdev); 1368d3f620b2SIra Snyder if (err) { 1369d3f620b2SIra Snyder dev_err(fdev->dev, "unable to request IRQs\n"); 1370d3f620b2SIra Snyder goto out_free_fdev; 1371d3f620b2SIra Snyder } 1372d3f620b2SIra Snyder 1373173acc7cSZhang Wei dma_async_device_register(&fdev->common); 1374173acc7cSZhang Wei return 0; 1375173acc7cSZhang Wei 1376e7a29151SIra Snyder out_free_fdev: 1377d3f620b2SIra Snyder irq_dispose_mapping(fdev->irq); 1378173acc7cSZhang Wei kfree(fdev); 1379e7a29151SIra Snyder out_return: 1380173acc7cSZhang Wei return err; 1381173acc7cSZhang Wei } 1382173acc7cSZhang Wei 1383e7a29151SIra Snyder static int fsldma_of_remove(struct of_device *op) 138477cd62e8STimur Tabi { 1385a4f56d4bSIra Snyder struct fsldma_device *fdev; 138677cd62e8STimur Tabi unsigned int i; 138777cd62e8STimur Tabi 1388e7a29151SIra Snyder fdev = dev_get_drvdata(&op->dev); 138977cd62e8STimur Tabi dma_async_device_unregister(&fdev->common); 139077cd62e8STimur Tabi 1391d3f620b2SIra Snyder fsldma_free_irqs(fdev); 1392d3f620b2SIra Snyder 1393e7a29151SIra Snyder for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) { 139477cd62e8STimur Tabi if (fdev->chan[i]) 139577cd62e8STimur Tabi fsl_dma_chan_remove(fdev->chan[i]); 1396e7a29151SIra Snyder } 139777cd62e8STimur Tabi 1398e7a29151SIra Snyder iounmap(fdev->regs); 1399e7a29151SIra Snyder dev_set_drvdata(&op->dev, NULL); 140077cd62e8STimur Tabi kfree(fdev); 140177cd62e8STimur Tabi 140277cd62e8STimur Tabi return 0; 140377cd62e8STimur Tabi } 140477cd62e8STimur Tabi 14054b1cf1faSMárton Németh static const struct of_device_id fsldma_of_ids[] = { 1406049c9d45SKumar Gala { .compatible = "fsl,eloplus-dma", }, 1407049c9d45SKumar Gala { .compatible = "fsl,elo-dma", }, 1408173acc7cSZhang Wei {} 1409173acc7cSZhang Wei }; 1410173acc7cSZhang Wei 1411a4f56d4bSIra Snyder static struct of_platform_driver fsldma_of_driver = { 14124018294bSGrant Likely .driver = { 141377cd62e8STimur Tabi .name = "fsl-elo-dma", 14144018294bSGrant Likely .owner = THIS_MODULE, 14154018294bSGrant Likely .of_match_table = fsldma_of_ids, 14164018294bSGrant Likely }, 1417a4f56d4bSIra Snyder .probe = fsldma_of_probe, 1418a4f56d4bSIra Snyder .remove = fsldma_of_remove, 1419173acc7cSZhang Wei }; 1420173acc7cSZhang Wei 1421a4f56d4bSIra Snyder /*----------------------------------------------------------------------------*/ 1422a4f56d4bSIra Snyder /* Module Init / Exit */ 1423a4f56d4bSIra Snyder /*----------------------------------------------------------------------------*/ 1424a4f56d4bSIra Snyder 1425a4f56d4bSIra Snyder static __init int fsldma_init(void) 1426173acc7cSZhang Wei { 142777cd62e8STimur Tabi int ret; 142877cd62e8STimur Tabi 142977cd62e8STimur Tabi pr_info("Freescale Elo / Elo Plus DMA driver\n"); 143077cd62e8STimur Tabi 1431a4f56d4bSIra Snyder ret = of_register_platform_driver(&fsldma_of_driver); 143277cd62e8STimur Tabi if (ret) 143377cd62e8STimur Tabi pr_err("fsldma: failed to register platform driver\n"); 143477cd62e8STimur Tabi 143577cd62e8STimur Tabi return ret; 1436173acc7cSZhang Wei } 1437173acc7cSZhang Wei 1438a4f56d4bSIra Snyder static void __exit fsldma_exit(void) 143977cd62e8STimur Tabi { 1440a4f56d4bSIra Snyder of_unregister_platform_driver(&fsldma_of_driver); 144177cd62e8STimur Tabi } 144277cd62e8STimur Tabi 1443a4f56d4bSIra Snyder subsys_initcall(fsldma_init); 1444a4f56d4bSIra Snyder module_exit(fsldma_exit); 144577cd62e8STimur Tabi 144677cd62e8STimur Tabi MODULE_DESCRIPTION("Freescale Elo / Elo Plus DMA driver"); 144777cd62e8STimur Tabi MODULE_LICENSE("GPL"); 1448