1173acc7cSZhang Wei /* 2173acc7cSZhang Wei * Freescale MPC85xx, MPC83xx DMA Engine support 3173acc7cSZhang Wei * 4173acc7cSZhang Wei * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved. 5173acc7cSZhang Wei * 6173acc7cSZhang Wei * Author: 7173acc7cSZhang Wei * Zhang Wei <wei.zhang@freescale.com>, Jul 2007 8173acc7cSZhang Wei * Ebony Zhu <ebony.zhu@freescale.com>, May 2007 9173acc7cSZhang Wei * 10173acc7cSZhang Wei * Description: 11173acc7cSZhang Wei * DMA engine driver for Freescale MPC8540 DMA controller, which is 12173acc7cSZhang Wei * also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc. 13173acc7cSZhang Wei * The support for MPC8349 DMA contorller is also added. 14173acc7cSZhang Wei * 15173acc7cSZhang Wei * This is free software; you can redistribute it and/or modify 16173acc7cSZhang Wei * it under the terms of the GNU General Public License as published by 17173acc7cSZhang Wei * the Free Software Foundation; either version 2 of the License, or 18173acc7cSZhang Wei * (at your option) any later version. 19173acc7cSZhang Wei * 20173acc7cSZhang Wei */ 21173acc7cSZhang Wei 22173acc7cSZhang Wei #include <linux/init.h> 23173acc7cSZhang Wei #include <linux/module.h> 24173acc7cSZhang Wei #include <linux/pci.h> 25173acc7cSZhang Wei #include <linux/interrupt.h> 26173acc7cSZhang Wei #include <linux/dmaengine.h> 27173acc7cSZhang Wei #include <linux/delay.h> 28173acc7cSZhang Wei #include <linux/dma-mapping.h> 29173acc7cSZhang Wei #include <linux/dmapool.h> 30173acc7cSZhang Wei #include <linux/of_platform.h> 31173acc7cSZhang Wei 32173acc7cSZhang Wei #include "fsldma.h" 33173acc7cSZhang Wei 34173acc7cSZhang Wei static void dma_init(struct fsl_dma_chan *fsl_chan) 35173acc7cSZhang Wei { 36173acc7cSZhang Wei /* Reset the channel */ 37173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 0, 32); 38173acc7cSZhang Wei 39173acc7cSZhang Wei switch (fsl_chan->feature & FSL_DMA_IP_MASK) { 40173acc7cSZhang Wei case FSL_DMA_IP_85XX: 41173acc7cSZhang Wei /* Set the channel to below modes: 42173acc7cSZhang Wei * EIE - Error interrupt enable 43173acc7cSZhang Wei * EOSIE - End of segments interrupt enable (basic mode) 44173acc7cSZhang Wei * EOLNIE - End of links interrupt enable 45173acc7cSZhang Wei */ 46173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, FSL_DMA_MR_EIE 47173acc7cSZhang Wei | FSL_DMA_MR_EOLNIE | FSL_DMA_MR_EOSIE, 32); 48173acc7cSZhang Wei break; 49173acc7cSZhang Wei case FSL_DMA_IP_83XX: 50173acc7cSZhang Wei /* Set the channel to below modes: 51173acc7cSZhang Wei * EOTIE - End-of-transfer interrupt enable 52173acc7cSZhang Wei */ 53173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, FSL_DMA_MR_EOTIE, 54173acc7cSZhang Wei 32); 55173acc7cSZhang Wei break; 56173acc7cSZhang Wei } 57173acc7cSZhang Wei 58173acc7cSZhang Wei } 59173acc7cSZhang Wei 6056822843SZhang Wei static void set_sr(struct fsl_dma_chan *fsl_chan, u32 val) 61173acc7cSZhang Wei { 62173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->sr, val, 32); 63173acc7cSZhang Wei } 64173acc7cSZhang Wei 6556822843SZhang Wei static u32 get_sr(struct fsl_dma_chan *fsl_chan) 66173acc7cSZhang Wei { 67173acc7cSZhang Wei return DMA_IN(fsl_chan, &fsl_chan->reg_base->sr, 32); 68173acc7cSZhang Wei } 69173acc7cSZhang Wei 70173acc7cSZhang Wei static void set_desc_cnt(struct fsl_dma_chan *fsl_chan, 71173acc7cSZhang Wei struct fsl_dma_ld_hw *hw, u32 count) 72173acc7cSZhang Wei { 73173acc7cSZhang Wei hw->count = CPU_TO_DMA(fsl_chan, count, 32); 74173acc7cSZhang Wei } 75173acc7cSZhang Wei 76173acc7cSZhang Wei static void set_desc_src(struct fsl_dma_chan *fsl_chan, 77173acc7cSZhang Wei struct fsl_dma_ld_hw *hw, dma_addr_t src) 78173acc7cSZhang Wei { 79173acc7cSZhang Wei u64 snoop_bits; 80173acc7cSZhang Wei 81173acc7cSZhang Wei snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) 82173acc7cSZhang Wei ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0; 83173acc7cSZhang Wei hw->src_addr = CPU_TO_DMA(fsl_chan, snoop_bits | src, 64); 84173acc7cSZhang Wei } 85173acc7cSZhang Wei 86173acc7cSZhang Wei static void set_desc_dest(struct fsl_dma_chan *fsl_chan, 87173acc7cSZhang Wei struct fsl_dma_ld_hw *hw, dma_addr_t dest) 88173acc7cSZhang Wei { 89173acc7cSZhang Wei u64 snoop_bits; 90173acc7cSZhang Wei 91173acc7cSZhang Wei snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) 92173acc7cSZhang Wei ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0; 93173acc7cSZhang Wei hw->dst_addr = CPU_TO_DMA(fsl_chan, snoop_bits | dest, 64); 94173acc7cSZhang Wei } 95173acc7cSZhang Wei 96173acc7cSZhang Wei static void set_desc_next(struct fsl_dma_chan *fsl_chan, 97173acc7cSZhang Wei struct fsl_dma_ld_hw *hw, dma_addr_t next) 98173acc7cSZhang Wei { 99173acc7cSZhang Wei u64 snoop_bits; 100173acc7cSZhang Wei 101173acc7cSZhang Wei snoop_bits = ((fsl_chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX) 102173acc7cSZhang Wei ? FSL_DMA_SNEN : 0; 103173acc7cSZhang Wei hw->next_ln_addr = CPU_TO_DMA(fsl_chan, snoop_bits | next, 64); 104173acc7cSZhang Wei } 105173acc7cSZhang Wei 106173acc7cSZhang Wei static void set_cdar(struct fsl_dma_chan *fsl_chan, dma_addr_t addr) 107173acc7cSZhang Wei { 108173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->cdar, addr | FSL_DMA_SNEN, 64); 109173acc7cSZhang Wei } 110173acc7cSZhang Wei 111173acc7cSZhang Wei static dma_addr_t get_cdar(struct fsl_dma_chan *fsl_chan) 112173acc7cSZhang Wei { 113173acc7cSZhang Wei return DMA_IN(fsl_chan, &fsl_chan->reg_base->cdar, 64) & ~FSL_DMA_SNEN; 114173acc7cSZhang Wei } 115173acc7cSZhang Wei 116173acc7cSZhang Wei static void set_ndar(struct fsl_dma_chan *fsl_chan, dma_addr_t addr) 117173acc7cSZhang Wei { 118173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->ndar, addr, 64); 119173acc7cSZhang Wei } 120173acc7cSZhang Wei 121173acc7cSZhang Wei static dma_addr_t get_ndar(struct fsl_dma_chan *fsl_chan) 122173acc7cSZhang Wei { 123173acc7cSZhang Wei return DMA_IN(fsl_chan, &fsl_chan->reg_base->ndar, 64); 124173acc7cSZhang Wei } 125173acc7cSZhang Wei 126f79abb62SZhang Wei static u32 get_bcr(struct fsl_dma_chan *fsl_chan) 127f79abb62SZhang Wei { 128f79abb62SZhang Wei return DMA_IN(fsl_chan, &fsl_chan->reg_base->bcr, 32); 129f79abb62SZhang Wei } 130f79abb62SZhang Wei 131173acc7cSZhang Wei static int dma_is_idle(struct fsl_dma_chan *fsl_chan) 132173acc7cSZhang Wei { 133173acc7cSZhang Wei u32 sr = get_sr(fsl_chan); 134173acc7cSZhang Wei return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH); 135173acc7cSZhang Wei } 136173acc7cSZhang Wei 137173acc7cSZhang Wei static void dma_start(struct fsl_dma_chan *fsl_chan) 138173acc7cSZhang Wei { 139173acc7cSZhang Wei u32 mr_set = 0;; 140173acc7cSZhang Wei 141173acc7cSZhang Wei if (fsl_chan->feature & FSL_DMA_CHAN_PAUSE_EXT) { 142173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->bcr, 0, 32); 143173acc7cSZhang Wei mr_set |= FSL_DMA_MR_EMP_EN; 144173acc7cSZhang Wei } else 145173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 146173acc7cSZhang Wei DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) 147173acc7cSZhang Wei & ~FSL_DMA_MR_EMP_EN, 32); 148173acc7cSZhang Wei 149173acc7cSZhang Wei if (fsl_chan->feature & FSL_DMA_CHAN_START_EXT) 150173acc7cSZhang Wei mr_set |= FSL_DMA_MR_EMS_EN; 151173acc7cSZhang Wei else 152173acc7cSZhang Wei mr_set |= FSL_DMA_MR_CS; 153173acc7cSZhang Wei 154173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 155173acc7cSZhang Wei DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) 156173acc7cSZhang Wei | mr_set, 32); 157173acc7cSZhang Wei } 158173acc7cSZhang Wei 159173acc7cSZhang Wei static void dma_halt(struct fsl_dma_chan *fsl_chan) 160173acc7cSZhang Wei { 161173acc7cSZhang Wei int i = 0; 162173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 163173acc7cSZhang Wei DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) | FSL_DMA_MR_CA, 164173acc7cSZhang Wei 32); 165173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 166173acc7cSZhang Wei DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) & ~(FSL_DMA_MR_CS 167173acc7cSZhang Wei | FSL_DMA_MR_EMS_EN | FSL_DMA_MR_CA), 32); 168173acc7cSZhang Wei 169173acc7cSZhang Wei while (!dma_is_idle(fsl_chan) && (i++ < 100)) 170173acc7cSZhang Wei udelay(10); 171173acc7cSZhang Wei if (i >= 100 && !dma_is_idle(fsl_chan)) 172173acc7cSZhang Wei dev_err(fsl_chan->dev, "DMA halt timeout!\n"); 173173acc7cSZhang Wei } 174173acc7cSZhang Wei 175173acc7cSZhang Wei static void set_ld_eol(struct fsl_dma_chan *fsl_chan, 176173acc7cSZhang Wei struct fsl_desc_sw *desc) 177173acc7cSZhang Wei { 178173acc7cSZhang Wei desc->hw.next_ln_addr = CPU_TO_DMA(fsl_chan, 179173acc7cSZhang Wei DMA_TO_CPU(fsl_chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL, 180173acc7cSZhang Wei 64); 181173acc7cSZhang Wei } 182173acc7cSZhang Wei 183173acc7cSZhang Wei static void append_ld_queue(struct fsl_dma_chan *fsl_chan, 184173acc7cSZhang Wei struct fsl_desc_sw *new_desc) 185173acc7cSZhang Wei { 186173acc7cSZhang Wei struct fsl_desc_sw *queue_tail = to_fsl_desc(fsl_chan->ld_queue.prev); 187173acc7cSZhang Wei 188173acc7cSZhang Wei if (list_empty(&fsl_chan->ld_queue)) 189173acc7cSZhang Wei return; 190173acc7cSZhang Wei 191173acc7cSZhang Wei /* Link to the new descriptor physical address and 192173acc7cSZhang Wei * Enable End-of-segment interrupt for 193173acc7cSZhang Wei * the last link descriptor. 194173acc7cSZhang Wei * (the previous node's next link descriptor) 195173acc7cSZhang Wei * 196173acc7cSZhang Wei * For FSL_DMA_IP_83xx, the snoop enable bit need be set. 197173acc7cSZhang Wei */ 198173acc7cSZhang Wei queue_tail->hw.next_ln_addr = CPU_TO_DMA(fsl_chan, 199173acc7cSZhang Wei new_desc->async_tx.phys | FSL_DMA_EOSIE | 200173acc7cSZhang Wei (((fsl_chan->feature & FSL_DMA_IP_MASK) 201173acc7cSZhang Wei == FSL_DMA_IP_83XX) ? FSL_DMA_SNEN : 0), 64); 202173acc7cSZhang Wei } 203173acc7cSZhang Wei 204173acc7cSZhang Wei /** 205173acc7cSZhang Wei * fsl_chan_set_src_loop_size - Set source address hold transfer size 206173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 207173acc7cSZhang Wei * @size : Address loop size, 0 for disable loop 208173acc7cSZhang Wei * 209173acc7cSZhang Wei * The set source address hold transfer size. The source 210173acc7cSZhang Wei * address hold or loop transfer size is when the DMA transfer 211173acc7cSZhang Wei * data from source address (SA), if the loop size is 4, the DMA will 212173acc7cSZhang Wei * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA, 213173acc7cSZhang Wei * SA + 1 ... and so on. 214173acc7cSZhang Wei */ 215173acc7cSZhang Wei static void fsl_chan_set_src_loop_size(struct fsl_dma_chan *fsl_chan, int size) 216173acc7cSZhang Wei { 217173acc7cSZhang Wei switch (size) { 218173acc7cSZhang Wei case 0: 219173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 220173acc7cSZhang Wei DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) & 221173acc7cSZhang Wei (~FSL_DMA_MR_SAHE), 32); 222173acc7cSZhang Wei break; 223173acc7cSZhang Wei case 1: 224173acc7cSZhang Wei case 2: 225173acc7cSZhang Wei case 4: 226173acc7cSZhang Wei case 8: 227173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 228173acc7cSZhang Wei DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) | 229173acc7cSZhang Wei FSL_DMA_MR_SAHE | (__ilog2(size) << 14), 230173acc7cSZhang Wei 32); 231173acc7cSZhang Wei break; 232173acc7cSZhang Wei } 233173acc7cSZhang Wei } 234173acc7cSZhang Wei 235173acc7cSZhang Wei /** 236173acc7cSZhang Wei * fsl_chan_set_dest_loop_size - Set destination address hold transfer size 237173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 238173acc7cSZhang Wei * @size : Address loop size, 0 for disable loop 239173acc7cSZhang Wei * 240173acc7cSZhang Wei * The set destination address hold transfer size. The destination 241173acc7cSZhang Wei * address hold or loop transfer size is when the DMA transfer 242173acc7cSZhang Wei * data to destination address (TA), if the loop size is 4, the DMA will 243173acc7cSZhang Wei * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA, 244173acc7cSZhang Wei * TA + 1 ... and so on. 245173acc7cSZhang Wei */ 246173acc7cSZhang Wei static void fsl_chan_set_dest_loop_size(struct fsl_dma_chan *fsl_chan, int size) 247173acc7cSZhang Wei { 248173acc7cSZhang Wei switch (size) { 249173acc7cSZhang Wei case 0: 250173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 251173acc7cSZhang Wei DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) & 252173acc7cSZhang Wei (~FSL_DMA_MR_DAHE), 32); 253173acc7cSZhang Wei break; 254173acc7cSZhang Wei case 1: 255173acc7cSZhang Wei case 2: 256173acc7cSZhang Wei case 4: 257173acc7cSZhang Wei case 8: 258173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 259173acc7cSZhang Wei DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) | 260173acc7cSZhang Wei FSL_DMA_MR_DAHE | (__ilog2(size) << 16), 261173acc7cSZhang Wei 32); 262173acc7cSZhang Wei break; 263173acc7cSZhang Wei } 264173acc7cSZhang Wei } 265173acc7cSZhang Wei 266173acc7cSZhang Wei /** 267173acc7cSZhang Wei * fsl_chan_toggle_ext_pause - Toggle channel external pause status 268173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 269173acc7cSZhang Wei * @size : Pause control size, 0 for disable external pause control. 270173acc7cSZhang Wei * The maximum is 1024. 271173acc7cSZhang Wei * 272173acc7cSZhang Wei * The Freescale DMA channel can be controlled by the external 273173acc7cSZhang Wei * signal DREQ#. The pause control size is how many bytes are allowed 274173acc7cSZhang Wei * to transfer before pausing the channel, after which a new assertion 275173acc7cSZhang Wei * of DREQ# resumes channel operation. 276173acc7cSZhang Wei */ 277173acc7cSZhang Wei static void fsl_chan_toggle_ext_pause(struct fsl_dma_chan *fsl_chan, int size) 278173acc7cSZhang Wei { 279173acc7cSZhang Wei if (size > 1024) 280173acc7cSZhang Wei return; 281173acc7cSZhang Wei 282173acc7cSZhang Wei if (size) { 283173acc7cSZhang Wei DMA_OUT(fsl_chan, &fsl_chan->reg_base->mr, 284173acc7cSZhang Wei DMA_IN(fsl_chan, &fsl_chan->reg_base->mr, 32) 285173acc7cSZhang Wei | ((__ilog2(size) << 24) & 0x0f000000), 286173acc7cSZhang Wei 32); 287173acc7cSZhang Wei fsl_chan->feature |= FSL_DMA_CHAN_PAUSE_EXT; 288173acc7cSZhang Wei } else 289173acc7cSZhang Wei fsl_chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT; 290173acc7cSZhang Wei } 291173acc7cSZhang Wei 292173acc7cSZhang Wei /** 293173acc7cSZhang Wei * fsl_chan_toggle_ext_start - Toggle channel external start status 294173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 295173acc7cSZhang Wei * @enable : 0 is disabled, 1 is enabled. 296173acc7cSZhang Wei * 297173acc7cSZhang Wei * If enable the external start, the channel can be started by an 298173acc7cSZhang Wei * external DMA start pin. So the dma_start() does not start the 299173acc7cSZhang Wei * transfer immediately. The DMA channel will wait for the 300173acc7cSZhang Wei * control pin asserted. 301173acc7cSZhang Wei */ 302173acc7cSZhang Wei static void fsl_chan_toggle_ext_start(struct fsl_dma_chan *fsl_chan, int enable) 303173acc7cSZhang Wei { 304173acc7cSZhang Wei if (enable) 305173acc7cSZhang Wei fsl_chan->feature |= FSL_DMA_CHAN_START_EXT; 306173acc7cSZhang Wei else 307173acc7cSZhang Wei fsl_chan->feature &= ~FSL_DMA_CHAN_START_EXT; 308173acc7cSZhang Wei } 309173acc7cSZhang Wei 310173acc7cSZhang Wei static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx) 311173acc7cSZhang Wei { 312173acc7cSZhang Wei struct fsl_desc_sw *desc = tx_to_fsl_desc(tx); 313173acc7cSZhang Wei struct fsl_dma_chan *fsl_chan = to_fsl_chan(tx->chan); 314173acc7cSZhang Wei unsigned long flags; 315173acc7cSZhang Wei dma_cookie_t cookie; 316173acc7cSZhang Wei 317173acc7cSZhang Wei /* cookie increment and adding to ld_queue must be atomic */ 318173acc7cSZhang Wei spin_lock_irqsave(&fsl_chan->desc_lock, flags); 319173acc7cSZhang Wei 320173acc7cSZhang Wei cookie = fsl_chan->common.cookie; 321173acc7cSZhang Wei cookie++; 322173acc7cSZhang Wei if (cookie < 0) 323173acc7cSZhang Wei cookie = 1; 324173acc7cSZhang Wei desc->async_tx.cookie = cookie; 325173acc7cSZhang Wei fsl_chan->common.cookie = desc->async_tx.cookie; 326173acc7cSZhang Wei 327173acc7cSZhang Wei append_ld_queue(fsl_chan, desc); 328173acc7cSZhang Wei list_splice_init(&desc->async_tx.tx_list, fsl_chan->ld_queue.prev); 329173acc7cSZhang Wei 330173acc7cSZhang Wei spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); 331173acc7cSZhang Wei 332173acc7cSZhang Wei return cookie; 333173acc7cSZhang Wei } 334173acc7cSZhang Wei 335173acc7cSZhang Wei /** 336173acc7cSZhang Wei * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool. 337173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 338173acc7cSZhang Wei * 339173acc7cSZhang Wei * Return - The descriptor allocated. NULL for failed. 340173acc7cSZhang Wei */ 341173acc7cSZhang Wei static struct fsl_desc_sw *fsl_dma_alloc_descriptor( 342173acc7cSZhang Wei struct fsl_dma_chan *fsl_chan) 343173acc7cSZhang Wei { 344173acc7cSZhang Wei dma_addr_t pdesc; 345173acc7cSZhang Wei struct fsl_desc_sw *desc_sw; 346173acc7cSZhang Wei 347173acc7cSZhang Wei desc_sw = dma_pool_alloc(fsl_chan->desc_pool, GFP_ATOMIC, &pdesc); 348173acc7cSZhang Wei if (desc_sw) { 349173acc7cSZhang Wei memset(desc_sw, 0, sizeof(struct fsl_desc_sw)); 350173acc7cSZhang Wei dma_async_tx_descriptor_init(&desc_sw->async_tx, 351173acc7cSZhang Wei &fsl_chan->common); 352173acc7cSZhang Wei desc_sw->async_tx.tx_submit = fsl_dma_tx_submit; 353173acc7cSZhang Wei INIT_LIST_HEAD(&desc_sw->async_tx.tx_list); 354173acc7cSZhang Wei desc_sw->async_tx.phys = pdesc; 355173acc7cSZhang Wei } 356173acc7cSZhang Wei 357173acc7cSZhang Wei return desc_sw; 358173acc7cSZhang Wei } 359173acc7cSZhang Wei 360173acc7cSZhang Wei 361173acc7cSZhang Wei /** 362173acc7cSZhang Wei * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel. 363173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 364173acc7cSZhang Wei * 365173acc7cSZhang Wei * This function will create a dma pool for descriptor allocation. 366173acc7cSZhang Wei * 367173acc7cSZhang Wei * Return - The number of descriptors allocated. 368173acc7cSZhang Wei */ 369aa1e6f1aSDan Williams static int fsl_dma_alloc_chan_resources(struct dma_chan *chan) 370173acc7cSZhang Wei { 371173acc7cSZhang Wei struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan); 37277cd62e8STimur Tabi 37377cd62e8STimur Tabi /* Has this channel already been allocated? */ 37477cd62e8STimur Tabi if (fsl_chan->desc_pool) 37577cd62e8STimur Tabi return 1; 376173acc7cSZhang Wei 377173acc7cSZhang Wei /* We need the descriptor to be aligned to 32bytes 378173acc7cSZhang Wei * for meeting FSL DMA specification requirement. 379173acc7cSZhang Wei */ 380173acc7cSZhang Wei fsl_chan->desc_pool = dma_pool_create("fsl_dma_engine_desc_pool", 381173acc7cSZhang Wei fsl_chan->dev, sizeof(struct fsl_desc_sw), 382173acc7cSZhang Wei 32, 0); 383173acc7cSZhang Wei if (!fsl_chan->desc_pool) { 384173acc7cSZhang Wei dev_err(fsl_chan->dev, "No memory for channel %d " 385173acc7cSZhang Wei "descriptor dma pool.\n", fsl_chan->id); 386173acc7cSZhang Wei return 0; 387173acc7cSZhang Wei } 388173acc7cSZhang Wei 389173acc7cSZhang Wei return 1; 390173acc7cSZhang Wei } 391173acc7cSZhang Wei 392173acc7cSZhang Wei /** 393173acc7cSZhang Wei * fsl_dma_free_chan_resources - Free all resources of the channel. 394173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 395173acc7cSZhang Wei */ 396173acc7cSZhang Wei static void fsl_dma_free_chan_resources(struct dma_chan *chan) 397173acc7cSZhang Wei { 398173acc7cSZhang Wei struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan); 399173acc7cSZhang Wei struct fsl_desc_sw *desc, *_desc; 400173acc7cSZhang Wei unsigned long flags; 401173acc7cSZhang Wei 402173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "Free all channel resources.\n"); 403173acc7cSZhang Wei spin_lock_irqsave(&fsl_chan->desc_lock, flags); 404173acc7cSZhang Wei list_for_each_entry_safe(desc, _desc, &fsl_chan->ld_queue, node) { 405173acc7cSZhang Wei #ifdef FSL_DMA_LD_DEBUG 406173acc7cSZhang Wei dev_dbg(fsl_chan->dev, 407173acc7cSZhang Wei "LD %p will be released.\n", desc); 408173acc7cSZhang Wei #endif 409173acc7cSZhang Wei list_del(&desc->node); 410173acc7cSZhang Wei /* free link descriptor */ 411173acc7cSZhang Wei dma_pool_free(fsl_chan->desc_pool, desc, desc->async_tx.phys); 412173acc7cSZhang Wei } 413173acc7cSZhang Wei spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); 414173acc7cSZhang Wei dma_pool_destroy(fsl_chan->desc_pool); 41577cd62e8STimur Tabi 41677cd62e8STimur Tabi fsl_chan->desc_pool = NULL; 417173acc7cSZhang Wei } 418173acc7cSZhang Wei 4192187c269SZhang Wei static struct dma_async_tx_descriptor * 420636bdeaaSDan Williams fsl_dma_prep_interrupt(struct dma_chan *chan, unsigned long flags) 4212187c269SZhang Wei { 4222187c269SZhang Wei struct fsl_dma_chan *fsl_chan; 4232187c269SZhang Wei struct fsl_desc_sw *new; 4242187c269SZhang Wei 4252187c269SZhang Wei if (!chan) 4262187c269SZhang Wei return NULL; 4272187c269SZhang Wei 4282187c269SZhang Wei fsl_chan = to_fsl_chan(chan); 4292187c269SZhang Wei 4302187c269SZhang Wei new = fsl_dma_alloc_descriptor(fsl_chan); 4312187c269SZhang Wei if (!new) { 4322187c269SZhang Wei dev_err(fsl_chan->dev, "No free memory for link descriptor\n"); 4332187c269SZhang Wei return NULL; 4342187c269SZhang Wei } 4352187c269SZhang Wei 4362187c269SZhang Wei new->async_tx.cookie = -EBUSY; 437636bdeaaSDan Williams new->async_tx.flags = flags; 4382187c269SZhang Wei 439f79abb62SZhang Wei /* Insert the link descriptor to the LD ring */ 440f79abb62SZhang Wei list_add_tail(&new->node, &new->async_tx.tx_list); 441f79abb62SZhang Wei 4422187c269SZhang Wei /* Set End-of-link to the last link descriptor of new list*/ 4432187c269SZhang Wei set_ld_eol(fsl_chan, new); 4442187c269SZhang Wei 4452187c269SZhang Wei return &new->async_tx; 4462187c269SZhang Wei } 4472187c269SZhang Wei 448173acc7cSZhang Wei static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy( 449173acc7cSZhang Wei struct dma_chan *chan, dma_addr_t dma_dest, dma_addr_t dma_src, 450173acc7cSZhang Wei size_t len, unsigned long flags) 451173acc7cSZhang Wei { 452173acc7cSZhang Wei struct fsl_dma_chan *fsl_chan; 453173acc7cSZhang Wei struct fsl_desc_sw *first = NULL, *prev = NULL, *new; 454173acc7cSZhang Wei size_t copy; 455173acc7cSZhang Wei LIST_HEAD(link_chain); 456173acc7cSZhang Wei 457173acc7cSZhang Wei if (!chan) 458173acc7cSZhang Wei return NULL; 459173acc7cSZhang Wei 460173acc7cSZhang Wei if (!len) 461173acc7cSZhang Wei return NULL; 462173acc7cSZhang Wei 463173acc7cSZhang Wei fsl_chan = to_fsl_chan(chan); 464173acc7cSZhang Wei 465173acc7cSZhang Wei do { 466173acc7cSZhang Wei 467173acc7cSZhang Wei /* Allocate the link descriptor from DMA pool */ 468173acc7cSZhang Wei new = fsl_dma_alloc_descriptor(fsl_chan); 469173acc7cSZhang Wei if (!new) { 470173acc7cSZhang Wei dev_err(fsl_chan->dev, 471173acc7cSZhang Wei "No free memory for link descriptor\n"); 472173acc7cSZhang Wei return NULL; 473173acc7cSZhang Wei } 474173acc7cSZhang Wei #ifdef FSL_DMA_LD_DEBUG 475173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "new link desc alloc %p\n", new); 476173acc7cSZhang Wei #endif 477173acc7cSZhang Wei 47856822843SZhang Wei copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT); 479173acc7cSZhang Wei 480173acc7cSZhang Wei set_desc_cnt(fsl_chan, &new->hw, copy); 481173acc7cSZhang Wei set_desc_src(fsl_chan, &new->hw, dma_src); 482173acc7cSZhang Wei set_desc_dest(fsl_chan, &new->hw, dma_dest); 483173acc7cSZhang Wei 484173acc7cSZhang Wei if (!first) 485173acc7cSZhang Wei first = new; 486173acc7cSZhang Wei else 487173acc7cSZhang Wei set_desc_next(fsl_chan, &prev->hw, new->async_tx.phys); 488173acc7cSZhang Wei 489173acc7cSZhang Wei new->async_tx.cookie = 0; 490636bdeaaSDan Williams async_tx_ack(&new->async_tx); 491173acc7cSZhang Wei 492173acc7cSZhang Wei prev = new; 493173acc7cSZhang Wei len -= copy; 494173acc7cSZhang Wei dma_src += copy; 495173acc7cSZhang Wei dma_dest += copy; 496173acc7cSZhang Wei 497173acc7cSZhang Wei /* Insert the link descriptor to the LD ring */ 498173acc7cSZhang Wei list_add_tail(&new->node, &first->async_tx.tx_list); 499173acc7cSZhang Wei } while (len); 500173acc7cSZhang Wei 501636bdeaaSDan Williams new->async_tx.flags = flags; /* client is in control of this ack */ 502173acc7cSZhang Wei new->async_tx.cookie = -EBUSY; 503173acc7cSZhang Wei 504173acc7cSZhang Wei /* Set End-of-link to the last link descriptor of new list*/ 505173acc7cSZhang Wei set_ld_eol(fsl_chan, new); 506173acc7cSZhang Wei 507173acc7cSZhang Wei return first ? &first->async_tx : NULL; 508173acc7cSZhang Wei } 509173acc7cSZhang Wei 510173acc7cSZhang Wei /** 511173acc7cSZhang Wei * fsl_dma_update_completed_cookie - Update the completed cookie. 512173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 513173acc7cSZhang Wei */ 514173acc7cSZhang Wei static void fsl_dma_update_completed_cookie(struct fsl_dma_chan *fsl_chan) 515173acc7cSZhang Wei { 516173acc7cSZhang Wei struct fsl_desc_sw *cur_desc, *desc; 517173acc7cSZhang Wei dma_addr_t ld_phy; 518173acc7cSZhang Wei 519173acc7cSZhang Wei ld_phy = get_cdar(fsl_chan) & FSL_DMA_NLDA_MASK; 520173acc7cSZhang Wei 521173acc7cSZhang Wei if (ld_phy) { 522173acc7cSZhang Wei cur_desc = NULL; 523173acc7cSZhang Wei list_for_each_entry(desc, &fsl_chan->ld_queue, node) 524173acc7cSZhang Wei if (desc->async_tx.phys == ld_phy) { 525173acc7cSZhang Wei cur_desc = desc; 526173acc7cSZhang Wei break; 527173acc7cSZhang Wei } 528173acc7cSZhang Wei 529173acc7cSZhang Wei if (cur_desc && cur_desc->async_tx.cookie) { 530173acc7cSZhang Wei if (dma_is_idle(fsl_chan)) 531173acc7cSZhang Wei fsl_chan->completed_cookie = 532173acc7cSZhang Wei cur_desc->async_tx.cookie; 533173acc7cSZhang Wei else 534173acc7cSZhang Wei fsl_chan->completed_cookie = 535173acc7cSZhang Wei cur_desc->async_tx.cookie - 1; 536173acc7cSZhang Wei } 537173acc7cSZhang Wei } 538173acc7cSZhang Wei } 539173acc7cSZhang Wei 540173acc7cSZhang Wei /** 541173acc7cSZhang Wei * fsl_chan_ld_cleanup - Clean up link descriptors 542173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 543173acc7cSZhang Wei * 544173acc7cSZhang Wei * This function clean up the ld_queue of DMA channel. 545173acc7cSZhang Wei * If 'in_intr' is set, the function will move the link descriptor to 546173acc7cSZhang Wei * the recycle list. Otherwise, free it directly. 547173acc7cSZhang Wei */ 548173acc7cSZhang Wei static void fsl_chan_ld_cleanup(struct fsl_dma_chan *fsl_chan) 549173acc7cSZhang Wei { 550173acc7cSZhang Wei struct fsl_desc_sw *desc, *_desc; 551173acc7cSZhang Wei unsigned long flags; 552173acc7cSZhang Wei 553173acc7cSZhang Wei spin_lock_irqsave(&fsl_chan->desc_lock, flags); 554173acc7cSZhang Wei 555173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "chan completed_cookie = %d\n", 556173acc7cSZhang Wei fsl_chan->completed_cookie); 557173acc7cSZhang Wei list_for_each_entry_safe(desc, _desc, &fsl_chan->ld_queue, node) { 558173acc7cSZhang Wei dma_async_tx_callback callback; 559173acc7cSZhang Wei void *callback_param; 560173acc7cSZhang Wei 561173acc7cSZhang Wei if (dma_async_is_complete(desc->async_tx.cookie, 562173acc7cSZhang Wei fsl_chan->completed_cookie, fsl_chan->common.cookie) 563173acc7cSZhang Wei == DMA_IN_PROGRESS) 564173acc7cSZhang Wei break; 565173acc7cSZhang Wei 566173acc7cSZhang Wei callback = desc->async_tx.callback; 567173acc7cSZhang Wei callback_param = desc->async_tx.callback_param; 568173acc7cSZhang Wei 569173acc7cSZhang Wei /* Remove from ld_queue list */ 570173acc7cSZhang Wei list_del(&desc->node); 571173acc7cSZhang Wei 572173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "link descriptor %p will be recycle.\n", 573173acc7cSZhang Wei desc); 574173acc7cSZhang Wei dma_pool_free(fsl_chan->desc_pool, desc, desc->async_tx.phys); 575173acc7cSZhang Wei 576173acc7cSZhang Wei /* Run the link descriptor callback function */ 577173acc7cSZhang Wei if (callback) { 578173acc7cSZhang Wei spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); 579173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "link descriptor %p callback\n", 580173acc7cSZhang Wei desc); 581173acc7cSZhang Wei callback(callback_param); 582173acc7cSZhang Wei spin_lock_irqsave(&fsl_chan->desc_lock, flags); 583173acc7cSZhang Wei } 584173acc7cSZhang Wei } 585173acc7cSZhang Wei spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); 586173acc7cSZhang Wei } 587173acc7cSZhang Wei 588173acc7cSZhang Wei /** 589173acc7cSZhang Wei * fsl_chan_xfer_ld_queue - Transfer link descriptors in channel ld_queue. 590173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 591173acc7cSZhang Wei */ 592173acc7cSZhang Wei static void fsl_chan_xfer_ld_queue(struct fsl_dma_chan *fsl_chan) 593173acc7cSZhang Wei { 594173acc7cSZhang Wei struct list_head *ld_node; 595173acc7cSZhang Wei dma_addr_t next_dest_addr; 596173acc7cSZhang Wei unsigned long flags; 597173acc7cSZhang Wei 598173acc7cSZhang Wei if (!dma_is_idle(fsl_chan)) 599173acc7cSZhang Wei return; 600173acc7cSZhang Wei 601173acc7cSZhang Wei dma_halt(fsl_chan); 602173acc7cSZhang Wei 603173acc7cSZhang Wei /* If there are some link descriptors 604173acc7cSZhang Wei * not transfered in queue. We need to start it. 605173acc7cSZhang Wei */ 606173acc7cSZhang Wei spin_lock_irqsave(&fsl_chan->desc_lock, flags); 607173acc7cSZhang Wei 608173acc7cSZhang Wei /* Find the first un-transfer desciptor */ 609173acc7cSZhang Wei for (ld_node = fsl_chan->ld_queue.next; 610173acc7cSZhang Wei (ld_node != &fsl_chan->ld_queue) 611173acc7cSZhang Wei && (dma_async_is_complete( 612173acc7cSZhang Wei to_fsl_desc(ld_node)->async_tx.cookie, 613173acc7cSZhang Wei fsl_chan->completed_cookie, 614173acc7cSZhang Wei fsl_chan->common.cookie) == DMA_SUCCESS); 615173acc7cSZhang Wei ld_node = ld_node->next); 616173acc7cSZhang Wei 617173acc7cSZhang Wei spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); 618173acc7cSZhang Wei 619173acc7cSZhang Wei if (ld_node != &fsl_chan->ld_queue) { 620173acc7cSZhang Wei /* Get the ld start address from ld_queue */ 621173acc7cSZhang Wei next_dest_addr = to_fsl_desc(ld_node)->async_tx.phys; 62256822843SZhang Wei dev_dbg(fsl_chan->dev, "xfer LDs staring from %p\n", 62356822843SZhang Wei (void *)next_dest_addr); 624173acc7cSZhang Wei set_cdar(fsl_chan, next_dest_addr); 625173acc7cSZhang Wei dma_start(fsl_chan); 626173acc7cSZhang Wei } else { 627173acc7cSZhang Wei set_cdar(fsl_chan, 0); 628173acc7cSZhang Wei set_ndar(fsl_chan, 0); 629173acc7cSZhang Wei } 630173acc7cSZhang Wei } 631173acc7cSZhang Wei 632173acc7cSZhang Wei /** 633173acc7cSZhang Wei * fsl_dma_memcpy_issue_pending - Issue the DMA start command 634173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 635173acc7cSZhang Wei */ 636173acc7cSZhang Wei static void fsl_dma_memcpy_issue_pending(struct dma_chan *chan) 637173acc7cSZhang Wei { 638173acc7cSZhang Wei struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan); 639173acc7cSZhang Wei 640173acc7cSZhang Wei #ifdef FSL_DMA_LD_DEBUG 641173acc7cSZhang Wei struct fsl_desc_sw *ld; 642173acc7cSZhang Wei unsigned long flags; 643173acc7cSZhang Wei 644173acc7cSZhang Wei spin_lock_irqsave(&fsl_chan->desc_lock, flags); 645173acc7cSZhang Wei if (list_empty(&fsl_chan->ld_queue)) { 646173acc7cSZhang Wei spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); 647173acc7cSZhang Wei return; 648173acc7cSZhang Wei } 649173acc7cSZhang Wei 650173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "--memcpy issue--\n"); 651173acc7cSZhang Wei list_for_each_entry(ld, &fsl_chan->ld_queue, node) { 652173acc7cSZhang Wei int i; 653173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "Ch %d, LD %08x\n", 654173acc7cSZhang Wei fsl_chan->id, ld->async_tx.phys); 655173acc7cSZhang Wei for (i = 0; i < 8; i++) 656173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "LD offset %d: %08x\n", 657173acc7cSZhang Wei i, *(((u32 *)&ld->hw) + i)); 658173acc7cSZhang Wei } 659173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "----------------\n"); 660173acc7cSZhang Wei spin_unlock_irqrestore(&fsl_chan->desc_lock, flags); 661173acc7cSZhang Wei #endif 662173acc7cSZhang Wei 663173acc7cSZhang Wei fsl_chan_xfer_ld_queue(fsl_chan); 664173acc7cSZhang Wei } 665173acc7cSZhang Wei 666173acc7cSZhang Wei /** 667173acc7cSZhang Wei * fsl_dma_is_complete - Determine the DMA status 668173acc7cSZhang Wei * @fsl_chan : Freescale DMA channel 669173acc7cSZhang Wei */ 670173acc7cSZhang Wei static enum dma_status fsl_dma_is_complete(struct dma_chan *chan, 671173acc7cSZhang Wei dma_cookie_t cookie, 672173acc7cSZhang Wei dma_cookie_t *done, 673173acc7cSZhang Wei dma_cookie_t *used) 674173acc7cSZhang Wei { 675173acc7cSZhang Wei struct fsl_dma_chan *fsl_chan = to_fsl_chan(chan); 676173acc7cSZhang Wei dma_cookie_t last_used; 677173acc7cSZhang Wei dma_cookie_t last_complete; 678173acc7cSZhang Wei 679173acc7cSZhang Wei fsl_chan_ld_cleanup(fsl_chan); 680173acc7cSZhang Wei 681173acc7cSZhang Wei last_used = chan->cookie; 682173acc7cSZhang Wei last_complete = fsl_chan->completed_cookie; 683173acc7cSZhang Wei 684173acc7cSZhang Wei if (done) 685173acc7cSZhang Wei *done = last_complete; 686173acc7cSZhang Wei 687173acc7cSZhang Wei if (used) 688173acc7cSZhang Wei *used = last_used; 689173acc7cSZhang Wei 690173acc7cSZhang Wei return dma_async_is_complete(cookie, last_complete, last_used); 691173acc7cSZhang Wei } 692173acc7cSZhang Wei 693173acc7cSZhang Wei static irqreturn_t fsl_dma_chan_do_interrupt(int irq, void *data) 694173acc7cSZhang Wei { 695173acc7cSZhang Wei struct fsl_dma_chan *fsl_chan = (struct fsl_dma_chan *)data; 69656822843SZhang Wei u32 stat; 6971c62979eSZhang Wei int update_cookie = 0; 6981c62979eSZhang Wei int xfer_ld_q = 0; 699173acc7cSZhang Wei 700173acc7cSZhang Wei stat = get_sr(fsl_chan); 701173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "event: channel %d, stat = 0x%x\n", 702173acc7cSZhang Wei fsl_chan->id, stat); 703173acc7cSZhang Wei set_sr(fsl_chan, stat); /* Clear the event register */ 704173acc7cSZhang Wei 705173acc7cSZhang Wei stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH); 706173acc7cSZhang Wei if (!stat) 707173acc7cSZhang Wei return IRQ_NONE; 708173acc7cSZhang Wei 709173acc7cSZhang Wei if (stat & FSL_DMA_SR_TE) 710173acc7cSZhang Wei dev_err(fsl_chan->dev, "Transfer Error!\n"); 711173acc7cSZhang Wei 712f79abb62SZhang Wei /* Programming Error 713f79abb62SZhang Wei * The DMA_INTERRUPT async_tx is a NULL transfer, which will 714f79abb62SZhang Wei * triger a PE interrupt. 715f79abb62SZhang Wei */ 716f79abb62SZhang Wei if (stat & FSL_DMA_SR_PE) { 717f79abb62SZhang Wei dev_dbg(fsl_chan->dev, "event: Programming Error INT\n"); 718f79abb62SZhang Wei if (get_bcr(fsl_chan) == 0) { 719f79abb62SZhang Wei /* BCR register is 0, this is a DMA_INTERRUPT async_tx. 720f79abb62SZhang Wei * Now, update the completed cookie, and continue the 721f79abb62SZhang Wei * next uncompleted transfer. 722f79abb62SZhang Wei */ 7231c62979eSZhang Wei update_cookie = 1; 7241c62979eSZhang Wei xfer_ld_q = 1; 725f79abb62SZhang Wei } 726f79abb62SZhang Wei stat &= ~FSL_DMA_SR_PE; 727f79abb62SZhang Wei } 728f79abb62SZhang Wei 729173acc7cSZhang Wei /* If the link descriptor segment transfer finishes, 730173acc7cSZhang Wei * we will recycle the used descriptor. 731173acc7cSZhang Wei */ 732173acc7cSZhang Wei if (stat & FSL_DMA_SR_EOSI) { 733173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "event: End-of-segments INT\n"); 73456822843SZhang Wei dev_dbg(fsl_chan->dev, "event: clndar %p, nlndar %p\n", 73556822843SZhang Wei (void *)get_cdar(fsl_chan), (void *)get_ndar(fsl_chan)); 736173acc7cSZhang Wei stat &= ~FSL_DMA_SR_EOSI; 7371c62979eSZhang Wei update_cookie = 1; 7381c62979eSZhang Wei } 7391c62979eSZhang Wei 7401c62979eSZhang Wei /* For MPC8349, EOCDI event need to update cookie 7411c62979eSZhang Wei * and start the next transfer if it exist. 7421c62979eSZhang Wei */ 7431c62979eSZhang Wei if (stat & FSL_DMA_SR_EOCDI) { 7441c62979eSZhang Wei dev_dbg(fsl_chan->dev, "event: End-of-Chain link INT\n"); 7451c62979eSZhang Wei stat &= ~FSL_DMA_SR_EOCDI; 7461c62979eSZhang Wei update_cookie = 1; 7471c62979eSZhang Wei xfer_ld_q = 1; 748173acc7cSZhang Wei } 749173acc7cSZhang Wei 750173acc7cSZhang Wei /* If it current transfer is the end-of-transfer, 751173acc7cSZhang Wei * we should clear the Channel Start bit for 752173acc7cSZhang Wei * prepare next transfer. 753173acc7cSZhang Wei */ 7541c62979eSZhang Wei if (stat & FSL_DMA_SR_EOLNI) { 755173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "event: End-of-link INT\n"); 756173acc7cSZhang Wei stat &= ~FSL_DMA_SR_EOLNI; 7571c62979eSZhang Wei xfer_ld_q = 1; 758173acc7cSZhang Wei } 759173acc7cSZhang Wei 7601c62979eSZhang Wei if (update_cookie) 7611c62979eSZhang Wei fsl_dma_update_completed_cookie(fsl_chan); 7621c62979eSZhang Wei if (xfer_ld_q) 7631c62979eSZhang Wei fsl_chan_xfer_ld_queue(fsl_chan); 764173acc7cSZhang Wei if (stat) 765173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "event: unhandled sr 0x%02x\n", 766173acc7cSZhang Wei stat); 767173acc7cSZhang Wei 768173acc7cSZhang Wei dev_dbg(fsl_chan->dev, "event: Exit\n"); 769173acc7cSZhang Wei tasklet_schedule(&fsl_chan->tasklet); 770173acc7cSZhang Wei return IRQ_HANDLED; 771173acc7cSZhang Wei } 772173acc7cSZhang Wei 773173acc7cSZhang Wei static irqreturn_t fsl_dma_do_interrupt(int irq, void *data) 774173acc7cSZhang Wei { 775173acc7cSZhang Wei struct fsl_dma_device *fdev = (struct fsl_dma_device *)data; 776173acc7cSZhang Wei u32 gsr; 777173acc7cSZhang Wei int ch_nr; 778173acc7cSZhang Wei 779173acc7cSZhang Wei gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->reg_base) 780173acc7cSZhang Wei : in_le32(fdev->reg_base); 781173acc7cSZhang Wei ch_nr = (32 - ffs(gsr)) / 8; 782173acc7cSZhang Wei 783173acc7cSZhang Wei return fdev->chan[ch_nr] ? fsl_dma_chan_do_interrupt(irq, 784173acc7cSZhang Wei fdev->chan[ch_nr]) : IRQ_NONE; 785173acc7cSZhang Wei } 786173acc7cSZhang Wei 787173acc7cSZhang Wei static void dma_do_tasklet(unsigned long data) 788173acc7cSZhang Wei { 789173acc7cSZhang Wei struct fsl_dma_chan *fsl_chan = (struct fsl_dma_chan *)data; 790173acc7cSZhang Wei fsl_chan_ld_cleanup(fsl_chan); 791173acc7cSZhang Wei } 792173acc7cSZhang Wei 79377cd62e8STimur Tabi static int __devinit fsl_dma_chan_probe(struct fsl_dma_device *fdev, 79477cd62e8STimur Tabi struct device_node *node, u32 feature, const char *compatible) 795173acc7cSZhang Wei { 796173acc7cSZhang Wei struct fsl_dma_chan *new_fsl_chan; 797173acc7cSZhang Wei int err; 798173acc7cSZhang Wei 799173acc7cSZhang Wei /* alloc channel */ 800173acc7cSZhang Wei new_fsl_chan = kzalloc(sizeof(struct fsl_dma_chan), GFP_KERNEL); 801173acc7cSZhang Wei if (!new_fsl_chan) { 80277cd62e8STimur Tabi dev_err(fdev->dev, "No free memory for allocating " 803173acc7cSZhang Wei "dma channels!\n"); 80451ee87f2SLi Yang return -ENOMEM; 805173acc7cSZhang Wei } 806173acc7cSZhang Wei 807173acc7cSZhang Wei /* get dma channel register base */ 80877cd62e8STimur Tabi err = of_address_to_resource(node, 0, &new_fsl_chan->reg); 809173acc7cSZhang Wei if (err) { 81077cd62e8STimur Tabi dev_err(fdev->dev, "Can't get %s property 'reg'\n", 81177cd62e8STimur Tabi node->full_name); 81251ee87f2SLi Yang goto err_no_reg; 813173acc7cSZhang Wei } 814173acc7cSZhang Wei 81577cd62e8STimur Tabi new_fsl_chan->feature = feature; 816173acc7cSZhang Wei 817173acc7cSZhang Wei if (!fdev->feature) 818173acc7cSZhang Wei fdev->feature = new_fsl_chan->feature; 819173acc7cSZhang Wei 820173acc7cSZhang Wei /* If the DMA device's feature is different than its channels', 821173acc7cSZhang Wei * report the bug. 822173acc7cSZhang Wei */ 823173acc7cSZhang Wei WARN_ON(fdev->feature != new_fsl_chan->feature); 824173acc7cSZhang Wei 8256527de6dSDan Williams new_fsl_chan->dev = fdev->dev; 826173acc7cSZhang Wei new_fsl_chan->reg_base = ioremap(new_fsl_chan->reg.start, 827173acc7cSZhang Wei new_fsl_chan->reg.end - new_fsl_chan->reg.start + 1); 828173acc7cSZhang Wei 829173acc7cSZhang Wei new_fsl_chan->id = ((new_fsl_chan->reg.start - 0x100) & 0xfff) >> 7; 830173acc7cSZhang Wei if (new_fsl_chan->id > FSL_DMA_MAX_CHANS_PER_DEVICE) { 83177cd62e8STimur Tabi dev_err(fdev->dev, "There is no %d channel!\n", 832173acc7cSZhang Wei new_fsl_chan->id); 833173acc7cSZhang Wei err = -EINVAL; 83451ee87f2SLi Yang goto err_no_chan; 835173acc7cSZhang Wei } 836173acc7cSZhang Wei fdev->chan[new_fsl_chan->id] = new_fsl_chan; 837173acc7cSZhang Wei tasklet_init(&new_fsl_chan->tasklet, dma_do_tasklet, 838173acc7cSZhang Wei (unsigned long)new_fsl_chan); 839173acc7cSZhang Wei 840173acc7cSZhang Wei /* Init the channel */ 841173acc7cSZhang Wei dma_init(new_fsl_chan); 842173acc7cSZhang Wei 843173acc7cSZhang Wei /* Clear cdar registers */ 844173acc7cSZhang Wei set_cdar(new_fsl_chan, 0); 845173acc7cSZhang Wei 846173acc7cSZhang Wei switch (new_fsl_chan->feature & FSL_DMA_IP_MASK) { 847173acc7cSZhang Wei case FSL_DMA_IP_85XX: 848173acc7cSZhang Wei new_fsl_chan->toggle_ext_start = fsl_chan_toggle_ext_start; 849173acc7cSZhang Wei new_fsl_chan->toggle_ext_pause = fsl_chan_toggle_ext_pause; 850173acc7cSZhang Wei case FSL_DMA_IP_83XX: 851173acc7cSZhang Wei new_fsl_chan->set_src_loop_size = fsl_chan_set_src_loop_size; 852173acc7cSZhang Wei new_fsl_chan->set_dest_loop_size = fsl_chan_set_dest_loop_size; 853173acc7cSZhang Wei } 854173acc7cSZhang Wei 855173acc7cSZhang Wei spin_lock_init(&new_fsl_chan->desc_lock); 856173acc7cSZhang Wei INIT_LIST_HEAD(&new_fsl_chan->ld_queue); 857173acc7cSZhang Wei 858173acc7cSZhang Wei new_fsl_chan->common.device = &fdev->common; 859173acc7cSZhang Wei 860173acc7cSZhang Wei /* Add the channel to DMA device channel list */ 861173acc7cSZhang Wei list_add_tail(&new_fsl_chan->common.device_node, 862173acc7cSZhang Wei &fdev->common.channels); 863173acc7cSZhang Wei fdev->common.chancnt++; 864173acc7cSZhang Wei 86577cd62e8STimur Tabi new_fsl_chan->irq = irq_of_parse_and_map(node, 0); 866173acc7cSZhang Wei if (new_fsl_chan->irq != NO_IRQ) { 867173acc7cSZhang Wei err = request_irq(new_fsl_chan->irq, 868173acc7cSZhang Wei &fsl_dma_chan_do_interrupt, IRQF_SHARED, 869173acc7cSZhang Wei "fsldma-channel", new_fsl_chan); 870173acc7cSZhang Wei if (err) { 87177cd62e8STimur Tabi dev_err(fdev->dev, "DMA channel %s request_irq error " 87277cd62e8STimur Tabi "with return %d\n", node->full_name, err); 87351ee87f2SLi Yang goto err_no_irq; 874173acc7cSZhang Wei } 875173acc7cSZhang Wei } 876173acc7cSZhang Wei 87777cd62e8STimur Tabi dev_info(fdev->dev, "#%d (%s), irq %d\n", new_fsl_chan->id, 878169d5f66SPeter Korsgaard compatible, 879169d5f66SPeter Korsgaard new_fsl_chan->irq != NO_IRQ ? new_fsl_chan->irq : fdev->irq); 880173acc7cSZhang Wei 881173acc7cSZhang Wei return 0; 88251ee87f2SLi Yang 88351ee87f2SLi Yang err_no_irq: 884173acc7cSZhang Wei list_del(&new_fsl_chan->common.device_node); 88551ee87f2SLi Yang err_no_chan: 88651ee87f2SLi Yang iounmap(new_fsl_chan->reg_base); 88751ee87f2SLi Yang err_no_reg: 888173acc7cSZhang Wei kfree(new_fsl_chan); 889173acc7cSZhang Wei return err; 890173acc7cSZhang Wei } 891173acc7cSZhang Wei 89277cd62e8STimur Tabi static void fsl_dma_chan_remove(struct fsl_dma_chan *fchan) 893173acc7cSZhang Wei { 8946782dfe4SPeter Korsgaard if (fchan->irq != NO_IRQ) 89577cd62e8STimur Tabi free_irq(fchan->irq, fchan); 89677cd62e8STimur Tabi list_del(&fchan->common.device_node); 89777cd62e8STimur Tabi iounmap(fchan->reg_base); 89877cd62e8STimur Tabi kfree(fchan); 899173acc7cSZhang Wei } 900173acc7cSZhang Wei 901173acc7cSZhang Wei static int __devinit of_fsl_dma_probe(struct of_device *dev, 902173acc7cSZhang Wei const struct of_device_id *match) 903173acc7cSZhang Wei { 904173acc7cSZhang Wei int err; 905173acc7cSZhang Wei struct fsl_dma_device *fdev; 90677cd62e8STimur Tabi struct device_node *child; 907173acc7cSZhang Wei 908173acc7cSZhang Wei fdev = kzalloc(sizeof(struct fsl_dma_device), GFP_KERNEL); 909173acc7cSZhang Wei if (!fdev) { 910173acc7cSZhang Wei dev_err(&dev->dev, "No enough memory for 'priv'\n"); 91151ee87f2SLi Yang return -ENOMEM; 912173acc7cSZhang Wei } 913173acc7cSZhang Wei fdev->dev = &dev->dev; 914173acc7cSZhang Wei INIT_LIST_HEAD(&fdev->common.channels); 915173acc7cSZhang Wei 916173acc7cSZhang Wei /* get DMA controller register base */ 917173acc7cSZhang Wei err = of_address_to_resource(dev->node, 0, &fdev->reg); 918173acc7cSZhang Wei if (err) { 919173acc7cSZhang Wei dev_err(&dev->dev, "Can't get %s property 'reg'\n", 920173acc7cSZhang Wei dev->node->full_name); 92151ee87f2SLi Yang goto err_no_reg; 922173acc7cSZhang Wei } 923173acc7cSZhang Wei 924173acc7cSZhang Wei dev_info(&dev->dev, "Probe the Freescale DMA driver for %s " 92556822843SZhang Wei "controller at %p...\n", 92656822843SZhang Wei match->compatible, (void *)fdev->reg.start); 927173acc7cSZhang Wei fdev->reg_base = ioremap(fdev->reg.start, fdev->reg.end 928173acc7cSZhang Wei - fdev->reg.start + 1); 929173acc7cSZhang Wei 930173acc7cSZhang Wei dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask); 931173acc7cSZhang Wei dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask); 932173acc7cSZhang Wei fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources; 933173acc7cSZhang Wei fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources; 9342187c269SZhang Wei fdev->common.device_prep_dma_interrupt = fsl_dma_prep_interrupt; 935173acc7cSZhang Wei fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy; 936173acc7cSZhang Wei fdev->common.device_is_tx_complete = fsl_dma_is_complete; 937173acc7cSZhang Wei fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending; 938173acc7cSZhang Wei fdev->common.dev = &dev->dev; 939173acc7cSZhang Wei 94077cd62e8STimur Tabi fdev->irq = irq_of_parse_and_map(dev->node, 0); 94177cd62e8STimur Tabi if (fdev->irq != NO_IRQ) { 94277cd62e8STimur Tabi err = request_irq(fdev->irq, &fsl_dma_do_interrupt, IRQF_SHARED, 943173acc7cSZhang Wei "fsldma-device", fdev); 944173acc7cSZhang Wei if (err) { 945173acc7cSZhang Wei dev_err(&dev->dev, "DMA device request_irq error " 946173acc7cSZhang Wei "with return %d\n", err); 947173acc7cSZhang Wei goto err; 948173acc7cSZhang Wei } 949173acc7cSZhang Wei } 950173acc7cSZhang Wei 951173acc7cSZhang Wei dev_set_drvdata(&(dev->dev), fdev); 95277cd62e8STimur Tabi 95377cd62e8STimur Tabi /* We cannot use of_platform_bus_probe() because there is no 95477cd62e8STimur Tabi * of_platform_bus_remove. Instead, we manually instantiate every DMA 95577cd62e8STimur Tabi * channel object. 95677cd62e8STimur Tabi */ 95777cd62e8STimur Tabi for_each_child_of_node(dev->node, child) { 95877cd62e8STimur Tabi if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) 95977cd62e8STimur Tabi fsl_dma_chan_probe(fdev, child, 96077cd62e8STimur Tabi FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN, 96177cd62e8STimur Tabi "fsl,eloplus-dma-channel"); 96277cd62e8STimur Tabi if (of_device_is_compatible(child, "fsl,elo-dma-channel")) 96377cd62e8STimur Tabi fsl_dma_chan_probe(fdev, child, 96477cd62e8STimur Tabi FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN, 96577cd62e8STimur Tabi "fsl,elo-dma-channel"); 96677cd62e8STimur Tabi } 967173acc7cSZhang Wei 968173acc7cSZhang Wei dma_async_device_register(&fdev->common); 969173acc7cSZhang Wei return 0; 970173acc7cSZhang Wei 971173acc7cSZhang Wei err: 972173acc7cSZhang Wei iounmap(fdev->reg_base); 97351ee87f2SLi Yang err_no_reg: 974173acc7cSZhang Wei kfree(fdev); 975173acc7cSZhang Wei return err; 976173acc7cSZhang Wei } 977173acc7cSZhang Wei 97877cd62e8STimur Tabi static int of_fsl_dma_remove(struct of_device *of_dev) 97977cd62e8STimur Tabi { 98077cd62e8STimur Tabi struct fsl_dma_device *fdev; 98177cd62e8STimur Tabi unsigned int i; 98277cd62e8STimur Tabi 98377cd62e8STimur Tabi fdev = dev_get_drvdata(&of_dev->dev); 98477cd62e8STimur Tabi 98577cd62e8STimur Tabi dma_async_device_unregister(&fdev->common); 98677cd62e8STimur Tabi 98777cd62e8STimur Tabi for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) 98877cd62e8STimur Tabi if (fdev->chan[i]) 98977cd62e8STimur Tabi fsl_dma_chan_remove(fdev->chan[i]); 99077cd62e8STimur Tabi 99177cd62e8STimur Tabi if (fdev->irq != NO_IRQ) 99277cd62e8STimur Tabi free_irq(fdev->irq, fdev); 99377cd62e8STimur Tabi 99477cd62e8STimur Tabi iounmap(fdev->reg_base); 99577cd62e8STimur Tabi 99677cd62e8STimur Tabi kfree(fdev); 99777cd62e8STimur Tabi dev_set_drvdata(&of_dev->dev, NULL); 99877cd62e8STimur Tabi 99977cd62e8STimur Tabi return 0; 100077cd62e8STimur Tabi } 100177cd62e8STimur Tabi 1002173acc7cSZhang Wei static struct of_device_id of_fsl_dma_ids[] = { 1003049c9d45SKumar Gala { .compatible = "fsl,eloplus-dma", }, 1004049c9d45SKumar Gala { .compatible = "fsl,elo-dma", }, 1005173acc7cSZhang Wei {} 1006173acc7cSZhang Wei }; 1007173acc7cSZhang Wei 1008173acc7cSZhang Wei static struct of_platform_driver of_fsl_dma_driver = { 100977cd62e8STimur Tabi .name = "fsl-elo-dma", 1010173acc7cSZhang Wei .match_table = of_fsl_dma_ids, 1011173acc7cSZhang Wei .probe = of_fsl_dma_probe, 101277cd62e8STimur Tabi .remove = of_fsl_dma_remove, 1013173acc7cSZhang Wei }; 1014173acc7cSZhang Wei 1015173acc7cSZhang Wei static __init int of_fsl_dma_init(void) 1016173acc7cSZhang Wei { 101777cd62e8STimur Tabi int ret; 101877cd62e8STimur Tabi 101977cd62e8STimur Tabi pr_info("Freescale Elo / Elo Plus DMA driver\n"); 102077cd62e8STimur Tabi 102177cd62e8STimur Tabi ret = of_register_platform_driver(&of_fsl_dma_driver); 102277cd62e8STimur Tabi if (ret) 102377cd62e8STimur Tabi pr_err("fsldma: failed to register platform driver\n"); 102477cd62e8STimur Tabi 102577cd62e8STimur Tabi return ret; 1026173acc7cSZhang Wei } 1027173acc7cSZhang Wei 102877cd62e8STimur Tabi static void __exit of_fsl_dma_exit(void) 102977cd62e8STimur Tabi { 103077cd62e8STimur Tabi of_unregister_platform_driver(&of_fsl_dma_driver); 103177cd62e8STimur Tabi } 103277cd62e8STimur Tabi 1033173acc7cSZhang Wei subsys_initcall(of_fsl_dma_init); 103477cd62e8STimur Tabi module_exit(of_fsl_dma_exit); 103577cd62e8STimur Tabi 103677cd62e8STimur Tabi MODULE_DESCRIPTION("Freescale Elo / Elo Plus DMA driver"); 103777cd62e8STimur Tabi MODULE_LICENSE("GPL"); 1038