1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * drivers/dma/fsl-edma.c 4 * 5 * Copyright 2013-2014 Freescale Semiconductor, Inc. 6 * 7 * Driver for the Freescale eDMA engine with flexible channel multiplexing 8 * capability for DMA request sources. The eDMA block can be found on some 9 * Vybrid and Layerscape SoCs. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/interrupt.h> 14 #include <linux/clk.h> 15 #include <linux/of.h> 16 #include <linux/of_device.h> 17 #include <linux/of_address.h> 18 #include <linux/of_irq.h> 19 #include <linux/of_dma.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/pm_domain.h> 23 24 #include "fsl-edma-common.h" 25 26 #define ARGS_RX BIT(0) 27 #define ARGS_REMOTE BIT(1) 28 #define ARGS_MULTI_FIFO BIT(2) 29 30 static void fsl_edma_synchronize(struct dma_chan *chan) 31 { 32 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 33 34 vchan_synchronize(&fsl_chan->vchan); 35 } 36 37 static irqreturn_t fsl_edma_tx_handler(int irq, void *dev_id) 38 { 39 struct fsl_edma_engine *fsl_edma = dev_id; 40 unsigned int intr, ch; 41 struct edma_regs *regs = &fsl_edma->regs; 42 43 intr = edma_readl(fsl_edma, regs->intl); 44 if (!intr) 45 return IRQ_NONE; 46 47 for (ch = 0; ch < fsl_edma->n_chans; ch++) { 48 if (intr & (0x1 << ch)) { 49 edma_writeb(fsl_edma, EDMA_CINT_CINT(ch), regs->cint); 50 fsl_edma_tx_chan_handler(&fsl_edma->chans[ch]); 51 } 52 } 53 return IRQ_HANDLED; 54 } 55 56 static irqreturn_t fsl_edma3_tx_handler(int irq, void *dev_id) 57 { 58 struct fsl_edma_chan *fsl_chan = dev_id; 59 unsigned int intr; 60 61 intr = edma_readl_chreg(fsl_chan, ch_int); 62 if (!intr) 63 return IRQ_HANDLED; 64 65 edma_writel_chreg(fsl_chan, 1, ch_int); 66 67 fsl_edma_tx_chan_handler(fsl_chan); 68 69 return IRQ_HANDLED; 70 } 71 72 static irqreturn_t fsl_edma_err_handler(int irq, void *dev_id) 73 { 74 struct fsl_edma_engine *fsl_edma = dev_id; 75 unsigned int err, ch; 76 struct edma_regs *regs = &fsl_edma->regs; 77 78 err = edma_readl(fsl_edma, regs->errl); 79 if (!err) 80 return IRQ_NONE; 81 82 for (ch = 0; ch < fsl_edma->n_chans; ch++) { 83 if (err & (0x1 << ch)) { 84 fsl_edma_disable_request(&fsl_edma->chans[ch]); 85 edma_writeb(fsl_edma, EDMA_CERR_CERR(ch), regs->cerr); 86 fsl_edma_err_chan_handler(&fsl_edma->chans[ch]); 87 } 88 } 89 return IRQ_HANDLED; 90 } 91 92 static irqreturn_t fsl_edma_irq_handler(int irq, void *dev_id) 93 { 94 if (fsl_edma_tx_handler(irq, dev_id) == IRQ_HANDLED) 95 return IRQ_HANDLED; 96 97 return fsl_edma_err_handler(irq, dev_id); 98 } 99 100 static struct dma_chan *fsl_edma_xlate(struct of_phandle_args *dma_spec, 101 struct of_dma *ofdma) 102 { 103 struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data; 104 struct dma_chan *chan, *_chan; 105 struct fsl_edma_chan *fsl_chan; 106 u32 dmamux_nr = fsl_edma->drvdata->dmamuxs; 107 unsigned long chans_per_mux = fsl_edma->n_chans / dmamux_nr; 108 109 if (dma_spec->args_count != 2) 110 return NULL; 111 112 mutex_lock(&fsl_edma->fsl_edma_mutex); 113 list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, device_node) { 114 if (chan->client_count) 115 continue; 116 if ((chan->chan_id / chans_per_mux) == dma_spec->args[0]) { 117 chan = dma_get_slave_channel(chan); 118 if (chan) { 119 chan->device->privatecnt++; 120 fsl_chan = to_fsl_edma_chan(chan); 121 fsl_chan->slave_id = dma_spec->args[1]; 122 fsl_edma_chan_mux(fsl_chan, fsl_chan->slave_id, 123 true); 124 mutex_unlock(&fsl_edma->fsl_edma_mutex); 125 return chan; 126 } 127 } 128 } 129 mutex_unlock(&fsl_edma->fsl_edma_mutex); 130 return NULL; 131 } 132 133 static struct dma_chan *fsl_edma3_xlate(struct of_phandle_args *dma_spec, 134 struct of_dma *ofdma) 135 { 136 struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data; 137 struct dma_chan *chan, *_chan; 138 struct fsl_edma_chan *fsl_chan; 139 bool b_chmux; 140 int i; 141 142 if (dma_spec->args_count != 3) 143 return NULL; 144 145 b_chmux = !!(fsl_edma->drvdata->flags & FSL_EDMA_DRV_HAS_CHMUX); 146 147 mutex_lock(&fsl_edma->fsl_edma_mutex); 148 list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, 149 device_node) { 150 151 if (chan->client_count) 152 continue; 153 154 fsl_chan = to_fsl_edma_chan(chan); 155 i = fsl_chan - fsl_edma->chans; 156 157 fsl_chan->priority = dma_spec->args[1]; 158 fsl_chan->is_rxchan = dma_spec->args[2] & ARGS_RX; 159 fsl_chan->is_remote = dma_spec->args[2] & ARGS_REMOTE; 160 fsl_chan->is_multi_fifo = dma_spec->args[2] & ARGS_MULTI_FIFO; 161 162 if (!b_chmux && i == dma_spec->args[0]) { 163 chan = dma_get_slave_channel(chan); 164 chan->device->privatecnt++; 165 mutex_unlock(&fsl_edma->fsl_edma_mutex); 166 return chan; 167 } else if (b_chmux && !fsl_chan->srcid) { 168 /* if controller support channel mux, choose a free channel */ 169 chan = dma_get_slave_channel(chan); 170 chan->device->privatecnt++; 171 fsl_chan->srcid = dma_spec->args[0]; 172 mutex_unlock(&fsl_edma->fsl_edma_mutex); 173 return chan; 174 } 175 } 176 mutex_unlock(&fsl_edma->fsl_edma_mutex); 177 return NULL; 178 } 179 180 static int 181 fsl_edma_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) 182 { 183 int ret; 184 185 edma_writel(fsl_edma, ~0, fsl_edma->regs.intl); 186 187 fsl_edma->txirq = platform_get_irq_byname(pdev, "edma-tx"); 188 if (fsl_edma->txirq < 0) 189 return fsl_edma->txirq; 190 191 fsl_edma->errirq = platform_get_irq_byname(pdev, "edma-err"); 192 if (fsl_edma->errirq < 0) 193 return fsl_edma->errirq; 194 195 if (fsl_edma->txirq == fsl_edma->errirq) { 196 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq, 197 fsl_edma_irq_handler, 0, "eDMA", fsl_edma); 198 if (ret) { 199 dev_err(&pdev->dev, "Can't register eDMA IRQ.\n"); 200 return ret; 201 } 202 } else { 203 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq, 204 fsl_edma_tx_handler, 0, "eDMA tx", fsl_edma); 205 if (ret) { 206 dev_err(&pdev->dev, "Can't register eDMA tx IRQ.\n"); 207 return ret; 208 } 209 210 ret = devm_request_irq(&pdev->dev, fsl_edma->errirq, 211 fsl_edma_err_handler, 0, "eDMA err", fsl_edma); 212 if (ret) { 213 dev_err(&pdev->dev, "Can't register eDMA err IRQ.\n"); 214 return ret; 215 } 216 } 217 218 return 0; 219 } 220 221 static int fsl_edma3_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) 222 { 223 int ret; 224 int i; 225 226 for (i = 0; i < fsl_edma->n_chans; i++) { 227 228 struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i]; 229 230 if (fsl_edma->chan_masked & BIT(i)) 231 continue; 232 233 /* request channel irq */ 234 fsl_chan->txirq = platform_get_irq(pdev, i); 235 if (fsl_chan->txirq < 0) { 236 dev_err(&pdev->dev, "Can't get chan %d's irq.\n", i); 237 return -EINVAL; 238 } 239 240 ret = devm_request_irq(&pdev->dev, fsl_chan->txirq, 241 fsl_edma3_tx_handler, IRQF_SHARED, 242 fsl_chan->chan_name, fsl_chan); 243 if (ret) { 244 dev_err(&pdev->dev, "Can't register chan%d's IRQ.\n", i); 245 return -EINVAL; 246 } 247 } 248 249 return 0; 250 } 251 252 static int 253 fsl_edma2_irq_init(struct platform_device *pdev, 254 struct fsl_edma_engine *fsl_edma) 255 { 256 int i, ret, irq; 257 int count; 258 259 edma_writel(fsl_edma, ~0, fsl_edma->regs.intl); 260 261 count = platform_irq_count(pdev); 262 dev_dbg(&pdev->dev, "%s Found %d interrupts\r\n", __func__, count); 263 if (count <= 2) { 264 dev_err(&pdev->dev, "Interrupts in DTS not correct.\n"); 265 return -EINVAL; 266 } 267 /* 268 * 16 channel independent interrupts + 1 error interrupt on i.mx7ulp. 269 * 2 channel share one interrupt, for example, ch0/ch16, ch1/ch17... 270 * For now, just simply request irq without IRQF_SHARED flag, since 16 271 * channels are enough on i.mx7ulp whose M4 domain own some peripherals. 272 */ 273 for (i = 0; i < count; i++) { 274 irq = platform_get_irq(pdev, i); 275 if (irq < 0) 276 return -ENXIO; 277 278 /* The last IRQ is for eDMA err */ 279 if (i == count - 1) 280 ret = devm_request_irq(&pdev->dev, irq, 281 fsl_edma_err_handler, 282 0, "eDMA2-ERR", fsl_edma); 283 else 284 ret = devm_request_irq(&pdev->dev, irq, 285 fsl_edma_tx_handler, 0, 286 fsl_edma->chans[i].chan_name, 287 fsl_edma); 288 if (ret) 289 return ret; 290 } 291 292 return 0; 293 } 294 295 static void fsl_edma_irq_exit( 296 struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) 297 { 298 if (fsl_edma->txirq == fsl_edma->errirq) { 299 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma); 300 } else { 301 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma); 302 devm_free_irq(&pdev->dev, fsl_edma->errirq, fsl_edma); 303 } 304 } 305 306 static void fsl_disable_clocks(struct fsl_edma_engine *fsl_edma, int nr_clocks) 307 { 308 int i; 309 310 for (i = 0; i < nr_clocks; i++) 311 clk_disable_unprepare(fsl_edma->muxclk[i]); 312 } 313 314 static struct fsl_edma_drvdata vf610_data = { 315 .dmamuxs = DMAMUX_NR, 316 .flags = FSL_EDMA_DRV_WRAP_IO, 317 .chreg_off = EDMA_TCD, 318 .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd), 319 .setup_irq = fsl_edma_irq_init, 320 }; 321 322 static struct fsl_edma_drvdata ls1028a_data = { 323 .dmamuxs = DMAMUX_NR, 324 .flags = FSL_EDMA_DRV_MUX_SWAP | FSL_EDMA_DRV_WRAP_IO, 325 .chreg_off = EDMA_TCD, 326 .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd), 327 .setup_irq = fsl_edma_irq_init, 328 }; 329 330 static struct fsl_edma_drvdata imx7ulp_data = { 331 .dmamuxs = 1, 332 .chreg_off = EDMA_TCD, 333 .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd), 334 .flags = FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_CONFIG32, 335 .setup_irq = fsl_edma2_irq_init, 336 }; 337 338 static struct fsl_edma_drvdata imx8qm_data = { 339 .flags = FSL_EDMA_DRV_HAS_PD | FSL_EDMA_DRV_EDMA3, 340 .chreg_space_sz = 0x10000, 341 .chreg_off = 0x10000, 342 .setup_irq = fsl_edma3_irq_init, 343 }; 344 345 static struct fsl_edma_drvdata imx8qm_audio_data = { 346 .flags = FSL_EDMA_DRV_QUIRK_SWAPPED | FSL_EDMA_DRV_HAS_PD | FSL_EDMA_DRV_EDMA3, 347 .chreg_space_sz = 0x10000, 348 .chreg_off = 0x10000, 349 .setup_irq = fsl_edma3_irq_init, 350 }; 351 352 static struct fsl_edma_drvdata imx93_data3 = { 353 .flags = FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA3, 354 .chreg_space_sz = 0x10000, 355 .chreg_off = 0x10000, 356 .setup_irq = fsl_edma3_irq_init, 357 }; 358 359 static struct fsl_edma_drvdata imx93_data4 = { 360 .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA4, 361 .chreg_space_sz = 0x8000, 362 .chreg_off = 0x10000, 363 .setup_irq = fsl_edma3_irq_init, 364 }; 365 366 static const struct of_device_id fsl_edma_dt_ids[] = { 367 { .compatible = "fsl,vf610-edma", .data = &vf610_data}, 368 { .compatible = "fsl,ls1028a-edma", .data = &ls1028a_data}, 369 { .compatible = "fsl,imx7ulp-edma", .data = &imx7ulp_data}, 370 { .compatible = "fsl,imx8qm-edma", .data = &imx8qm_data}, 371 { .compatible = "fsl,imx8qm-adma", .data = &imx8qm_audio_data}, 372 { .compatible = "fsl,imx93-edma3", .data = &imx93_data3}, 373 { .compatible = "fsl,imx93-edma4", .data = &imx93_data4}, 374 { /* sentinel */ } 375 }; 376 MODULE_DEVICE_TABLE(of, fsl_edma_dt_ids); 377 378 static int fsl_edma3_attach_pd(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) 379 { 380 struct fsl_edma_chan *fsl_chan; 381 struct device_link *link; 382 struct device *pd_chan; 383 struct device *dev; 384 int i; 385 386 dev = &pdev->dev; 387 388 for (i = 0; i < fsl_edma->n_chans; i++) { 389 if (fsl_edma->chan_masked & BIT(i)) 390 continue; 391 392 fsl_chan = &fsl_edma->chans[i]; 393 394 pd_chan = dev_pm_domain_attach_by_id(dev, i); 395 if (IS_ERR_OR_NULL(pd_chan)) { 396 dev_err(dev, "Failed attach pd %d\n", i); 397 return -EINVAL; 398 } 399 400 link = device_link_add(dev, pd_chan, DL_FLAG_STATELESS | 401 DL_FLAG_PM_RUNTIME | 402 DL_FLAG_RPM_ACTIVE); 403 if (IS_ERR(link)) { 404 dev_err(dev, "Failed to add device_link to %d: %ld\n", i, 405 PTR_ERR(link)); 406 return -EINVAL; 407 } 408 409 fsl_chan->pd_dev = pd_chan; 410 411 pm_runtime_use_autosuspend(fsl_chan->pd_dev); 412 pm_runtime_set_autosuspend_delay(fsl_chan->pd_dev, 200); 413 pm_runtime_set_active(fsl_chan->pd_dev); 414 } 415 416 return 0; 417 } 418 419 static int fsl_edma_probe(struct platform_device *pdev) 420 { 421 const struct of_device_id *of_id = 422 of_match_device(fsl_edma_dt_ids, &pdev->dev); 423 struct device_node *np = pdev->dev.of_node; 424 struct fsl_edma_engine *fsl_edma; 425 const struct fsl_edma_drvdata *drvdata = NULL; 426 u32 chan_mask[2] = {0, 0}; 427 struct edma_regs *regs; 428 int chans; 429 int ret, i; 430 431 if (of_id) 432 drvdata = of_id->data; 433 if (!drvdata) { 434 dev_err(&pdev->dev, "unable to find driver data\n"); 435 return -EINVAL; 436 } 437 438 ret = of_property_read_u32(np, "dma-channels", &chans); 439 if (ret) { 440 dev_err(&pdev->dev, "Can't get dma-channels.\n"); 441 return ret; 442 } 443 444 fsl_edma = devm_kzalloc(&pdev->dev, struct_size(fsl_edma, chans, chans), 445 GFP_KERNEL); 446 if (!fsl_edma) 447 return -ENOMEM; 448 449 fsl_edma->drvdata = drvdata; 450 fsl_edma->n_chans = chans; 451 mutex_init(&fsl_edma->fsl_edma_mutex); 452 453 fsl_edma->membase = devm_platform_ioremap_resource(pdev, 0); 454 if (IS_ERR(fsl_edma->membase)) 455 return PTR_ERR(fsl_edma->membase); 456 457 if (!(drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)) { 458 fsl_edma_setup_regs(fsl_edma); 459 regs = &fsl_edma->regs; 460 } 461 462 if (drvdata->flags & FSL_EDMA_DRV_HAS_DMACLK) { 463 fsl_edma->dmaclk = devm_clk_get_enabled(&pdev->dev, "dma"); 464 if (IS_ERR(fsl_edma->dmaclk)) { 465 dev_err(&pdev->dev, "Missing DMA block clock.\n"); 466 return PTR_ERR(fsl_edma->dmaclk); 467 } 468 } 469 470 if (drvdata->flags & FSL_EDMA_DRV_HAS_CHCLK) { 471 fsl_edma->chclk = devm_clk_get_enabled(&pdev->dev, "mp"); 472 if (IS_ERR(fsl_edma->chclk)) { 473 dev_err(&pdev->dev, "Missing MP block clock.\n"); 474 return PTR_ERR(fsl_edma->chclk); 475 } 476 } 477 478 ret = of_property_read_variable_u32_array(np, "dma-channel-mask", chan_mask, 1, 2); 479 480 if (ret > 0) { 481 fsl_edma->chan_masked = chan_mask[1]; 482 fsl_edma->chan_masked <<= 32; 483 fsl_edma->chan_masked |= chan_mask[0]; 484 } 485 486 for (i = 0; i < fsl_edma->drvdata->dmamuxs; i++) { 487 char clkname[32]; 488 489 /* eDMAv3 mux register move to TCD area if ch_mux exist */ 490 if (drvdata->flags & FSL_EDMA_DRV_SPLIT_REG) 491 break; 492 493 fsl_edma->muxbase[i] = devm_platform_ioremap_resource(pdev, 494 1 + i); 495 if (IS_ERR(fsl_edma->muxbase[i])) { 496 /* on error: disable all previously enabled clks */ 497 fsl_disable_clocks(fsl_edma, i); 498 return PTR_ERR(fsl_edma->muxbase[i]); 499 } 500 501 sprintf(clkname, "dmamux%d", i); 502 fsl_edma->muxclk[i] = devm_clk_get_enabled(&pdev->dev, clkname); 503 if (IS_ERR(fsl_edma->muxclk[i])) { 504 dev_err(&pdev->dev, "Missing DMAMUX block clock.\n"); 505 /* on error: disable all previously enabled clks */ 506 return PTR_ERR(fsl_edma->muxclk[i]); 507 } 508 } 509 510 fsl_edma->big_endian = of_property_read_bool(np, "big-endian"); 511 512 if (drvdata->flags & FSL_EDMA_DRV_HAS_PD) { 513 ret = fsl_edma3_attach_pd(pdev, fsl_edma); 514 if (ret) 515 return ret; 516 } 517 518 INIT_LIST_HEAD(&fsl_edma->dma_dev.channels); 519 for (i = 0; i < fsl_edma->n_chans; i++) { 520 struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i]; 521 int len; 522 523 if (fsl_edma->chan_masked & BIT(i)) 524 continue; 525 526 snprintf(fsl_chan->chan_name, sizeof(fsl_chan->chan_name), "%s-CH%02d", 527 dev_name(&pdev->dev), i); 528 529 fsl_chan->edma = fsl_edma; 530 fsl_chan->pm_state = RUNNING; 531 fsl_chan->slave_id = 0; 532 fsl_chan->idle = true; 533 fsl_chan->dma_dir = DMA_NONE; 534 fsl_chan->vchan.desc_free = fsl_edma_free_desc; 535 536 len = (drvdata->flags & FSL_EDMA_DRV_SPLIT_REG) ? 537 offsetof(struct fsl_edma3_ch_reg, tcd) : 0; 538 fsl_chan->tcd = fsl_edma->membase 539 + i * drvdata->chreg_space_sz + drvdata->chreg_off + len; 540 541 fsl_chan->pdev = pdev; 542 vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev); 543 544 edma_write_tcdreg(fsl_chan, 0, csr); 545 fsl_edma_chan_mux(fsl_chan, 0, false); 546 } 547 548 ret = fsl_edma->drvdata->setup_irq(pdev, fsl_edma); 549 if (ret) 550 return ret; 551 552 dma_cap_set(DMA_PRIVATE, fsl_edma->dma_dev.cap_mask); 553 dma_cap_set(DMA_SLAVE, fsl_edma->dma_dev.cap_mask); 554 dma_cap_set(DMA_CYCLIC, fsl_edma->dma_dev.cap_mask); 555 dma_cap_set(DMA_MEMCPY, fsl_edma->dma_dev.cap_mask); 556 557 fsl_edma->dma_dev.dev = &pdev->dev; 558 fsl_edma->dma_dev.device_alloc_chan_resources 559 = fsl_edma_alloc_chan_resources; 560 fsl_edma->dma_dev.device_free_chan_resources 561 = fsl_edma_free_chan_resources; 562 fsl_edma->dma_dev.device_tx_status = fsl_edma_tx_status; 563 fsl_edma->dma_dev.device_prep_slave_sg = fsl_edma_prep_slave_sg; 564 fsl_edma->dma_dev.device_prep_dma_cyclic = fsl_edma_prep_dma_cyclic; 565 fsl_edma->dma_dev.device_prep_dma_memcpy = fsl_edma_prep_memcpy; 566 fsl_edma->dma_dev.device_config = fsl_edma_slave_config; 567 fsl_edma->dma_dev.device_pause = fsl_edma_pause; 568 fsl_edma->dma_dev.device_resume = fsl_edma_resume; 569 fsl_edma->dma_dev.device_terminate_all = fsl_edma_terminate_all; 570 fsl_edma->dma_dev.device_synchronize = fsl_edma_synchronize; 571 fsl_edma->dma_dev.device_issue_pending = fsl_edma_issue_pending; 572 573 fsl_edma->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS; 574 fsl_edma->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS; 575 576 if (drvdata->flags & FSL_EDMA_DRV_BUS_8BYTE) { 577 fsl_edma->dma_dev.src_addr_widths |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES); 578 fsl_edma->dma_dev.dst_addr_widths |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES); 579 } 580 581 fsl_edma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); 582 if (drvdata->flags & FSL_EDMA_DRV_DEV_TO_DEV) 583 fsl_edma->dma_dev.directions |= BIT(DMA_DEV_TO_DEV); 584 585 fsl_edma->dma_dev.copy_align = drvdata->flags & FSL_EDMA_DRV_ALIGN_64BYTE ? 586 DMAENGINE_ALIGN_64_BYTES : 587 DMAENGINE_ALIGN_32_BYTES; 588 589 /* Per worst case 'nbytes = 1' take CITER as the max_seg_size */ 590 dma_set_max_seg_size(fsl_edma->dma_dev.dev, 0x3fff); 591 592 fsl_edma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; 593 594 platform_set_drvdata(pdev, fsl_edma); 595 596 ret = dma_async_device_register(&fsl_edma->dma_dev); 597 if (ret) { 598 dev_err(&pdev->dev, 599 "Can't register Freescale eDMA engine. (%d)\n", ret); 600 return ret; 601 } 602 603 ret = of_dma_controller_register(np, 604 drvdata->flags & FSL_EDMA_DRV_SPLIT_REG ? fsl_edma3_xlate : fsl_edma_xlate, 605 fsl_edma); 606 if (ret) { 607 dev_err(&pdev->dev, 608 "Can't register Freescale eDMA of_dma. (%d)\n", ret); 609 dma_async_device_unregister(&fsl_edma->dma_dev); 610 return ret; 611 } 612 613 /* enable round robin arbitration */ 614 if (!(drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)) 615 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr); 616 617 return 0; 618 } 619 620 static int fsl_edma_remove(struct platform_device *pdev) 621 { 622 struct device_node *np = pdev->dev.of_node; 623 struct fsl_edma_engine *fsl_edma = platform_get_drvdata(pdev); 624 625 fsl_edma_irq_exit(pdev, fsl_edma); 626 fsl_edma_cleanup_vchan(&fsl_edma->dma_dev); 627 of_dma_controller_free(np); 628 dma_async_device_unregister(&fsl_edma->dma_dev); 629 fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs); 630 631 return 0; 632 } 633 634 static int fsl_edma_suspend_late(struct device *dev) 635 { 636 struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev); 637 struct fsl_edma_chan *fsl_chan; 638 unsigned long flags; 639 int i; 640 641 for (i = 0; i < fsl_edma->n_chans; i++) { 642 fsl_chan = &fsl_edma->chans[i]; 643 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 644 /* Make sure chan is idle or will force disable. */ 645 if (unlikely(!fsl_chan->idle)) { 646 dev_warn(dev, "WARN: There is non-idle channel."); 647 fsl_edma_disable_request(fsl_chan); 648 fsl_edma_chan_mux(fsl_chan, 0, false); 649 } 650 651 fsl_chan->pm_state = SUSPENDED; 652 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 653 } 654 655 return 0; 656 } 657 658 static int fsl_edma_resume_early(struct device *dev) 659 { 660 struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev); 661 struct fsl_edma_chan *fsl_chan; 662 struct edma_regs *regs = &fsl_edma->regs; 663 int i; 664 665 for (i = 0; i < fsl_edma->n_chans; i++) { 666 fsl_chan = &fsl_edma->chans[i]; 667 fsl_chan->pm_state = RUNNING; 668 edma_write_tcdreg(fsl_chan, 0, csr); 669 if (fsl_chan->slave_id != 0) 670 fsl_edma_chan_mux(fsl_chan, fsl_chan->slave_id, true); 671 } 672 673 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr); 674 675 return 0; 676 } 677 678 /* 679 * eDMA provides the service to others, so it should be suspend late 680 * and resume early. When eDMA suspend, all of the clients should stop 681 * the DMA data transmission and let the channel idle. 682 */ 683 static const struct dev_pm_ops fsl_edma_pm_ops = { 684 .suspend_late = fsl_edma_suspend_late, 685 .resume_early = fsl_edma_resume_early, 686 }; 687 688 static struct platform_driver fsl_edma_driver = { 689 .driver = { 690 .name = "fsl-edma", 691 .of_match_table = fsl_edma_dt_ids, 692 .pm = &fsl_edma_pm_ops, 693 }, 694 .probe = fsl_edma_probe, 695 .remove = fsl_edma_remove, 696 }; 697 698 static int __init fsl_edma_init(void) 699 { 700 return platform_driver_register(&fsl_edma_driver); 701 } 702 subsys_initcall(fsl_edma_init); 703 704 static void __exit fsl_edma_exit(void) 705 { 706 platform_driver_unregister(&fsl_edma_driver); 707 } 708 module_exit(fsl_edma_exit); 709 710 MODULE_ALIAS("platform:fsl-edma"); 711 MODULE_DESCRIPTION("Freescale eDMA engine driver"); 712 MODULE_LICENSE("GPL v2"); 713