1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * drivers/dma/fsl-edma.c 4 * 5 * Copyright 2013-2014 Freescale Semiconductor, Inc. 6 * 7 * Driver for the Freescale eDMA engine with flexible channel multiplexing 8 * capability for DMA request sources. The eDMA block can be found on some 9 * Vybrid and Layerscape SoCs. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/interrupt.h> 14 #include <linux/clk.h> 15 #include <linux/of.h> 16 #include <linux/of_device.h> 17 #include <linux/of_address.h> 18 #include <linux/of_irq.h> 19 #include <linux/of_dma.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/pm_domain.h> 23 24 #include "fsl-edma-common.h" 25 26 #define ARGS_RX BIT(0) 27 #define ARGS_REMOTE BIT(1) 28 #define ARGS_MULTI_FIFO BIT(2) 29 #define ARGS_EVEN_CH BIT(3) 30 #define ARGS_ODD_CH BIT(4) 31 32 static void fsl_edma_synchronize(struct dma_chan *chan) 33 { 34 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 35 36 vchan_synchronize(&fsl_chan->vchan); 37 } 38 39 static irqreturn_t fsl_edma_tx_handler(int irq, void *dev_id) 40 { 41 struct fsl_edma_engine *fsl_edma = dev_id; 42 unsigned int intr, ch; 43 struct edma_regs *regs = &fsl_edma->regs; 44 45 intr = edma_readl(fsl_edma, regs->intl); 46 if (!intr) 47 return IRQ_NONE; 48 49 for (ch = 0; ch < fsl_edma->n_chans; ch++) { 50 if (intr & (0x1 << ch)) { 51 edma_writeb(fsl_edma, EDMA_CINT_CINT(ch), regs->cint); 52 fsl_edma_tx_chan_handler(&fsl_edma->chans[ch]); 53 } 54 } 55 return IRQ_HANDLED; 56 } 57 58 static irqreturn_t fsl_edma3_tx_handler(int irq, void *dev_id) 59 { 60 struct fsl_edma_chan *fsl_chan = dev_id; 61 unsigned int intr; 62 63 intr = edma_readl_chreg(fsl_chan, ch_int); 64 if (!intr) 65 return IRQ_HANDLED; 66 67 edma_writel_chreg(fsl_chan, 1, ch_int); 68 69 fsl_edma_tx_chan_handler(fsl_chan); 70 71 return IRQ_HANDLED; 72 } 73 74 static irqreturn_t fsl_edma_err_handler(int irq, void *dev_id) 75 { 76 struct fsl_edma_engine *fsl_edma = dev_id; 77 unsigned int err, ch; 78 struct edma_regs *regs = &fsl_edma->regs; 79 80 err = edma_readl(fsl_edma, regs->errl); 81 if (!err) 82 return IRQ_NONE; 83 84 for (ch = 0; ch < fsl_edma->n_chans; ch++) { 85 if (err & (0x1 << ch)) { 86 fsl_edma_disable_request(&fsl_edma->chans[ch]); 87 edma_writeb(fsl_edma, EDMA_CERR_CERR(ch), regs->cerr); 88 fsl_edma_err_chan_handler(&fsl_edma->chans[ch]); 89 } 90 } 91 return IRQ_HANDLED; 92 } 93 94 static irqreturn_t fsl_edma_irq_handler(int irq, void *dev_id) 95 { 96 if (fsl_edma_tx_handler(irq, dev_id) == IRQ_HANDLED) 97 return IRQ_HANDLED; 98 99 return fsl_edma_err_handler(irq, dev_id); 100 } 101 102 static struct dma_chan *fsl_edma_xlate(struct of_phandle_args *dma_spec, 103 struct of_dma *ofdma) 104 { 105 struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data; 106 struct dma_chan *chan, *_chan; 107 struct fsl_edma_chan *fsl_chan; 108 u32 dmamux_nr = fsl_edma->drvdata->dmamuxs; 109 unsigned long chans_per_mux = fsl_edma->n_chans / dmamux_nr; 110 111 if (dma_spec->args_count != 2) 112 return NULL; 113 114 mutex_lock(&fsl_edma->fsl_edma_mutex); 115 list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, device_node) { 116 if (chan->client_count) 117 continue; 118 if ((chan->chan_id / chans_per_mux) == dma_spec->args[0]) { 119 chan = dma_get_slave_channel(chan); 120 if (chan) { 121 chan->device->privatecnt++; 122 fsl_chan = to_fsl_edma_chan(chan); 123 fsl_chan->slave_id = dma_spec->args[1]; 124 fsl_edma_chan_mux(fsl_chan, fsl_chan->slave_id, 125 true); 126 mutex_unlock(&fsl_edma->fsl_edma_mutex); 127 return chan; 128 } 129 } 130 } 131 mutex_unlock(&fsl_edma->fsl_edma_mutex); 132 return NULL; 133 } 134 135 static struct dma_chan *fsl_edma3_xlate(struct of_phandle_args *dma_spec, 136 struct of_dma *ofdma) 137 { 138 struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data; 139 struct dma_chan *chan, *_chan; 140 struct fsl_edma_chan *fsl_chan; 141 bool b_chmux; 142 int i; 143 144 if (dma_spec->args_count != 3) 145 return NULL; 146 147 b_chmux = !!(fsl_edma->drvdata->flags & FSL_EDMA_DRV_HAS_CHMUX); 148 149 mutex_lock(&fsl_edma->fsl_edma_mutex); 150 list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, 151 device_node) { 152 153 if (chan->client_count) 154 continue; 155 156 fsl_chan = to_fsl_edma_chan(chan); 157 i = fsl_chan - fsl_edma->chans; 158 159 fsl_chan->priority = dma_spec->args[1]; 160 fsl_chan->is_rxchan = dma_spec->args[2] & ARGS_RX; 161 fsl_chan->is_remote = dma_spec->args[2] & ARGS_REMOTE; 162 fsl_chan->is_multi_fifo = dma_spec->args[2] & ARGS_MULTI_FIFO; 163 164 if ((dma_spec->args[2] & ARGS_EVEN_CH) && (i & 0x1)) 165 continue; 166 167 if ((dma_spec->args[2] & ARGS_ODD_CH) && !(i & 0x1)) 168 continue; 169 170 if (!b_chmux && i == dma_spec->args[0]) { 171 chan = dma_get_slave_channel(chan); 172 chan->device->privatecnt++; 173 mutex_unlock(&fsl_edma->fsl_edma_mutex); 174 return chan; 175 } else if (b_chmux && !fsl_chan->srcid) { 176 /* if controller support channel mux, choose a free channel */ 177 chan = dma_get_slave_channel(chan); 178 chan->device->privatecnt++; 179 fsl_chan->srcid = dma_spec->args[0]; 180 mutex_unlock(&fsl_edma->fsl_edma_mutex); 181 return chan; 182 } 183 } 184 mutex_unlock(&fsl_edma->fsl_edma_mutex); 185 return NULL; 186 } 187 188 static int 189 fsl_edma_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) 190 { 191 int ret; 192 193 edma_writel(fsl_edma, ~0, fsl_edma->regs.intl); 194 195 fsl_edma->txirq = platform_get_irq_byname(pdev, "edma-tx"); 196 if (fsl_edma->txirq < 0) 197 return fsl_edma->txirq; 198 199 fsl_edma->errirq = platform_get_irq_byname(pdev, "edma-err"); 200 if (fsl_edma->errirq < 0) 201 return fsl_edma->errirq; 202 203 if (fsl_edma->txirq == fsl_edma->errirq) { 204 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq, 205 fsl_edma_irq_handler, 0, "eDMA", fsl_edma); 206 if (ret) { 207 dev_err(&pdev->dev, "Can't register eDMA IRQ.\n"); 208 return ret; 209 } 210 } else { 211 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq, 212 fsl_edma_tx_handler, 0, "eDMA tx", fsl_edma); 213 if (ret) { 214 dev_err(&pdev->dev, "Can't register eDMA tx IRQ.\n"); 215 return ret; 216 } 217 218 ret = devm_request_irq(&pdev->dev, fsl_edma->errirq, 219 fsl_edma_err_handler, 0, "eDMA err", fsl_edma); 220 if (ret) { 221 dev_err(&pdev->dev, "Can't register eDMA err IRQ.\n"); 222 return ret; 223 } 224 } 225 226 return 0; 227 } 228 229 static int fsl_edma3_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) 230 { 231 int ret; 232 int i; 233 234 for (i = 0; i < fsl_edma->n_chans; i++) { 235 236 struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i]; 237 238 if (fsl_edma->chan_masked & BIT(i)) 239 continue; 240 241 /* request channel irq */ 242 fsl_chan->txirq = platform_get_irq(pdev, i); 243 if (fsl_chan->txirq < 0) { 244 dev_err(&pdev->dev, "Can't get chan %d's irq.\n", i); 245 return -EINVAL; 246 } 247 248 ret = devm_request_irq(&pdev->dev, fsl_chan->txirq, 249 fsl_edma3_tx_handler, IRQF_SHARED, 250 fsl_chan->chan_name, fsl_chan); 251 if (ret) { 252 dev_err(&pdev->dev, "Can't register chan%d's IRQ.\n", i); 253 return -EINVAL; 254 } 255 } 256 257 return 0; 258 } 259 260 static int 261 fsl_edma2_irq_init(struct platform_device *pdev, 262 struct fsl_edma_engine *fsl_edma) 263 { 264 int i, ret, irq; 265 int count; 266 267 edma_writel(fsl_edma, ~0, fsl_edma->regs.intl); 268 269 count = platform_irq_count(pdev); 270 dev_dbg(&pdev->dev, "%s Found %d interrupts\r\n", __func__, count); 271 if (count <= 2) { 272 dev_err(&pdev->dev, "Interrupts in DTS not correct.\n"); 273 return -EINVAL; 274 } 275 /* 276 * 16 channel independent interrupts + 1 error interrupt on i.mx7ulp. 277 * 2 channel share one interrupt, for example, ch0/ch16, ch1/ch17... 278 * For now, just simply request irq without IRQF_SHARED flag, since 16 279 * channels are enough on i.mx7ulp whose M4 domain own some peripherals. 280 */ 281 for (i = 0; i < count; i++) { 282 irq = platform_get_irq(pdev, i); 283 if (irq < 0) 284 return -ENXIO; 285 286 /* The last IRQ is for eDMA err */ 287 if (i == count - 1) 288 ret = devm_request_irq(&pdev->dev, irq, 289 fsl_edma_err_handler, 290 0, "eDMA2-ERR", fsl_edma); 291 else 292 ret = devm_request_irq(&pdev->dev, irq, 293 fsl_edma_tx_handler, 0, 294 fsl_edma->chans[i].chan_name, 295 fsl_edma); 296 if (ret) 297 return ret; 298 } 299 300 return 0; 301 } 302 303 static void fsl_edma_irq_exit( 304 struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) 305 { 306 if (fsl_edma->txirq == fsl_edma->errirq) { 307 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma); 308 } else { 309 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma); 310 devm_free_irq(&pdev->dev, fsl_edma->errirq, fsl_edma); 311 } 312 } 313 314 static void fsl_disable_clocks(struct fsl_edma_engine *fsl_edma, int nr_clocks) 315 { 316 int i; 317 318 for (i = 0; i < nr_clocks; i++) 319 clk_disable_unprepare(fsl_edma->muxclk[i]); 320 } 321 322 static struct fsl_edma_drvdata vf610_data = { 323 .dmamuxs = DMAMUX_NR, 324 .flags = FSL_EDMA_DRV_WRAP_IO, 325 .chreg_off = EDMA_TCD, 326 .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd), 327 .setup_irq = fsl_edma_irq_init, 328 }; 329 330 static struct fsl_edma_drvdata ls1028a_data = { 331 .dmamuxs = DMAMUX_NR, 332 .flags = FSL_EDMA_DRV_MUX_SWAP | FSL_EDMA_DRV_WRAP_IO, 333 .chreg_off = EDMA_TCD, 334 .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd), 335 .setup_irq = fsl_edma_irq_init, 336 }; 337 338 static struct fsl_edma_drvdata imx7ulp_data = { 339 .dmamuxs = 1, 340 .chreg_off = EDMA_TCD, 341 .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd), 342 .flags = FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_CONFIG32, 343 .setup_irq = fsl_edma2_irq_init, 344 }; 345 346 static struct fsl_edma_drvdata imx8qm_data = { 347 .flags = FSL_EDMA_DRV_HAS_PD | FSL_EDMA_DRV_EDMA3, 348 .chreg_space_sz = 0x10000, 349 .chreg_off = 0x10000, 350 .setup_irq = fsl_edma3_irq_init, 351 }; 352 353 static struct fsl_edma_drvdata imx8qm_audio_data = { 354 .flags = FSL_EDMA_DRV_QUIRK_SWAPPED | FSL_EDMA_DRV_HAS_PD | FSL_EDMA_DRV_EDMA3, 355 .chreg_space_sz = 0x10000, 356 .chreg_off = 0x10000, 357 .setup_irq = fsl_edma3_irq_init, 358 }; 359 360 static struct fsl_edma_drvdata imx93_data3 = { 361 .flags = FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA3, 362 .chreg_space_sz = 0x10000, 363 .chreg_off = 0x10000, 364 .setup_irq = fsl_edma3_irq_init, 365 }; 366 367 static struct fsl_edma_drvdata imx93_data4 = { 368 .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA4, 369 .chreg_space_sz = 0x8000, 370 .chreg_off = 0x10000, 371 .setup_irq = fsl_edma3_irq_init, 372 }; 373 374 static const struct of_device_id fsl_edma_dt_ids[] = { 375 { .compatible = "fsl,vf610-edma", .data = &vf610_data}, 376 { .compatible = "fsl,ls1028a-edma", .data = &ls1028a_data}, 377 { .compatible = "fsl,imx7ulp-edma", .data = &imx7ulp_data}, 378 { .compatible = "fsl,imx8qm-edma", .data = &imx8qm_data}, 379 { .compatible = "fsl,imx8qm-adma", .data = &imx8qm_audio_data}, 380 { .compatible = "fsl,imx93-edma3", .data = &imx93_data3}, 381 { .compatible = "fsl,imx93-edma4", .data = &imx93_data4}, 382 { /* sentinel */ } 383 }; 384 MODULE_DEVICE_TABLE(of, fsl_edma_dt_ids); 385 386 static int fsl_edma3_attach_pd(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) 387 { 388 struct fsl_edma_chan *fsl_chan; 389 struct device_link *link; 390 struct device *pd_chan; 391 struct device *dev; 392 int i; 393 394 dev = &pdev->dev; 395 396 for (i = 0; i < fsl_edma->n_chans; i++) { 397 if (fsl_edma->chan_masked & BIT(i)) 398 continue; 399 400 fsl_chan = &fsl_edma->chans[i]; 401 402 pd_chan = dev_pm_domain_attach_by_id(dev, i); 403 if (IS_ERR_OR_NULL(pd_chan)) { 404 dev_err(dev, "Failed attach pd %d\n", i); 405 return -EINVAL; 406 } 407 408 link = device_link_add(dev, pd_chan, DL_FLAG_STATELESS | 409 DL_FLAG_PM_RUNTIME | 410 DL_FLAG_RPM_ACTIVE); 411 if (!link) { 412 dev_err(dev, "Failed to add device_link to %d\n", i); 413 return -EINVAL; 414 } 415 416 fsl_chan->pd_dev = pd_chan; 417 418 pm_runtime_use_autosuspend(fsl_chan->pd_dev); 419 pm_runtime_set_autosuspend_delay(fsl_chan->pd_dev, 200); 420 pm_runtime_set_active(fsl_chan->pd_dev); 421 } 422 423 return 0; 424 } 425 426 static int fsl_edma_probe(struct platform_device *pdev) 427 { 428 const struct of_device_id *of_id = 429 of_match_device(fsl_edma_dt_ids, &pdev->dev); 430 struct device_node *np = pdev->dev.of_node; 431 struct fsl_edma_engine *fsl_edma; 432 const struct fsl_edma_drvdata *drvdata = NULL; 433 u32 chan_mask[2] = {0, 0}; 434 struct edma_regs *regs; 435 int chans; 436 int ret, i; 437 438 if (of_id) 439 drvdata = of_id->data; 440 if (!drvdata) { 441 dev_err(&pdev->dev, "unable to find driver data\n"); 442 return -EINVAL; 443 } 444 445 ret = of_property_read_u32(np, "dma-channels", &chans); 446 if (ret) { 447 dev_err(&pdev->dev, "Can't get dma-channels.\n"); 448 return ret; 449 } 450 451 fsl_edma = devm_kzalloc(&pdev->dev, struct_size(fsl_edma, chans, chans), 452 GFP_KERNEL); 453 if (!fsl_edma) 454 return -ENOMEM; 455 456 fsl_edma->drvdata = drvdata; 457 fsl_edma->n_chans = chans; 458 mutex_init(&fsl_edma->fsl_edma_mutex); 459 460 fsl_edma->membase = devm_platform_ioremap_resource(pdev, 0); 461 if (IS_ERR(fsl_edma->membase)) 462 return PTR_ERR(fsl_edma->membase); 463 464 if (!(drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)) { 465 fsl_edma_setup_regs(fsl_edma); 466 regs = &fsl_edma->regs; 467 } 468 469 if (drvdata->flags & FSL_EDMA_DRV_HAS_DMACLK) { 470 fsl_edma->dmaclk = devm_clk_get_enabled(&pdev->dev, "dma"); 471 if (IS_ERR(fsl_edma->dmaclk)) { 472 dev_err(&pdev->dev, "Missing DMA block clock.\n"); 473 return PTR_ERR(fsl_edma->dmaclk); 474 } 475 } 476 477 if (drvdata->flags & FSL_EDMA_DRV_HAS_CHCLK) { 478 fsl_edma->chclk = devm_clk_get_enabled(&pdev->dev, "mp"); 479 if (IS_ERR(fsl_edma->chclk)) { 480 dev_err(&pdev->dev, "Missing MP block clock.\n"); 481 return PTR_ERR(fsl_edma->chclk); 482 } 483 } 484 485 ret = of_property_read_variable_u32_array(np, "dma-channel-mask", chan_mask, 1, 2); 486 487 if (ret > 0) { 488 fsl_edma->chan_masked = chan_mask[1]; 489 fsl_edma->chan_masked <<= 32; 490 fsl_edma->chan_masked |= chan_mask[0]; 491 } 492 493 for (i = 0; i < fsl_edma->drvdata->dmamuxs; i++) { 494 char clkname[32]; 495 496 /* eDMAv3 mux register move to TCD area if ch_mux exist */ 497 if (drvdata->flags & FSL_EDMA_DRV_SPLIT_REG) 498 break; 499 500 fsl_edma->muxbase[i] = devm_platform_ioremap_resource(pdev, 501 1 + i); 502 if (IS_ERR(fsl_edma->muxbase[i])) { 503 /* on error: disable all previously enabled clks */ 504 fsl_disable_clocks(fsl_edma, i); 505 return PTR_ERR(fsl_edma->muxbase[i]); 506 } 507 508 sprintf(clkname, "dmamux%d", i); 509 fsl_edma->muxclk[i] = devm_clk_get_enabled(&pdev->dev, clkname); 510 if (IS_ERR(fsl_edma->muxclk[i])) { 511 dev_err(&pdev->dev, "Missing DMAMUX block clock.\n"); 512 /* on error: disable all previously enabled clks */ 513 return PTR_ERR(fsl_edma->muxclk[i]); 514 } 515 } 516 517 fsl_edma->big_endian = of_property_read_bool(np, "big-endian"); 518 519 if (drvdata->flags & FSL_EDMA_DRV_HAS_PD) { 520 ret = fsl_edma3_attach_pd(pdev, fsl_edma); 521 if (ret) 522 return ret; 523 } 524 525 INIT_LIST_HEAD(&fsl_edma->dma_dev.channels); 526 for (i = 0; i < fsl_edma->n_chans; i++) { 527 struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i]; 528 int len; 529 530 if (fsl_edma->chan_masked & BIT(i)) 531 continue; 532 533 snprintf(fsl_chan->chan_name, sizeof(fsl_chan->chan_name), "%s-CH%02d", 534 dev_name(&pdev->dev), i); 535 536 fsl_chan->edma = fsl_edma; 537 fsl_chan->pm_state = RUNNING; 538 fsl_chan->slave_id = 0; 539 fsl_chan->idle = true; 540 fsl_chan->dma_dir = DMA_NONE; 541 fsl_chan->vchan.desc_free = fsl_edma_free_desc; 542 543 len = (drvdata->flags & FSL_EDMA_DRV_SPLIT_REG) ? 544 offsetof(struct fsl_edma3_ch_reg, tcd) : 0; 545 fsl_chan->tcd = fsl_edma->membase 546 + i * drvdata->chreg_space_sz + drvdata->chreg_off + len; 547 548 fsl_chan->pdev = pdev; 549 vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev); 550 551 edma_write_tcdreg(fsl_chan, 0, csr); 552 fsl_edma_chan_mux(fsl_chan, 0, false); 553 } 554 555 ret = fsl_edma->drvdata->setup_irq(pdev, fsl_edma); 556 if (ret) 557 return ret; 558 559 dma_cap_set(DMA_PRIVATE, fsl_edma->dma_dev.cap_mask); 560 dma_cap_set(DMA_SLAVE, fsl_edma->dma_dev.cap_mask); 561 dma_cap_set(DMA_CYCLIC, fsl_edma->dma_dev.cap_mask); 562 dma_cap_set(DMA_MEMCPY, fsl_edma->dma_dev.cap_mask); 563 564 fsl_edma->dma_dev.dev = &pdev->dev; 565 fsl_edma->dma_dev.device_alloc_chan_resources 566 = fsl_edma_alloc_chan_resources; 567 fsl_edma->dma_dev.device_free_chan_resources 568 = fsl_edma_free_chan_resources; 569 fsl_edma->dma_dev.device_tx_status = fsl_edma_tx_status; 570 fsl_edma->dma_dev.device_prep_slave_sg = fsl_edma_prep_slave_sg; 571 fsl_edma->dma_dev.device_prep_dma_cyclic = fsl_edma_prep_dma_cyclic; 572 fsl_edma->dma_dev.device_prep_dma_memcpy = fsl_edma_prep_memcpy; 573 fsl_edma->dma_dev.device_config = fsl_edma_slave_config; 574 fsl_edma->dma_dev.device_pause = fsl_edma_pause; 575 fsl_edma->dma_dev.device_resume = fsl_edma_resume; 576 fsl_edma->dma_dev.device_terminate_all = fsl_edma_terminate_all; 577 fsl_edma->dma_dev.device_synchronize = fsl_edma_synchronize; 578 fsl_edma->dma_dev.device_issue_pending = fsl_edma_issue_pending; 579 580 fsl_edma->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS; 581 fsl_edma->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS; 582 583 if (drvdata->flags & FSL_EDMA_DRV_BUS_8BYTE) { 584 fsl_edma->dma_dev.src_addr_widths |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES); 585 fsl_edma->dma_dev.dst_addr_widths |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES); 586 } 587 588 fsl_edma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); 589 if (drvdata->flags & FSL_EDMA_DRV_DEV_TO_DEV) 590 fsl_edma->dma_dev.directions |= BIT(DMA_DEV_TO_DEV); 591 592 fsl_edma->dma_dev.copy_align = drvdata->flags & FSL_EDMA_DRV_ALIGN_64BYTE ? 593 DMAENGINE_ALIGN_64_BYTES : 594 DMAENGINE_ALIGN_32_BYTES; 595 596 /* Per worst case 'nbytes = 1' take CITER as the max_seg_size */ 597 dma_set_max_seg_size(fsl_edma->dma_dev.dev, 0x3fff); 598 599 fsl_edma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; 600 601 platform_set_drvdata(pdev, fsl_edma); 602 603 ret = dma_async_device_register(&fsl_edma->dma_dev); 604 if (ret) { 605 dev_err(&pdev->dev, 606 "Can't register Freescale eDMA engine. (%d)\n", ret); 607 return ret; 608 } 609 610 ret = of_dma_controller_register(np, 611 drvdata->flags & FSL_EDMA_DRV_SPLIT_REG ? fsl_edma3_xlate : fsl_edma_xlate, 612 fsl_edma); 613 if (ret) { 614 dev_err(&pdev->dev, 615 "Can't register Freescale eDMA of_dma. (%d)\n", ret); 616 dma_async_device_unregister(&fsl_edma->dma_dev); 617 return ret; 618 } 619 620 /* enable round robin arbitration */ 621 if (!(drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)) 622 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr); 623 624 return 0; 625 } 626 627 static int fsl_edma_remove(struct platform_device *pdev) 628 { 629 struct device_node *np = pdev->dev.of_node; 630 struct fsl_edma_engine *fsl_edma = platform_get_drvdata(pdev); 631 632 fsl_edma_irq_exit(pdev, fsl_edma); 633 fsl_edma_cleanup_vchan(&fsl_edma->dma_dev); 634 of_dma_controller_free(np); 635 dma_async_device_unregister(&fsl_edma->dma_dev); 636 fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs); 637 638 return 0; 639 } 640 641 static int fsl_edma_suspend_late(struct device *dev) 642 { 643 struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev); 644 struct fsl_edma_chan *fsl_chan; 645 unsigned long flags; 646 int i; 647 648 for (i = 0; i < fsl_edma->n_chans; i++) { 649 fsl_chan = &fsl_edma->chans[i]; 650 if (fsl_edma->chan_masked & BIT(i)) 651 continue; 652 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 653 /* Make sure chan is idle or will force disable. */ 654 if (unlikely(!fsl_chan->idle)) { 655 dev_warn(dev, "WARN: There is non-idle channel."); 656 fsl_edma_disable_request(fsl_chan); 657 fsl_edma_chan_mux(fsl_chan, 0, false); 658 } 659 660 fsl_chan->pm_state = SUSPENDED; 661 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 662 } 663 664 return 0; 665 } 666 667 static int fsl_edma_resume_early(struct device *dev) 668 { 669 struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev); 670 struct fsl_edma_chan *fsl_chan; 671 struct edma_regs *regs = &fsl_edma->regs; 672 int i; 673 674 for (i = 0; i < fsl_edma->n_chans; i++) { 675 fsl_chan = &fsl_edma->chans[i]; 676 if (fsl_edma->chan_masked & BIT(i)) 677 continue; 678 fsl_chan->pm_state = RUNNING; 679 edma_write_tcdreg(fsl_chan, 0, csr); 680 if (fsl_chan->slave_id != 0) 681 fsl_edma_chan_mux(fsl_chan, fsl_chan->slave_id, true); 682 } 683 684 if (!(fsl_edma->drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)) 685 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr); 686 687 return 0; 688 } 689 690 /* 691 * eDMA provides the service to others, so it should be suspend late 692 * and resume early. When eDMA suspend, all of the clients should stop 693 * the DMA data transmission and let the channel idle. 694 */ 695 static const struct dev_pm_ops fsl_edma_pm_ops = { 696 .suspend_late = fsl_edma_suspend_late, 697 .resume_early = fsl_edma_resume_early, 698 }; 699 700 static struct platform_driver fsl_edma_driver = { 701 .driver = { 702 .name = "fsl-edma", 703 .of_match_table = fsl_edma_dt_ids, 704 .pm = &fsl_edma_pm_ops, 705 }, 706 .probe = fsl_edma_probe, 707 .remove = fsl_edma_remove, 708 }; 709 710 static int __init fsl_edma_init(void) 711 { 712 return platform_driver_register(&fsl_edma_driver); 713 } 714 subsys_initcall(fsl_edma_init); 715 716 static void __exit fsl_edma_exit(void) 717 { 718 platform_driver_unregister(&fsl_edma_driver); 719 } 720 module_exit(fsl_edma_exit); 721 722 MODULE_ALIAS("platform:fsl-edma"); 723 MODULE_DESCRIPTION("Freescale eDMA engine driver"); 724 MODULE_LICENSE("GPL v2"); 725