1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * drivers/dma/fsl-edma.c 4 * 5 * Copyright 2013-2014 Freescale Semiconductor, Inc. 6 * 7 * Driver for the Freescale eDMA engine with flexible channel multiplexing 8 * capability for DMA request sources. The eDMA block can be found on some 9 * Vybrid and Layerscape SoCs. 10 */ 11 12 #include <dt-bindings/dma/fsl-edma.h> 13 #include <linux/bitfield.h> 14 #include <linux/module.h> 15 #include <linux/interrupt.h> 16 #include <linux/clk.h> 17 #include <linux/of.h> 18 #include <linux/of_device.h> 19 #include <linux/of_address.h> 20 #include <linux/of_irq.h> 21 #include <linux/of_dma.h> 22 #include <linux/dma-mapping.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/pm_domain.h> 25 26 #include "fsl-edma-common.h" 27 28 static void fsl_edma_synchronize(struct dma_chan *chan) 29 { 30 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); 31 32 vchan_synchronize(&fsl_chan->vchan); 33 } 34 35 static irqreturn_t fsl_edma_tx_handler(int irq, void *dev_id) 36 { 37 struct fsl_edma_engine *fsl_edma = dev_id; 38 unsigned int intr, ch; 39 struct edma_regs *regs = &fsl_edma->regs; 40 41 intr = edma_readl(fsl_edma, regs->intl); 42 if (!intr) 43 return IRQ_NONE; 44 45 for (ch = 0; ch < fsl_edma->n_chans; ch++) { 46 if (intr & (0x1 << ch)) { 47 edma_writeb(fsl_edma, EDMA_CINT_CINT(ch), regs->cint); 48 fsl_edma_tx_chan_handler(&fsl_edma->chans[ch]); 49 } 50 } 51 return IRQ_HANDLED; 52 } 53 54 static irqreturn_t fsl_edma3_tx_handler(int irq, void *dev_id) 55 { 56 struct fsl_edma_chan *fsl_chan = dev_id; 57 unsigned int intr; 58 59 intr = edma_readl_chreg(fsl_chan, ch_int); 60 if (!intr) 61 return IRQ_HANDLED; 62 63 edma_writel_chreg(fsl_chan, 1, ch_int); 64 65 fsl_edma_tx_chan_handler(fsl_chan); 66 67 return IRQ_HANDLED; 68 } 69 70 static irqreturn_t fsl_edma_err_handler(int irq, void *dev_id) 71 { 72 struct fsl_edma_engine *fsl_edma = dev_id; 73 unsigned int err, ch; 74 struct edma_regs *regs = &fsl_edma->regs; 75 76 err = edma_readl(fsl_edma, regs->errl); 77 if (!err) 78 return IRQ_NONE; 79 80 for (ch = 0; ch < fsl_edma->n_chans; ch++) { 81 if (err & (0x1 << ch)) { 82 fsl_edma_disable_request(&fsl_edma->chans[ch]); 83 edma_writeb(fsl_edma, EDMA_CERR_CERR(ch), regs->cerr); 84 fsl_edma_err_chan_handler(&fsl_edma->chans[ch]); 85 } 86 } 87 return IRQ_HANDLED; 88 } 89 90 static irqreturn_t fsl_edma_irq_handler(int irq, void *dev_id) 91 { 92 if (fsl_edma_tx_handler(irq, dev_id) == IRQ_HANDLED) 93 return IRQ_HANDLED; 94 95 return fsl_edma_err_handler(irq, dev_id); 96 } 97 98 static struct dma_chan *fsl_edma_xlate(struct of_phandle_args *dma_spec, 99 struct of_dma *ofdma) 100 { 101 struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data; 102 struct dma_chan *chan, *_chan; 103 struct fsl_edma_chan *fsl_chan; 104 u32 dmamux_nr = fsl_edma->drvdata->dmamuxs; 105 unsigned long chans_per_mux = fsl_edma->n_chans / dmamux_nr; 106 107 if (dma_spec->args_count != 2) 108 return NULL; 109 110 mutex_lock(&fsl_edma->fsl_edma_mutex); 111 list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, device_node) { 112 if (chan->client_count) 113 continue; 114 if ((chan->chan_id / chans_per_mux) == dma_spec->args[0]) { 115 chan = dma_get_slave_channel(chan); 116 if (chan) { 117 chan->device->privatecnt++; 118 fsl_chan = to_fsl_edma_chan(chan); 119 fsl_chan->slave_id = dma_spec->args[1]; 120 fsl_edma_chan_mux(fsl_chan, fsl_chan->slave_id, 121 true); 122 mutex_unlock(&fsl_edma->fsl_edma_mutex); 123 return chan; 124 } 125 } 126 } 127 mutex_unlock(&fsl_edma->fsl_edma_mutex); 128 return NULL; 129 } 130 131 static struct dma_chan *fsl_edma3_xlate(struct of_phandle_args *dma_spec, 132 struct of_dma *ofdma) 133 { 134 struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data; 135 struct dma_chan *chan, *_chan; 136 struct fsl_edma_chan *fsl_chan; 137 bool b_chmux; 138 int i; 139 140 if (dma_spec->args_count != 3) 141 return NULL; 142 143 b_chmux = !!(fsl_edma->drvdata->flags & FSL_EDMA_DRV_HAS_CHMUX); 144 145 mutex_lock(&fsl_edma->fsl_edma_mutex); 146 list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, 147 device_node) { 148 149 if (chan->client_count) 150 continue; 151 152 fsl_chan = to_fsl_edma_chan(chan); 153 i = fsl_chan - fsl_edma->chans; 154 155 fsl_chan->priority = dma_spec->args[1]; 156 fsl_chan->is_rxchan = dma_spec->args[2] & FSL_EDMA_RX; 157 fsl_chan->is_remote = dma_spec->args[2] & FSL_EDMA_REMOTE; 158 fsl_chan->is_multi_fifo = dma_spec->args[2] & FSL_EDMA_MULTI_FIFO; 159 160 if ((dma_spec->args[2] & FSL_EDMA_EVEN_CH) && (i & 0x1)) 161 continue; 162 163 if ((dma_spec->args[2] & FSL_EDMA_ODD_CH) && !(i & 0x1)) 164 continue; 165 166 if (!b_chmux && i == dma_spec->args[0]) { 167 chan = dma_get_slave_channel(chan); 168 chan->device->privatecnt++; 169 mutex_unlock(&fsl_edma->fsl_edma_mutex); 170 return chan; 171 } else if (b_chmux && !fsl_chan->srcid) { 172 /* if controller support channel mux, choose a free channel */ 173 chan = dma_get_slave_channel(chan); 174 chan->device->privatecnt++; 175 fsl_chan->srcid = dma_spec->args[0]; 176 mutex_unlock(&fsl_edma->fsl_edma_mutex); 177 return chan; 178 } 179 } 180 mutex_unlock(&fsl_edma->fsl_edma_mutex); 181 return NULL; 182 } 183 184 static int 185 fsl_edma_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) 186 { 187 int ret; 188 189 edma_writel(fsl_edma, ~0, fsl_edma->regs.intl); 190 191 fsl_edma->txirq = platform_get_irq_byname(pdev, "edma-tx"); 192 if (fsl_edma->txirq < 0) 193 return fsl_edma->txirq; 194 195 fsl_edma->errirq = platform_get_irq_byname(pdev, "edma-err"); 196 if (fsl_edma->errirq < 0) 197 return fsl_edma->errirq; 198 199 if (fsl_edma->txirq == fsl_edma->errirq) { 200 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq, 201 fsl_edma_irq_handler, 0, "eDMA", fsl_edma); 202 if (ret) { 203 dev_err(&pdev->dev, "Can't register eDMA IRQ.\n"); 204 return ret; 205 } 206 } else { 207 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq, 208 fsl_edma_tx_handler, 0, "eDMA tx", fsl_edma); 209 if (ret) { 210 dev_err(&pdev->dev, "Can't register eDMA tx IRQ.\n"); 211 return ret; 212 } 213 214 ret = devm_request_irq(&pdev->dev, fsl_edma->errirq, 215 fsl_edma_err_handler, 0, "eDMA err", fsl_edma); 216 if (ret) { 217 dev_err(&pdev->dev, "Can't register eDMA err IRQ.\n"); 218 return ret; 219 } 220 } 221 222 return 0; 223 } 224 225 static int fsl_edma3_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) 226 { 227 int ret; 228 int i; 229 230 for (i = 0; i < fsl_edma->n_chans; i++) { 231 232 struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i]; 233 234 if (fsl_edma->chan_masked & BIT(i)) 235 continue; 236 237 /* request channel irq */ 238 fsl_chan->txirq = platform_get_irq(pdev, i); 239 if (fsl_chan->txirq < 0) { 240 dev_err(&pdev->dev, "Can't get chan %d's irq.\n", i); 241 return -EINVAL; 242 } 243 244 ret = devm_request_irq(&pdev->dev, fsl_chan->txirq, 245 fsl_edma3_tx_handler, IRQF_SHARED, 246 fsl_chan->chan_name, fsl_chan); 247 if (ret) { 248 dev_err(&pdev->dev, "Can't register chan%d's IRQ.\n", i); 249 return -EINVAL; 250 } 251 } 252 253 return 0; 254 } 255 256 static int 257 fsl_edma2_irq_init(struct platform_device *pdev, 258 struct fsl_edma_engine *fsl_edma) 259 { 260 int i, ret, irq; 261 int count; 262 263 edma_writel(fsl_edma, ~0, fsl_edma->regs.intl); 264 265 count = platform_irq_count(pdev); 266 dev_dbg(&pdev->dev, "%s Found %d interrupts\r\n", __func__, count); 267 if (count <= 2) { 268 dev_err(&pdev->dev, "Interrupts in DTS not correct.\n"); 269 return -EINVAL; 270 } 271 /* 272 * 16 channel independent interrupts + 1 error interrupt on i.mx7ulp. 273 * 2 channel share one interrupt, for example, ch0/ch16, ch1/ch17... 274 * For now, just simply request irq without IRQF_SHARED flag, since 16 275 * channels are enough on i.mx7ulp whose M4 domain own some peripherals. 276 */ 277 for (i = 0; i < count; i++) { 278 irq = platform_get_irq(pdev, i); 279 if (irq < 0) 280 return -ENXIO; 281 282 /* The last IRQ is for eDMA err */ 283 if (i == count - 1) 284 ret = devm_request_irq(&pdev->dev, irq, 285 fsl_edma_err_handler, 286 0, "eDMA2-ERR", fsl_edma); 287 else 288 ret = devm_request_irq(&pdev->dev, irq, 289 fsl_edma_tx_handler, 0, 290 fsl_edma->chans[i].chan_name, 291 fsl_edma); 292 if (ret) 293 return ret; 294 } 295 296 return 0; 297 } 298 299 static void fsl_edma_irq_exit( 300 struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) 301 { 302 if (fsl_edma->txirq == fsl_edma->errirq) { 303 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma); 304 } else { 305 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma); 306 devm_free_irq(&pdev->dev, fsl_edma->errirq, fsl_edma); 307 } 308 } 309 310 static void fsl_disable_clocks(struct fsl_edma_engine *fsl_edma, int nr_clocks) 311 { 312 int i; 313 314 for (i = 0; i < nr_clocks; i++) 315 clk_disable_unprepare(fsl_edma->muxclk[i]); 316 } 317 318 static struct fsl_edma_drvdata vf610_data = { 319 .dmamuxs = DMAMUX_NR, 320 .flags = FSL_EDMA_DRV_WRAP_IO, 321 .chreg_off = EDMA_TCD, 322 .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd), 323 .setup_irq = fsl_edma_irq_init, 324 }; 325 326 static struct fsl_edma_drvdata ls1028a_data = { 327 .dmamuxs = DMAMUX_NR, 328 .flags = FSL_EDMA_DRV_MUX_SWAP | FSL_EDMA_DRV_WRAP_IO, 329 .chreg_off = EDMA_TCD, 330 .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd), 331 .setup_irq = fsl_edma_irq_init, 332 }; 333 334 static struct fsl_edma_drvdata imx7ulp_data = { 335 .dmamuxs = 1, 336 .chreg_off = EDMA_TCD, 337 .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd), 338 .flags = FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_CONFIG32, 339 .setup_irq = fsl_edma2_irq_init, 340 }; 341 342 static struct fsl_edma_drvdata imx8qm_data = { 343 .flags = FSL_EDMA_DRV_HAS_PD | FSL_EDMA_DRV_EDMA3 | FSL_EDMA_DRV_MEM_REMOTE, 344 .chreg_space_sz = 0x10000, 345 .chreg_off = 0x10000, 346 .setup_irq = fsl_edma3_irq_init, 347 }; 348 349 static struct fsl_edma_drvdata imx8ulp_data = { 350 .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_CHCLK | FSL_EDMA_DRV_HAS_DMACLK | 351 FSL_EDMA_DRV_EDMA3, 352 .chreg_space_sz = 0x10000, 353 .chreg_off = 0x10000, 354 .mux_off = 0x10000 + offsetof(struct fsl_edma3_ch_reg, ch_mux), 355 .mux_skip = 0x10000, 356 .setup_irq = fsl_edma3_irq_init, 357 }; 358 359 static struct fsl_edma_drvdata imx93_data3 = { 360 .flags = FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA3, 361 .chreg_space_sz = 0x10000, 362 .chreg_off = 0x10000, 363 .setup_irq = fsl_edma3_irq_init, 364 }; 365 366 static struct fsl_edma_drvdata imx93_data4 = { 367 .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA4, 368 .chreg_space_sz = 0x8000, 369 .chreg_off = 0x10000, 370 .mux_off = 0x10000 + offsetof(struct fsl_edma3_ch_reg, ch_mux), 371 .mux_skip = 0x8000, 372 .setup_irq = fsl_edma3_irq_init, 373 }; 374 375 static const struct of_device_id fsl_edma_dt_ids[] = { 376 { .compatible = "fsl,vf610-edma", .data = &vf610_data}, 377 { .compatible = "fsl,ls1028a-edma", .data = &ls1028a_data}, 378 { .compatible = "fsl,imx7ulp-edma", .data = &imx7ulp_data}, 379 { .compatible = "fsl,imx8qm-edma", .data = &imx8qm_data}, 380 { .compatible = "fsl,imx8ulp-edma", .data = &imx8ulp_data}, 381 { .compatible = "fsl,imx93-edma3", .data = &imx93_data3}, 382 { .compatible = "fsl,imx93-edma4", .data = &imx93_data4}, 383 { /* sentinel */ } 384 }; 385 MODULE_DEVICE_TABLE(of, fsl_edma_dt_ids); 386 387 static int fsl_edma3_attach_pd(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma) 388 { 389 struct fsl_edma_chan *fsl_chan; 390 struct device_link *link; 391 struct device *pd_chan; 392 struct device *dev; 393 int i; 394 395 dev = &pdev->dev; 396 397 for (i = 0; i < fsl_edma->n_chans; i++) { 398 if (fsl_edma->chan_masked & BIT(i)) 399 continue; 400 401 fsl_chan = &fsl_edma->chans[i]; 402 403 pd_chan = dev_pm_domain_attach_by_id(dev, i); 404 if (IS_ERR_OR_NULL(pd_chan)) { 405 dev_err(dev, "Failed attach pd %d\n", i); 406 return -EINVAL; 407 } 408 409 link = device_link_add(dev, pd_chan, DL_FLAG_STATELESS | 410 DL_FLAG_PM_RUNTIME | 411 DL_FLAG_RPM_ACTIVE); 412 if (!link) { 413 dev_err(dev, "Failed to add device_link to %d\n", i); 414 return -EINVAL; 415 } 416 417 fsl_chan->pd_dev = pd_chan; 418 419 pm_runtime_use_autosuspend(fsl_chan->pd_dev); 420 pm_runtime_set_autosuspend_delay(fsl_chan->pd_dev, 200); 421 pm_runtime_set_active(fsl_chan->pd_dev); 422 } 423 424 return 0; 425 } 426 427 static int fsl_edma_probe(struct platform_device *pdev) 428 { 429 const struct of_device_id *of_id = 430 of_match_device(fsl_edma_dt_ids, &pdev->dev); 431 struct device_node *np = pdev->dev.of_node; 432 struct fsl_edma_engine *fsl_edma; 433 const struct fsl_edma_drvdata *drvdata = NULL; 434 u32 chan_mask[2] = {0, 0}; 435 char clk_name[36]; 436 struct edma_regs *regs; 437 int chans; 438 int ret, i; 439 440 if (of_id) 441 drvdata = of_id->data; 442 if (!drvdata) { 443 dev_err(&pdev->dev, "unable to find driver data\n"); 444 return -EINVAL; 445 } 446 447 ret = of_property_read_u32(np, "dma-channels", &chans); 448 if (ret) { 449 dev_err(&pdev->dev, "Can't get dma-channels.\n"); 450 return ret; 451 } 452 453 fsl_edma = devm_kzalloc(&pdev->dev, struct_size(fsl_edma, chans, chans), 454 GFP_KERNEL); 455 if (!fsl_edma) 456 return -ENOMEM; 457 458 fsl_edma->drvdata = drvdata; 459 fsl_edma->n_chans = chans; 460 mutex_init(&fsl_edma->fsl_edma_mutex); 461 462 fsl_edma->membase = devm_platform_ioremap_resource(pdev, 0); 463 if (IS_ERR(fsl_edma->membase)) 464 return PTR_ERR(fsl_edma->membase); 465 466 if (!(drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)) { 467 fsl_edma_setup_regs(fsl_edma); 468 regs = &fsl_edma->regs; 469 } 470 471 if (drvdata->flags & FSL_EDMA_DRV_HAS_DMACLK) { 472 fsl_edma->dmaclk = devm_clk_get_enabled(&pdev->dev, "dma"); 473 if (IS_ERR(fsl_edma->dmaclk)) { 474 dev_err(&pdev->dev, "Missing DMA block clock.\n"); 475 return PTR_ERR(fsl_edma->dmaclk); 476 } 477 } 478 479 if (drvdata->flags & FSL_EDMA_DRV_HAS_CHCLK) { 480 fsl_edma->chclk = devm_clk_get_enabled(&pdev->dev, "mp"); 481 if (IS_ERR(fsl_edma->chclk)) { 482 dev_err(&pdev->dev, "Missing MP block clock.\n"); 483 return PTR_ERR(fsl_edma->chclk); 484 } 485 } 486 487 ret = of_property_read_variable_u32_array(np, "dma-channel-mask", chan_mask, 1, 2); 488 489 if (ret > 0) { 490 fsl_edma->chan_masked = chan_mask[1]; 491 fsl_edma->chan_masked <<= 32; 492 fsl_edma->chan_masked |= chan_mask[0]; 493 } 494 495 for (i = 0; i < fsl_edma->drvdata->dmamuxs; i++) { 496 char clkname[32]; 497 498 /* eDMAv3 mux register move to TCD area if ch_mux exist */ 499 if (drvdata->flags & FSL_EDMA_DRV_SPLIT_REG) 500 break; 501 502 fsl_edma->muxbase[i] = devm_platform_ioremap_resource(pdev, 503 1 + i); 504 if (IS_ERR(fsl_edma->muxbase[i])) { 505 /* on error: disable all previously enabled clks */ 506 fsl_disable_clocks(fsl_edma, i); 507 return PTR_ERR(fsl_edma->muxbase[i]); 508 } 509 510 sprintf(clkname, "dmamux%d", i); 511 fsl_edma->muxclk[i] = devm_clk_get_enabled(&pdev->dev, clkname); 512 if (IS_ERR(fsl_edma->muxclk[i])) { 513 dev_err(&pdev->dev, "Missing DMAMUX block clock.\n"); 514 /* on error: disable all previously enabled clks */ 515 return PTR_ERR(fsl_edma->muxclk[i]); 516 } 517 } 518 519 fsl_edma->big_endian = of_property_read_bool(np, "big-endian"); 520 521 if (drvdata->flags & FSL_EDMA_DRV_HAS_PD) { 522 ret = fsl_edma3_attach_pd(pdev, fsl_edma); 523 if (ret) 524 return ret; 525 } 526 527 INIT_LIST_HEAD(&fsl_edma->dma_dev.channels); 528 for (i = 0; i < fsl_edma->n_chans; i++) { 529 struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i]; 530 int len; 531 532 if (fsl_edma->chan_masked & BIT(i)) 533 continue; 534 535 snprintf(fsl_chan->chan_name, sizeof(fsl_chan->chan_name), "%s-CH%02d", 536 dev_name(&pdev->dev), i); 537 538 fsl_chan->edma = fsl_edma; 539 fsl_chan->pm_state = RUNNING; 540 fsl_chan->slave_id = 0; 541 fsl_chan->idle = true; 542 fsl_chan->dma_dir = DMA_NONE; 543 fsl_chan->vchan.desc_free = fsl_edma_free_desc; 544 545 len = (drvdata->flags & FSL_EDMA_DRV_SPLIT_REG) ? 546 offsetof(struct fsl_edma3_ch_reg, tcd) : 0; 547 fsl_chan->tcd = fsl_edma->membase 548 + i * drvdata->chreg_space_sz + drvdata->chreg_off + len; 549 fsl_chan->mux_addr = fsl_edma->membase + drvdata->mux_off + i * drvdata->mux_skip; 550 551 if (drvdata->flags & FSL_EDMA_DRV_HAS_CHCLK) { 552 snprintf(clk_name, sizeof(clk_name), "ch%02d", i); 553 fsl_chan->clk = devm_clk_get_enabled(&pdev->dev, 554 (const char *)clk_name); 555 556 if (IS_ERR(fsl_chan->clk)) 557 return PTR_ERR(fsl_chan->clk); 558 } 559 fsl_chan->pdev = pdev; 560 vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev); 561 562 edma_write_tcdreg(fsl_chan, 0, csr); 563 fsl_edma_chan_mux(fsl_chan, 0, false); 564 if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_HAS_CHCLK) 565 clk_disable_unprepare(fsl_chan->clk); 566 } 567 568 ret = fsl_edma->drvdata->setup_irq(pdev, fsl_edma); 569 if (ret) 570 return ret; 571 572 dma_cap_set(DMA_PRIVATE, fsl_edma->dma_dev.cap_mask); 573 dma_cap_set(DMA_SLAVE, fsl_edma->dma_dev.cap_mask); 574 dma_cap_set(DMA_CYCLIC, fsl_edma->dma_dev.cap_mask); 575 dma_cap_set(DMA_MEMCPY, fsl_edma->dma_dev.cap_mask); 576 577 fsl_edma->dma_dev.dev = &pdev->dev; 578 fsl_edma->dma_dev.device_alloc_chan_resources 579 = fsl_edma_alloc_chan_resources; 580 fsl_edma->dma_dev.device_free_chan_resources 581 = fsl_edma_free_chan_resources; 582 fsl_edma->dma_dev.device_tx_status = fsl_edma_tx_status; 583 fsl_edma->dma_dev.device_prep_slave_sg = fsl_edma_prep_slave_sg; 584 fsl_edma->dma_dev.device_prep_dma_cyclic = fsl_edma_prep_dma_cyclic; 585 fsl_edma->dma_dev.device_prep_dma_memcpy = fsl_edma_prep_memcpy; 586 fsl_edma->dma_dev.device_config = fsl_edma_slave_config; 587 fsl_edma->dma_dev.device_pause = fsl_edma_pause; 588 fsl_edma->dma_dev.device_resume = fsl_edma_resume; 589 fsl_edma->dma_dev.device_terminate_all = fsl_edma_terminate_all; 590 fsl_edma->dma_dev.device_synchronize = fsl_edma_synchronize; 591 fsl_edma->dma_dev.device_issue_pending = fsl_edma_issue_pending; 592 593 fsl_edma->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS; 594 fsl_edma->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS; 595 596 if (drvdata->flags & FSL_EDMA_DRV_BUS_8BYTE) { 597 fsl_edma->dma_dev.src_addr_widths |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES); 598 fsl_edma->dma_dev.dst_addr_widths |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES); 599 } 600 601 fsl_edma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); 602 if (drvdata->flags & FSL_EDMA_DRV_DEV_TO_DEV) 603 fsl_edma->dma_dev.directions |= BIT(DMA_DEV_TO_DEV); 604 605 fsl_edma->dma_dev.copy_align = drvdata->flags & FSL_EDMA_DRV_ALIGN_64BYTE ? 606 DMAENGINE_ALIGN_64_BYTES : 607 DMAENGINE_ALIGN_32_BYTES; 608 609 /* Per worst case 'nbytes = 1' take CITER as the max_seg_size */ 610 dma_set_max_seg_size(fsl_edma->dma_dev.dev, 611 FIELD_GET(EDMA_TCD_ITER_MASK, EDMA_TCD_ITER_MASK)); 612 613 fsl_edma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT; 614 615 platform_set_drvdata(pdev, fsl_edma); 616 617 ret = dma_async_device_register(&fsl_edma->dma_dev); 618 if (ret) { 619 dev_err(&pdev->dev, 620 "Can't register Freescale eDMA engine. (%d)\n", ret); 621 return ret; 622 } 623 624 ret = of_dma_controller_register(np, 625 drvdata->flags & FSL_EDMA_DRV_SPLIT_REG ? fsl_edma3_xlate : fsl_edma_xlate, 626 fsl_edma); 627 if (ret) { 628 dev_err(&pdev->dev, 629 "Can't register Freescale eDMA of_dma. (%d)\n", ret); 630 dma_async_device_unregister(&fsl_edma->dma_dev); 631 return ret; 632 } 633 634 /* enable round robin arbitration */ 635 if (!(drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)) 636 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr); 637 638 return 0; 639 } 640 641 static int fsl_edma_remove(struct platform_device *pdev) 642 { 643 struct device_node *np = pdev->dev.of_node; 644 struct fsl_edma_engine *fsl_edma = platform_get_drvdata(pdev); 645 646 fsl_edma_irq_exit(pdev, fsl_edma); 647 fsl_edma_cleanup_vchan(&fsl_edma->dma_dev); 648 of_dma_controller_free(np); 649 dma_async_device_unregister(&fsl_edma->dma_dev); 650 fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs); 651 652 return 0; 653 } 654 655 static int fsl_edma_suspend_late(struct device *dev) 656 { 657 struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev); 658 struct fsl_edma_chan *fsl_chan; 659 unsigned long flags; 660 int i; 661 662 for (i = 0; i < fsl_edma->n_chans; i++) { 663 fsl_chan = &fsl_edma->chans[i]; 664 if (fsl_edma->chan_masked & BIT(i)) 665 continue; 666 spin_lock_irqsave(&fsl_chan->vchan.lock, flags); 667 /* Make sure chan is idle or will force disable. */ 668 if (unlikely(!fsl_chan->idle)) { 669 dev_warn(dev, "WARN: There is non-idle channel."); 670 fsl_edma_disable_request(fsl_chan); 671 fsl_edma_chan_mux(fsl_chan, 0, false); 672 } 673 674 fsl_chan->pm_state = SUSPENDED; 675 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags); 676 } 677 678 return 0; 679 } 680 681 static int fsl_edma_resume_early(struct device *dev) 682 { 683 struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev); 684 struct fsl_edma_chan *fsl_chan; 685 struct edma_regs *regs = &fsl_edma->regs; 686 int i; 687 688 for (i = 0; i < fsl_edma->n_chans; i++) { 689 fsl_chan = &fsl_edma->chans[i]; 690 if (fsl_edma->chan_masked & BIT(i)) 691 continue; 692 fsl_chan->pm_state = RUNNING; 693 edma_write_tcdreg(fsl_chan, 0, csr); 694 if (fsl_chan->slave_id != 0) 695 fsl_edma_chan_mux(fsl_chan, fsl_chan->slave_id, true); 696 } 697 698 if (!(fsl_edma->drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)) 699 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr); 700 701 return 0; 702 } 703 704 /* 705 * eDMA provides the service to others, so it should be suspend late 706 * and resume early. When eDMA suspend, all of the clients should stop 707 * the DMA data transmission and let the channel idle. 708 */ 709 static const struct dev_pm_ops fsl_edma_pm_ops = { 710 .suspend_late = fsl_edma_suspend_late, 711 .resume_early = fsl_edma_resume_early, 712 }; 713 714 static struct platform_driver fsl_edma_driver = { 715 .driver = { 716 .name = "fsl-edma", 717 .of_match_table = fsl_edma_dt_ids, 718 .pm = &fsl_edma_pm_ops, 719 }, 720 .probe = fsl_edma_probe, 721 .remove = fsl_edma_remove, 722 }; 723 724 static int __init fsl_edma_init(void) 725 { 726 return platform_driver_register(&fsl_edma_driver); 727 } 728 subsys_initcall(fsl_edma_init); 729 730 static void __exit fsl_edma_exit(void) 731 { 732 platform_driver_unregister(&fsl_edma_driver); 733 } 734 module_exit(fsl_edma_exit); 735 736 MODULE_ALIAS("platform:fsl-edma"); 737 MODULE_DESCRIPTION("Freescale eDMA engine driver"); 738 MODULE_LICENSE("GPL v2"); 739