1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * drivers/dma/fsl-edma.c
4 *
5 * Copyright 2013-2014 Freescale Semiconductor, Inc.
6 *
7 * Driver for the Freescale eDMA engine with flexible channel multiplexing
8 * capability for DMA request sources. The eDMA block can be found on some
9 * Vybrid and Layerscape SoCs.
10 */
11
12 #include <dt-bindings/dma/fsl-edma.h>
13 #include <linux/bitfield.h>
14 #include <linux/module.h>
15 #include <linux/interrupt.h>
16 #include <linux/clk.h>
17 #include <linux/of.h>
18 #include <linux/of_device.h>
19 #include <linux/of_address.h>
20 #include <linux/of_irq.h>
21 #include <linux/of_dma.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/pm_domain.h>
25
26 #include "fsl-edma-common.h"
27
fsl_edma_synchronize(struct dma_chan * chan)28 static void fsl_edma_synchronize(struct dma_chan *chan)
29 {
30 struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
31
32 vchan_synchronize(&fsl_chan->vchan);
33 }
34
fsl_edma_tx_handler(int irq,void * dev_id)35 static irqreturn_t fsl_edma_tx_handler(int irq, void *dev_id)
36 {
37 struct fsl_edma_engine *fsl_edma = dev_id;
38 unsigned int intr, ch;
39 struct edma_regs *regs = &fsl_edma->regs;
40
41 intr = edma_readl(fsl_edma, regs->intl);
42 if (!intr)
43 return IRQ_NONE;
44
45 for (ch = 0; ch < fsl_edma->n_chans; ch++) {
46 if (intr & (0x1 << ch)) {
47 edma_writeb(fsl_edma, EDMA_CINT_CINT(ch), regs->cint);
48 fsl_edma_tx_chan_handler(&fsl_edma->chans[ch]);
49 }
50 }
51 return IRQ_HANDLED;
52 }
53
fsl_edma3_tx_handler(int irq,void * dev_id)54 static irqreturn_t fsl_edma3_tx_handler(int irq, void *dev_id)
55 {
56 struct fsl_edma_chan *fsl_chan = dev_id;
57 unsigned int intr;
58
59 intr = edma_readl_chreg(fsl_chan, ch_int);
60 if (!intr)
61 return IRQ_HANDLED;
62
63 edma_writel_chreg(fsl_chan, 1, ch_int);
64
65 fsl_edma_tx_chan_handler(fsl_chan);
66
67 return IRQ_HANDLED;
68 }
69
fsl_edma_err_handler(int irq,void * dev_id)70 static irqreturn_t fsl_edma_err_handler(int irq, void *dev_id)
71 {
72 struct fsl_edma_engine *fsl_edma = dev_id;
73 unsigned int err, ch;
74 struct edma_regs *regs = &fsl_edma->regs;
75
76 err = edma_readl(fsl_edma, regs->errl);
77 if (!err)
78 return IRQ_NONE;
79
80 for (ch = 0; ch < fsl_edma->n_chans; ch++) {
81 if (err & (0x1 << ch)) {
82 fsl_edma_disable_request(&fsl_edma->chans[ch]);
83 edma_writeb(fsl_edma, EDMA_CERR_CERR(ch), regs->cerr);
84 fsl_edma_err_chan_handler(&fsl_edma->chans[ch]);
85 }
86 }
87 return IRQ_HANDLED;
88 }
89
fsl_edma_irq_handler(int irq,void * dev_id)90 static irqreturn_t fsl_edma_irq_handler(int irq, void *dev_id)
91 {
92 if (fsl_edma_tx_handler(irq, dev_id) == IRQ_HANDLED)
93 return IRQ_HANDLED;
94
95 return fsl_edma_err_handler(irq, dev_id);
96 }
97
fsl_edma_xlate(struct of_phandle_args * dma_spec,struct of_dma * ofdma)98 static struct dma_chan *fsl_edma_xlate(struct of_phandle_args *dma_spec,
99 struct of_dma *ofdma)
100 {
101 struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data;
102 struct dma_chan *chan, *_chan;
103 struct fsl_edma_chan *fsl_chan;
104 u32 dmamux_nr = fsl_edma->drvdata->dmamuxs;
105 unsigned long chans_per_mux = fsl_edma->n_chans / dmamux_nr;
106
107 if (dma_spec->args_count != 2)
108 return NULL;
109
110 mutex_lock(&fsl_edma->fsl_edma_mutex);
111 list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, device_node) {
112 if (chan->client_count)
113 continue;
114 if ((chan->chan_id / chans_per_mux) == dma_spec->args[0]) {
115 chan = dma_get_slave_channel(chan);
116 if (chan) {
117 chan->device->privatecnt++;
118 fsl_chan = to_fsl_edma_chan(chan);
119 fsl_chan->slave_id = dma_spec->args[1];
120 fsl_edma_chan_mux(fsl_chan, fsl_chan->slave_id,
121 true);
122 mutex_unlock(&fsl_edma->fsl_edma_mutex);
123 return chan;
124 }
125 }
126 }
127 mutex_unlock(&fsl_edma->fsl_edma_mutex);
128 return NULL;
129 }
130
fsl_edma3_xlate(struct of_phandle_args * dma_spec,struct of_dma * ofdma)131 static struct dma_chan *fsl_edma3_xlate(struct of_phandle_args *dma_spec,
132 struct of_dma *ofdma)
133 {
134 struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data;
135 struct dma_chan *chan, *_chan;
136 struct fsl_edma_chan *fsl_chan;
137 bool b_chmux;
138 int i;
139
140 if (dma_spec->args_count != 3)
141 return NULL;
142
143 b_chmux = !!(fsl_edma->drvdata->flags & FSL_EDMA_DRV_HAS_CHMUX);
144
145 mutex_lock(&fsl_edma->fsl_edma_mutex);
146 list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels,
147 device_node) {
148
149 if (chan->client_count)
150 continue;
151
152 fsl_chan = to_fsl_edma_chan(chan);
153 i = fsl_chan - fsl_edma->chans;
154
155 fsl_chan->priority = dma_spec->args[1];
156 fsl_chan->is_rxchan = dma_spec->args[2] & FSL_EDMA_RX;
157 fsl_chan->is_remote = dma_spec->args[2] & FSL_EDMA_REMOTE;
158 fsl_chan->is_multi_fifo = dma_spec->args[2] & FSL_EDMA_MULTI_FIFO;
159
160 if ((dma_spec->args[2] & FSL_EDMA_EVEN_CH) && (i & 0x1))
161 continue;
162
163 if ((dma_spec->args[2] & FSL_EDMA_ODD_CH) && !(i & 0x1))
164 continue;
165
166 if (!b_chmux && i == dma_spec->args[0]) {
167 chan = dma_get_slave_channel(chan);
168 chan->device->privatecnt++;
169 mutex_unlock(&fsl_edma->fsl_edma_mutex);
170 return chan;
171 } else if (b_chmux && !fsl_chan->srcid) {
172 /* if controller support channel mux, choose a free channel */
173 chan = dma_get_slave_channel(chan);
174 chan->device->privatecnt++;
175 fsl_chan->srcid = dma_spec->args[0];
176 mutex_unlock(&fsl_edma->fsl_edma_mutex);
177 return chan;
178 }
179 }
180 mutex_unlock(&fsl_edma->fsl_edma_mutex);
181 return NULL;
182 }
183
184 static int
fsl_edma_irq_init(struct platform_device * pdev,struct fsl_edma_engine * fsl_edma)185 fsl_edma_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
186 {
187 int ret;
188
189 edma_writel(fsl_edma, ~0, fsl_edma->regs.intl);
190
191 fsl_edma->txirq = platform_get_irq_byname(pdev, "edma-tx");
192 if (fsl_edma->txirq < 0)
193 return fsl_edma->txirq;
194
195 fsl_edma->errirq = platform_get_irq_byname(pdev, "edma-err");
196 if (fsl_edma->errirq < 0)
197 return fsl_edma->errirq;
198
199 if (fsl_edma->txirq == fsl_edma->errirq) {
200 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq,
201 fsl_edma_irq_handler, 0, "eDMA", fsl_edma);
202 if (ret) {
203 dev_err(&pdev->dev, "Can't register eDMA IRQ.\n");
204 return ret;
205 }
206 } else {
207 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq,
208 fsl_edma_tx_handler, 0, "eDMA tx", fsl_edma);
209 if (ret) {
210 dev_err(&pdev->dev, "Can't register eDMA tx IRQ.\n");
211 return ret;
212 }
213
214 ret = devm_request_irq(&pdev->dev, fsl_edma->errirq,
215 fsl_edma_err_handler, 0, "eDMA err", fsl_edma);
216 if (ret) {
217 dev_err(&pdev->dev, "Can't register eDMA err IRQ.\n");
218 return ret;
219 }
220 }
221
222 return 0;
223 }
224
fsl_edma3_irq_init(struct platform_device * pdev,struct fsl_edma_engine * fsl_edma)225 static int fsl_edma3_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
226 {
227 int ret;
228 int i;
229
230 for (i = 0; i < fsl_edma->n_chans; i++) {
231
232 struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i];
233
234 if (fsl_edma->chan_masked & BIT(i))
235 continue;
236
237 /* request channel irq */
238 fsl_chan->txirq = platform_get_irq(pdev, i);
239 if (fsl_chan->txirq < 0) {
240 dev_err(&pdev->dev, "Can't get chan %d's irq.\n", i);
241 return -EINVAL;
242 }
243
244 ret = devm_request_irq(&pdev->dev, fsl_chan->txirq,
245 fsl_edma3_tx_handler, IRQF_SHARED,
246 fsl_chan->chan_name, fsl_chan);
247 if (ret) {
248 dev_err(&pdev->dev, "Can't register chan%d's IRQ.\n", i);
249 return -EINVAL;
250 }
251 }
252
253 return 0;
254 }
255
256 static int
fsl_edma2_irq_init(struct platform_device * pdev,struct fsl_edma_engine * fsl_edma)257 fsl_edma2_irq_init(struct platform_device *pdev,
258 struct fsl_edma_engine *fsl_edma)
259 {
260 int i, ret, irq;
261 int count;
262
263 edma_writel(fsl_edma, ~0, fsl_edma->regs.intl);
264
265 count = platform_irq_count(pdev);
266 dev_dbg(&pdev->dev, "%s Found %d interrupts\r\n", __func__, count);
267 if (count <= 2) {
268 dev_err(&pdev->dev, "Interrupts in DTS not correct.\n");
269 return -EINVAL;
270 }
271 /*
272 * 16 channel independent interrupts + 1 error interrupt on i.mx7ulp.
273 * 2 channel share one interrupt, for example, ch0/ch16, ch1/ch17...
274 * For now, just simply request irq without IRQF_SHARED flag, since 16
275 * channels are enough on i.mx7ulp whose M4 domain own some peripherals.
276 */
277 for (i = 0; i < count; i++) {
278 irq = platform_get_irq(pdev, i);
279 if (irq < 0)
280 return -ENXIO;
281
282 /* The last IRQ is for eDMA err */
283 if (i == count - 1)
284 ret = devm_request_irq(&pdev->dev, irq,
285 fsl_edma_err_handler,
286 0, "eDMA2-ERR", fsl_edma);
287 else
288 ret = devm_request_irq(&pdev->dev, irq,
289 fsl_edma_tx_handler, 0,
290 fsl_edma->chans[i].chan_name,
291 fsl_edma);
292 if (ret)
293 return ret;
294 }
295
296 return 0;
297 }
298
fsl_edma_irq_exit(struct platform_device * pdev,struct fsl_edma_engine * fsl_edma)299 static void fsl_edma_irq_exit(
300 struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
301 {
302 if (fsl_edma->txirq == fsl_edma->errirq) {
303 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma);
304 } else {
305 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma);
306 devm_free_irq(&pdev->dev, fsl_edma->errirq, fsl_edma);
307 }
308 }
309
fsl_disable_clocks(struct fsl_edma_engine * fsl_edma,int nr_clocks)310 static void fsl_disable_clocks(struct fsl_edma_engine *fsl_edma, int nr_clocks)
311 {
312 int i;
313
314 for (i = 0; i < nr_clocks; i++)
315 clk_disable_unprepare(fsl_edma->muxclk[i]);
316 }
317
318 static struct fsl_edma_drvdata vf610_data = {
319 .dmamuxs = DMAMUX_NR,
320 .flags = FSL_EDMA_DRV_WRAP_IO,
321 .chreg_off = EDMA_TCD,
322 .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd),
323 .setup_irq = fsl_edma_irq_init,
324 };
325
326 static struct fsl_edma_drvdata ls1028a_data = {
327 .dmamuxs = DMAMUX_NR,
328 .flags = FSL_EDMA_DRV_MUX_SWAP | FSL_EDMA_DRV_WRAP_IO,
329 .chreg_off = EDMA_TCD,
330 .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd),
331 .setup_irq = fsl_edma_irq_init,
332 };
333
334 static struct fsl_edma_drvdata imx7ulp_data = {
335 .dmamuxs = 1,
336 .chreg_off = EDMA_TCD,
337 .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd),
338 .flags = FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_CONFIG32,
339 .setup_irq = fsl_edma2_irq_init,
340 };
341
342 static struct fsl_edma_drvdata imx8qm_data = {
343 .flags = FSL_EDMA_DRV_HAS_PD | FSL_EDMA_DRV_EDMA3,
344 .chreg_space_sz = 0x10000,
345 .chreg_off = 0x10000,
346 .setup_irq = fsl_edma3_irq_init,
347 };
348
349 static struct fsl_edma_drvdata imx8qm_audio_data = {
350 .flags = FSL_EDMA_DRV_QUIRK_SWAPPED | FSL_EDMA_DRV_HAS_PD | FSL_EDMA_DRV_EDMA3,
351 .chreg_space_sz = 0x10000,
352 .chreg_off = 0x10000,
353 .setup_irq = fsl_edma3_irq_init,
354 };
355
356 static struct fsl_edma_drvdata imx93_data3 = {
357 .flags = FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA3,
358 .chreg_space_sz = 0x10000,
359 .chreg_off = 0x10000,
360 .setup_irq = fsl_edma3_irq_init,
361 };
362
363 static struct fsl_edma_drvdata imx93_data4 = {
364 .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA4,
365 .chreg_space_sz = 0x8000,
366 .chreg_off = 0x10000,
367 .setup_irq = fsl_edma3_irq_init,
368 };
369
370 static const struct of_device_id fsl_edma_dt_ids[] = {
371 { .compatible = "fsl,vf610-edma", .data = &vf610_data},
372 { .compatible = "fsl,ls1028a-edma", .data = &ls1028a_data},
373 { .compatible = "fsl,imx7ulp-edma", .data = &imx7ulp_data},
374 { .compatible = "fsl,imx8qm-edma", .data = &imx8qm_data},
375 { .compatible = "fsl,imx8qm-adma", .data = &imx8qm_audio_data},
376 { .compatible = "fsl,imx93-edma3", .data = &imx93_data3},
377 { .compatible = "fsl,imx93-edma4", .data = &imx93_data4},
378 { /* sentinel */ }
379 };
380 MODULE_DEVICE_TABLE(of, fsl_edma_dt_ids);
381
fsl_edma3_attach_pd(struct platform_device * pdev,struct fsl_edma_engine * fsl_edma)382 static int fsl_edma3_attach_pd(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
383 {
384 struct fsl_edma_chan *fsl_chan;
385 struct device_link *link;
386 struct device *pd_chan;
387 struct device *dev;
388 int i;
389
390 dev = &pdev->dev;
391
392 for (i = 0; i < fsl_edma->n_chans; i++) {
393 if (fsl_edma->chan_masked & BIT(i))
394 continue;
395
396 fsl_chan = &fsl_edma->chans[i];
397
398 pd_chan = dev_pm_domain_attach_by_id(dev, i);
399 if (IS_ERR_OR_NULL(pd_chan)) {
400 dev_err(dev, "Failed attach pd %d\n", i);
401 return -EINVAL;
402 }
403
404 link = device_link_add(dev, pd_chan, DL_FLAG_STATELESS |
405 DL_FLAG_PM_RUNTIME |
406 DL_FLAG_RPM_ACTIVE);
407 if (!link) {
408 dev_err(dev, "Failed to add device_link to %d\n", i);
409 return -EINVAL;
410 }
411
412 fsl_chan->pd_dev = pd_chan;
413
414 pm_runtime_use_autosuspend(fsl_chan->pd_dev);
415 pm_runtime_set_autosuspend_delay(fsl_chan->pd_dev, 200);
416 pm_runtime_set_active(fsl_chan->pd_dev);
417 }
418
419 return 0;
420 }
421
fsl_edma_probe(struct platform_device * pdev)422 static int fsl_edma_probe(struct platform_device *pdev)
423 {
424 const struct of_device_id *of_id =
425 of_match_device(fsl_edma_dt_ids, &pdev->dev);
426 struct device_node *np = pdev->dev.of_node;
427 struct fsl_edma_engine *fsl_edma;
428 const struct fsl_edma_drvdata *drvdata = NULL;
429 u32 chan_mask[2] = {0, 0};
430 struct edma_regs *regs;
431 int chans;
432 int ret, i;
433
434 if (of_id)
435 drvdata = of_id->data;
436 if (!drvdata) {
437 dev_err(&pdev->dev, "unable to find driver data\n");
438 return -EINVAL;
439 }
440
441 ret = of_property_read_u32(np, "dma-channels", &chans);
442 if (ret) {
443 dev_err(&pdev->dev, "Can't get dma-channels.\n");
444 return ret;
445 }
446
447 fsl_edma = devm_kzalloc(&pdev->dev, struct_size(fsl_edma, chans, chans),
448 GFP_KERNEL);
449 if (!fsl_edma)
450 return -ENOMEM;
451
452 fsl_edma->drvdata = drvdata;
453 fsl_edma->n_chans = chans;
454 mutex_init(&fsl_edma->fsl_edma_mutex);
455
456 fsl_edma->membase = devm_platform_ioremap_resource(pdev, 0);
457 if (IS_ERR(fsl_edma->membase))
458 return PTR_ERR(fsl_edma->membase);
459
460 if (!(drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)) {
461 fsl_edma_setup_regs(fsl_edma);
462 regs = &fsl_edma->regs;
463 }
464
465 if (drvdata->flags & FSL_EDMA_DRV_HAS_DMACLK) {
466 fsl_edma->dmaclk = devm_clk_get_enabled(&pdev->dev, "dma");
467 if (IS_ERR(fsl_edma->dmaclk)) {
468 dev_err(&pdev->dev, "Missing DMA block clock.\n");
469 return PTR_ERR(fsl_edma->dmaclk);
470 }
471 }
472
473 if (drvdata->flags & FSL_EDMA_DRV_HAS_CHCLK) {
474 fsl_edma->chclk = devm_clk_get_enabled(&pdev->dev, "mp");
475 if (IS_ERR(fsl_edma->chclk)) {
476 dev_err(&pdev->dev, "Missing MP block clock.\n");
477 return PTR_ERR(fsl_edma->chclk);
478 }
479 }
480
481 ret = of_property_read_variable_u32_array(np, "dma-channel-mask", chan_mask, 1, 2);
482
483 if (ret > 0) {
484 fsl_edma->chan_masked = chan_mask[1];
485 fsl_edma->chan_masked <<= 32;
486 fsl_edma->chan_masked |= chan_mask[0];
487 }
488
489 for (i = 0; i < fsl_edma->drvdata->dmamuxs; i++) {
490 char clkname[32];
491
492 /* eDMAv3 mux register move to TCD area if ch_mux exist */
493 if (drvdata->flags & FSL_EDMA_DRV_SPLIT_REG)
494 break;
495
496 fsl_edma->muxbase[i] = devm_platform_ioremap_resource(pdev,
497 1 + i);
498 if (IS_ERR(fsl_edma->muxbase[i])) {
499 /* on error: disable all previously enabled clks */
500 fsl_disable_clocks(fsl_edma, i);
501 return PTR_ERR(fsl_edma->muxbase[i]);
502 }
503
504 sprintf(clkname, "dmamux%d", i);
505 fsl_edma->muxclk[i] = devm_clk_get_enabled(&pdev->dev, clkname);
506 if (IS_ERR(fsl_edma->muxclk[i])) {
507 dev_err(&pdev->dev, "Missing DMAMUX block clock.\n");
508 /* on error: disable all previously enabled clks */
509 return PTR_ERR(fsl_edma->muxclk[i]);
510 }
511 }
512
513 fsl_edma->big_endian = of_property_read_bool(np, "big-endian");
514
515 if (drvdata->flags & FSL_EDMA_DRV_HAS_PD) {
516 ret = fsl_edma3_attach_pd(pdev, fsl_edma);
517 if (ret)
518 return ret;
519 }
520
521 INIT_LIST_HEAD(&fsl_edma->dma_dev.channels);
522 for (i = 0; i < fsl_edma->n_chans; i++) {
523 struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i];
524 int len;
525
526 if (fsl_edma->chan_masked & BIT(i))
527 continue;
528
529 snprintf(fsl_chan->chan_name, sizeof(fsl_chan->chan_name), "%s-CH%02d",
530 dev_name(&pdev->dev), i);
531
532 fsl_chan->edma = fsl_edma;
533 fsl_chan->pm_state = RUNNING;
534 fsl_chan->slave_id = 0;
535 fsl_chan->idle = true;
536 fsl_chan->dma_dir = DMA_NONE;
537 fsl_chan->vchan.desc_free = fsl_edma_free_desc;
538
539 len = (drvdata->flags & FSL_EDMA_DRV_SPLIT_REG) ?
540 offsetof(struct fsl_edma3_ch_reg, tcd) : 0;
541 fsl_chan->tcd = fsl_edma->membase
542 + i * drvdata->chreg_space_sz + drvdata->chreg_off + len;
543
544 fsl_chan->pdev = pdev;
545 vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev);
546
547 edma_write_tcdreg(fsl_chan, 0, csr);
548 fsl_edma_chan_mux(fsl_chan, 0, false);
549 }
550
551 ret = fsl_edma->drvdata->setup_irq(pdev, fsl_edma);
552 if (ret)
553 return ret;
554
555 dma_cap_set(DMA_PRIVATE, fsl_edma->dma_dev.cap_mask);
556 dma_cap_set(DMA_SLAVE, fsl_edma->dma_dev.cap_mask);
557 dma_cap_set(DMA_CYCLIC, fsl_edma->dma_dev.cap_mask);
558 dma_cap_set(DMA_MEMCPY, fsl_edma->dma_dev.cap_mask);
559
560 fsl_edma->dma_dev.dev = &pdev->dev;
561 fsl_edma->dma_dev.device_alloc_chan_resources
562 = fsl_edma_alloc_chan_resources;
563 fsl_edma->dma_dev.device_free_chan_resources
564 = fsl_edma_free_chan_resources;
565 fsl_edma->dma_dev.device_tx_status = fsl_edma_tx_status;
566 fsl_edma->dma_dev.device_prep_slave_sg = fsl_edma_prep_slave_sg;
567 fsl_edma->dma_dev.device_prep_dma_cyclic = fsl_edma_prep_dma_cyclic;
568 fsl_edma->dma_dev.device_prep_dma_memcpy = fsl_edma_prep_memcpy;
569 fsl_edma->dma_dev.device_config = fsl_edma_slave_config;
570 fsl_edma->dma_dev.device_pause = fsl_edma_pause;
571 fsl_edma->dma_dev.device_resume = fsl_edma_resume;
572 fsl_edma->dma_dev.device_terminate_all = fsl_edma_terminate_all;
573 fsl_edma->dma_dev.device_synchronize = fsl_edma_synchronize;
574 fsl_edma->dma_dev.device_issue_pending = fsl_edma_issue_pending;
575
576 fsl_edma->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS;
577 fsl_edma->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS;
578
579 if (drvdata->flags & FSL_EDMA_DRV_BUS_8BYTE) {
580 fsl_edma->dma_dev.src_addr_widths |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
581 fsl_edma->dma_dev.dst_addr_widths |= BIT(DMA_SLAVE_BUSWIDTH_8_BYTES);
582 }
583
584 fsl_edma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
585 if (drvdata->flags & FSL_EDMA_DRV_DEV_TO_DEV)
586 fsl_edma->dma_dev.directions |= BIT(DMA_DEV_TO_DEV);
587
588 fsl_edma->dma_dev.copy_align = drvdata->flags & FSL_EDMA_DRV_ALIGN_64BYTE ?
589 DMAENGINE_ALIGN_64_BYTES :
590 DMAENGINE_ALIGN_32_BYTES;
591
592 /* Per worst case 'nbytes = 1' take CITER as the max_seg_size */
593 dma_set_max_seg_size(fsl_edma->dma_dev.dev,
594 FIELD_GET(EDMA_TCD_ITER_MASK, EDMA_TCD_ITER_MASK));
595
596 fsl_edma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
597
598 platform_set_drvdata(pdev, fsl_edma);
599
600 ret = dma_async_device_register(&fsl_edma->dma_dev);
601 if (ret) {
602 dev_err(&pdev->dev,
603 "Can't register Freescale eDMA engine. (%d)\n", ret);
604 return ret;
605 }
606
607 ret = of_dma_controller_register(np,
608 drvdata->flags & FSL_EDMA_DRV_SPLIT_REG ? fsl_edma3_xlate : fsl_edma_xlate,
609 fsl_edma);
610 if (ret) {
611 dev_err(&pdev->dev,
612 "Can't register Freescale eDMA of_dma. (%d)\n", ret);
613 dma_async_device_unregister(&fsl_edma->dma_dev);
614 return ret;
615 }
616
617 /* enable round robin arbitration */
618 if (!(drvdata->flags & FSL_EDMA_DRV_SPLIT_REG))
619 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr);
620
621 return 0;
622 }
623
fsl_edma_remove(struct platform_device * pdev)624 static int fsl_edma_remove(struct platform_device *pdev)
625 {
626 struct device_node *np = pdev->dev.of_node;
627 struct fsl_edma_engine *fsl_edma = platform_get_drvdata(pdev);
628
629 fsl_edma_irq_exit(pdev, fsl_edma);
630 fsl_edma_cleanup_vchan(&fsl_edma->dma_dev);
631 of_dma_controller_free(np);
632 dma_async_device_unregister(&fsl_edma->dma_dev);
633 fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs);
634
635 return 0;
636 }
637
fsl_edma_suspend_late(struct device * dev)638 static int fsl_edma_suspend_late(struct device *dev)
639 {
640 struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev);
641 struct fsl_edma_chan *fsl_chan;
642 unsigned long flags;
643 int i;
644
645 for (i = 0; i < fsl_edma->n_chans; i++) {
646 fsl_chan = &fsl_edma->chans[i];
647 if (fsl_edma->chan_masked & BIT(i))
648 continue;
649 spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
650 /* Make sure chan is idle or will force disable. */
651 if (unlikely(!fsl_chan->idle)) {
652 dev_warn(dev, "WARN: There is non-idle channel.");
653 fsl_edma_disable_request(fsl_chan);
654 fsl_edma_chan_mux(fsl_chan, 0, false);
655 }
656
657 fsl_chan->pm_state = SUSPENDED;
658 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
659 }
660
661 return 0;
662 }
663
fsl_edma_resume_early(struct device * dev)664 static int fsl_edma_resume_early(struct device *dev)
665 {
666 struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev);
667 struct fsl_edma_chan *fsl_chan;
668 struct edma_regs *regs = &fsl_edma->regs;
669 int i;
670
671 for (i = 0; i < fsl_edma->n_chans; i++) {
672 fsl_chan = &fsl_edma->chans[i];
673 if (fsl_edma->chan_masked & BIT(i))
674 continue;
675 fsl_chan->pm_state = RUNNING;
676 edma_write_tcdreg(fsl_chan, 0, csr);
677 if (fsl_chan->slave_id != 0)
678 fsl_edma_chan_mux(fsl_chan, fsl_chan->slave_id, true);
679 }
680
681 if (!(fsl_edma->drvdata->flags & FSL_EDMA_DRV_SPLIT_REG))
682 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr);
683
684 return 0;
685 }
686
687 /*
688 * eDMA provides the service to others, so it should be suspend late
689 * and resume early. When eDMA suspend, all of the clients should stop
690 * the DMA data transmission and let the channel idle.
691 */
692 static const struct dev_pm_ops fsl_edma_pm_ops = {
693 .suspend_late = fsl_edma_suspend_late,
694 .resume_early = fsl_edma_resume_early,
695 };
696
697 static struct platform_driver fsl_edma_driver = {
698 .driver = {
699 .name = "fsl-edma",
700 .of_match_table = fsl_edma_dt_ids,
701 .pm = &fsl_edma_pm_ops,
702 },
703 .probe = fsl_edma_probe,
704 .remove = fsl_edma_remove,
705 };
706
fsl_edma_init(void)707 static int __init fsl_edma_init(void)
708 {
709 return platform_driver_register(&fsl_edma_driver);
710 }
711 subsys_initcall(fsl_edma_init);
712
fsl_edma_exit(void)713 static void __exit fsl_edma_exit(void)
714 {
715 platform_driver_unregister(&fsl_edma_driver);
716 }
717 module_exit(fsl_edma_exit);
718
719 MODULE_ALIAS("platform:fsl-edma");
720 MODULE_DESCRIPTION("Freescale eDMA engine driver");
721 MODULE_LICENSE("GPL v2");
722