1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2013-2014 Freescale Semiconductor, Inc. 4 * Copyright 2018 Angelo Dureghello <angelo@sysam.it> 5 */ 6 #ifndef _FSL_EDMA_COMMON_H_ 7 #define _FSL_EDMA_COMMON_H_ 8 9 #include "virt-dma.h" 10 11 #define EDMA_CR_EDBG BIT(1) 12 #define EDMA_CR_ERCA BIT(2) 13 #define EDMA_CR_ERGA BIT(3) 14 #define EDMA_CR_HOE BIT(4) 15 #define EDMA_CR_HALT BIT(5) 16 #define EDMA_CR_CLM BIT(6) 17 #define EDMA_CR_EMLM BIT(7) 18 #define EDMA_CR_ECX BIT(16) 19 #define EDMA_CR_CX BIT(17) 20 21 #define EDMA_SEEI_SEEI(x) ((x) & GENMASK(4, 0)) 22 #define EDMA_CEEI_CEEI(x) ((x) & GENMASK(4, 0)) 23 #define EDMA_CINT_CINT(x) ((x) & GENMASK(4, 0)) 24 #define EDMA_CERR_CERR(x) ((x) & GENMASK(4, 0)) 25 26 #define EDMA_TCD_ATTR_DSIZE(x) (((x) & GENMASK(2, 0))) 27 #define EDMA_TCD_ATTR_DMOD(x) (((x) & GENMASK(4, 0)) << 3) 28 #define EDMA_TCD_ATTR_SSIZE(x) (((x) & GENMASK(2, 0)) << 8) 29 #define EDMA_TCD_ATTR_SMOD(x) (((x) & GENMASK(4, 0)) << 11) 30 #define EDMA_TCD_ATTR_DSIZE_8BIT 0 31 #define EDMA_TCD_ATTR_DSIZE_16BIT BIT(0) 32 #define EDMA_TCD_ATTR_DSIZE_32BIT BIT(1) 33 #define EDMA_TCD_ATTR_DSIZE_64BIT (BIT(0) | BIT(1)) 34 #define EDMA_TCD_ATTR_DSIZE_32BYTE (BIT(3) | BIT(0)) 35 #define EDMA_TCD_ATTR_SSIZE_8BIT 0 36 #define EDMA_TCD_ATTR_SSIZE_16BIT (EDMA_TCD_ATTR_DSIZE_16BIT << 8) 37 #define EDMA_TCD_ATTR_SSIZE_32BIT (EDMA_TCD_ATTR_DSIZE_32BIT << 8) 38 #define EDMA_TCD_ATTR_SSIZE_64BIT (EDMA_TCD_ATTR_DSIZE_64BIT << 8) 39 #define EDMA_TCD_ATTR_SSIZE_32BYTE (EDMA_TCD_ATTR_DSIZE_32BYTE << 8) 40 41 #define EDMA_TCD_CITER_CITER(x) ((x) & GENMASK(14, 0)) 42 #define EDMA_TCD_BITER_BITER(x) ((x) & GENMASK(14, 0)) 43 44 #define EDMA_TCD_CSR_START BIT(0) 45 #define EDMA_TCD_CSR_INT_MAJOR BIT(1) 46 #define EDMA_TCD_CSR_INT_HALF BIT(2) 47 #define EDMA_TCD_CSR_D_REQ BIT(3) 48 #define EDMA_TCD_CSR_E_SG BIT(4) 49 #define EDMA_TCD_CSR_E_LINK BIT(5) 50 #define EDMA_TCD_CSR_ACTIVE BIT(6) 51 #define EDMA_TCD_CSR_DONE BIT(7) 52 53 #define EDMAMUX_CHCFG_DIS 0x0 54 #define EDMAMUX_CHCFG_ENBL 0x80 55 #define EDMAMUX_CHCFG_SOURCE(n) ((n) & 0x3F) 56 57 #define DMAMUX_NR 2 58 59 #define FSL_EDMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ 60 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ 61 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \ 62 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)) 63 enum fsl_edma_pm_state { 64 RUNNING = 0, 65 SUSPENDED, 66 }; 67 68 struct fsl_edma_hw_tcd { 69 __le32 saddr; 70 __le16 soff; 71 __le16 attr; 72 __le32 nbytes; 73 __le32 slast; 74 __le32 daddr; 75 __le16 doff; 76 __le16 citer; 77 __le32 dlast_sga; 78 __le16 csr; 79 __le16 biter; 80 }; 81 82 /* 83 * These are iomem pointers, for both v32 and v64. 84 */ 85 struct edma_regs { 86 void __iomem *cr; 87 void __iomem *es; 88 void __iomem *erqh; 89 void __iomem *erql; /* aka erq on v32 */ 90 void __iomem *eeih; 91 void __iomem *eeil; /* aka eei on v32 */ 92 void __iomem *seei; 93 void __iomem *ceei; 94 void __iomem *serq; 95 void __iomem *cerq; 96 void __iomem *cint; 97 void __iomem *cerr; 98 void __iomem *ssrt; 99 void __iomem *cdne; 100 void __iomem *inth; 101 void __iomem *intl; 102 void __iomem *errh; 103 void __iomem *errl; 104 struct fsl_edma_hw_tcd __iomem *tcd; 105 }; 106 107 struct fsl_edma_sw_tcd { 108 dma_addr_t ptcd; 109 struct fsl_edma_hw_tcd *vtcd; 110 }; 111 112 struct fsl_edma_chan { 113 struct virt_dma_chan vchan; 114 enum dma_status status; 115 enum fsl_edma_pm_state pm_state; 116 bool idle; 117 u32 slave_id; 118 struct fsl_edma_engine *edma; 119 struct fsl_edma_desc *edesc; 120 struct dma_slave_config cfg; 121 u32 attr; 122 struct dma_pool *tcd_pool; 123 }; 124 125 struct fsl_edma_desc { 126 struct virt_dma_desc vdesc; 127 struct fsl_edma_chan *echan; 128 bool iscyclic; 129 enum dma_transfer_direction dirn; 130 unsigned int n_tcds; 131 struct fsl_edma_sw_tcd tcd[]; 132 }; 133 134 enum edma_version { 135 v1, /* 32ch, Vybdir, mpc57x, etc */ 136 v2, /* 64ch Coldfire */ 137 }; 138 139 struct fsl_edma_engine { 140 struct dma_device dma_dev; 141 void __iomem *membase; 142 void __iomem *muxbase[DMAMUX_NR]; 143 struct clk *muxclk[DMAMUX_NR]; 144 struct mutex fsl_edma_mutex; 145 u32 n_chans; 146 int txirq; 147 int errirq; 148 bool big_endian; 149 enum edma_version version; 150 struct edma_regs regs; 151 struct fsl_edma_chan chans[]; 152 }; 153 154 /* 155 * R/W functions for big- or little-endian registers: 156 * The eDMA controller's endian is independent of the CPU core's endian. 157 * For the big-endian IP module, the offset for 8-bit or 16-bit registers 158 * should also be swapped opposite to that in little-endian IP. 159 */ 160 static inline u32 edma_readl(struct fsl_edma_engine *edma, void __iomem *addr) 161 { 162 if (edma->big_endian) 163 return ioread32be(addr); 164 else 165 return ioread32(addr); 166 } 167 168 static inline void edma_writeb(struct fsl_edma_engine *edma, 169 u8 val, void __iomem *addr) 170 { 171 /* swap the reg offset for these in big-endian mode */ 172 if (edma->big_endian) 173 iowrite8(val, (void __iomem *)((unsigned long)addr ^ 0x3)); 174 else 175 iowrite8(val, addr); 176 } 177 178 static inline void edma_writew(struct fsl_edma_engine *edma, 179 u16 val, void __iomem *addr) 180 { 181 /* swap the reg offset for these in big-endian mode */ 182 if (edma->big_endian) 183 iowrite16be(val, (void __iomem *)((unsigned long)addr ^ 0x2)); 184 else 185 iowrite16(val, addr); 186 } 187 188 static inline void edma_writel(struct fsl_edma_engine *edma, 189 u32 val, void __iomem *addr) 190 { 191 if (edma->big_endian) 192 iowrite32be(val, addr); 193 else 194 iowrite32(val, addr); 195 } 196 197 static inline struct fsl_edma_chan *to_fsl_edma_chan(struct dma_chan *chan) 198 { 199 return container_of(chan, struct fsl_edma_chan, vchan.chan); 200 } 201 202 static inline struct fsl_edma_desc *to_fsl_edma_desc(struct virt_dma_desc *vd) 203 { 204 return container_of(vd, struct fsl_edma_desc, vdesc); 205 } 206 207 void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan); 208 void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan, 209 unsigned int slot, bool enable); 210 void fsl_edma_free_desc(struct virt_dma_desc *vdesc); 211 int fsl_edma_terminate_all(struct dma_chan *chan); 212 int fsl_edma_pause(struct dma_chan *chan); 213 int fsl_edma_resume(struct dma_chan *chan); 214 int fsl_edma_slave_config(struct dma_chan *chan, 215 struct dma_slave_config *cfg); 216 enum dma_status fsl_edma_tx_status(struct dma_chan *chan, 217 dma_cookie_t cookie, struct dma_tx_state *txstate); 218 struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic( 219 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, 220 size_t period_len, enum dma_transfer_direction direction, 221 unsigned long flags); 222 struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg( 223 struct dma_chan *chan, struct scatterlist *sgl, 224 unsigned int sg_len, enum dma_transfer_direction direction, 225 unsigned long flags, void *context); 226 void fsl_edma_xfer_desc(struct fsl_edma_chan *fsl_chan); 227 void fsl_edma_issue_pending(struct dma_chan *chan); 228 int fsl_edma_alloc_chan_resources(struct dma_chan *chan); 229 void fsl_edma_free_chan_resources(struct dma_chan *chan); 230 void fsl_edma_cleanup_vchan(struct dma_device *dmadev); 231 void fsl_edma_setup_regs(struct fsl_edma_engine *edma); 232 233 #endif /* _FSL_EDMA_COMMON_H_ */ 234