1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2013-2014 Freescale Semiconductor, Inc. 4 * Copyright 2018 Angelo Dureghello <angelo@sysam.it> 5 */ 6 #ifndef _FSL_EDMA_COMMON_H_ 7 #define _FSL_EDMA_COMMON_H_ 8 9 #include <linux/dma-direction.h> 10 #include <linux/platform_device.h> 11 #include "virt-dma.h" 12 13 #define EDMA_CR_EDBG BIT(1) 14 #define EDMA_CR_ERCA BIT(2) 15 #define EDMA_CR_ERGA BIT(3) 16 #define EDMA_CR_HOE BIT(4) 17 #define EDMA_CR_HALT BIT(5) 18 #define EDMA_CR_CLM BIT(6) 19 #define EDMA_CR_EMLM BIT(7) 20 #define EDMA_CR_ECX BIT(16) 21 #define EDMA_CR_CX BIT(17) 22 23 #define EDMA_SEEI_SEEI(x) ((x) & GENMASK(4, 0)) 24 #define EDMA_CEEI_CEEI(x) ((x) & GENMASK(4, 0)) 25 #define EDMA_CINT_CINT(x) ((x) & GENMASK(4, 0)) 26 #define EDMA_CERR_CERR(x) ((x) & GENMASK(4, 0)) 27 28 #define EDMA_TCD_ATTR_DSIZE(x) (((x) & GENMASK(2, 0))) 29 #define EDMA_TCD_ATTR_DMOD(x) (((x) & GENMASK(4, 0)) << 3) 30 #define EDMA_TCD_ATTR_SSIZE(x) (((x) & GENMASK(2, 0)) << 8) 31 #define EDMA_TCD_ATTR_SMOD(x) (((x) & GENMASK(4, 0)) << 11) 32 33 #define EDMA_TCD_ITER_MASK GENMASK(14, 0) 34 #define EDMA_TCD_CITER_CITER(x) ((x) & EDMA_TCD_ITER_MASK) 35 #define EDMA_TCD_BITER_BITER(x) ((x) & EDMA_TCD_ITER_MASK) 36 37 #define EDMA_TCD_CSR_START BIT(0) 38 #define EDMA_TCD_CSR_INT_MAJOR BIT(1) 39 #define EDMA_TCD_CSR_INT_HALF BIT(2) 40 #define EDMA_TCD_CSR_D_REQ BIT(3) 41 #define EDMA_TCD_CSR_E_SG BIT(4) 42 #define EDMA_TCD_CSR_E_LINK BIT(5) 43 #define EDMA_TCD_CSR_ACTIVE BIT(6) 44 #define EDMA_TCD_CSR_DONE BIT(7) 45 46 #define EDMA_V3_TCD_NBYTES_MLOFF_NBYTES(x) ((x) & GENMASK(9, 0)) 47 #define EDMA_V3_TCD_NBYTES_MLOFF(x) (x << 10) 48 #define EDMA_V3_TCD_NBYTES_DMLOE (1 << 30) 49 #define EDMA_V3_TCD_NBYTES_SMLOE (1 << 31) 50 51 #define EDMAMUX_CHCFG_DIS 0x0 52 #define EDMAMUX_CHCFG_ENBL 0x80 53 #define EDMAMUX_CHCFG_SOURCE(n) ((n) & 0x3F) 54 55 #define DMAMUX_NR 2 56 57 #define EDMA_TCD 0x1000 58 59 #define FSL_EDMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ 60 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ 61 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) | \ 62 BIT(DMA_SLAVE_BUSWIDTH_8_BYTES)) 63 64 #define EDMA_V3_CH_SBR_RD BIT(22) 65 #define EDMA_V3_CH_SBR_WR BIT(21) 66 #define EDMA_V3_CH_CSR_ERQ BIT(0) 67 #define EDMA_V3_CH_CSR_EARQ BIT(1) 68 #define EDMA_V3_CH_CSR_EEI BIT(2) 69 #define EDMA_V3_CH_CSR_DONE BIT(30) 70 #define EDMA_V3_CH_CSR_ACTIVE BIT(31) 71 72 enum fsl_edma_pm_state { 73 RUNNING = 0, 74 SUSPENDED, 75 }; 76 77 struct fsl_edma_hw_tcd { 78 __le32 saddr; 79 __le16 soff; 80 __le16 attr; 81 __le32 nbytes; 82 __le32 slast; 83 __le32 daddr; 84 __le16 doff; 85 __le16 citer; 86 __le32 dlast_sga; 87 __le16 csr; 88 __le16 biter; 89 }; 90 91 struct fsl_edma3_ch_reg { 92 __le32 ch_csr; 93 __le32 ch_es; 94 __le32 ch_int; 95 __le32 ch_sbr; 96 __le32 ch_pri; 97 __le32 ch_mux; 98 __le32 ch_mattr; /* edma4, reserved for edma3 */ 99 __le32 ch_reserved; 100 struct fsl_edma_hw_tcd tcd; 101 } __packed; 102 103 /* 104 * These are iomem pointers, for both v32 and v64. 105 */ 106 struct edma_regs { 107 void __iomem *cr; 108 void __iomem *es; 109 void __iomem *erqh; 110 void __iomem *erql; /* aka erq on v32 */ 111 void __iomem *eeih; 112 void __iomem *eeil; /* aka eei on v32 */ 113 void __iomem *seei; 114 void __iomem *ceei; 115 void __iomem *serq; 116 void __iomem *cerq; 117 void __iomem *cint; 118 void __iomem *cerr; 119 void __iomem *ssrt; 120 void __iomem *cdne; 121 void __iomem *inth; 122 void __iomem *intl; 123 void __iomem *errh; 124 void __iomem *errl; 125 }; 126 127 struct fsl_edma_sw_tcd { 128 dma_addr_t ptcd; 129 struct fsl_edma_hw_tcd *vtcd; 130 }; 131 132 struct fsl_edma_chan { 133 struct virt_dma_chan vchan; 134 enum dma_status status; 135 enum fsl_edma_pm_state pm_state; 136 bool idle; 137 u32 slave_id; 138 struct fsl_edma_engine *edma; 139 struct fsl_edma_desc *edesc; 140 struct dma_slave_config cfg; 141 u32 attr; 142 bool is_sw; 143 struct dma_pool *tcd_pool; 144 dma_addr_t dma_dev_addr; 145 u32 dma_dev_size; 146 enum dma_data_direction dma_dir; 147 char chan_name[32]; 148 struct fsl_edma_hw_tcd __iomem *tcd; 149 u32 real_count; 150 struct work_struct issue_worker; 151 struct platform_device *pdev; 152 struct device *pd_dev; 153 u32 srcid; 154 struct clk *clk; 155 int priority; 156 int hw_chanid; 157 int txirq; 158 bool is_rxchan; 159 bool is_remote; 160 bool is_multi_fifo; 161 }; 162 163 struct fsl_edma_desc { 164 struct virt_dma_desc vdesc; 165 struct fsl_edma_chan *echan; 166 bool iscyclic; 167 enum dma_transfer_direction dirn; 168 unsigned int n_tcds; 169 struct fsl_edma_sw_tcd tcd[]; 170 }; 171 172 #define FSL_EDMA_DRV_HAS_DMACLK BIT(0) 173 #define FSL_EDMA_DRV_MUX_SWAP BIT(1) 174 #define FSL_EDMA_DRV_CONFIG32 BIT(2) 175 #define FSL_EDMA_DRV_WRAP_IO BIT(3) 176 #define FSL_EDMA_DRV_EDMA64 BIT(4) 177 #define FSL_EDMA_DRV_HAS_PD BIT(5) 178 #define FSL_EDMA_DRV_HAS_CHCLK BIT(6) 179 #define FSL_EDMA_DRV_HAS_CHMUX BIT(7) 180 /* imx8 QM audio edma remote local swapped */ 181 #define FSL_EDMA_DRV_QUIRK_SWAPPED BIT(8) 182 /* control and status register is in tcd address space, edma3 reg layout */ 183 #define FSL_EDMA_DRV_SPLIT_REG BIT(9) 184 #define FSL_EDMA_DRV_BUS_8BYTE BIT(10) 185 #define FSL_EDMA_DRV_DEV_TO_DEV BIT(11) 186 #define FSL_EDMA_DRV_ALIGN_64BYTE BIT(12) 187 /* Need clean CHn_CSR DONE before enable TCD's ESG */ 188 #define FSL_EDMA_DRV_CLEAR_DONE_E_SG BIT(13) 189 /* Need clean CHn_CSR DONE before enable TCD's MAJORELINK */ 190 #define FSL_EDMA_DRV_CLEAR_DONE_E_LINK BIT(14) 191 192 #define FSL_EDMA_DRV_EDMA3 (FSL_EDMA_DRV_SPLIT_REG | \ 193 FSL_EDMA_DRV_BUS_8BYTE | \ 194 FSL_EDMA_DRV_DEV_TO_DEV | \ 195 FSL_EDMA_DRV_ALIGN_64BYTE | \ 196 FSL_EDMA_DRV_CLEAR_DONE_E_SG | \ 197 FSL_EDMA_DRV_CLEAR_DONE_E_LINK) 198 199 #define FSL_EDMA_DRV_EDMA4 (FSL_EDMA_DRV_SPLIT_REG | \ 200 FSL_EDMA_DRV_BUS_8BYTE | \ 201 FSL_EDMA_DRV_DEV_TO_DEV | \ 202 FSL_EDMA_DRV_ALIGN_64BYTE | \ 203 FSL_EDMA_DRV_CLEAR_DONE_E_LINK) 204 205 struct fsl_edma_drvdata { 206 u32 dmamuxs; /* only used before v3 */ 207 u32 chreg_off; 208 u32 chreg_space_sz; 209 u32 flags; 210 int (*setup_irq)(struct platform_device *pdev, 211 struct fsl_edma_engine *fsl_edma); 212 }; 213 214 struct fsl_edma_engine { 215 struct dma_device dma_dev; 216 void __iomem *membase; 217 void __iomem *muxbase[DMAMUX_NR]; 218 struct clk *muxclk[DMAMUX_NR]; 219 struct clk *dmaclk; 220 struct clk *chclk; 221 struct mutex fsl_edma_mutex; 222 const struct fsl_edma_drvdata *drvdata; 223 u32 n_chans; 224 int txirq; 225 int errirq; 226 bool big_endian; 227 struct edma_regs regs; 228 u64 chan_masked; 229 struct fsl_edma_chan chans[]; 230 }; 231 232 #define edma_read_tcdreg(chan, __name) \ 233 (sizeof(chan->tcd->__name) == sizeof(u32) ? \ 234 edma_readl(chan->edma, &chan->tcd->__name) : \ 235 edma_readw(chan->edma, &chan->tcd->__name)) 236 237 #define edma_write_tcdreg(chan, val, __name) \ 238 (sizeof(chan->tcd->__name) == sizeof(u32) ? \ 239 edma_writel(chan->edma, (u32 __force)val, &chan->tcd->__name) : \ 240 edma_writew(chan->edma, (u16 __force)val, &chan->tcd->__name)) 241 242 #define edma_readl_chreg(chan, __name) \ 243 edma_readl(chan->edma, \ 244 (void __iomem *)&(container_of(chan->tcd, struct fsl_edma3_ch_reg, tcd)->__name)) 245 246 #define edma_writel_chreg(chan, val, __name) \ 247 edma_writel(chan->edma, val, \ 248 (void __iomem *)&(container_of(chan->tcd, struct fsl_edma3_ch_reg, tcd)->__name)) 249 250 /* 251 * R/W functions for big- or little-endian registers: 252 * The eDMA controller's endian is independent of the CPU core's endian. 253 * For the big-endian IP module, the offset for 8-bit or 16-bit registers 254 * should also be swapped opposite to that in little-endian IP. 255 */ 256 static inline u32 edma_readl(struct fsl_edma_engine *edma, void __iomem *addr) 257 { 258 if (edma->big_endian) 259 return ioread32be(addr); 260 else 261 return ioread32(addr); 262 } 263 264 static inline u16 edma_readw(struct fsl_edma_engine *edma, void __iomem *addr) 265 { 266 if (edma->big_endian) 267 return ioread16be(addr); 268 else 269 return ioread16(addr); 270 } 271 272 static inline void edma_writeb(struct fsl_edma_engine *edma, 273 u8 val, void __iomem *addr) 274 { 275 /* swap the reg offset for these in big-endian mode */ 276 if (edma->big_endian) 277 iowrite8(val, (void __iomem *)((unsigned long)addr ^ 0x3)); 278 else 279 iowrite8(val, addr); 280 } 281 282 static inline void edma_writew(struct fsl_edma_engine *edma, 283 u16 val, void __iomem *addr) 284 { 285 /* swap the reg offset for these in big-endian mode */ 286 if (edma->big_endian) 287 iowrite16be(val, (void __iomem *)((unsigned long)addr ^ 0x2)); 288 else 289 iowrite16(val, addr); 290 } 291 292 static inline void edma_writel(struct fsl_edma_engine *edma, 293 u32 val, void __iomem *addr) 294 { 295 if (edma->big_endian) 296 iowrite32be(val, addr); 297 else 298 iowrite32(val, addr); 299 } 300 301 static inline struct fsl_edma_chan *to_fsl_edma_chan(struct dma_chan *chan) 302 { 303 return container_of(chan, struct fsl_edma_chan, vchan.chan); 304 } 305 306 static inline u32 fsl_edma_drvflags(struct fsl_edma_chan *fsl_chan) 307 { 308 return fsl_chan->edma->drvdata->flags; 309 } 310 311 static inline struct fsl_edma_desc *to_fsl_edma_desc(struct virt_dma_desc *vd) 312 { 313 return container_of(vd, struct fsl_edma_desc, vdesc); 314 } 315 316 static inline void fsl_edma_err_chan_handler(struct fsl_edma_chan *fsl_chan) 317 { 318 fsl_chan->status = DMA_ERROR; 319 fsl_chan->idle = true; 320 } 321 322 void fsl_edma_tx_chan_handler(struct fsl_edma_chan *fsl_chan); 323 void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan); 324 void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan, 325 unsigned int slot, bool enable); 326 void fsl_edma_free_desc(struct virt_dma_desc *vdesc); 327 int fsl_edma_terminate_all(struct dma_chan *chan); 328 int fsl_edma_pause(struct dma_chan *chan); 329 int fsl_edma_resume(struct dma_chan *chan); 330 int fsl_edma_slave_config(struct dma_chan *chan, 331 struct dma_slave_config *cfg); 332 enum dma_status fsl_edma_tx_status(struct dma_chan *chan, 333 dma_cookie_t cookie, struct dma_tx_state *txstate); 334 struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic( 335 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len, 336 size_t period_len, enum dma_transfer_direction direction, 337 unsigned long flags); 338 struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg( 339 struct dma_chan *chan, struct scatterlist *sgl, 340 unsigned int sg_len, enum dma_transfer_direction direction, 341 unsigned long flags, void *context); 342 struct dma_async_tx_descriptor *fsl_edma_prep_memcpy( 343 struct dma_chan *chan, dma_addr_t dma_dst, dma_addr_t dma_src, 344 size_t len, unsigned long flags); 345 void fsl_edma_xfer_desc(struct fsl_edma_chan *fsl_chan); 346 void fsl_edma_issue_pending(struct dma_chan *chan); 347 int fsl_edma_alloc_chan_resources(struct dma_chan *chan); 348 void fsl_edma_free_chan_resources(struct dma_chan *chan); 349 void fsl_edma_cleanup_vchan(struct dma_device *dmadev); 350 void fsl_edma_setup_regs(struct fsl_edma_engine *edma); 351 352 #endif /* _FSL_EDMA_COMMON_H_ */ 353