1 /* 2 * Driver for the Synopsys DesignWare AHB DMA Controller 3 * 4 * Copyright (C) 2005-2007 Atmel Corporation 5 * Copyright (C) 2010-2011 ST Microelectronics 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/interrupt.h> 13 #include <linux/dmaengine.h> 14 #include <linux/dw_dmac.h> 15 16 #define DW_DMA_MAX_NR_CHANNELS 8 17 #define DW_DMA_MAX_NR_REQUESTS 16 18 19 /* flow controller */ 20 enum dw_dma_fc { 21 DW_DMA_FC_D_M2M, 22 DW_DMA_FC_D_M2P, 23 DW_DMA_FC_D_P2M, 24 DW_DMA_FC_D_P2P, 25 DW_DMA_FC_P_P2M, 26 DW_DMA_FC_SP_P2P, 27 DW_DMA_FC_P_M2P, 28 DW_DMA_FC_DP_P2P, 29 }; 30 31 /* 32 * Redefine this macro to handle differences between 32- and 64-bit 33 * addressing, big vs. little endian, etc. 34 */ 35 #define DW_REG(name) u32 name; u32 __pad_##name 36 37 /* Hardware register definitions. */ 38 struct dw_dma_chan_regs { 39 DW_REG(SAR); /* Source Address Register */ 40 DW_REG(DAR); /* Destination Address Register */ 41 DW_REG(LLP); /* Linked List Pointer */ 42 u32 CTL_LO; /* Control Register Low */ 43 u32 CTL_HI; /* Control Register High */ 44 DW_REG(SSTAT); 45 DW_REG(DSTAT); 46 DW_REG(SSTATAR); 47 DW_REG(DSTATAR); 48 u32 CFG_LO; /* Configuration Register Low */ 49 u32 CFG_HI; /* Configuration Register High */ 50 DW_REG(SGR); 51 DW_REG(DSR); 52 }; 53 54 struct dw_dma_irq_regs { 55 DW_REG(XFER); 56 DW_REG(BLOCK); 57 DW_REG(SRC_TRAN); 58 DW_REG(DST_TRAN); 59 DW_REG(ERROR); 60 }; 61 62 struct dw_dma_regs { 63 /* per-channel registers */ 64 struct dw_dma_chan_regs CHAN[DW_DMA_MAX_NR_CHANNELS]; 65 66 /* irq handling */ 67 struct dw_dma_irq_regs RAW; /* r */ 68 struct dw_dma_irq_regs STATUS; /* r (raw & mask) */ 69 struct dw_dma_irq_regs MASK; /* rw (set = irq enabled) */ 70 struct dw_dma_irq_regs CLEAR; /* w (ack, affects "raw") */ 71 72 DW_REG(STATUS_INT); /* r */ 73 74 /* software handshaking */ 75 DW_REG(REQ_SRC); 76 DW_REG(REQ_DST); 77 DW_REG(SGL_REQ_SRC); 78 DW_REG(SGL_REQ_DST); 79 DW_REG(LAST_SRC); 80 DW_REG(LAST_DST); 81 82 /* miscellaneous */ 83 DW_REG(CFG); 84 DW_REG(CH_EN); 85 DW_REG(ID); 86 DW_REG(TEST); 87 88 /* reserved */ 89 DW_REG(__reserved0); 90 DW_REG(__reserved1); 91 92 /* optional encoded params, 0x3c8..0x3f7 */ 93 u32 __reserved; 94 95 /* per-channel configuration registers */ 96 u32 DWC_PARAMS[DW_DMA_MAX_NR_CHANNELS]; 97 u32 MULTI_BLK_TYPE; 98 u32 MAX_BLK_SIZE; 99 100 /* top-level parameters */ 101 u32 DW_PARAMS; 102 }; 103 104 /* 105 * Big endian I/O access when reading and writing to the DMA controller 106 * registers. This is needed on some platforms, like the Atmel AVR32 107 * architecture. 108 */ 109 110 #ifdef CONFIG_DW_DMAC_BIG_ENDIAN_IO 111 #define dma_readl_native ioread32be 112 #define dma_writel_native iowrite32be 113 #else 114 #define dma_readl_native readl 115 #define dma_writel_native writel 116 #endif 117 118 /* To access the registers in early stage of probe */ 119 #define dma_read_byaddr(addr, name) \ 120 dma_readl_native((addr) + offsetof(struct dw_dma_regs, name)) 121 122 /* Bitfields in DW_PARAMS */ 123 #define DW_PARAMS_NR_CHAN 8 /* number of channels */ 124 #define DW_PARAMS_NR_MASTER 11 /* number of AHB masters */ 125 #define DW_PARAMS_DATA_WIDTH(n) (15 + 2 * (n)) 126 #define DW_PARAMS_DATA_WIDTH1 15 /* master 1 data width */ 127 #define DW_PARAMS_DATA_WIDTH2 17 /* master 2 data width */ 128 #define DW_PARAMS_DATA_WIDTH3 19 /* master 3 data width */ 129 #define DW_PARAMS_DATA_WIDTH4 21 /* master 4 data width */ 130 #define DW_PARAMS_EN 28 /* encoded parameters */ 131 132 /* Bitfields in DWC_PARAMS */ 133 #define DWC_PARAMS_MBLK_EN 11 /* multi block transfer */ 134 135 /* Bitfields in CTL_LO */ 136 #define DWC_CTLL_INT_EN (1 << 0) /* irqs enabled? */ 137 #define DWC_CTLL_DST_WIDTH(n) ((n)<<1) /* bytes per element */ 138 #define DWC_CTLL_SRC_WIDTH(n) ((n)<<4) 139 #define DWC_CTLL_DST_INC (0<<7) /* DAR update/not */ 140 #define DWC_CTLL_DST_DEC (1<<7) 141 #define DWC_CTLL_DST_FIX (2<<7) 142 #define DWC_CTLL_SRC_INC (0<<7) /* SAR update/not */ 143 #define DWC_CTLL_SRC_DEC (1<<9) 144 #define DWC_CTLL_SRC_FIX (2<<9) 145 #define DWC_CTLL_DST_MSIZE(n) ((n)<<11) /* burst, #elements */ 146 #define DWC_CTLL_SRC_MSIZE(n) ((n)<<14) 147 #define DWC_CTLL_S_GATH_EN (1 << 17) /* src gather, !FIX */ 148 #define DWC_CTLL_D_SCAT_EN (1 << 18) /* dst scatter, !FIX */ 149 #define DWC_CTLL_FC(n) ((n) << 20) 150 #define DWC_CTLL_FC_M2M (0 << 20) /* mem-to-mem */ 151 #define DWC_CTLL_FC_M2P (1 << 20) /* mem-to-periph */ 152 #define DWC_CTLL_FC_P2M (2 << 20) /* periph-to-mem */ 153 #define DWC_CTLL_FC_P2P (3 << 20) /* periph-to-periph */ 154 /* plus 4 transfer types for peripheral-as-flow-controller */ 155 #define DWC_CTLL_DMS(n) ((n)<<23) /* dst master select */ 156 #define DWC_CTLL_SMS(n) ((n)<<25) /* src master select */ 157 #define DWC_CTLL_LLP_D_EN (1 << 27) /* dest block chain */ 158 #define DWC_CTLL_LLP_S_EN (1 << 28) /* src block chain */ 159 160 /* Bitfields in CTL_HI */ 161 #define DWC_CTLH_DONE 0x00001000 162 #define DWC_CTLH_BLOCK_TS_MASK 0x00000fff 163 164 /* Bitfields in CFG_LO. Platform-configurable bits are in <linux/dw_dmac.h> */ 165 #define DWC_CFGL_CH_PRIOR_MASK (0x7 << 5) /* priority mask */ 166 #define DWC_CFGL_CH_PRIOR(x) ((x) << 5) /* priority */ 167 #define DWC_CFGL_CH_SUSP (1 << 8) /* pause xfer */ 168 #define DWC_CFGL_FIFO_EMPTY (1 << 9) /* pause xfer */ 169 #define DWC_CFGL_HS_DST (1 << 10) /* handshake w/dst */ 170 #define DWC_CFGL_HS_SRC (1 << 11) /* handshake w/src */ 171 #define DWC_CFGL_MAX_BURST(x) ((x) << 20) 172 #define DWC_CFGL_RELOAD_SAR (1 << 30) 173 #define DWC_CFGL_RELOAD_DAR (1 << 31) 174 175 /* Bitfields in CFG_HI. Platform-configurable bits are in <linux/dw_dmac.h> */ 176 #define DWC_CFGH_DS_UPD_EN (1 << 5) 177 #define DWC_CFGH_SS_UPD_EN (1 << 6) 178 179 /* Bitfields in SGR */ 180 #define DWC_SGR_SGI(x) ((x) << 0) 181 #define DWC_SGR_SGC(x) ((x) << 20) 182 183 /* Bitfields in DSR */ 184 #define DWC_DSR_DSI(x) ((x) << 0) 185 #define DWC_DSR_DSC(x) ((x) << 20) 186 187 /* Bitfields in CFG */ 188 #define DW_CFG_DMA_EN (1 << 0) 189 190 enum dw_dmac_flags { 191 DW_DMA_IS_CYCLIC = 0, 192 DW_DMA_IS_SOFT_LLP = 1, 193 }; 194 195 struct dw_dma_chan { 196 struct dma_chan chan; 197 void __iomem *ch_regs; 198 u8 mask; 199 u8 priority; 200 enum dma_transfer_direction direction; 201 bool paused; 202 bool initialized; 203 204 /* software emulation of the LLP transfers */ 205 struct list_head *tx_node_active; 206 207 spinlock_t lock; 208 209 /* these other elements are all protected by lock */ 210 unsigned long flags; 211 struct list_head active_list; 212 struct list_head queue; 213 struct list_head free_list; 214 u32 residue; 215 struct dw_cyclic_desc *cdesc; 216 217 unsigned int descs_allocated; 218 219 /* hardware configuration */ 220 unsigned int block_size; 221 bool nollp; 222 223 /* custom slave configuration */ 224 unsigned int request_line; 225 unsigned char src_master; 226 unsigned char dst_master; 227 228 /* configuration passed via DMA_SLAVE_CONFIG */ 229 struct dma_slave_config dma_sconfig; 230 }; 231 232 static inline struct dw_dma_chan_regs __iomem * 233 __dwc_regs(struct dw_dma_chan *dwc) 234 { 235 return dwc->ch_regs; 236 } 237 238 #define channel_readl(dwc, name) \ 239 dma_readl_native(&(__dwc_regs(dwc)->name)) 240 #define channel_writel(dwc, name, val) \ 241 dma_writel_native((val), &(__dwc_regs(dwc)->name)) 242 243 static inline struct dw_dma_chan *to_dw_dma_chan(struct dma_chan *chan) 244 { 245 return container_of(chan, struct dw_dma_chan, chan); 246 } 247 248 struct dw_dma { 249 struct dma_device dma; 250 void __iomem *regs; 251 struct dma_pool *desc_pool; 252 struct tasklet_struct tasklet; 253 struct clk *clk; 254 255 /* channels */ 256 struct dw_dma_chan *chan; 257 u8 all_chan_mask; 258 259 /* hardware configuration */ 260 unsigned char nr_masters; 261 unsigned char data_width[4]; 262 }; 263 264 static inline struct dw_dma_regs __iomem *__dw_regs(struct dw_dma *dw) 265 { 266 return dw->regs; 267 } 268 269 #define dma_readl(dw, name) \ 270 dma_readl_native(&(__dw_regs(dw)->name)) 271 #define dma_writel(dw, name, val) \ 272 dma_writel_native((val), &(__dw_regs(dw)->name)) 273 274 #define channel_set_bit(dw, reg, mask) \ 275 dma_writel(dw, reg, ((mask) << 8) | (mask)) 276 #define channel_clear_bit(dw, reg, mask) \ 277 dma_writel(dw, reg, ((mask) << 8) | 0) 278 279 static inline struct dw_dma *to_dw_dma(struct dma_device *ddev) 280 { 281 return container_of(ddev, struct dw_dma, dma); 282 } 283 284 /* LLI == Linked List Item; a.k.a. DMA block descriptor */ 285 struct dw_lli { 286 /* values that are not changed by hardware */ 287 u32 sar; 288 u32 dar; 289 u32 llp; /* chain to next lli */ 290 u32 ctllo; 291 /* values that may get written back: */ 292 u32 ctlhi; 293 /* sstat and dstat can snapshot peripheral register state. 294 * silicon config may discard either or both... 295 */ 296 u32 sstat; 297 u32 dstat; 298 }; 299 300 struct dw_desc { 301 /* FIRST values the hardware uses */ 302 struct dw_lli lli; 303 304 /* THEN values for driver housekeeping */ 305 struct list_head desc_node; 306 struct list_head tx_list; 307 struct dma_async_tx_descriptor txd; 308 size_t len; 309 size_t total_len; 310 }; 311 312 #define to_dw_desc(h) list_entry(h, struct dw_desc, desc_node) 313 314 static inline struct dw_desc * 315 txd_to_dw_desc(struct dma_async_tx_descriptor *txd) 316 { 317 return container_of(txd, struct dw_desc, txd); 318 } 319