1 /* 2 * Driver for the Synopsys DesignWare AHB DMA Controller 3 * 4 * Copyright (C) 2005-2007 Atmel Corporation 5 * Copyright (C) 2010-2011 ST Microelectronics 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12 #include <linux/bitops.h> 13 #include <linux/interrupt.h> 14 #include <linux/dmaengine.h> 15 16 #include "internal.h" 17 18 #define DW_DMA_MAX_NR_REQUESTS 16 19 20 /* flow controller */ 21 enum dw_dma_fc { 22 DW_DMA_FC_D_M2M, 23 DW_DMA_FC_D_M2P, 24 DW_DMA_FC_D_P2M, 25 DW_DMA_FC_D_P2P, 26 DW_DMA_FC_P_P2M, 27 DW_DMA_FC_SP_P2P, 28 DW_DMA_FC_P_M2P, 29 DW_DMA_FC_DP_P2P, 30 }; 31 32 /* 33 * Redefine this macro to handle differences between 32- and 64-bit 34 * addressing, big vs. little endian, etc. 35 */ 36 #define DW_REG(name) u32 name; u32 __pad_##name 37 38 /* Hardware register definitions. */ 39 struct dw_dma_chan_regs { 40 DW_REG(SAR); /* Source Address Register */ 41 DW_REG(DAR); /* Destination Address Register */ 42 DW_REG(LLP); /* Linked List Pointer */ 43 u32 CTL_LO; /* Control Register Low */ 44 u32 CTL_HI; /* Control Register High */ 45 DW_REG(SSTAT); 46 DW_REG(DSTAT); 47 DW_REG(SSTATAR); 48 DW_REG(DSTATAR); 49 u32 CFG_LO; /* Configuration Register Low */ 50 u32 CFG_HI; /* Configuration Register High */ 51 DW_REG(SGR); 52 DW_REG(DSR); 53 }; 54 55 struct dw_dma_irq_regs { 56 DW_REG(XFER); 57 DW_REG(BLOCK); 58 DW_REG(SRC_TRAN); 59 DW_REG(DST_TRAN); 60 DW_REG(ERROR); 61 }; 62 63 struct dw_dma_regs { 64 /* per-channel registers */ 65 struct dw_dma_chan_regs CHAN[DW_DMA_MAX_NR_CHANNELS]; 66 67 /* irq handling */ 68 struct dw_dma_irq_regs RAW; /* r */ 69 struct dw_dma_irq_regs STATUS; /* r (raw & mask) */ 70 struct dw_dma_irq_regs MASK; /* rw (set = irq enabled) */ 71 struct dw_dma_irq_regs CLEAR; /* w (ack, affects "raw") */ 72 73 DW_REG(STATUS_INT); /* r */ 74 75 /* software handshaking */ 76 DW_REG(REQ_SRC); 77 DW_REG(REQ_DST); 78 DW_REG(SGL_REQ_SRC); 79 DW_REG(SGL_REQ_DST); 80 DW_REG(LAST_SRC); 81 DW_REG(LAST_DST); 82 83 /* miscellaneous */ 84 DW_REG(CFG); 85 DW_REG(CH_EN); 86 DW_REG(ID); 87 DW_REG(TEST); 88 89 /* reserved */ 90 DW_REG(__reserved0); 91 DW_REG(__reserved1); 92 93 /* optional encoded params, 0x3c8..0x3f7 */ 94 u32 __reserved; 95 96 /* per-channel configuration registers */ 97 u32 DWC_PARAMS[DW_DMA_MAX_NR_CHANNELS]; 98 u32 MULTI_BLK_TYPE; 99 u32 MAX_BLK_SIZE; 100 101 /* top-level parameters */ 102 u32 DW_PARAMS; 103 }; 104 105 /* 106 * Big endian I/O access when reading and writing to the DMA controller 107 * registers. This is needed on some platforms, like the Atmel AVR32 108 * architecture. 109 */ 110 111 #ifdef CONFIG_DW_DMAC_BIG_ENDIAN_IO 112 #define dma_readl_native ioread32be 113 #define dma_writel_native iowrite32be 114 #else 115 #define dma_readl_native readl 116 #define dma_writel_native writel 117 #endif 118 119 /* Bitfields in DW_PARAMS */ 120 #define DW_PARAMS_NR_CHAN 8 /* number of channels */ 121 #define DW_PARAMS_NR_MASTER 11 /* number of AHB masters */ 122 #define DW_PARAMS_DATA_WIDTH(n) (15 + 2 * (n)) 123 #define DW_PARAMS_DATA_WIDTH1 15 /* master 1 data width */ 124 #define DW_PARAMS_DATA_WIDTH2 17 /* master 2 data width */ 125 #define DW_PARAMS_DATA_WIDTH3 19 /* master 3 data width */ 126 #define DW_PARAMS_DATA_WIDTH4 21 /* master 4 data width */ 127 #define DW_PARAMS_EN 28 /* encoded parameters */ 128 129 /* Bitfields in DWC_PARAMS */ 130 #define DWC_PARAMS_MBLK_EN 11 /* multi block transfer */ 131 132 /* bursts size */ 133 enum dw_dma_msize { 134 DW_DMA_MSIZE_1, 135 DW_DMA_MSIZE_4, 136 DW_DMA_MSIZE_8, 137 DW_DMA_MSIZE_16, 138 DW_DMA_MSIZE_32, 139 DW_DMA_MSIZE_64, 140 DW_DMA_MSIZE_128, 141 DW_DMA_MSIZE_256, 142 }; 143 144 /* Bitfields in LLP */ 145 #define DWC_LLP_LMS(x) ((x) & 3) /* list master select */ 146 #define DWC_LLP_LOC(x) ((x) & ~3) /* next lli */ 147 148 /* Bitfields in CTL_LO */ 149 #define DWC_CTLL_INT_EN (1 << 0) /* irqs enabled? */ 150 #define DWC_CTLL_DST_WIDTH(n) ((n)<<1) /* bytes per element */ 151 #define DWC_CTLL_SRC_WIDTH(n) ((n)<<4) 152 #define DWC_CTLL_DST_INC (0<<7) /* DAR update/not */ 153 #define DWC_CTLL_DST_DEC (1<<7) 154 #define DWC_CTLL_DST_FIX (2<<7) 155 #define DWC_CTLL_SRC_INC (0<<9) /* SAR update/not */ 156 #define DWC_CTLL_SRC_DEC (1<<9) 157 #define DWC_CTLL_SRC_FIX (2<<9) 158 #define DWC_CTLL_DST_MSIZE(n) ((n)<<11) /* burst, #elements */ 159 #define DWC_CTLL_SRC_MSIZE(n) ((n)<<14) 160 #define DWC_CTLL_S_GATH_EN (1 << 17) /* src gather, !FIX */ 161 #define DWC_CTLL_D_SCAT_EN (1 << 18) /* dst scatter, !FIX */ 162 #define DWC_CTLL_FC(n) ((n) << 20) 163 #define DWC_CTLL_FC_M2M (0 << 20) /* mem-to-mem */ 164 #define DWC_CTLL_FC_M2P (1 << 20) /* mem-to-periph */ 165 #define DWC_CTLL_FC_P2M (2 << 20) /* periph-to-mem */ 166 #define DWC_CTLL_FC_P2P (3 << 20) /* periph-to-periph */ 167 /* plus 4 transfer types for peripheral-as-flow-controller */ 168 #define DWC_CTLL_DMS(n) ((n)<<23) /* dst master select */ 169 #define DWC_CTLL_SMS(n) ((n)<<25) /* src master select */ 170 #define DWC_CTLL_LLP_D_EN (1 << 27) /* dest block chain */ 171 #define DWC_CTLL_LLP_S_EN (1 << 28) /* src block chain */ 172 173 /* Bitfields in CTL_HI */ 174 #define DWC_CTLH_BLOCK_TS_MASK GENMASK(11, 0) 175 #define DWC_CTLH_BLOCK_TS(x) ((x) & DWC_CTLH_BLOCK_TS_MASK) 176 #define DWC_CTLH_DONE (1 << 12) 177 178 /* Bitfields in CFG_LO */ 179 #define DWC_CFGL_CH_PRIOR_MASK (0x7 << 5) /* priority mask */ 180 #define DWC_CFGL_CH_PRIOR(x) ((x) << 5) /* priority */ 181 #define DWC_CFGL_CH_SUSP (1 << 8) /* pause xfer */ 182 #define DWC_CFGL_FIFO_EMPTY (1 << 9) /* pause xfer */ 183 #define DWC_CFGL_HS_DST (1 << 10) /* handshake w/dst */ 184 #define DWC_CFGL_HS_SRC (1 << 11) /* handshake w/src */ 185 #define DWC_CFGL_LOCK_CH_XFER (0 << 12) /* scope of LOCK_CH */ 186 #define DWC_CFGL_LOCK_CH_BLOCK (1 << 12) 187 #define DWC_CFGL_LOCK_CH_XACT (2 << 12) 188 #define DWC_CFGL_LOCK_BUS_XFER (0 << 14) /* scope of LOCK_BUS */ 189 #define DWC_CFGL_LOCK_BUS_BLOCK (1 << 14) 190 #define DWC_CFGL_LOCK_BUS_XACT (2 << 14) 191 #define DWC_CFGL_LOCK_CH (1 << 15) /* channel lockout */ 192 #define DWC_CFGL_LOCK_BUS (1 << 16) /* busmaster lockout */ 193 #define DWC_CFGL_HS_DST_POL (1 << 18) /* dst handshake active low */ 194 #define DWC_CFGL_HS_SRC_POL (1 << 19) /* src handshake active low */ 195 #define DWC_CFGL_MAX_BURST(x) ((x) << 20) 196 #define DWC_CFGL_RELOAD_SAR (1 << 30) 197 #define DWC_CFGL_RELOAD_DAR (1 << 31) 198 199 /* Bitfields in CFG_HI */ 200 #define DWC_CFGH_FCMODE (1 << 0) 201 #define DWC_CFGH_FIFO_MODE (1 << 1) 202 #define DWC_CFGH_PROTCTL(x) ((x) << 2) 203 #define DWC_CFGH_DS_UPD_EN (1 << 5) 204 #define DWC_CFGH_SS_UPD_EN (1 << 6) 205 #define DWC_CFGH_SRC_PER(x) ((x) << 7) 206 #define DWC_CFGH_DST_PER(x) ((x) << 11) 207 208 /* Bitfields in SGR */ 209 #define DWC_SGR_SGI(x) ((x) << 0) 210 #define DWC_SGR_SGC(x) ((x) << 20) 211 212 /* Bitfields in DSR */ 213 #define DWC_DSR_DSI(x) ((x) << 0) 214 #define DWC_DSR_DSC(x) ((x) << 20) 215 216 /* Bitfields in CFG */ 217 #define DW_CFG_DMA_EN (1 << 0) 218 219 enum dw_dmac_flags { 220 DW_DMA_IS_CYCLIC = 0, 221 DW_DMA_IS_SOFT_LLP = 1, 222 DW_DMA_IS_PAUSED = 2, 223 DW_DMA_IS_INITIALIZED = 3, 224 }; 225 226 struct dw_dma_chan { 227 struct dma_chan chan; 228 void __iomem *ch_regs; 229 u8 mask; 230 u8 priority; 231 enum dma_transfer_direction direction; 232 233 /* software emulation of the LLP transfers */ 234 struct list_head *tx_node_active; 235 236 spinlock_t lock; 237 238 /* these other elements are all protected by lock */ 239 unsigned long flags; 240 struct list_head active_list; 241 struct list_head queue; 242 struct dw_cyclic_desc *cdesc; 243 244 unsigned int descs_allocated; 245 246 /* hardware configuration */ 247 unsigned int block_size; 248 bool nollp; 249 250 /* custom slave configuration */ 251 struct dw_dma_slave dws; 252 253 /* configuration passed via .device_config */ 254 struct dma_slave_config dma_sconfig; 255 }; 256 257 static inline struct dw_dma_chan_regs __iomem * 258 __dwc_regs(struct dw_dma_chan *dwc) 259 { 260 return dwc->ch_regs; 261 } 262 263 #define channel_readl(dwc, name) \ 264 dma_readl_native(&(__dwc_regs(dwc)->name)) 265 #define channel_writel(dwc, name, val) \ 266 dma_writel_native((val), &(__dwc_regs(dwc)->name)) 267 268 static inline struct dw_dma_chan *to_dw_dma_chan(struct dma_chan *chan) 269 { 270 return container_of(chan, struct dw_dma_chan, chan); 271 } 272 273 struct dw_dma { 274 struct dma_device dma; 275 char name[20]; 276 void __iomem *regs; 277 struct dma_pool *desc_pool; 278 struct tasklet_struct tasklet; 279 280 /* channels */ 281 struct dw_dma_chan *chan; 282 u8 all_chan_mask; 283 u8 in_use; 284 285 /* platform data */ 286 struct dw_dma_platform_data *pdata; 287 }; 288 289 static inline struct dw_dma_regs __iomem *__dw_regs(struct dw_dma *dw) 290 { 291 return dw->regs; 292 } 293 294 #define dma_readl(dw, name) \ 295 dma_readl_native(&(__dw_regs(dw)->name)) 296 #define dma_writel(dw, name, val) \ 297 dma_writel_native((val), &(__dw_regs(dw)->name)) 298 299 #define channel_set_bit(dw, reg, mask) \ 300 dma_writel(dw, reg, ((mask) << 8) | (mask)) 301 #define channel_clear_bit(dw, reg, mask) \ 302 dma_writel(dw, reg, ((mask) << 8) | 0) 303 304 static inline struct dw_dma *to_dw_dma(struct dma_device *ddev) 305 { 306 return container_of(ddev, struct dw_dma, dma); 307 } 308 309 #ifdef CONFIG_DW_DMAC_BIG_ENDIAN_IO 310 typedef __be32 __dw32; 311 #else 312 typedef __le32 __dw32; 313 #endif 314 315 /* LLI == Linked List Item; a.k.a. DMA block descriptor */ 316 struct dw_lli { 317 /* values that are not changed by hardware */ 318 __dw32 sar; 319 __dw32 dar; 320 __dw32 llp; /* chain to next lli */ 321 __dw32 ctllo; 322 /* values that may get written back: */ 323 __dw32 ctlhi; 324 /* sstat and dstat can snapshot peripheral register state. 325 * silicon config may discard either or both... 326 */ 327 __dw32 sstat; 328 __dw32 dstat; 329 }; 330 331 struct dw_desc { 332 /* FIRST values the hardware uses */ 333 struct dw_lli lli; 334 335 #ifdef CONFIG_DW_DMAC_BIG_ENDIAN_IO 336 #define lli_set(d, reg, v) ((d)->lli.reg |= cpu_to_be32(v)) 337 #define lli_clear(d, reg, v) ((d)->lli.reg &= ~cpu_to_be32(v)) 338 #define lli_read(d, reg) be32_to_cpu((d)->lli.reg) 339 #define lli_write(d, reg, v) ((d)->lli.reg = cpu_to_be32(v)) 340 #else 341 #define lli_set(d, reg, v) ((d)->lli.reg |= cpu_to_le32(v)) 342 #define lli_clear(d, reg, v) ((d)->lli.reg &= ~cpu_to_le32(v)) 343 #define lli_read(d, reg) le32_to_cpu((d)->lli.reg) 344 #define lli_write(d, reg, v) ((d)->lli.reg = cpu_to_le32(v)) 345 #endif 346 347 /* THEN values for driver housekeeping */ 348 struct list_head desc_node; 349 struct list_head tx_list; 350 struct dma_async_tx_descriptor txd; 351 size_t len; 352 size_t total_len; 353 u32 residue; 354 }; 355 356 #define to_dw_desc(h) list_entry(h, struct dw_desc, desc_node) 357 358 static inline struct dw_desc * 359 txd_to_dw_desc(struct dma_async_tx_descriptor *txd) 360 { 361 return container_of(txd, struct dw_desc, txd); 362 } 363