1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Platform driver for the Synopsys DesignWare DMA Controller 4 * 5 * Copyright (C) 2007-2008 Atmel Corporation 6 * Copyright (C) 2010-2011 ST Microelectronics 7 * Copyright (C) 2013 Intel Corporation 8 */ 9 10 #include <linux/of.h> 11 #include <linux/of_dma.h> 12 #include <linux/platform_device.h> 13 14 #include "internal.h" 15 16 static struct dma_chan *dw_dma_of_xlate(struct of_phandle_args *dma_spec, 17 struct of_dma *ofdma) 18 { 19 struct dw_dma *dw = ofdma->of_dma_data; 20 struct dw_dma_slave slave = { 21 .dma_dev = dw->dma.dev, 22 }; 23 dma_cap_mask_t cap; 24 25 if (dma_spec->args_count < 3 || dma_spec->args_count > 4) 26 return NULL; 27 28 slave.src_id = dma_spec->args[0]; 29 slave.dst_id = dma_spec->args[0]; 30 slave.m_master = dma_spec->args[1]; 31 slave.p_master = dma_spec->args[2]; 32 if (dma_spec->args_count >= 4) 33 slave.channels = dma_spec->args[3]; 34 35 if (WARN_ON(slave.src_id >= DW_DMA_MAX_NR_REQUESTS || 36 slave.dst_id >= DW_DMA_MAX_NR_REQUESTS || 37 slave.m_master >= dw->pdata->nr_masters || 38 slave.p_master >= dw->pdata->nr_masters || 39 slave.channels >= BIT(dw->pdata->nr_channels))) 40 return NULL; 41 42 dma_cap_zero(cap); 43 dma_cap_set(DMA_SLAVE, cap); 44 45 /* TODO: there should be a simpler way to do this */ 46 return dma_request_channel(cap, dw_dma_filter, &slave); 47 } 48 49 struct dw_dma_platform_data *dw_dma_parse_dt(struct platform_device *pdev) 50 { 51 struct device_node *np = pdev->dev.of_node; 52 struct dw_dma_platform_data *pdata; 53 u32 tmp, arr[DW_DMA_MAX_NR_MASTERS], mb[DW_DMA_MAX_NR_CHANNELS]; 54 u32 nr_masters; 55 u32 nr_channels; 56 57 if (!np) { 58 dev_err(&pdev->dev, "Missing DT data\n"); 59 return NULL; 60 } 61 62 if (of_property_read_u32(np, "dma-masters", &nr_masters)) 63 return NULL; 64 if (nr_masters < 1 || nr_masters > DW_DMA_MAX_NR_MASTERS) 65 return NULL; 66 67 if (of_property_read_u32(np, "dma-channels", &nr_channels)) 68 return NULL; 69 if (nr_channels > DW_DMA_MAX_NR_CHANNELS) 70 return NULL; 71 72 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 73 if (!pdata) 74 return NULL; 75 76 pdata->nr_masters = nr_masters; 77 pdata->nr_channels = nr_channels; 78 79 if (!of_property_read_u32(np, "chan_allocation_order", &tmp)) 80 pdata->chan_allocation_order = (unsigned char)tmp; 81 82 if (!of_property_read_u32(np, "chan_priority", &tmp)) 83 pdata->chan_priority = tmp; 84 85 if (!of_property_read_u32(np, "block_size", &tmp)) 86 pdata->block_size = tmp; 87 88 if (!of_property_read_u32_array(np, "data-width", arr, nr_masters)) { 89 for (tmp = 0; tmp < nr_masters; tmp++) 90 pdata->data_width[tmp] = arr[tmp]; 91 } else if (!of_property_read_u32_array(np, "data_width", arr, nr_masters)) { 92 for (tmp = 0; tmp < nr_masters; tmp++) 93 pdata->data_width[tmp] = BIT(arr[tmp] & 0x07); 94 } 95 96 if (!of_property_read_u32_array(np, "multi-block", mb, nr_channels)) { 97 for (tmp = 0; tmp < nr_channels; tmp++) 98 pdata->multi_block[tmp] = mb[tmp]; 99 } else { 100 for (tmp = 0; tmp < nr_channels; tmp++) 101 pdata->multi_block[tmp] = 1; 102 } 103 104 if (of_property_read_u32_array(np, "snps,max-burst-len", pdata->max_burst, 105 nr_channels)) { 106 memset32(pdata->max_burst, DW_DMA_MAX_BURST, nr_channels); 107 } 108 109 if (!of_property_read_u32(np, "snps,dma-protection-control", &tmp)) { 110 if (tmp > CHAN_PROTCTL_MASK) 111 return NULL; 112 pdata->protctl = tmp; 113 } 114 115 return pdata; 116 } 117 118 void dw_dma_of_controller_register(struct dw_dma *dw) 119 { 120 struct device *dev = dw->dma.dev; 121 int ret; 122 123 if (!dev->of_node) 124 return; 125 126 ret = of_dma_controller_register(dev->of_node, dw_dma_of_xlate, dw); 127 if (ret) 128 dev_err(dev, "could not register of_dma_controller\n"); 129 } 130 131 void dw_dma_of_controller_free(struct dw_dma *dw) 132 { 133 struct device *dev = dw->dma.dev; 134 135 if (!dev->of_node) 136 return; 137 138 of_dma_controller_free(dev->of_node); 139 } 140