1 /* 2 * Core driver for the Synopsys DesignWare DMA Controller 3 * 4 * Copyright (C) 2007-2008 Atmel Corporation 5 * Copyright (C) 2010-2011 ST Microelectronics 6 * Copyright (C) 2013 Intel Corporation 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 */ 12 13 #include <linux/bitops.h> 14 #include <linux/delay.h> 15 #include <linux/dmaengine.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/dmapool.h> 18 #include <linux/err.h> 19 #include <linux/init.h> 20 #include <linux/interrupt.h> 21 #include <linux/io.h> 22 #include <linux/mm.h> 23 #include <linux/module.h> 24 #include <linux/slab.h> 25 #include <linux/pm_runtime.h> 26 27 #include "../dmaengine.h" 28 #include "internal.h" 29 30 /* 31 * This supports the Synopsys "DesignWare AHB Central DMA Controller", 32 * (DW_ahb_dmac) which is used with various AMBA 2.0 systems (not all 33 * of which use ARM any more). See the "Databook" from Synopsys for 34 * information beyond what licensees probably provide. 35 * 36 * The driver has been tested with the Atmel AT32AP7000, which does not 37 * support descriptor writeback. 38 */ 39 40 #define DWC_DEFAULT_CTLLO(_chan) ({ \ 41 struct dw_dma_chan *_dwc = to_dw_dma_chan(_chan); \ 42 struct dma_slave_config *_sconfig = &_dwc->dma_sconfig; \ 43 bool _is_slave = is_slave_direction(_dwc->direction); \ 44 u8 _smsize = _is_slave ? _sconfig->src_maxburst : \ 45 DW_DMA_MSIZE_16; \ 46 u8 _dmsize = _is_slave ? _sconfig->dst_maxburst : \ 47 DW_DMA_MSIZE_16; \ 48 u8 _dms = (_dwc->direction == DMA_MEM_TO_DEV) ? \ 49 _dwc->dws.p_master : _dwc->dws.m_master; \ 50 u8 _sms = (_dwc->direction == DMA_DEV_TO_MEM) ? \ 51 _dwc->dws.p_master : _dwc->dws.m_master; \ 52 \ 53 (DWC_CTLL_DST_MSIZE(_dmsize) \ 54 | DWC_CTLL_SRC_MSIZE(_smsize) \ 55 | DWC_CTLL_LLP_D_EN \ 56 | DWC_CTLL_LLP_S_EN \ 57 | DWC_CTLL_DMS(_dms) \ 58 | DWC_CTLL_SMS(_sms)); \ 59 }) 60 61 /* The set of bus widths supported by the DMA controller */ 62 #define DW_DMA_BUSWIDTHS \ 63 BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \ 64 BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ 65 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ 66 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) 67 68 /*----------------------------------------------------------------------*/ 69 70 static struct device *chan2dev(struct dma_chan *chan) 71 { 72 return &chan->dev->device; 73 } 74 75 static struct dw_desc *dwc_first_active(struct dw_dma_chan *dwc) 76 { 77 return to_dw_desc(dwc->active_list.next); 78 } 79 80 static dma_cookie_t dwc_tx_submit(struct dma_async_tx_descriptor *tx) 81 { 82 struct dw_desc *desc = txd_to_dw_desc(tx); 83 struct dw_dma_chan *dwc = to_dw_dma_chan(tx->chan); 84 dma_cookie_t cookie; 85 unsigned long flags; 86 87 spin_lock_irqsave(&dwc->lock, flags); 88 cookie = dma_cookie_assign(tx); 89 90 /* 91 * REVISIT: We should attempt to chain as many descriptors as 92 * possible, perhaps even appending to those already submitted 93 * for DMA. But this is hard to do in a race-free manner. 94 */ 95 96 list_add_tail(&desc->desc_node, &dwc->queue); 97 spin_unlock_irqrestore(&dwc->lock, flags); 98 dev_vdbg(chan2dev(tx->chan), "%s: queued %u\n", 99 __func__, desc->txd.cookie); 100 101 return cookie; 102 } 103 104 static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc) 105 { 106 struct dw_dma *dw = to_dw_dma(dwc->chan.device); 107 struct dw_desc *desc; 108 dma_addr_t phys; 109 110 desc = dma_pool_zalloc(dw->desc_pool, GFP_ATOMIC, &phys); 111 if (!desc) 112 return NULL; 113 114 dwc->descs_allocated++; 115 INIT_LIST_HEAD(&desc->tx_list); 116 dma_async_tx_descriptor_init(&desc->txd, &dwc->chan); 117 desc->txd.tx_submit = dwc_tx_submit; 118 desc->txd.flags = DMA_CTRL_ACK; 119 desc->txd.phys = phys; 120 return desc; 121 } 122 123 static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc) 124 { 125 struct dw_dma *dw = to_dw_dma(dwc->chan.device); 126 struct dw_desc *child, *_next; 127 128 if (unlikely(!desc)) 129 return; 130 131 list_for_each_entry_safe(child, _next, &desc->tx_list, desc_node) { 132 list_del(&child->desc_node); 133 dma_pool_free(dw->desc_pool, child, child->txd.phys); 134 dwc->descs_allocated--; 135 } 136 137 dma_pool_free(dw->desc_pool, desc, desc->txd.phys); 138 dwc->descs_allocated--; 139 } 140 141 static void dwc_initialize_chan_idma32(struct dw_dma_chan *dwc) 142 { 143 u32 cfghi = 0; 144 u32 cfglo = 0; 145 146 /* Set default burst alignment */ 147 cfglo |= IDMA32C_CFGL_DST_BURST_ALIGN | IDMA32C_CFGL_SRC_BURST_ALIGN; 148 149 /* Low 4 bits of the request lines */ 150 cfghi |= IDMA32C_CFGH_DST_PER(dwc->dws.dst_id & 0xf); 151 cfghi |= IDMA32C_CFGH_SRC_PER(dwc->dws.src_id & 0xf); 152 153 /* Request line extension (2 bits) */ 154 cfghi |= IDMA32C_CFGH_DST_PER_EXT(dwc->dws.dst_id >> 4 & 0x3); 155 cfghi |= IDMA32C_CFGH_SRC_PER_EXT(dwc->dws.src_id >> 4 & 0x3); 156 157 channel_writel(dwc, CFG_LO, cfglo); 158 channel_writel(dwc, CFG_HI, cfghi); 159 } 160 161 static void dwc_initialize_chan_dw(struct dw_dma_chan *dwc) 162 { 163 u32 cfghi = DWC_CFGH_FIFO_MODE; 164 u32 cfglo = DWC_CFGL_CH_PRIOR(dwc->priority); 165 bool hs_polarity = dwc->dws.hs_polarity; 166 167 cfghi |= DWC_CFGH_DST_PER(dwc->dws.dst_id); 168 cfghi |= DWC_CFGH_SRC_PER(dwc->dws.src_id); 169 170 /* Set polarity of handshake interface */ 171 cfglo |= hs_polarity ? DWC_CFGL_HS_DST_POL | DWC_CFGL_HS_SRC_POL : 0; 172 173 channel_writel(dwc, CFG_LO, cfglo); 174 channel_writel(dwc, CFG_HI, cfghi); 175 } 176 177 static void dwc_initialize(struct dw_dma_chan *dwc) 178 { 179 struct dw_dma *dw = to_dw_dma(dwc->chan.device); 180 181 if (test_bit(DW_DMA_IS_INITIALIZED, &dwc->flags)) 182 return; 183 184 if (dw->pdata->is_idma32) 185 dwc_initialize_chan_idma32(dwc); 186 else 187 dwc_initialize_chan_dw(dwc); 188 189 /* Enable interrupts */ 190 channel_set_bit(dw, MASK.XFER, dwc->mask); 191 channel_set_bit(dw, MASK.ERROR, dwc->mask); 192 193 set_bit(DW_DMA_IS_INITIALIZED, &dwc->flags); 194 } 195 196 /*----------------------------------------------------------------------*/ 197 198 static inline void dwc_dump_chan_regs(struct dw_dma_chan *dwc) 199 { 200 dev_err(chan2dev(&dwc->chan), 201 " SAR: 0x%x DAR: 0x%x LLP: 0x%x CTL: 0x%x:%08x\n", 202 channel_readl(dwc, SAR), 203 channel_readl(dwc, DAR), 204 channel_readl(dwc, LLP), 205 channel_readl(dwc, CTL_HI), 206 channel_readl(dwc, CTL_LO)); 207 } 208 209 static inline void dwc_chan_disable(struct dw_dma *dw, struct dw_dma_chan *dwc) 210 { 211 channel_clear_bit(dw, CH_EN, dwc->mask); 212 while (dma_readl(dw, CH_EN) & dwc->mask) 213 cpu_relax(); 214 } 215 216 static u32 bytes2block(struct dw_dma_chan *dwc, size_t bytes, 217 unsigned int width, size_t *len) 218 { 219 struct dw_dma *dw = to_dw_dma(dwc->chan.device); 220 u32 block; 221 222 /* Always in bytes for iDMA 32-bit */ 223 if (dw->pdata->is_idma32) 224 width = 0; 225 226 if ((bytes >> width) > dwc->block_size) { 227 block = dwc->block_size; 228 *len = block << width; 229 } else { 230 block = bytes >> width; 231 *len = bytes; 232 } 233 234 return block; 235 } 236 237 static size_t block2bytes(struct dw_dma_chan *dwc, u32 block, u32 width) 238 { 239 struct dw_dma *dw = to_dw_dma(dwc->chan.device); 240 241 if (dw->pdata->is_idma32) 242 return IDMA32C_CTLH_BLOCK_TS(block); 243 244 return DWC_CTLH_BLOCK_TS(block) << width; 245 } 246 247 /*----------------------------------------------------------------------*/ 248 249 /* Perform single block transfer */ 250 static inline void dwc_do_single_block(struct dw_dma_chan *dwc, 251 struct dw_desc *desc) 252 { 253 struct dw_dma *dw = to_dw_dma(dwc->chan.device); 254 u32 ctllo; 255 256 /* 257 * Software emulation of LLP mode relies on interrupts to continue 258 * multi block transfer. 259 */ 260 ctllo = lli_read(desc, ctllo) | DWC_CTLL_INT_EN; 261 262 channel_writel(dwc, SAR, lli_read(desc, sar)); 263 channel_writel(dwc, DAR, lli_read(desc, dar)); 264 channel_writel(dwc, CTL_LO, ctllo); 265 channel_writel(dwc, CTL_HI, lli_read(desc, ctlhi)); 266 channel_set_bit(dw, CH_EN, dwc->mask); 267 268 /* Move pointer to next descriptor */ 269 dwc->tx_node_active = dwc->tx_node_active->next; 270 } 271 272 /* Called with dwc->lock held and bh disabled */ 273 static void dwc_dostart(struct dw_dma_chan *dwc, struct dw_desc *first) 274 { 275 struct dw_dma *dw = to_dw_dma(dwc->chan.device); 276 u8 lms = DWC_LLP_LMS(dwc->dws.m_master); 277 unsigned long was_soft_llp; 278 279 /* ASSERT: channel is idle */ 280 if (dma_readl(dw, CH_EN) & dwc->mask) { 281 dev_err(chan2dev(&dwc->chan), 282 "%s: BUG: Attempted to start non-idle channel\n", 283 __func__); 284 dwc_dump_chan_regs(dwc); 285 286 /* The tasklet will hopefully advance the queue... */ 287 return; 288 } 289 290 if (dwc->nollp) { 291 was_soft_llp = test_and_set_bit(DW_DMA_IS_SOFT_LLP, 292 &dwc->flags); 293 if (was_soft_llp) { 294 dev_err(chan2dev(&dwc->chan), 295 "BUG: Attempted to start new LLP transfer inside ongoing one\n"); 296 return; 297 } 298 299 dwc_initialize(dwc); 300 301 first->residue = first->total_len; 302 dwc->tx_node_active = &first->tx_list; 303 304 /* Submit first block */ 305 dwc_do_single_block(dwc, first); 306 307 return; 308 } 309 310 dwc_initialize(dwc); 311 312 channel_writel(dwc, LLP, first->txd.phys | lms); 313 channel_writel(dwc, CTL_LO, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); 314 channel_writel(dwc, CTL_HI, 0); 315 channel_set_bit(dw, CH_EN, dwc->mask); 316 } 317 318 static void dwc_dostart_first_queued(struct dw_dma_chan *dwc) 319 { 320 struct dw_desc *desc; 321 322 if (list_empty(&dwc->queue)) 323 return; 324 325 list_move(dwc->queue.next, &dwc->active_list); 326 desc = dwc_first_active(dwc); 327 dev_vdbg(chan2dev(&dwc->chan), "%s: started %u\n", __func__, desc->txd.cookie); 328 dwc_dostart(dwc, desc); 329 } 330 331 /*----------------------------------------------------------------------*/ 332 333 static void 334 dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc, 335 bool callback_required) 336 { 337 struct dma_async_tx_descriptor *txd = &desc->txd; 338 struct dw_desc *child; 339 unsigned long flags; 340 struct dmaengine_desc_callback cb; 341 342 dev_vdbg(chan2dev(&dwc->chan), "descriptor %u complete\n", txd->cookie); 343 344 spin_lock_irqsave(&dwc->lock, flags); 345 dma_cookie_complete(txd); 346 if (callback_required) 347 dmaengine_desc_get_callback(txd, &cb); 348 else 349 memset(&cb, 0, sizeof(cb)); 350 351 /* async_tx_ack */ 352 list_for_each_entry(child, &desc->tx_list, desc_node) 353 async_tx_ack(&child->txd); 354 async_tx_ack(&desc->txd); 355 dwc_desc_put(dwc, desc); 356 spin_unlock_irqrestore(&dwc->lock, flags); 357 358 dmaengine_desc_callback_invoke(&cb, NULL); 359 } 360 361 static void dwc_complete_all(struct dw_dma *dw, struct dw_dma_chan *dwc) 362 { 363 struct dw_desc *desc, *_desc; 364 LIST_HEAD(list); 365 unsigned long flags; 366 367 spin_lock_irqsave(&dwc->lock, flags); 368 if (dma_readl(dw, CH_EN) & dwc->mask) { 369 dev_err(chan2dev(&dwc->chan), 370 "BUG: XFER bit set, but channel not idle!\n"); 371 372 /* Try to continue after resetting the channel... */ 373 dwc_chan_disable(dw, dwc); 374 } 375 376 /* 377 * Submit queued descriptors ASAP, i.e. before we go through 378 * the completed ones. 379 */ 380 list_splice_init(&dwc->active_list, &list); 381 dwc_dostart_first_queued(dwc); 382 383 spin_unlock_irqrestore(&dwc->lock, flags); 384 385 list_for_each_entry_safe(desc, _desc, &list, desc_node) 386 dwc_descriptor_complete(dwc, desc, true); 387 } 388 389 /* Returns how many bytes were already received from source */ 390 static inline u32 dwc_get_sent(struct dw_dma_chan *dwc) 391 { 392 u32 ctlhi = channel_readl(dwc, CTL_HI); 393 u32 ctllo = channel_readl(dwc, CTL_LO); 394 395 return block2bytes(dwc, ctlhi, ctllo >> 4 & 7); 396 } 397 398 static void dwc_scan_descriptors(struct dw_dma *dw, struct dw_dma_chan *dwc) 399 { 400 dma_addr_t llp; 401 struct dw_desc *desc, *_desc; 402 struct dw_desc *child; 403 u32 status_xfer; 404 unsigned long flags; 405 406 spin_lock_irqsave(&dwc->lock, flags); 407 llp = channel_readl(dwc, LLP); 408 status_xfer = dma_readl(dw, RAW.XFER); 409 410 if (status_xfer & dwc->mask) { 411 /* Everything we've submitted is done */ 412 dma_writel(dw, CLEAR.XFER, dwc->mask); 413 414 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { 415 struct list_head *head, *active = dwc->tx_node_active; 416 417 /* 418 * We are inside first active descriptor. 419 * Otherwise something is really wrong. 420 */ 421 desc = dwc_first_active(dwc); 422 423 head = &desc->tx_list; 424 if (active != head) { 425 /* Update residue to reflect last sent descriptor */ 426 if (active == head->next) 427 desc->residue -= desc->len; 428 else 429 desc->residue -= to_dw_desc(active->prev)->len; 430 431 child = to_dw_desc(active); 432 433 /* Submit next block */ 434 dwc_do_single_block(dwc, child); 435 436 spin_unlock_irqrestore(&dwc->lock, flags); 437 return; 438 } 439 440 /* We are done here */ 441 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); 442 } 443 444 spin_unlock_irqrestore(&dwc->lock, flags); 445 446 dwc_complete_all(dw, dwc); 447 return; 448 } 449 450 if (list_empty(&dwc->active_list)) { 451 spin_unlock_irqrestore(&dwc->lock, flags); 452 return; 453 } 454 455 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags)) { 456 dev_vdbg(chan2dev(&dwc->chan), "%s: soft LLP mode\n", __func__); 457 spin_unlock_irqrestore(&dwc->lock, flags); 458 return; 459 } 460 461 dev_vdbg(chan2dev(&dwc->chan), "%s: llp=%pad\n", __func__, &llp); 462 463 list_for_each_entry_safe(desc, _desc, &dwc->active_list, desc_node) { 464 /* Initial residue value */ 465 desc->residue = desc->total_len; 466 467 /* Check first descriptors addr */ 468 if (desc->txd.phys == DWC_LLP_LOC(llp)) { 469 spin_unlock_irqrestore(&dwc->lock, flags); 470 return; 471 } 472 473 /* Check first descriptors llp */ 474 if (lli_read(desc, llp) == llp) { 475 /* This one is currently in progress */ 476 desc->residue -= dwc_get_sent(dwc); 477 spin_unlock_irqrestore(&dwc->lock, flags); 478 return; 479 } 480 481 desc->residue -= desc->len; 482 list_for_each_entry(child, &desc->tx_list, desc_node) { 483 if (lli_read(child, llp) == llp) { 484 /* Currently in progress */ 485 desc->residue -= dwc_get_sent(dwc); 486 spin_unlock_irqrestore(&dwc->lock, flags); 487 return; 488 } 489 desc->residue -= child->len; 490 } 491 492 /* 493 * No descriptors so far seem to be in progress, i.e. 494 * this one must be done. 495 */ 496 spin_unlock_irqrestore(&dwc->lock, flags); 497 dwc_descriptor_complete(dwc, desc, true); 498 spin_lock_irqsave(&dwc->lock, flags); 499 } 500 501 dev_err(chan2dev(&dwc->chan), 502 "BUG: All descriptors done, but channel not idle!\n"); 503 504 /* Try to continue after resetting the channel... */ 505 dwc_chan_disable(dw, dwc); 506 507 dwc_dostart_first_queued(dwc); 508 spin_unlock_irqrestore(&dwc->lock, flags); 509 } 510 511 static inline void dwc_dump_lli(struct dw_dma_chan *dwc, struct dw_desc *desc) 512 { 513 dev_crit(chan2dev(&dwc->chan), " desc: s0x%x d0x%x l0x%x c0x%x:%x\n", 514 lli_read(desc, sar), 515 lli_read(desc, dar), 516 lli_read(desc, llp), 517 lli_read(desc, ctlhi), 518 lli_read(desc, ctllo)); 519 } 520 521 static void dwc_handle_error(struct dw_dma *dw, struct dw_dma_chan *dwc) 522 { 523 struct dw_desc *bad_desc; 524 struct dw_desc *child; 525 unsigned long flags; 526 527 dwc_scan_descriptors(dw, dwc); 528 529 spin_lock_irqsave(&dwc->lock, flags); 530 531 /* 532 * The descriptor currently at the head of the active list is 533 * borked. Since we don't have any way to report errors, we'll 534 * just have to scream loudly and try to carry on. 535 */ 536 bad_desc = dwc_first_active(dwc); 537 list_del_init(&bad_desc->desc_node); 538 list_move(dwc->queue.next, dwc->active_list.prev); 539 540 /* Clear the error flag and try to restart the controller */ 541 dma_writel(dw, CLEAR.ERROR, dwc->mask); 542 if (!list_empty(&dwc->active_list)) 543 dwc_dostart(dwc, dwc_first_active(dwc)); 544 545 /* 546 * WARN may seem harsh, but since this only happens 547 * when someone submits a bad physical address in a 548 * descriptor, we should consider ourselves lucky that the 549 * controller flagged an error instead of scribbling over 550 * random memory locations. 551 */ 552 dev_WARN(chan2dev(&dwc->chan), "Bad descriptor submitted for DMA!\n" 553 " cookie: %d\n", bad_desc->txd.cookie); 554 dwc_dump_lli(dwc, bad_desc); 555 list_for_each_entry(child, &bad_desc->tx_list, desc_node) 556 dwc_dump_lli(dwc, child); 557 558 spin_unlock_irqrestore(&dwc->lock, flags); 559 560 /* Pretend the descriptor completed successfully */ 561 dwc_descriptor_complete(dwc, bad_desc, true); 562 } 563 564 /* --------------------- Cyclic DMA API extensions -------------------- */ 565 566 dma_addr_t dw_dma_get_src_addr(struct dma_chan *chan) 567 { 568 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 569 return channel_readl(dwc, SAR); 570 } 571 EXPORT_SYMBOL(dw_dma_get_src_addr); 572 573 dma_addr_t dw_dma_get_dst_addr(struct dma_chan *chan) 574 { 575 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 576 return channel_readl(dwc, DAR); 577 } 578 EXPORT_SYMBOL(dw_dma_get_dst_addr); 579 580 /* Called with dwc->lock held and all DMAC interrupts disabled */ 581 static void dwc_handle_cyclic(struct dw_dma *dw, struct dw_dma_chan *dwc, 582 u32 status_block, u32 status_err, u32 status_xfer) 583 { 584 unsigned long flags; 585 586 if (status_block & dwc->mask) { 587 void (*callback)(void *param); 588 void *callback_param; 589 590 dev_vdbg(chan2dev(&dwc->chan), "new cyclic period llp 0x%08x\n", 591 channel_readl(dwc, LLP)); 592 dma_writel(dw, CLEAR.BLOCK, dwc->mask); 593 594 callback = dwc->cdesc->period_callback; 595 callback_param = dwc->cdesc->period_callback_param; 596 597 if (callback) 598 callback(callback_param); 599 } 600 601 /* 602 * Error and transfer complete are highly unlikely, and will most 603 * likely be due to a configuration error by the user. 604 */ 605 if (unlikely(status_err & dwc->mask) || 606 unlikely(status_xfer & dwc->mask)) { 607 unsigned int i; 608 609 dev_err(chan2dev(&dwc->chan), 610 "cyclic DMA unexpected %s interrupt, stopping DMA transfer\n", 611 status_xfer ? "xfer" : "error"); 612 613 spin_lock_irqsave(&dwc->lock, flags); 614 615 dwc_dump_chan_regs(dwc); 616 617 dwc_chan_disable(dw, dwc); 618 619 /* Make sure DMA does not restart by loading a new list */ 620 channel_writel(dwc, LLP, 0); 621 channel_writel(dwc, CTL_LO, 0); 622 channel_writel(dwc, CTL_HI, 0); 623 624 dma_writel(dw, CLEAR.BLOCK, dwc->mask); 625 dma_writel(dw, CLEAR.ERROR, dwc->mask); 626 dma_writel(dw, CLEAR.XFER, dwc->mask); 627 628 for (i = 0; i < dwc->cdesc->periods; i++) 629 dwc_dump_lli(dwc, dwc->cdesc->desc[i]); 630 631 spin_unlock_irqrestore(&dwc->lock, flags); 632 } 633 634 /* Re-enable interrupts */ 635 channel_set_bit(dw, MASK.BLOCK, dwc->mask); 636 } 637 638 /* ------------------------------------------------------------------------- */ 639 640 static void dw_dma_tasklet(unsigned long data) 641 { 642 struct dw_dma *dw = (struct dw_dma *)data; 643 struct dw_dma_chan *dwc; 644 u32 status_block; 645 u32 status_xfer; 646 u32 status_err; 647 unsigned int i; 648 649 status_block = dma_readl(dw, RAW.BLOCK); 650 status_xfer = dma_readl(dw, RAW.XFER); 651 status_err = dma_readl(dw, RAW.ERROR); 652 653 dev_vdbg(dw->dma.dev, "%s: status_err=%x\n", __func__, status_err); 654 655 for (i = 0; i < dw->dma.chancnt; i++) { 656 dwc = &dw->chan[i]; 657 if (test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) 658 dwc_handle_cyclic(dw, dwc, status_block, status_err, 659 status_xfer); 660 else if (status_err & (1 << i)) 661 dwc_handle_error(dw, dwc); 662 else if (status_xfer & (1 << i)) 663 dwc_scan_descriptors(dw, dwc); 664 } 665 666 /* Re-enable interrupts */ 667 channel_set_bit(dw, MASK.XFER, dw->all_chan_mask); 668 channel_set_bit(dw, MASK.ERROR, dw->all_chan_mask); 669 } 670 671 static irqreturn_t dw_dma_interrupt(int irq, void *dev_id) 672 { 673 struct dw_dma *dw = dev_id; 674 u32 status; 675 676 /* Check if we have any interrupt from the DMAC which is not in use */ 677 if (!dw->in_use) 678 return IRQ_NONE; 679 680 status = dma_readl(dw, STATUS_INT); 681 dev_vdbg(dw->dma.dev, "%s: status=0x%x\n", __func__, status); 682 683 /* Check if we have any interrupt from the DMAC */ 684 if (!status) 685 return IRQ_NONE; 686 687 /* 688 * Just disable the interrupts. We'll turn them back on in the 689 * softirq handler. 690 */ 691 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); 692 channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); 693 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); 694 695 status = dma_readl(dw, STATUS_INT); 696 if (status) { 697 dev_err(dw->dma.dev, 698 "BUG: Unexpected interrupts pending: 0x%x\n", 699 status); 700 701 /* Try to recover */ 702 channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1); 703 channel_clear_bit(dw, MASK.BLOCK, (1 << 8) - 1); 704 channel_clear_bit(dw, MASK.SRC_TRAN, (1 << 8) - 1); 705 channel_clear_bit(dw, MASK.DST_TRAN, (1 << 8) - 1); 706 channel_clear_bit(dw, MASK.ERROR, (1 << 8) - 1); 707 } 708 709 tasklet_schedule(&dw->tasklet); 710 711 return IRQ_HANDLED; 712 } 713 714 /*----------------------------------------------------------------------*/ 715 716 static struct dma_async_tx_descriptor * 717 dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, 718 size_t len, unsigned long flags) 719 { 720 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 721 struct dw_dma *dw = to_dw_dma(chan->device); 722 struct dw_desc *desc; 723 struct dw_desc *first; 724 struct dw_desc *prev; 725 size_t xfer_count; 726 size_t offset; 727 u8 m_master = dwc->dws.m_master; 728 unsigned int src_width; 729 unsigned int dst_width; 730 unsigned int data_width = dw->pdata->data_width[m_master]; 731 u32 ctllo; 732 u8 lms = DWC_LLP_LMS(m_master); 733 734 dev_vdbg(chan2dev(chan), 735 "%s: d%pad s%pad l0x%zx f0x%lx\n", __func__, 736 &dest, &src, len, flags); 737 738 if (unlikely(!len)) { 739 dev_dbg(chan2dev(chan), "%s: length is zero!\n", __func__); 740 return NULL; 741 } 742 743 dwc->direction = DMA_MEM_TO_MEM; 744 745 src_width = dst_width = __ffs(data_width | src | dest | len); 746 747 ctllo = DWC_DEFAULT_CTLLO(chan) 748 | DWC_CTLL_DST_WIDTH(dst_width) 749 | DWC_CTLL_SRC_WIDTH(src_width) 750 | DWC_CTLL_DST_INC 751 | DWC_CTLL_SRC_INC 752 | DWC_CTLL_FC_M2M; 753 prev = first = NULL; 754 755 for (offset = 0; offset < len; offset += xfer_count) { 756 desc = dwc_desc_get(dwc); 757 if (!desc) 758 goto err_desc_get; 759 760 lli_write(desc, sar, src + offset); 761 lli_write(desc, dar, dest + offset); 762 lli_write(desc, ctllo, ctllo); 763 lli_write(desc, ctlhi, bytes2block(dwc, len - offset, src_width, &xfer_count)); 764 desc->len = xfer_count; 765 766 if (!first) { 767 first = desc; 768 } else { 769 lli_write(prev, llp, desc->txd.phys | lms); 770 list_add_tail(&desc->desc_node, &first->tx_list); 771 } 772 prev = desc; 773 } 774 775 if (flags & DMA_PREP_INTERRUPT) 776 /* Trigger interrupt after last block */ 777 lli_set(prev, ctllo, DWC_CTLL_INT_EN); 778 779 prev->lli.llp = 0; 780 lli_clear(prev, ctllo, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); 781 first->txd.flags = flags; 782 first->total_len = len; 783 784 return &first->txd; 785 786 err_desc_get: 787 dwc_desc_put(dwc, first); 788 return NULL; 789 } 790 791 static struct dma_async_tx_descriptor * 792 dwc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, 793 unsigned int sg_len, enum dma_transfer_direction direction, 794 unsigned long flags, void *context) 795 { 796 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 797 struct dw_dma *dw = to_dw_dma(chan->device); 798 struct dma_slave_config *sconfig = &dwc->dma_sconfig; 799 struct dw_desc *prev; 800 struct dw_desc *first; 801 u32 ctllo; 802 u8 m_master = dwc->dws.m_master; 803 u8 lms = DWC_LLP_LMS(m_master); 804 dma_addr_t reg; 805 unsigned int reg_width; 806 unsigned int mem_width; 807 unsigned int data_width = dw->pdata->data_width[m_master]; 808 unsigned int i; 809 struct scatterlist *sg; 810 size_t total_len = 0; 811 812 dev_vdbg(chan2dev(chan), "%s\n", __func__); 813 814 if (unlikely(!is_slave_direction(direction) || !sg_len)) 815 return NULL; 816 817 dwc->direction = direction; 818 819 prev = first = NULL; 820 821 switch (direction) { 822 case DMA_MEM_TO_DEV: 823 reg_width = __ffs(sconfig->dst_addr_width); 824 reg = sconfig->dst_addr; 825 ctllo = (DWC_DEFAULT_CTLLO(chan) 826 | DWC_CTLL_DST_WIDTH(reg_width) 827 | DWC_CTLL_DST_FIX 828 | DWC_CTLL_SRC_INC); 829 830 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_M2P) : 831 DWC_CTLL_FC(DW_DMA_FC_D_M2P); 832 833 for_each_sg(sgl, sg, sg_len, i) { 834 struct dw_desc *desc; 835 u32 len, mem; 836 size_t dlen; 837 838 mem = sg_dma_address(sg); 839 len = sg_dma_len(sg); 840 841 mem_width = __ffs(data_width | mem | len); 842 843 slave_sg_todev_fill_desc: 844 desc = dwc_desc_get(dwc); 845 if (!desc) 846 goto err_desc_get; 847 848 lli_write(desc, sar, mem); 849 lli_write(desc, dar, reg); 850 lli_write(desc, ctlhi, bytes2block(dwc, len, mem_width, &dlen)); 851 lli_write(desc, ctllo, ctllo | DWC_CTLL_SRC_WIDTH(mem_width)); 852 desc->len = dlen; 853 854 if (!first) { 855 first = desc; 856 } else { 857 lli_write(prev, llp, desc->txd.phys | lms); 858 list_add_tail(&desc->desc_node, &first->tx_list); 859 } 860 prev = desc; 861 862 mem += dlen; 863 len -= dlen; 864 total_len += dlen; 865 866 if (len) 867 goto slave_sg_todev_fill_desc; 868 } 869 break; 870 case DMA_DEV_TO_MEM: 871 reg_width = __ffs(sconfig->src_addr_width); 872 reg = sconfig->src_addr; 873 ctllo = (DWC_DEFAULT_CTLLO(chan) 874 | DWC_CTLL_SRC_WIDTH(reg_width) 875 | DWC_CTLL_DST_INC 876 | DWC_CTLL_SRC_FIX); 877 878 ctllo |= sconfig->device_fc ? DWC_CTLL_FC(DW_DMA_FC_P_P2M) : 879 DWC_CTLL_FC(DW_DMA_FC_D_P2M); 880 881 for_each_sg(sgl, sg, sg_len, i) { 882 struct dw_desc *desc; 883 u32 len, mem; 884 size_t dlen; 885 886 mem = sg_dma_address(sg); 887 len = sg_dma_len(sg); 888 889 slave_sg_fromdev_fill_desc: 890 desc = dwc_desc_get(dwc); 891 if (!desc) 892 goto err_desc_get; 893 894 lli_write(desc, sar, reg); 895 lli_write(desc, dar, mem); 896 lli_write(desc, ctlhi, bytes2block(dwc, len, reg_width, &dlen)); 897 mem_width = __ffs(data_width | mem | dlen); 898 lli_write(desc, ctllo, ctllo | DWC_CTLL_DST_WIDTH(mem_width)); 899 desc->len = dlen; 900 901 if (!first) { 902 first = desc; 903 } else { 904 lli_write(prev, llp, desc->txd.phys | lms); 905 list_add_tail(&desc->desc_node, &first->tx_list); 906 } 907 prev = desc; 908 909 mem += dlen; 910 len -= dlen; 911 total_len += dlen; 912 913 if (len) 914 goto slave_sg_fromdev_fill_desc; 915 } 916 break; 917 default: 918 return NULL; 919 } 920 921 if (flags & DMA_PREP_INTERRUPT) 922 /* Trigger interrupt after last block */ 923 lli_set(prev, ctllo, DWC_CTLL_INT_EN); 924 925 prev->lli.llp = 0; 926 lli_clear(prev, ctllo, DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN); 927 first->total_len = total_len; 928 929 return &first->txd; 930 931 err_desc_get: 932 dev_err(chan2dev(chan), 933 "not enough descriptors available. Direction %d\n", direction); 934 dwc_desc_put(dwc, first); 935 return NULL; 936 } 937 938 bool dw_dma_filter(struct dma_chan *chan, void *param) 939 { 940 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 941 struct dw_dma_slave *dws = param; 942 943 if (dws->dma_dev != chan->device->dev) 944 return false; 945 946 /* We have to copy data since dws can be temporary storage */ 947 memcpy(&dwc->dws, dws, sizeof(struct dw_dma_slave)); 948 949 return true; 950 } 951 EXPORT_SYMBOL_GPL(dw_dma_filter); 952 953 static int dwc_config(struct dma_chan *chan, struct dma_slave_config *sconfig) 954 { 955 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 956 struct dma_slave_config *sc = &dwc->dma_sconfig; 957 struct dw_dma *dw = to_dw_dma(chan->device); 958 /* 959 * Fix sconfig's burst size according to dw_dmac. We need to convert 960 * them as: 961 * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3. 962 * 963 * NOTE: burst size 2 is not supported by DesignWare controller. 964 * iDMA 32-bit supports it. 965 */ 966 u32 s = dw->pdata->is_idma32 ? 1 : 2; 967 968 /* Check if chan will be configured for slave transfers */ 969 if (!is_slave_direction(sconfig->direction)) 970 return -EINVAL; 971 972 memcpy(&dwc->dma_sconfig, sconfig, sizeof(*sconfig)); 973 dwc->direction = sconfig->direction; 974 975 sc->src_maxburst = sc->src_maxburst > 1 ? fls(sc->src_maxburst) - s : 0; 976 sc->dst_maxburst = sc->dst_maxburst > 1 ? fls(sc->dst_maxburst) - s : 0; 977 978 return 0; 979 } 980 981 static void dwc_chan_pause(struct dw_dma_chan *dwc, bool drain) 982 { 983 struct dw_dma *dw = to_dw_dma(dwc->chan.device); 984 unsigned int count = 20; /* timeout iterations */ 985 u32 cfglo; 986 987 cfglo = channel_readl(dwc, CFG_LO); 988 if (dw->pdata->is_idma32) { 989 if (drain) 990 cfglo |= IDMA32C_CFGL_CH_DRAIN; 991 else 992 cfglo &= ~IDMA32C_CFGL_CH_DRAIN; 993 } 994 channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP); 995 while (!(channel_readl(dwc, CFG_LO) & DWC_CFGL_FIFO_EMPTY) && count--) 996 udelay(2); 997 998 set_bit(DW_DMA_IS_PAUSED, &dwc->flags); 999 } 1000 1001 static int dwc_pause(struct dma_chan *chan) 1002 { 1003 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 1004 unsigned long flags; 1005 1006 spin_lock_irqsave(&dwc->lock, flags); 1007 dwc_chan_pause(dwc, false); 1008 spin_unlock_irqrestore(&dwc->lock, flags); 1009 1010 return 0; 1011 } 1012 1013 static inline void dwc_chan_resume(struct dw_dma_chan *dwc) 1014 { 1015 u32 cfglo = channel_readl(dwc, CFG_LO); 1016 1017 channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP); 1018 1019 clear_bit(DW_DMA_IS_PAUSED, &dwc->flags); 1020 } 1021 1022 static int dwc_resume(struct dma_chan *chan) 1023 { 1024 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 1025 unsigned long flags; 1026 1027 spin_lock_irqsave(&dwc->lock, flags); 1028 1029 if (test_bit(DW_DMA_IS_PAUSED, &dwc->flags)) 1030 dwc_chan_resume(dwc); 1031 1032 spin_unlock_irqrestore(&dwc->lock, flags); 1033 1034 return 0; 1035 } 1036 1037 static int dwc_terminate_all(struct dma_chan *chan) 1038 { 1039 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 1040 struct dw_dma *dw = to_dw_dma(chan->device); 1041 struct dw_desc *desc, *_desc; 1042 unsigned long flags; 1043 LIST_HEAD(list); 1044 1045 spin_lock_irqsave(&dwc->lock, flags); 1046 1047 clear_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags); 1048 1049 dwc_chan_pause(dwc, true); 1050 1051 dwc_chan_disable(dw, dwc); 1052 1053 dwc_chan_resume(dwc); 1054 1055 /* active_list entries will end up before queued entries */ 1056 list_splice_init(&dwc->queue, &list); 1057 list_splice_init(&dwc->active_list, &list); 1058 1059 spin_unlock_irqrestore(&dwc->lock, flags); 1060 1061 /* Flush all pending and queued descriptors */ 1062 list_for_each_entry_safe(desc, _desc, &list, desc_node) 1063 dwc_descriptor_complete(dwc, desc, false); 1064 1065 return 0; 1066 } 1067 1068 static struct dw_desc *dwc_find_desc(struct dw_dma_chan *dwc, dma_cookie_t c) 1069 { 1070 struct dw_desc *desc; 1071 1072 list_for_each_entry(desc, &dwc->active_list, desc_node) 1073 if (desc->txd.cookie == c) 1074 return desc; 1075 1076 return NULL; 1077 } 1078 1079 static u32 dwc_get_residue(struct dw_dma_chan *dwc, dma_cookie_t cookie) 1080 { 1081 struct dw_desc *desc; 1082 unsigned long flags; 1083 u32 residue; 1084 1085 spin_lock_irqsave(&dwc->lock, flags); 1086 1087 desc = dwc_find_desc(dwc, cookie); 1088 if (desc) { 1089 if (desc == dwc_first_active(dwc)) { 1090 residue = desc->residue; 1091 if (test_bit(DW_DMA_IS_SOFT_LLP, &dwc->flags) && residue) 1092 residue -= dwc_get_sent(dwc); 1093 } else { 1094 residue = desc->total_len; 1095 } 1096 } else { 1097 residue = 0; 1098 } 1099 1100 spin_unlock_irqrestore(&dwc->lock, flags); 1101 return residue; 1102 } 1103 1104 static enum dma_status 1105 dwc_tx_status(struct dma_chan *chan, 1106 dma_cookie_t cookie, 1107 struct dma_tx_state *txstate) 1108 { 1109 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 1110 enum dma_status ret; 1111 1112 ret = dma_cookie_status(chan, cookie, txstate); 1113 if (ret == DMA_COMPLETE) 1114 return ret; 1115 1116 dwc_scan_descriptors(to_dw_dma(chan->device), dwc); 1117 1118 ret = dma_cookie_status(chan, cookie, txstate); 1119 if (ret == DMA_COMPLETE) 1120 return ret; 1121 1122 dma_set_residue(txstate, dwc_get_residue(dwc, cookie)); 1123 1124 if (test_bit(DW_DMA_IS_PAUSED, &dwc->flags) && ret == DMA_IN_PROGRESS) 1125 return DMA_PAUSED; 1126 1127 return ret; 1128 } 1129 1130 static void dwc_issue_pending(struct dma_chan *chan) 1131 { 1132 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 1133 unsigned long flags; 1134 1135 spin_lock_irqsave(&dwc->lock, flags); 1136 if (list_empty(&dwc->active_list)) 1137 dwc_dostart_first_queued(dwc); 1138 spin_unlock_irqrestore(&dwc->lock, flags); 1139 } 1140 1141 /*----------------------------------------------------------------------*/ 1142 1143 /* 1144 * Program FIFO size of channels. 1145 * 1146 * By default full FIFO (1024 bytes) is assigned to channel 0. Here we 1147 * slice FIFO on equal parts between channels. 1148 */ 1149 static void idma32_fifo_partition(struct dw_dma *dw) 1150 { 1151 u64 value = IDMA32C_FP_PSIZE_CH0(128) | IDMA32C_FP_PSIZE_CH1(128) | 1152 IDMA32C_FP_UPDATE; 1153 u64 fifo_partition = 0; 1154 1155 if (!dw->pdata->is_idma32) 1156 return; 1157 1158 /* Fill FIFO_PARTITION low bits (Channels 0..1, 4..5) */ 1159 fifo_partition |= value << 0; 1160 1161 /* Fill FIFO_PARTITION high bits (Channels 2..3, 6..7) */ 1162 fifo_partition |= value << 32; 1163 1164 /* Program FIFO Partition registers - 128 bytes for each channel */ 1165 idma32_writeq(dw, FIFO_PARTITION1, fifo_partition); 1166 idma32_writeq(dw, FIFO_PARTITION0, fifo_partition); 1167 } 1168 1169 static void dw_dma_off(struct dw_dma *dw) 1170 { 1171 unsigned int i; 1172 1173 dma_writel(dw, CFG, 0); 1174 1175 channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask); 1176 channel_clear_bit(dw, MASK.BLOCK, dw->all_chan_mask); 1177 channel_clear_bit(dw, MASK.SRC_TRAN, dw->all_chan_mask); 1178 channel_clear_bit(dw, MASK.DST_TRAN, dw->all_chan_mask); 1179 channel_clear_bit(dw, MASK.ERROR, dw->all_chan_mask); 1180 1181 while (dma_readl(dw, CFG) & DW_CFG_DMA_EN) 1182 cpu_relax(); 1183 1184 for (i = 0; i < dw->dma.chancnt; i++) 1185 clear_bit(DW_DMA_IS_INITIALIZED, &dw->chan[i].flags); 1186 } 1187 1188 static void dw_dma_on(struct dw_dma *dw) 1189 { 1190 dma_writel(dw, CFG, DW_CFG_DMA_EN); 1191 } 1192 1193 static int dwc_alloc_chan_resources(struct dma_chan *chan) 1194 { 1195 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 1196 struct dw_dma *dw = to_dw_dma(chan->device); 1197 1198 dev_vdbg(chan2dev(chan), "%s\n", __func__); 1199 1200 /* ASSERT: channel is idle */ 1201 if (dma_readl(dw, CH_EN) & dwc->mask) { 1202 dev_dbg(chan2dev(chan), "DMA channel not idle?\n"); 1203 return -EIO; 1204 } 1205 1206 dma_cookie_init(chan); 1207 1208 /* 1209 * NOTE: some controllers may have additional features that we 1210 * need to initialize here, like "scatter-gather" (which 1211 * doesn't mean what you think it means), and status writeback. 1212 */ 1213 1214 /* 1215 * We need controller-specific data to set up slave transfers. 1216 */ 1217 if (chan->private && !dw_dma_filter(chan, chan->private)) { 1218 dev_warn(chan2dev(chan), "Wrong controller-specific data\n"); 1219 return -EINVAL; 1220 } 1221 1222 /* Enable controller here if needed */ 1223 if (!dw->in_use) 1224 dw_dma_on(dw); 1225 dw->in_use |= dwc->mask; 1226 1227 return 0; 1228 } 1229 1230 static void dwc_free_chan_resources(struct dma_chan *chan) 1231 { 1232 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 1233 struct dw_dma *dw = to_dw_dma(chan->device); 1234 unsigned long flags; 1235 LIST_HEAD(list); 1236 1237 dev_dbg(chan2dev(chan), "%s: descs allocated=%u\n", __func__, 1238 dwc->descs_allocated); 1239 1240 /* ASSERT: channel is idle */ 1241 BUG_ON(!list_empty(&dwc->active_list)); 1242 BUG_ON(!list_empty(&dwc->queue)); 1243 BUG_ON(dma_readl(to_dw_dma(chan->device), CH_EN) & dwc->mask); 1244 1245 spin_lock_irqsave(&dwc->lock, flags); 1246 1247 /* Clear custom channel configuration */ 1248 memset(&dwc->dws, 0, sizeof(struct dw_dma_slave)); 1249 1250 clear_bit(DW_DMA_IS_INITIALIZED, &dwc->flags); 1251 1252 /* Disable interrupts */ 1253 channel_clear_bit(dw, MASK.XFER, dwc->mask); 1254 channel_clear_bit(dw, MASK.BLOCK, dwc->mask); 1255 channel_clear_bit(dw, MASK.ERROR, dwc->mask); 1256 1257 spin_unlock_irqrestore(&dwc->lock, flags); 1258 1259 /* Disable controller in case it was a last user */ 1260 dw->in_use &= ~dwc->mask; 1261 if (!dw->in_use) 1262 dw_dma_off(dw); 1263 1264 dev_vdbg(chan2dev(chan), "%s: done\n", __func__); 1265 } 1266 1267 /* --------------------- Cyclic DMA API extensions -------------------- */ 1268 1269 /** 1270 * dw_dma_cyclic_start - start the cyclic DMA transfer 1271 * @chan: the DMA channel to start 1272 * 1273 * Must be called with soft interrupts disabled. Returns zero on success or 1274 * -errno on failure. 1275 */ 1276 int dw_dma_cyclic_start(struct dma_chan *chan) 1277 { 1278 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 1279 struct dw_dma *dw = to_dw_dma(chan->device); 1280 unsigned long flags; 1281 1282 if (!test_bit(DW_DMA_IS_CYCLIC, &dwc->flags)) { 1283 dev_err(chan2dev(&dwc->chan), "missing prep for cyclic DMA\n"); 1284 return -ENODEV; 1285 } 1286 1287 spin_lock_irqsave(&dwc->lock, flags); 1288 1289 /* Enable interrupts to perform cyclic transfer */ 1290 channel_set_bit(dw, MASK.BLOCK, dwc->mask); 1291 1292 dwc_dostart(dwc, dwc->cdesc->desc[0]); 1293 1294 spin_unlock_irqrestore(&dwc->lock, flags); 1295 1296 return 0; 1297 } 1298 EXPORT_SYMBOL(dw_dma_cyclic_start); 1299 1300 /** 1301 * dw_dma_cyclic_stop - stop the cyclic DMA transfer 1302 * @chan: the DMA channel to stop 1303 * 1304 * Must be called with soft interrupts disabled. 1305 */ 1306 void dw_dma_cyclic_stop(struct dma_chan *chan) 1307 { 1308 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 1309 struct dw_dma *dw = to_dw_dma(dwc->chan.device); 1310 unsigned long flags; 1311 1312 spin_lock_irqsave(&dwc->lock, flags); 1313 1314 dwc_chan_disable(dw, dwc); 1315 1316 spin_unlock_irqrestore(&dwc->lock, flags); 1317 } 1318 EXPORT_SYMBOL(dw_dma_cyclic_stop); 1319 1320 /** 1321 * dw_dma_cyclic_prep - prepare the cyclic DMA transfer 1322 * @chan: the DMA channel to prepare 1323 * @buf_addr: physical DMA address where the buffer starts 1324 * @buf_len: total number of bytes for the entire buffer 1325 * @period_len: number of bytes for each period 1326 * @direction: transfer direction, to or from device 1327 * 1328 * Must be called before trying to start the transfer. Returns a valid struct 1329 * dw_cyclic_desc if successful or an ERR_PTR(-errno) if not successful. 1330 */ 1331 struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan, 1332 dma_addr_t buf_addr, size_t buf_len, size_t period_len, 1333 enum dma_transfer_direction direction) 1334 { 1335 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 1336 struct dma_slave_config *sconfig = &dwc->dma_sconfig; 1337 struct dw_cyclic_desc *cdesc; 1338 struct dw_cyclic_desc *retval = NULL; 1339 struct dw_desc *desc; 1340 struct dw_desc *last = NULL; 1341 u8 lms = DWC_LLP_LMS(dwc->dws.m_master); 1342 unsigned long was_cyclic; 1343 unsigned int reg_width; 1344 unsigned int periods; 1345 unsigned int i; 1346 unsigned long flags; 1347 1348 spin_lock_irqsave(&dwc->lock, flags); 1349 if (dwc->nollp) { 1350 spin_unlock_irqrestore(&dwc->lock, flags); 1351 dev_dbg(chan2dev(&dwc->chan), 1352 "channel doesn't support LLP transfers\n"); 1353 return ERR_PTR(-EINVAL); 1354 } 1355 1356 if (!list_empty(&dwc->queue) || !list_empty(&dwc->active_list)) { 1357 spin_unlock_irqrestore(&dwc->lock, flags); 1358 dev_dbg(chan2dev(&dwc->chan), 1359 "queue and/or active list are not empty\n"); 1360 return ERR_PTR(-EBUSY); 1361 } 1362 1363 was_cyclic = test_and_set_bit(DW_DMA_IS_CYCLIC, &dwc->flags); 1364 spin_unlock_irqrestore(&dwc->lock, flags); 1365 if (was_cyclic) { 1366 dev_dbg(chan2dev(&dwc->chan), 1367 "channel already prepared for cyclic DMA\n"); 1368 return ERR_PTR(-EBUSY); 1369 } 1370 1371 retval = ERR_PTR(-EINVAL); 1372 1373 if (unlikely(!is_slave_direction(direction))) 1374 goto out_err; 1375 1376 dwc->direction = direction; 1377 1378 if (direction == DMA_MEM_TO_DEV) 1379 reg_width = __ffs(sconfig->dst_addr_width); 1380 else 1381 reg_width = __ffs(sconfig->src_addr_width); 1382 1383 periods = buf_len / period_len; 1384 1385 /* Check for too big/unaligned periods and unaligned DMA buffer. */ 1386 if (period_len > (dwc->block_size << reg_width)) 1387 goto out_err; 1388 if (unlikely(period_len & ((1 << reg_width) - 1))) 1389 goto out_err; 1390 if (unlikely(buf_addr & ((1 << reg_width) - 1))) 1391 goto out_err; 1392 1393 retval = ERR_PTR(-ENOMEM); 1394 1395 cdesc = kzalloc(sizeof(struct dw_cyclic_desc), GFP_KERNEL); 1396 if (!cdesc) 1397 goto out_err; 1398 1399 cdesc->desc = kzalloc(sizeof(struct dw_desc *) * periods, GFP_KERNEL); 1400 if (!cdesc->desc) 1401 goto out_err_alloc; 1402 1403 for (i = 0; i < periods; i++) { 1404 desc = dwc_desc_get(dwc); 1405 if (!desc) 1406 goto out_err_desc_get; 1407 1408 switch (direction) { 1409 case DMA_MEM_TO_DEV: 1410 lli_write(desc, dar, sconfig->dst_addr); 1411 lli_write(desc, sar, buf_addr + period_len * i); 1412 lli_write(desc, ctllo, (DWC_DEFAULT_CTLLO(chan) 1413 | DWC_CTLL_DST_WIDTH(reg_width) 1414 | DWC_CTLL_SRC_WIDTH(reg_width) 1415 | DWC_CTLL_DST_FIX 1416 | DWC_CTLL_SRC_INC 1417 | DWC_CTLL_INT_EN)); 1418 1419 lli_set(desc, ctllo, sconfig->device_fc ? 1420 DWC_CTLL_FC(DW_DMA_FC_P_M2P) : 1421 DWC_CTLL_FC(DW_DMA_FC_D_M2P)); 1422 1423 break; 1424 case DMA_DEV_TO_MEM: 1425 lli_write(desc, dar, buf_addr + period_len * i); 1426 lli_write(desc, sar, sconfig->src_addr); 1427 lli_write(desc, ctllo, (DWC_DEFAULT_CTLLO(chan) 1428 | DWC_CTLL_SRC_WIDTH(reg_width) 1429 | DWC_CTLL_DST_WIDTH(reg_width) 1430 | DWC_CTLL_DST_INC 1431 | DWC_CTLL_SRC_FIX 1432 | DWC_CTLL_INT_EN)); 1433 1434 lli_set(desc, ctllo, sconfig->device_fc ? 1435 DWC_CTLL_FC(DW_DMA_FC_P_P2M) : 1436 DWC_CTLL_FC(DW_DMA_FC_D_P2M)); 1437 1438 break; 1439 default: 1440 break; 1441 } 1442 1443 lli_write(desc, ctlhi, period_len >> reg_width); 1444 cdesc->desc[i] = desc; 1445 1446 if (last) 1447 lli_write(last, llp, desc->txd.phys | lms); 1448 1449 last = desc; 1450 } 1451 1452 /* Let's make a cyclic list */ 1453 lli_write(last, llp, cdesc->desc[0]->txd.phys | lms); 1454 1455 dev_dbg(chan2dev(&dwc->chan), 1456 "cyclic prepared buf %pad len %zu period %zu periods %d\n", 1457 &buf_addr, buf_len, period_len, periods); 1458 1459 cdesc->periods = periods; 1460 dwc->cdesc = cdesc; 1461 1462 return cdesc; 1463 1464 out_err_desc_get: 1465 while (i--) 1466 dwc_desc_put(dwc, cdesc->desc[i]); 1467 out_err_alloc: 1468 kfree(cdesc); 1469 out_err: 1470 clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); 1471 return (struct dw_cyclic_desc *)retval; 1472 } 1473 EXPORT_SYMBOL(dw_dma_cyclic_prep); 1474 1475 /** 1476 * dw_dma_cyclic_free - free a prepared cyclic DMA transfer 1477 * @chan: the DMA channel to free 1478 */ 1479 void dw_dma_cyclic_free(struct dma_chan *chan) 1480 { 1481 struct dw_dma_chan *dwc = to_dw_dma_chan(chan); 1482 struct dw_dma *dw = to_dw_dma(dwc->chan.device); 1483 struct dw_cyclic_desc *cdesc = dwc->cdesc; 1484 unsigned int i; 1485 unsigned long flags; 1486 1487 dev_dbg(chan2dev(&dwc->chan), "%s\n", __func__); 1488 1489 if (!cdesc) 1490 return; 1491 1492 spin_lock_irqsave(&dwc->lock, flags); 1493 1494 dwc_chan_disable(dw, dwc); 1495 1496 dma_writel(dw, CLEAR.BLOCK, dwc->mask); 1497 dma_writel(dw, CLEAR.ERROR, dwc->mask); 1498 dma_writel(dw, CLEAR.XFER, dwc->mask); 1499 1500 spin_unlock_irqrestore(&dwc->lock, flags); 1501 1502 for (i = 0; i < cdesc->periods; i++) 1503 dwc_desc_put(dwc, cdesc->desc[i]); 1504 1505 kfree(cdesc->desc); 1506 kfree(cdesc); 1507 1508 dwc->cdesc = NULL; 1509 1510 clear_bit(DW_DMA_IS_CYCLIC, &dwc->flags); 1511 } 1512 EXPORT_SYMBOL(dw_dma_cyclic_free); 1513 1514 /*----------------------------------------------------------------------*/ 1515 1516 int dw_dma_probe(struct dw_dma_chip *chip) 1517 { 1518 struct dw_dma_platform_data *pdata; 1519 struct dw_dma *dw; 1520 bool autocfg = false; 1521 unsigned int dw_params; 1522 unsigned int i; 1523 int err; 1524 1525 dw = devm_kzalloc(chip->dev, sizeof(*dw), GFP_KERNEL); 1526 if (!dw) 1527 return -ENOMEM; 1528 1529 dw->pdata = devm_kzalloc(chip->dev, sizeof(*dw->pdata), GFP_KERNEL); 1530 if (!dw->pdata) 1531 return -ENOMEM; 1532 1533 dw->regs = chip->regs; 1534 chip->dw = dw; 1535 1536 pm_runtime_get_sync(chip->dev); 1537 1538 if (!chip->pdata) { 1539 dw_params = dma_readl(dw, DW_PARAMS); 1540 dev_dbg(chip->dev, "DW_PARAMS: 0x%08x\n", dw_params); 1541 1542 autocfg = dw_params >> DW_PARAMS_EN & 1; 1543 if (!autocfg) { 1544 err = -EINVAL; 1545 goto err_pdata; 1546 } 1547 1548 /* Reassign the platform data pointer */ 1549 pdata = dw->pdata; 1550 1551 /* Get hardware configuration parameters */ 1552 pdata->nr_channels = (dw_params >> DW_PARAMS_NR_CHAN & 7) + 1; 1553 pdata->nr_masters = (dw_params >> DW_PARAMS_NR_MASTER & 3) + 1; 1554 for (i = 0; i < pdata->nr_masters; i++) { 1555 pdata->data_width[i] = 1556 4 << (dw_params >> DW_PARAMS_DATA_WIDTH(i) & 3); 1557 } 1558 pdata->block_size = dma_readl(dw, MAX_BLK_SIZE); 1559 1560 /* Fill platform data with the default values */ 1561 pdata->is_private = true; 1562 pdata->is_memcpy = true; 1563 pdata->chan_allocation_order = CHAN_ALLOCATION_ASCENDING; 1564 pdata->chan_priority = CHAN_PRIORITY_ASCENDING; 1565 } else if (chip->pdata->nr_channels > DW_DMA_MAX_NR_CHANNELS) { 1566 err = -EINVAL; 1567 goto err_pdata; 1568 } else { 1569 memcpy(dw->pdata, chip->pdata, sizeof(*dw->pdata)); 1570 1571 /* Reassign the platform data pointer */ 1572 pdata = dw->pdata; 1573 } 1574 1575 dw->chan = devm_kcalloc(chip->dev, pdata->nr_channels, sizeof(*dw->chan), 1576 GFP_KERNEL); 1577 if (!dw->chan) { 1578 err = -ENOMEM; 1579 goto err_pdata; 1580 } 1581 1582 /* Calculate all channel mask before DMA setup */ 1583 dw->all_chan_mask = (1 << pdata->nr_channels) - 1; 1584 1585 /* Force dma off, just in case */ 1586 dw_dma_off(dw); 1587 1588 idma32_fifo_partition(dw); 1589 1590 /* Device and instance ID for IRQ and DMA pool */ 1591 if (pdata->is_idma32) 1592 snprintf(dw->name, sizeof(dw->name), "idma32:dmac%d", chip->id); 1593 else 1594 snprintf(dw->name, sizeof(dw->name), "dw:dmac%d", chip->id); 1595 1596 /* Create a pool of consistent memory blocks for hardware descriptors */ 1597 dw->desc_pool = dmam_pool_create(dw->name, chip->dev, 1598 sizeof(struct dw_desc), 4, 0); 1599 if (!dw->desc_pool) { 1600 dev_err(chip->dev, "No memory for descriptors dma pool\n"); 1601 err = -ENOMEM; 1602 goto err_pdata; 1603 } 1604 1605 tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw); 1606 1607 err = request_irq(chip->irq, dw_dma_interrupt, IRQF_SHARED, 1608 dw->name, dw); 1609 if (err) 1610 goto err_pdata; 1611 1612 INIT_LIST_HEAD(&dw->dma.channels); 1613 for (i = 0; i < pdata->nr_channels; i++) { 1614 struct dw_dma_chan *dwc = &dw->chan[i]; 1615 1616 dwc->chan.device = &dw->dma; 1617 dma_cookie_init(&dwc->chan); 1618 if (pdata->chan_allocation_order == CHAN_ALLOCATION_ASCENDING) 1619 list_add_tail(&dwc->chan.device_node, 1620 &dw->dma.channels); 1621 else 1622 list_add(&dwc->chan.device_node, &dw->dma.channels); 1623 1624 /* 7 is highest priority & 0 is lowest. */ 1625 if (pdata->chan_priority == CHAN_PRIORITY_ASCENDING) 1626 dwc->priority = pdata->nr_channels - i - 1; 1627 else 1628 dwc->priority = i; 1629 1630 dwc->ch_regs = &__dw_regs(dw)->CHAN[i]; 1631 spin_lock_init(&dwc->lock); 1632 dwc->mask = 1 << i; 1633 1634 INIT_LIST_HEAD(&dwc->active_list); 1635 INIT_LIST_HEAD(&dwc->queue); 1636 1637 channel_clear_bit(dw, CH_EN, dwc->mask); 1638 1639 dwc->direction = DMA_TRANS_NONE; 1640 1641 /* Hardware configuration */ 1642 if (autocfg) { 1643 unsigned int r = DW_DMA_MAX_NR_CHANNELS - i - 1; 1644 void __iomem *addr = &__dw_regs(dw)->DWC_PARAMS[r]; 1645 unsigned int dwc_params = dma_readl_native(addr); 1646 1647 dev_dbg(chip->dev, "DWC_PARAMS[%d]: 0x%08x\n", i, 1648 dwc_params); 1649 1650 /* 1651 * Decode maximum block size for given channel. The 1652 * stored 4 bit value represents blocks from 0x00 for 3 1653 * up to 0x0a for 4095. 1654 */ 1655 dwc->block_size = 1656 (4 << ((pdata->block_size >> 4 * i) & 0xf)) - 1; 1657 dwc->nollp = 1658 (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0; 1659 } else { 1660 dwc->block_size = pdata->block_size; 1661 dwc->nollp = !pdata->multi_block[i]; 1662 } 1663 } 1664 1665 /* Clear all interrupts on all channels. */ 1666 dma_writel(dw, CLEAR.XFER, dw->all_chan_mask); 1667 dma_writel(dw, CLEAR.BLOCK, dw->all_chan_mask); 1668 dma_writel(dw, CLEAR.SRC_TRAN, dw->all_chan_mask); 1669 dma_writel(dw, CLEAR.DST_TRAN, dw->all_chan_mask); 1670 dma_writel(dw, CLEAR.ERROR, dw->all_chan_mask); 1671 1672 /* Set capabilities */ 1673 dma_cap_set(DMA_SLAVE, dw->dma.cap_mask); 1674 if (pdata->is_private) 1675 dma_cap_set(DMA_PRIVATE, dw->dma.cap_mask); 1676 if (pdata->is_memcpy) 1677 dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask); 1678 1679 dw->dma.dev = chip->dev; 1680 dw->dma.device_alloc_chan_resources = dwc_alloc_chan_resources; 1681 dw->dma.device_free_chan_resources = dwc_free_chan_resources; 1682 1683 dw->dma.device_prep_dma_memcpy = dwc_prep_dma_memcpy; 1684 dw->dma.device_prep_slave_sg = dwc_prep_slave_sg; 1685 1686 dw->dma.device_config = dwc_config; 1687 dw->dma.device_pause = dwc_pause; 1688 dw->dma.device_resume = dwc_resume; 1689 dw->dma.device_terminate_all = dwc_terminate_all; 1690 1691 dw->dma.device_tx_status = dwc_tx_status; 1692 dw->dma.device_issue_pending = dwc_issue_pending; 1693 1694 /* DMA capabilities */ 1695 dw->dma.src_addr_widths = DW_DMA_BUSWIDTHS; 1696 dw->dma.dst_addr_widths = DW_DMA_BUSWIDTHS; 1697 dw->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) | 1698 BIT(DMA_MEM_TO_MEM); 1699 dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; 1700 1701 err = dma_async_device_register(&dw->dma); 1702 if (err) 1703 goto err_dma_register; 1704 1705 dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n", 1706 pdata->nr_channels); 1707 1708 pm_runtime_put_sync_suspend(chip->dev); 1709 1710 return 0; 1711 1712 err_dma_register: 1713 free_irq(chip->irq, dw); 1714 err_pdata: 1715 pm_runtime_put_sync_suspend(chip->dev); 1716 return err; 1717 } 1718 EXPORT_SYMBOL_GPL(dw_dma_probe); 1719 1720 int dw_dma_remove(struct dw_dma_chip *chip) 1721 { 1722 struct dw_dma *dw = chip->dw; 1723 struct dw_dma_chan *dwc, *_dwc; 1724 1725 pm_runtime_get_sync(chip->dev); 1726 1727 dw_dma_off(dw); 1728 dma_async_device_unregister(&dw->dma); 1729 1730 free_irq(chip->irq, dw); 1731 tasklet_kill(&dw->tasklet); 1732 1733 list_for_each_entry_safe(dwc, _dwc, &dw->dma.channels, 1734 chan.device_node) { 1735 list_del(&dwc->chan.device_node); 1736 channel_clear_bit(dw, CH_EN, dwc->mask); 1737 } 1738 1739 pm_runtime_put_sync_suspend(chip->dev); 1740 return 0; 1741 } 1742 EXPORT_SYMBOL_GPL(dw_dma_remove); 1743 1744 int dw_dma_disable(struct dw_dma_chip *chip) 1745 { 1746 struct dw_dma *dw = chip->dw; 1747 1748 dw_dma_off(dw); 1749 return 0; 1750 } 1751 EXPORT_SYMBOL_GPL(dw_dma_disable); 1752 1753 int dw_dma_enable(struct dw_dma_chip *chip) 1754 { 1755 struct dw_dma *dw = chip->dw; 1756 1757 idma32_fifo_partition(dw); 1758 1759 dw_dma_on(dw); 1760 return 0; 1761 } 1762 EXPORT_SYMBOL_GPL(dw_dma_enable); 1763 1764 MODULE_LICENSE("GPL v2"); 1765 MODULE_DESCRIPTION("Synopsys DesignWare DMA Controller core driver"); 1766 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); 1767 MODULE_AUTHOR("Viresh Kumar <vireshk@kernel.org>"); 1768