1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates. 4 * Synopsys DesignWare eDMA PCIe driver 5 * 6 * Author: Gustavo Pimentel <gustavo.pimentel@synopsys.com> 7 */ 8 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/device.h> 13 #include <linux/dma/edma.h> 14 #include <linux/pci-epf.h> 15 #include <linux/msi.h> 16 #include <linux/bitfield.h> 17 18 #include "dw-edma-core.h" 19 20 #define DW_PCIE_VSEC_DMA_ID 0x6 21 #define DW_PCIE_VSEC_DMA_BAR GENMASK(10, 8) 22 #define DW_PCIE_VSEC_DMA_MAP GENMASK(2, 0) 23 #define DW_PCIE_VSEC_DMA_WR_CH GENMASK(9, 0) 24 #define DW_PCIE_VSEC_DMA_RD_CH GENMASK(25, 16) 25 26 #define DW_BLOCK(a, b, c) \ 27 { \ 28 .bar = a, \ 29 .off = b, \ 30 .sz = c, \ 31 }, 32 33 struct dw_edma_block { 34 enum pci_barno bar; 35 off_t off; 36 size_t sz; 37 }; 38 39 struct dw_edma_pcie_data { 40 /* eDMA registers location */ 41 struct dw_edma_block rg; 42 /* eDMA memory linked list location */ 43 struct dw_edma_block ll_wr[EDMA_MAX_WR_CH]; 44 struct dw_edma_block ll_rd[EDMA_MAX_RD_CH]; 45 /* eDMA memory data location */ 46 struct dw_edma_block dt_wr[EDMA_MAX_WR_CH]; 47 struct dw_edma_block dt_rd[EDMA_MAX_RD_CH]; 48 /* Other */ 49 enum dw_edma_map_format mf; 50 u8 irqs; 51 u16 wr_ch_cnt; 52 u16 rd_ch_cnt; 53 }; 54 55 static const struct dw_edma_pcie_data snps_edda_data = { 56 /* eDMA registers location */ 57 .rg.bar = BAR_0, 58 .rg.off = 0x00001000, /* 4 Kbytes */ 59 .rg.sz = 0x00002000, /* 8 Kbytes */ 60 /* eDMA memory linked list location */ 61 .ll_wr = { 62 /* Channel 0 - BAR 2, offset 0 Mbytes, size 2 Kbytes */ 63 DW_BLOCK(BAR_2, 0x00000000, 0x00000800) 64 /* Channel 1 - BAR 2, offset 2 Mbytes, size 2 Kbytes */ 65 DW_BLOCK(BAR_2, 0x00200000, 0x00000800) 66 }, 67 .ll_rd = { 68 /* Channel 0 - BAR 2, offset 4 Mbytes, size 2 Kbytes */ 69 DW_BLOCK(BAR_2, 0x00400000, 0x00000800) 70 /* Channel 1 - BAR 2, offset 6 Mbytes, size 2 Kbytes */ 71 DW_BLOCK(BAR_2, 0x00600000, 0x00000800) 72 }, 73 /* eDMA memory data location */ 74 .dt_wr = { 75 /* Channel 0 - BAR 2, offset 8 Mbytes, size 2 Kbytes */ 76 DW_BLOCK(BAR_2, 0x00800000, 0x00000800) 77 /* Channel 1 - BAR 2, offset 9 Mbytes, size 2 Kbytes */ 78 DW_BLOCK(BAR_2, 0x00900000, 0x00000800) 79 }, 80 .dt_rd = { 81 /* Channel 0 - BAR 2, offset 10 Mbytes, size 2 Kbytes */ 82 DW_BLOCK(BAR_2, 0x00a00000, 0x00000800) 83 /* Channel 1 - BAR 2, offset 11 Mbytes, size 2 Kbytes */ 84 DW_BLOCK(BAR_2, 0x00b00000, 0x00000800) 85 }, 86 /* Other */ 87 .mf = EDMA_MF_EDMA_UNROLL, 88 .irqs = 1, 89 .wr_ch_cnt = 2, 90 .rd_ch_cnt = 2, 91 }; 92 93 static int dw_edma_pcie_irq_vector(struct device *dev, unsigned int nr) 94 { 95 return pci_irq_vector(to_pci_dev(dev), nr); 96 } 97 98 static const struct dw_edma_core_ops dw_edma_pcie_core_ops = { 99 .irq_vector = dw_edma_pcie_irq_vector, 100 }; 101 102 static void dw_edma_pcie_get_vsec_dma_data(struct pci_dev *pdev, 103 struct dw_edma_pcie_data *pdata) 104 { 105 u32 val, map; 106 u16 vsec; 107 u64 off; 108 109 vsec = pci_find_vsec_capability(pdev, PCI_VENDOR_ID_SYNOPSYS, 110 DW_PCIE_VSEC_DMA_ID); 111 if (!vsec) 112 return; 113 114 pci_read_config_dword(pdev, vsec + PCI_VNDR_HEADER, &val); 115 if (PCI_VNDR_HEADER_REV(val) != 0x00 || 116 PCI_VNDR_HEADER_LEN(val) != 0x18) 117 return; 118 119 pci_dbg(pdev, "Detected PCIe Vendor-Specific Extended Capability DMA\n"); 120 pci_read_config_dword(pdev, vsec + 0x8, &val); 121 map = FIELD_GET(DW_PCIE_VSEC_DMA_MAP, val); 122 if (map != EDMA_MF_EDMA_LEGACY && 123 map != EDMA_MF_EDMA_UNROLL && 124 map != EDMA_MF_HDMA_COMPAT) 125 return; 126 127 pdata->mf = map; 128 pdata->rg.bar = FIELD_GET(DW_PCIE_VSEC_DMA_BAR, val); 129 130 pci_read_config_dword(pdev, vsec + 0xc, &val); 131 pdata->wr_ch_cnt = min_t(u16, pdata->wr_ch_cnt, 132 FIELD_GET(DW_PCIE_VSEC_DMA_WR_CH, val)); 133 pdata->rd_ch_cnt = min_t(u16, pdata->rd_ch_cnt, 134 FIELD_GET(DW_PCIE_VSEC_DMA_RD_CH, val)); 135 136 pci_read_config_dword(pdev, vsec + 0x14, &val); 137 off = val; 138 pci_read_config_dword(pdev, vsec + 0x10, &val); 139 off <<= 32; 140 off |= val; 141 pdata->rg.off = off; 142 } 143 144 static int dw_edma_pcie_probe(struct pci_dev *pdev, 145 const struct pci_device_id *pid) 146 { 147 struct dw_edma_pcie_data *pdata = (void *)pid->driver_data; 148 struct dw_edma_pcie_data vsec_data; 149 struct device *dev = &pdev->dev; 150 struct dw_edma_chip *chip; 151 int err, nr_irqs; 152 int i, mask; 153 154 /* Enable PCI device */ 155 err = pcim_enable_device(pdev); 156 if (err) { 157 pci_err(pdev, "enabling device failed\n"); 158 return err; 159 } 160 161 memcpy(&vsec_data, pdata, sizeof(struct dw_edma_pcie_data)); 162 163 /* 164 * Tries to find if exists a PCIe Vendor-Specific Extended Capability 165 * for the DMA, if one exists, then reconfigures it. 166 */ 167 dw_edma_pcie_get_vsec_dma_data(pdev, &vsec_data); 168 169 /* Mapping PCI BAR regions */ 170 mask = BIT(vsec_data.rg.bar); 171 for (i = 0; i < vsec_data.wr_ch_cnt; i++) { 172 mask |= BIT(vsec_data.ll_wr[i].bar); 173 mask |= BIT(vsec_data.dt_wr[i].bar); 174 } 175 for (i = 0; i < vsec_data.rd_ch_cnt; i++) { 176 mask |= BIT(vsec_data.ll_rd[i].bar); 177 mask |= BIT(vsec_data.dt_rd[i].bar); 178 } 179 err = pcim_iomap_regions(pdev, mask, pci_name(pdev)); 180 if (err) { 181 pci_err(pdev, "eDMA BAR I/O remapping failed\n"); 182 return err; 183 } 184 185 pci_set_master(pdev); 186 187 /* DMA configuration */ 188 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 189 if (err) { 190 pci_err(pdev, "DMA mask 64 set failed\n"); 191 return err; 192 } 193 194 /* Data structure allocation */ 195 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 196 if (!chip) 197 return -ENOMEM; 198 199 /* IRQs allocation */ 200 nr_irqs = pci_alloc_irq_vectors(pdev, 1, vsec_data.irqs, 201 PCI_IRQ_MSI | PCI_IRQ_MSIX); 202 if (nr_irqs < 1) { 203 pci_err(pdev, "fail to alloc IRQ vector (number of IRQs=%u)\n", 204 nr_irqs); 205 return -EPERM; 206 } 207 208 /* Data structure initialization */ 209 chip->dev = dev; 210 chip->id = pdev->devfn; 211 212 chip->mf = vsec_data.mf; 213 chip->nr_irqs = nr_irqs; 214 chip->ops = &dw_edma_pcie_core_ops; 215 216 chip->ll_wr_cnt = vsec_data.wr_ch_cnt; 217 chip->ll_rd_cnt = vsec_data.rd_ch_cnt; 218 219 chip->reg_base = pcim_iomap_table(pdev)[vsec_data.rg.bar]; 220 if (!chip->reg_base) 221 return -ENOMEM; 222 223 for (i = 0; i < chip->ll_wr_cnt; i++) { 224 struct dw_edma_region *ll_region = &chip->ll_region_wr[i]; 225 struct dw_edma_region *dt_region = &chip->dt_region_wr[i]; 226 struct dw_edma_block *ll_block = &vsec_data.ll_wr[i]; 227 struct dw_edma_block *dt_block = &vsec_data.dt_wr[i]; 228 229 ll_region->vaddr = pcim_iomap_table(pdev)[ll_block->bar]; 230 if (!ll_region->vaddr) 231 return -ENOMEM; 232 233 ll_region->vaddr += ll_block->off; 234 ll_region->paddr = pdev->resource[ll_block->bar].start; 235 ll_region->paddr += ll_block->off; 236 ll_region->sz = ll_block->sz; 237 238 dt_region->vaddr = pcim_iomap_table(pdev)[dt_block->bar]; 239 if (!dt_region->vaddr) 240 return -ENOMEM; 241 242 dt_region->vaddr += dt_block->off; 243 dt_region->paddr = pdev->resource[dt_block->bar].start; 244 dt_region->paddr += dt_block->off; 245 dt_region->sz = dt_block->sz; 246 } 247 248 for (i = 0; i < chip->ll_rd_cnt; i++) { 249 struct dw_edma_region *ll_region = &chip->ll_region_rd[i]; 250 struct dw_edma_region *dt_region = &chip->dt_region_rd[i]; 251 struct dw_edma_block *ll_block = &vsec_data.ll_rd[i]; 252 struct dw_edma_block *dt_block = &vsec_data.dt_rd[i]; 253 254 ll_region->vaddr = pcim_iomap_table(pdev)[ll_block->bar]; 255 if (!ll_region->vaddr) 256 return -ENOMEM; 257 258 ll_region->vaddr += ll_block->off; 259 ll_region->paddr = pdev->resource[ll_block->bar].start; 260 ll_region->paddr += ll_block->off; 261 ll_region->sz = ll_block->sz; 262 263 dt_region->vaddr = pcim_iomap_table(pdev)[dt_block->bar]; 264 if (!dt_region->vaddr) 265 return -ENOMEM; 266 267 dt_region->vaddr += dt_block->off; 268 dt_region->paddr = pdev->resource[dt_block->bar].start; 269 dt_region->paddr += dt_block->off; 270 dt_region->sz = dt_block->sz; 271 } 272 273 /* Debug info */ 274 if (chip->mf == EDMA_MF_EDMA_LEGACY) 275 pci_dbg(pdev, "Version:\teDMA Port Logic (0x%x)\n", chip->mf); 276 else if (chip->mf == EDMA_MF_EDMA_UNROLL) 277 pci_dbg(pdev, "Version:\teDMA Unroll (0x%x)\n", chip->mf); 278 else if (chip->mf == EDMA_MF_HDMA_COMPAT) 279 pci_dbg(pdev, "Version:\tHDMA Compatible (0x%x)\n", chip->mf); 280 else 281 pci_dbg(pdev, "Version:\tUnknown (0x%x)\n", chip->mf); 282 283 pci_dbg(pdev, "Registers:\tBAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%p)\n", 284 vsec_data.rg.bar, vsec_data.rg.off, vsec_data.rg.sz, 285 chip->reg_base); 286 287 288 for (i = 0; i < chip->ll_wr_cnt; i++) { 289 pci_dbg(pdev, "L. List:\tWRITE CH%.2u, BAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%p, p=%pa)\n", 290 i, vsec_data.ll_wr[i].bar, 291 vsec_data.ll_wr[i].off, chip->ll_region_wr[i].sz, 292 chip->ll_region_wr[i].vaddr, &chip->ll_region_wr[i].paddr); 293 294 pci_dbg(pdev, "Data:\tWRITE CH%.2u, BAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%p, p=%pa)\n", 295 i, vsec_data.dt_wr[i].bar, 296 vsec_data.dt_wr[i].off, chip->dt_region_wr[i].sz, 297 chip->dt_region_wr[i].vaddr, &chip->dt_region_wr[i].paddr); 298 } 299 300 for (i = 0; i < chip->ll_rd_cnt; i++) { 301 pci_dbg(pdev, "L. List:\tREAD CH%.2u, BAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%p, p=%pa)\n", 302 i, vsec_data.ll_rd[i].bar, 303 vsec_data.ll_rd[i].off, chip->ll_region_rd[i].sz, 304 chip->ll_region_rd[i].vaddr, &chip->ll_region_rd[i].paddr); 305 306 pci_dbg(pdev, "Data:\tREAD CH%.2u, BAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%p, p=%pa)\n", 307 i, vsec_data.dt_rd[i].bar, 308 vsec_data.dt_rd[i].off, chip->dt_region_rd[i].sz, 309 chip->dt_region_rd[i].vaddr, &chip->dt_region_rd[i].paddr); 310 } 311 312 pci_dbg(pdev, "Nr. IRQs:\t%u\n", chip->nr_irqs); 313 314 /* Validating if PCI interrupts were enabled */ 315 if (!pci_dev_msi_enabled(pdev)) { 316 pci_err(pdev, "enable interrupt failed\n"); 317 return -EPERM; 318 } 319 320 /* Starting eDMA driver */ 321 err = dw_edma_probe(chip); 322 if (err) { 323 pci_err(pdev, "eDMA probe failed\n"); 324 return err; 325 } 326 327 /* Saving data structure reference */ 328 pci_set_drvdata(pdev, chip); 329 330 return 0; 331 } 332 333 static void dw_edma_pcie_remove(struct pci_dev *pdev) 334 { 335 struct dw_edma_chip *chip = pci_get_drvdata(pdev); 336 int err; 337 338 /* Stopping eDMA driver */ 339 err = dw_edma_remove(chip); 340 if (err) 341 pci_warn(pdev, "can't remove device properly: %d\n", err); 342 343 /* Freeing IRQs */ 344 pci_free_irq_vectors(pdev); 345 } 346 347 static const struct pci_device_id dw_edma_pcie_id_table[] = { 348 { PCI_DEVICE_DATA(SYNOPSYS, EDDA, &snps_edda_data) }, 349 { } 350 }; 351 MODULE_DEVICE_TABLE(pci, dw_edma_pcie_id_table); 352 353 static struct pci_driver dw_edma_pcie_driver = { 354 .name = "dw-edma-pcie", 355 .id_table = dw_edma_pcie_id_table, 356 .probe = dw_edma_pcie_probe, 357 .remove = dw_edma_pcie_remove, 358 }; 359 360 module_pci_driver(dw_edma_pcie_driver); 361 362 MODULE_LICENSE("GPL v2"); 363 MODULE_DESCRIPTION("Synopsys DesignWare eDMA PCIe driver"); 364 MODULE_AUTHOR("Gustavo Pimentel <gustavo.pimentel@synopsys.com>"); 365