1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates. 4 * Synopsys DesignWare eDMA core driver 5 * 6 * Author: Gustavo Pimentel <gustavo.pimentel@synopsys.com> 7 */ 8 9 #ifndef _DW_EDMA_CORE_H 10 #define _DW_EDMA_CORE_H 11 12 #include <linux/msi.h> 13 #include <linux/dma/edma.h> 14 15 #include "../virt-dma.h" 16 17 #define EDMA_LL_SZ 24 18 #define EDMA_MAX_WR_CH 8 19 #define EDMA_MAX_RD_CH 8 20 21 enum dw_edma_dir { 22 EDMA_DIR_WRITE = 0, 23 EDMA_DIR_READ 24 }; 25 26 enum dw_edma_map_format { 27 EDMA_MF_EDMA_LEGACY = 0x0, 28 EDMA_MF_EDMA_UNROLL = 0x1, 29 EDMA_MF_HDMA_COMPAT = 0x5 30 }; 31 32 enum dw_edma_request { 33 EDMA_REQ_NONE = 0, 34 EDMA_REQ_STOP, 35 EDMA_REQ_PAUSE 36 }; 37 38 enum dw_edma_status { 39 EDMA_ST_IDLE = 0, 40 EDMA_ST_PAUSE, 41 EDMA_ST_BUSY 42 }; 43 44 enum dw_edma_xfer_type { 45 EDMA_XFER_SCATTER_GATHER = 0, 46 EDMA_XFER_CYCLIC, 47 EDMA_XFER_INTERLEAVED 48 }; 49 50 struct dw_edma_chan; 51 struct dw_edma_chunk; 52 53 struct dw_edma_burst { 54 struct list_head list; 55 u64 sar; 56 u64 dar; 57 u32 sz; 58 }; 59 60 struct dw_edma_region { 61 phys_addr_t paddr; 62 void __iomem *vaddr; 63 size_t sz; 64 }; 65 66 struct dw_edma_chunk { 67 struct list_head list; 68 struct dw_edma_chan *chan; 69 struct dw_edma_burst *burst; 70 71 u32 bursts_alloc; 72 73 u8 cb; 74 struct dw_edma_region ll_region; /* Linked list */ 75 }; 76 77 struct dw_edma_desc { 78 struct virt_dma_desc vd; 79 struct dw_edma_chan *chan; 80 struct dw_edma_chunk *chunk; 81 82 u32 chunks_alloc; 83 84 u32 alloc_sz; 85 u32 xfer_sz; 86 }; 87 88 struct dw_edma_chan { 89 struct virt_dma_chan vc; 90 struct dw_edma_chip *chip; 91 int id; 92 enum dw_edma_dir dir; 93 94 u32 ll_max; 95 96 struct msi_msg msi; 97 98 enum dw_edma_request request; 99 enum dw_edma_status status; 100 u8 configured; 101 102 struct dma_slave_config config; 103 }; 104 105 struct dw_edma_irq { 106 struct msi_msg msi; 107 u32 wr_mask; 108 u32 rd_mask; 109 struct dw_edma *dw; 110 }; 111 112 struct dw_edma_core_ops { 113 int (*irq_vector)(struct device *dev, unsigned int nr); 114 }; 115 116 struct dw_edma { 117 char name[20]; 118 119 struct dma_device wr_edma; 120 u16 wr_ch_cnt; 121 122 struct dma_device rd_edma; 123 u16 rd_ch_cnt; 124 125 struct dw_edma_region rg_region; /* Registers */ 126 struct dw_edma_region ll_region_wr[EDMA_MAX_WR_CH]; 127 struct dw_edma_region ll_region_rd[EDMA_MAX_RD_CH]; 128 struct dw_edma_region dt_region_wr[EDMA_MAX_WR_CH]; 129 struct dw_edma_region dt_region_rd[EDMA_MAX_RD_CH]; 130 131 struct dw_edma_irq *irq; 132 int nr_irqs; 133 134 enum dw_edma_map_format mf; 135 136 struct dw_edma_chan *chan; 137 const struct dw_edma_core_ops *ops; 138 139 raw_spinlock_t lock; /* Only for legacy */ 140 #ifdef CONFIG_DEBUG_FS 141 struct dentry *debugfs; 142 #endif /* CONFIG_DEBUG_FS */ 143 }; 144 145 struct dw_edma_sg { 146 struct scatterlist *sgl; 147 unsigned int len; 148 }; 149 150 struct dw_edma_cyclic { 151 dma_addr_t paddr; 152 size_t len; 153 size_t cnt; 154 }; 155 156 struct dw_edma_transfer { 157 struct dma_chan *dchan; 158 union dw_edma_xfer { 159 struct dw_edma_sg sg; 160 struct dw_edma_cyclic cyclic; 161 struct dma_interleaved_template *il; 162 } xfer; 163 enum dma_transfer_direction direction; 164 unsigned long flags; 165 enum dw_edma_xfer_type type; 166 }; 167 168 static inline 169 struct dw_edma_chan *vc2dw_edma_chan(struct virt_dma_chan *vc) 170 { 171 return container_of(vc, struct dw_edma_chan, vc); 172 } 173 174 static inline 175 struct dw_edma_chan *dchan2dw_edma_chan(struct dma_chan *dchan) 176 { 177 return vc2dw_edma_chan(to_virt_chan(dchan)); 178 } 179 180 #endif /* _DW_EDMA_CORE_H */ 181