1 /* SPDX-License-Identifier: GPL-2.0 */
2 // (C) 2017-2018 Synopsys, Inc. (www.synopsys.com)
3 
4 /*
5  * Synopsys DesignWare AXI DMA Controller driver.
6  *
7  * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
8  */
9 
10 #ifndef _AXI_DMA_PLATFORM_H
11 #define _AXI_DMA_PLATFORM_H
12 
13 #include <linux/bitops.h>
14 #include <linux/clk.h>
15 #include <linux/device.h>
16 #include <linux/dmaengine.h>
17 #include <linux/types.h>
18 
19 #include "../virt-dma.h"
20 
21 #define DMAC_MAX_CHANNELS	16
22 #define DMAC_MAX_MASTERS	2
23 #define DMAC_MAX_BLK_SIZE	0x200000
24 
25 struct dw_axi_dma_hcfg {
26 	u32	nr_channels;
27 	u32	nr_masters;
28 	u32	m_data_width;
29 	u32	block_size[DMAC_MAX_CHANNELS];
30 	u32	priority[DMAC_MAX_CHANNELS];
31 	/* maximum supported axi burst length */
32 	u32	axi_rw_burst_len;
33 	/* Register map for DMAX_NUM_CHANNELS <= 8 */
34 	bool	reg_map_8_channels;
35 	bool	restrict_axi_burst_len;
36 };
37 
38 struct axi_dma_chan {
39 	struct axi_dma_chip		*chip;
40 	void __iomem			*chan_regs;
41 	u8				id;
42 	u8				hw_handshake_num;
43 	atomic_t			descs_allocated;
44 
45 	struct dma_pool			*desc_pool;
46 	struct virt_dma_chan		vc;
47 
48 	struct axi_dma_desc		*desc;
49 	struct dma_slave_config		config;
50 	enum dma_transfer_direction	direction;
51 	bool				cyclic;
52 	/* these other elements are all protected by vc.lock */
53 	bool				is_paused;
54 };
55 
56 struct dw_axi_dma {
57 	struct dma_device	dma;
58 	struct dw_axi_dma_hcfg	*hdata;
59 	struct device_dma_parameters	dma_parms;
60 
61 	/* channels */
62 	struct axi_dma_chan	*chan;
63 };
64 
65 struct axi_dma_chip {
66 	struct device		*dev;
67 	int			irq;
68 	void __iomem		*regs;
69 	void __iomem		*apb_regs;
70 	struct clk		*core_clk;
71 	struct clk		*cfgr_clk;
72 	struct dw_axi_dma	*dw;
73 };
74 
75 /* LLI == Linked List Item */
76 struct __packed axi_dma_lli {
77 	__le64		sar;
78 	__le64		dar;
79 	__le32		block_ts_lo;
80 	__le32		block_ts_hi;
81 	__le64		llp;
82 	__le32		ctl_lo;
83 	__le32		ctl_hi;
84 	__le32		sstat;
85 	__le32		dstat;
86 	__le32		status_lo;
87 	__le32		status_hi;
88 	__le32		reserved_lo;
89 	__le32		reserved_hi;
90 };
91 
92 struct axi_dma_hw_desc {
93 	struct axi_dma_lli	*lli;
94 	dma_addr_t		llp;
95 	u32			len;
96 };
97 
98 struct axi_dma_desc {
99 	struct axi_dma_hw_desc	*hw_desc;
100 
101 	struct virt_dma_desc		vd;
102 	struct axi_dma_chan		*chan;
103 	u32				completed_blocks;
104 	u32				length;
105 	u32				period_len;
106 };
107 
108 struct axi_dma_chan_config {
109 	u8 dst_multblk_type;
110 	u8 src_multblk_type;
111 	u8 dst_per;
112 	u8 src_per;
113 	u8 tt_fc;
114 	u8 prior;
115 	u8 hs_sel_dst;
116 	u8 hs_sel_src;
117 };
118 
119 static inline struct device *dchan2dev(struct dma_chan *dchan)
120 {
121 	return &dchan->dev->device;
122 }
123 
124 static inline struct device *chan2dev(struct axi_dma_chan *chan)
125 {
126 	return &chan->vc.chan.dev->device;
127 }
128 
129 static inline struct axi_dma_desc *vd_to_axi_desc(struct virt_dma_desc *vd)
130 {
131 	return container_of(vd, struct axi_dma_desc, vd);
132 }
133 
134 static inline struct axi_dma_chan *vc_to_axi_dma_chan(struct virt_dma_chan *vc)
135 {
136 	return container_of(vc, struct axi_dma_chan, vc);
137 }
138 
139 static inline struct axi_dma_chan *dchan_to_axi_dma_chan(struct dma_chan *dchan)
140 {
141 	return vc_to_axi_dma_chan(to_virt_chan(dchan));
142 }
143 
144 
145 #define COMMON_REG_LEN		0x100
146 #define CHAN_REG_LEN		0x100
147 
148 /* Common registers offset */
149 #define DMAC_ID			0x000 /* R DMAC ID */
150 #define DMAC_COMPVER		0x008 /* R DMAC Component Version */
151 #define DMAC_CFG		0x010 /* R/W DMAC Configuration */
152 #define DMAC_CHEN		0x018 /* R/W DMAC Channel Enable */
153 #define DMAC_CHEN_L		0x018 /* R/W DMAC Channel Enable 00-31 */
154 #define DMAC_CHEN_H		0x01C /* R/W DMAC Channel Enable 32-63 */
155 #define DMAC_CHSUSPREG		0x020 /* R/W DMAC Channel Suspend */
156 #define DMAC_CHABORTREG		0x028 /* R/W DMAC Channel Abort */
157 #define DMAC_INTSTATUS		0x030 /* R DMAC Interrupt Status */
158 #define DMAC_COMMON_INTCLEAR	0x038 /* W DMAC Interrupt Clear */
159 #define DMAC_COMMON_INTSTATUS_ENA 0x040 /* R DMAC Interrupt Status Enable */
160 #define DMAC_COMMON_INTSIGNAL_ENA 0x048 /* R/W DMAC Interrupt Signal Enable */
161 #define DMAC_COMMON_INTSTATUS	0x050 /* R DMAC Interrupt Status */
162 #define DMAC_RESET		0x058 /* R DMAC Reset Register1 */
163 
164 /* DMA channel registers offset */
165 #define CH_SAR			0x000 /* R/W Chan Source Address */
166 #define CH_DAR			0x008 /* R/W Chan Destination Address */
167 #define CH_BLOCK_TS		0x010 /* R/W Chan Block Transfer Size */
168 #define CH_CTL			0x018 /* R/W Chan Control */
169 #define CH_CTL_L		0x018 /* R/W Chan Control 00-31 */
170 #define CH_CTL_H		0x01C /* R/W Chan Control 32-63 */
171 #define CH_CFG			0x020 /* R/W Chan Configuration */
172 #define CH_CFG_L		0x020 /* R/W Chan Configuration 00-31 */
173 #define CH_CFG_H		0x024 /* R/W Chan Configuration 32-63 */
174 #define CH_LLP			0x028 /* R/W Chan Linked List Pointer */
175 #define CH_STATUS		0x030 /* R Chan Status */
176 #define CH_SWHSSRC		0x038 /* R/W Chan SW Handshake Source */
177 #define CH_SWHSDST		0x040 /* R/W Chan SW Handshake Destination */
178 #define CH_BLK_TFR_RESUMEREQ	0x048 /* W Chan Block Transfer Resume Req */
179 #define CH_AXI_ID		0x050 /* R/W Chan AXI ID */
180 #define CH_AXI_QOS		0x058 /* R/W Chan AXI QOS */
181 #define CH_SSTAT		0x060 /* R Chan Source Status */
182 #define CH_DSTAT		0x068 /* R Chan Destination Status */
183 #define CH_SSTATAR		0x070 /* R/W Chan Source Status Fetch Addr */
184 #define CH_DSTATAR		0x078 /* R/W Chan Destination Status Fetch Addr */
185 #define CH_INTSTATUS_ENA	0x080 /* R/W Chan Interrupt Status Enable */
186 #define CH_INTSTATUS		0x088 /* R/W Chan Interrupt Status */
187 #define CH_INTSIGNAL_ENA	0x090 /* R/W Chan Interrupt Signal Enable */
188 #define CH_INTCLEAR		0x098 /* W Chan Interrupt Clear */
189 
190 /* These Apb registers are used by Intel KeemBay SoC */
191 #define DMAC_APB_CFG		0x000 /* DMAC Apb Configuration Register */
192 #define DMAC_APB_STAT		0x004 /* DMAC Apb Status Register */
193 #define DMAC_APB_DEBUG_STAT_0	0x008 /* DMAC Apb Debug Status Register 0 */
194 #define DMAC_APB_DEBUG_STAT_1	0x00C /* DMAC Apb Debug Status Register 1 */
195 #define DMAC_APB_HW_HS_SEL_0	0x010 /* DMAC Apb HW HS register 0 */
196 #define DMAC_APB_HW_HS_SEL_1	0x014 /* DMAC Apb HW HS register 1 */
197 #define DMAC_APB_LPI		0x018 /* DMAC Apb Low Power Interface Reg */
198 #define DMAC_APB_BYTE_WR_CH_EN	0x01C /* DMAC Apb Byte Write Enable */
199 #define DMAC_APB_HALFWORD_WR_CH_EN	0x020 /* DMAC Halfword write enables */
200 
201 #define UNUSED_CHANNEL		0x3F /* Set unused DMA channel to 0x3F */
202 #define DMA_APB_HS_SEL_BIT_SIZE	0x08 /* HW handshake bits per channel */
203 #define DMA_APB_HS_SEL_MASK	0xFF /* HW handshake select masks */
204 #define MAX_BLOCK_SIZE		0x1000 /* 1024 blocks * 4 bytes data width */
205 #define DMA_REG_MAP_CH_REF	0x08 /* Channel count to choose register map */
206 
207 /* DMAC_CFG */
208 #define DMAC_EN_POS			0
209 #define DMAC_EN_MASK			BIT(DMAC_EN_POS)
210 
211 #define INT_EN_POS			1
212 #define INT_EN_MASK			BIT(INT_EN_POS)
213 
214 /* DMAC_CHEN */
215 #define DMAC_CHAN_EN_SHIFT		0
216 #define DMAC_CHAN_EN_WE_SHIFT		8
217 
218 #define DMAC_CHAN_SUSP_SHIFT		16
219 #define DMAC_CHAN_SUSP_WE_SHIFT		24
220 
221 /* DMAC_CHEN2 */
222 #define DMAC_CHAN_EN2_WE_SHIFT		16
223 
224 /* DMAC_CHSUSP */
225 #define DMAC_CHAN_SUSP2_SHIFT		0
226 #define DMAC_CHAN_SUSP2_WE_SHIFT	16
227 
228 /* CH_CTL_H */
229 #define CH_CTL_H_ARLEN_EN		BIT(6)
230 #define CH_CTL_H_ARLEN_POS		7
231 #define CH_CTL_H_AWLEN_EN		BIT(15)
232 #define CH_CTL_H_AWLEN_POS		16
233 
234 enum {
235 	DWAXIDMAC_ARWLEN_1		= 0,
236 	DWAXIDMAC_ARWLEN_2		= 1,
237 	DWAXIDMAC_ARWLEN_4		= 3,
238 	DWAXIDMAC_ARWLEN_8		= 7,
239 	DWAXIDMAC_ARWLEN_16		= 15,
240 	DWAXIDMAC_ARWLEN_32		= 31,
241 	DWAXIDMAC_ARWLEN_64		= 63,
242 	DWAXIDMAC_ARWLEN_128		= 127,
243 	DWAXIDMAC_ARWLEN_256		= 255,
244 	DWAXIDMAC_ARWLEN_MIN		= DWAXIDMAC_ARWLEN_1,
245 	DWAXIDMAC_ARWLEN_MAX		= DWAXIDMAC_ARWLEN_256
246 };
247 
248 #define CH_CTL_H_LLI_LAST		BIT(30)
249 #define CH_CTL_H_LLI_VALID		BIT(31)
250 
251 /* CH_CTL_L */
252 #define CH_CTL_L_LAST_WRITE_EN		BIT(30)
253 
254 #define CH_CTL_L_DST_MSIZE_POS		18
255 #define CH_CTL_L_SRC_MSIZE_POS		14
256 
257 enum {
258 	DWAXIDMAC_BURST_TRANS_LEN_1	= 0,
259 	DWAXIDMAC_BURST_TRANS_LEN_4,
260 	DWAXIDMAC_BURST_TRANS_LEN_8,
261 	DWAXIDMAC_BURST_TRANS_LEN_16,
262 	DWAXIDMAC_BURST_TRANS_LEN_32,
263 	DWAXIDMAC_BURST_TRANS_LEN_64,
264 	DWAXIDMAC_BURST_TRANS_LEN_128,
265 	DWAXIDMAC_BURST_TRANS_LEN_256,
266 	DWAXIDMAC_BURST_TRANS_LEN_512,
267 	DWAXIDMAC_BURST_TRANS_LEN_1024
268 };
269 
270 #define CH_CTL_L_DST_WIDTH_POS		11
271 #define CH_CTL_L_SRC_WIDTH_POS		8
272 
273 #define CH_CTL_L_DST_INC_POS		6
274 #define CH_CTL_L_SRC_INC_POS		4
275 enum {
276 	DWAXIDMAC_CH_CTL_L_INC		= 0,
277 	DWAXIDMAC_CH_CTL_L_NOINC
278 };
279 
280 #define CH_CTL_L_DST_MAST		BIT(2)
281 #define CH_CTL_L_SRC_MAST		BIT(0)
282 
283 /* CH_CFG_H */
284 #define CH_CFG_H_PRIORITY_POS		17
285 #define CH_CFG_H_DST_PER_POS		12
286 #define CH_CFG_H_SRC_PER_POS		7
287 #define CH_CFG_H_HS_SEL_DST_POS		4
288 #define CH_CFG_H_HS_SEL_SRC_POS		3
289 enum {
290 	DWAXIDMAC_HS_SEL_HW		= 0,
291 	DWAXIDMAC_HS_SEL_SW
292 };
293 
294 #define CH_CFG_H_TT_FC_POS		0
295 enum {
296 	DWAXIDMAC_TT_FC_MEM_TO_MEM_DMAC	= 0,
297 	DWAXIDMAC_TT_FC_MEM_TO_PER_DMAC,
298 	DWAXIDMAC_TT_FC_PER_TO_MEM_DMAC,
299 	DWAXIDMAC_TT_FC_PER_TO_PER_DMAC,
300 	DWAXIDMAC_TT_FC_PER_TO_MEM_SRC,
301 	DWAXIDMAC_TT_FC_PER_TO_PER_SRC,
302 	DWAXIDMAC_TT_FC_MEM_TO_PER_DST,
303 	DWAXIDMAC_TT_FC_PER_TO_PER_DST
304 };
305 
306 /* CH_CFG_L */
307 #define CH_CFG_L_DST_MULTBLK_TYPE_POS	2
308 #define CH_CFG_L_SRC_MULTBLK_TYPE_POS	0
309 enum {
310 	DWAXIDMAC_MBLK_TYPE_CONTIGUOUS	= 0,
311 	DWAXIDMAC_MBLK_TYPE_RELOAD,
312 	DWAXIDMAC_MBLK_TYPE_SHADOW_REG,
313 	DWAXIDMAC_MBLK_TYPE_LL
314 };
315 
316 /* CH_CFG2 */
317 #define CH_CFG2_L_SRC_PER_POS		4
318 #define CH_CFG2_L_DST_PER_POS		11
319 
320 #define CH_CFG2_H_TT_FC_POS		0
321 #define CH_CFG2_H_HS_SEL_SRC_POS	3
322 #define CH_CFG2_H_HS_SEL_DST_POS	4
323 #define CH_CFG2_H_PRIORITY_POS		20
324 
325 /**
326  * DW AXI DMA channel interrupts
327  *
328  * @DWAXIDMAC_IRQ_NONE: Bitmask of no one interrupt
329  * @DWAXIDMAC_IRQ_BLOCK_TRF: Block transfer complete
330  * @DWAXIDMAC_IRQ_DMA_TRF: Dma transfer complete
331  * @DWAXIDMAC_IRQ_SRC_TRAN: Source transaction complete
332  * @DWAXIDMAC_IRQ_DST_TRAN: Destination transaction complete
333  * @DWAXIDMAC_IRQ_SRC_DEC_ERR: Source decode error
334  * @DWAXIDMAC_IRQ_DST_DEC_ERR: Destination decode error
335  * @DWAXIDMAC_IRQ_SRC_SLV_ERR: Source slave error
336  * @DWAXIDMAC_IRQ_DST_SLV_ERR: Destination slave error
337  * @DWAXIDMAC_IRQ_LLI_RD_DEC_ERR: LLI read decode error
338  * @DWAXIDMAC_IRQ_LLI_WR_DEC_ERR: LLI write decode error
339  * @DWAXIDMAC_IRQ_LLI_RD_SLV_ERR: LLI read slave error
340  * @DWAXIDMAC_IRQ_LLI_WR_SLV_ERR: LLI write slave error
341  * @DWAXIDMAC_IRQ_INVALID_ERR: LLI invalid error or Shadow register error
342  * @DWAXIDMAC_IRQ_MULTIBLKTYPE_ERR: Slave Interface Multiblock type error
343  * @DWAXIDMAC_IRQ_DEC_ERR: Slave Interface decode error
344  * @DWAXIDMAC_IRQ_WR2RO_ERR: Slave Interface write to read only error
345  * @DWAXIDMAC_IRQ_RD2RWO_ERR: Slave Interface read to write only error
346  * @DWAXIDMAC_IRQ_WRONCHEN_ERR: Slave Interface write to channel error
347  * @DWAXIDMAC_IRQ_SHADOWREG_ERR: Slave Interface shadow reg error
348  * @DWAXIDMAC_IRQ_WRONHOLD_ERR: Slave Interface hold error
349  * @DWAXIDMAC_IRQ_LOCK_CLEARED: Lock Cleared Status
350  * @DWAXIDMAC_IRQ_SRC_SUSPENDED: Source Suspended Status
351  * @DWAXIDMAC_IRQ_SUSPENDED: Channel Suspended Status
352  * @DWAXIDMAC_IRQ_DISABLED: Channel Disabled Status
353  * @DWAXIDMAC_IRQ_ABORTED: Channel Aborted Status
354  * @DWAXIDMAC_IRQ_ALL_ERR: Bitmask of all error interrupts
355  * @DWAXIDMAC_IRQ_ALL: Bitmask of all interrupts
356  */
357 enum {
358 	DWAXIDMAC_IRQ_NONE		= 0,
359 	DWAXIDMAC_IRQ_BLOCK_TRF		= BIT(0),
360 	DWAXIDMAC_IRQ_DMA_TRF		= BIT(1),
361 	DWAXIDMAC_IRQ_SRC_TRAN		= BIT(3),
362 	DWAXIDMAC_IRQ_DST_TRAN		= BIT(4),
363 	DWAXIDMAC_IRQ_SRC_DEC_ERR	= BIT(5),
364 	DWAXIDMAC_IRQ_DST_DEC_ERR	= BIT(6),
365 	DWAXIDMAC_IRQ_SRC_SLV_ERR	= BIT(7),
366 	DWAXIDMAC_IRQ_DST_SLV_ERR	= BIT(8),
367 	DWAXIDMAC_IRQ_LLI_RD_DEC_ERR	= BIT(9),
368 	DWAXIDMAC_IRQ_LLI_WR_DEC_ERR	= BIT(10),
369 	DWAXIDMAC_IRQ_LLI_RD_SLV_ERR	= BIT(11),
370 	DWAXIDMAC_IRQ_LLI_WR_SLV_ERR	= BIT(12),
371 	DWAXIDMAC_IRQ_INVALID_ERR	= BIT(13),
372 	DWAXIDMAC_IRQ_MULTIBLKTYPE_ERR	= BIT(14),
373 	DWAXIDMAC_IRQ_DEC_ERR		= BIT(16),
374 	DWAXIDMAC_IRQ_WR2RO_ERR		= BIT(17),
375 	DWAXIDMAC_IRQ_RD2RWO_ERR	= BIT(18),
376 	DWAXIDMAC_IRQ_WRONCHEN_ERR	= BIT(19),
377 	DWAXIDMAC_IRQ_SHADOWREG_ERR	= BIT(20),
378 	DWAXIDMAC_IRQ_WRONHOLD_ERR	= BIT(21),
379 	DWAXIDMAC_IRQ_LOCK_CLEARED	= BIT(27),
380 	DWAXIDMAC_IRQ_SRC_SUSPENDED	= BIT(28),
381 	DWAXIDMAC_IRQ_SUSPENDED		= BIT(29),
382 	DWAXIDMAC_IRQ_DISABLED		= BIT(30),
383 	DWAXIDMAC_IRQ_ABORTED		= BIT(31),
384 	DWAXIDMAC_IRQ_ALL_ERR		= (GENMASK(21, 16) | GENMASK(14, 5)),
385 	DWAXIDMAC_IRQ_ALL		= GENMASK(31, 0)
386 };
387 
388 enum {
389 	DWAXIDMAC_TRANS_WIDTH_8		= 0,
390 	DWAXIDMAC_TRANS_WIDTH_16,
391 	DWAXIDMAC_TRANS_WIDTH_32,
392 	DWAXIDMAC_TRANS_WIDTH_64,
393 	DWAXIDMAC_TRANS_WIDTH_128,
394 	DWAXIDMAC_TRANS_WIDTH_256,
395 	DWAXIDMAC_TRANS_WIDTH_512,
396 	DWAXIDMAC_TRANS_WIDTH_MAX	= DWAXIDMAC_TRANS_WIDTH_512
397 };
398 
399 #endif /* _AXI_DMA_PLATFORM_H */
400