1 // SPDX-License-Identifier: GPL-2.0 2 // (C) 2017-2018 Synopsys, Inc. (www.synopsys.com) 3 4 /* 5 * Synopsys DesignWare AXI DMA Controller driver. 6 * 7 * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> 8 */ 9 10 #include <linux/bitops.h> 11 #include <linux/delay.h> 12 #include <linux/device.h> 13 #include <linux/dmaengine.h> 14 #include <linux/dmapool.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/err.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/iopoll.h> 20 #include <linux/io-64-nonatomic-lo-hi.h> 21 #include <linux/kernel.h> 22 #include <linux/module.h> 23 #include <linux/of.h> 24 #include <linux/of_dma.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/property.h> 28 #include <linux/slab.h> 29 #include <linux/types.h> 30 31 #include "dw-axi-dmac.h" 32 #include "../dmaengine.h" 33 #include "../virt-dma.h" 34 35 /* 36 * The set of bus widths supported by the DMA controller. DW AXI DMAC supports 37 * master data bus width up to 512 bits (for both AXI master interfaces), but 38 * it depends on IP block configuration. 39 */ 40 #define AXI_DMA_BUSWIDTHS \ 41 (DMA_SLAVE_BUSWIDTH_1_BYTE | \ 42 DMA_SLAVE_BUSWIDTH_2_BYTES | \ 43 DMA_SLAVE_BUSWIDTH_4_BYTES | \ 44 DMA_SLAVE_BUSWIDTH_8_BYTES | \ 45 DMA_SLAVE_BUSWIDTH_16_BYTES | \ 46 DMA_SLAVE_BUSWIDTH_32_BYTES | \ 47 DMA_SLAVE_BUSWIDTH_64_BYTES) 48 49 static inline void 50 axi_dma_iowrite32(struct axi_dma_chip *chip, u32 reg, u32 val) 51 { 52 iowrite32(val, chip->regs + reg); 53 } 54 55 static inline u32 axi_dma_ioread32(struct axi_dma_chip *chip, u32 reg) 56 { 57 return ioread32(chip->regs + reg); 58 } 59 60 static inline void 61 axi_chan_iowrite32(struct axi_dma_chan *chan, u32 reg, u32 val) 62 { 63 iowrite32(val, chan->chan_regs + reg); 64 } 65 66 static inline u32 axi_chan_ioread32(struct axi_dma_chan *chan, u32 reg) 67 { 68 return ioread32(chan->chan_regs + reg); 69 } 70 71 static inline void 72 axi_chan_iowrite64(struct axi_dma_chan *chan, u32 reg, u64 val) 73 { 74 /* 75 * We split one 64 bit write for two 32 bit write as some HW doesn't 76 * support 64 bit access. 77 */ 78 iowrite32(lower_32_bits(val), chan->chan_regs + reg); 79 iowrite32(upper_32_bits(val), chan->chan_regs + reg + 4); 80 } 81 82 static inline void axi_chan_config_write(struct axi_dma_chan *chan, 83 struct axi_dma_chan_config *config) 84 { 85 u32 cfg_lo, cfg_hi; 86 87 cfg_lo = (config->dst_multblk_type << CH_CFG_L_DST_MULTBLK_TYPE_POS | 88 config->src_multblk_type << CH_CFG_L_SRC_MULTBLK_TYPE_POS); 89 if (chan->chip->dw->hdata->reg_map_8_channels) { 90 cfg_hi = config->tt_fc << CH_CFG_H_TT_FC_POS | 91 config->hs_sel_src << CH_CFG_H_HS_SEL_SRC_POS | 92 config->hs_sel_dst << CH_CFG_H_HS_SEL_DST_POS | 93 config->src_per << CH_CFG_H_SRC_PER_POS | 94 config->dst_per << CH_CFG_H_DST_PER_POS | 95 config->prior << CH_CFG_H_PRIORITY_POS; 96 } else { 97 cfg_lo |= config->src_per << CH_CFG2_L_SRC_PER_POS | 98 config->dst_per << CH_CFG2_L_DST_PER_POS; 99 cfg_hi = config->tt_fc << CH_CFG2_H_TT_FC_POS | 100 config->hs_sel_src << CH_CFG2_H_HS_SEL_SRC_POS | 101 config->hs_sel_dst << CH_CFG2_H_HS_SEL_DST_POS | 102 config->prior << CH_CFG2_H_PRIORITY_POS; 103 } 104 axi_chan_iowrite32(chan, CH_CFG_L, cfg_lo); 105 axi_chan_iowrite32(chan, CH_CFG_H, cfg_hi); 106 } 107 108 static inline void axi_dma_disable(struct axi_dma_chip *chip) 109 { 110 u32 val; 111 112 val = axi_dma_ioread32(chip, DMAC_CFG); 113 val &= ~DMAC_EN_MASK; 114 axi_dma_iowrite32(chip, DMAC_CFG, val); 115 } 116 117 static inline void axi_dma_enable(struct axi_dma_chip *chip) 118 { 119 u32 val; 120 121 val = axi_dma_ioread32(chip, DMAC_CFG); 122 val |= DMAC_EN_MASK; 123 axi_dma_iowrite32(chip, DMAC_CFG, val); 124 } 125 126 static inline void axi_dma_irq_disable(struct axi_dma_chip *chip) 127 { 128 u32 val; 129 130 val = axi_dma_ioread32(chip, DMAC_CFG); 131 val &= ~INT_EN_MASK; 132 axi_dma_iowrite32(chip, DMAC_CFG, val); 133 } 134 135 static inline void axi_dma_irq_enable(struct axi_dma_chip *chip) 136 { 137 u32 val; 138 139 val = axi_dma_ioread32(chip, DMAC_CFG); 140 val |= INT_EN_MASK; 141 axi_dma_iowrite32(chip, DMAC_CFG, val); 142 } 143 144 static inline void axi_chan_irq_disable(struct axi_dma_chan *chan, u32 irq_mask) 145 { 146 u32 val; 147 148 if (likely(irq_mask == DWAXIDMAC_IRQ_ALL)) { 149 axi_chan_iowrite32(chan, CH_INTSTATUS_ENA, DWAXIDMAC_IRQ_NONE); 150 } else { 151 val = axi_chan_ioread32(chan, CH_INTSTATUS_ENA); 152 val &= ~irq_mask; 153 axi_chan_iowrite32(chan, CH_INTSTATUS_ENA, val); 154 } 155 } 156 157 static inline void axi_chan_irq_set(struct axi_dma_chan *chan, u32 irq_mask) 158 { 159 axi_chan_iowrite32(chan, CH_INTSTATUS_ENA, irq_mask); 160 } 161 162 static inline void axi_chan_irq_sig_set(struct axi_dma_chan *chan, u32 irq_mask) 163 { 164 axi_chan_iowrite32(chan, CH_INTSIGNAL_ENA, irq_mask); 165 } 166 167 static inline void axi_chan_irq_clear(struct axi_dma_chan *chan, u32 irq_mask) 168 { 169 axi_chan_iowrite32(chan, CH_INTCLEAR, irq_mask); 170 } 171 172 static inline u32 axi_chan_irq_read(struct axi_dma_chan *chan) 173 { 174 return axi_chan_ioread32(chan, CH_INTSTATUS); 175 } 176 177 static inline void axi_chan_disable(struct axi_dma_chan *chan) 178 { 179 u32 val; 180 181 val = axi_dma_ioread32(chan->chip, DMAC_CHEN); 182 val &= ~(BIT(chan->id) << DMAC_CHAN_EN_SHIFT); 183 if (chan->chip->dw->hdata->reg_map_8_channels) 184 val |= BIT(chan->id) << DMAC_CHAN_EN_WE_SHIFT; 185 else 186 val |= BIT(chan->id) << DMAC_CHAN_EN2_WE_SHIFT; 187 axi_dma_iowrite32(chan->chip, DMAC_CHEN, val); 188 } 189 190 static inline void axi_chan_enable(struct axi_dma_chan *chan) 191 { 192 u32 val; 193 194 val = axi_dma_ioread32(chan->chip, DMAC_CHEN); 195 if (chan->chip->dw->hdata->reg_map_8_channels) 196 val |= BIT(chan->id) << DMAC_CHAN_EN_SHIFT | 197 BIT(chan->id) << DMAC_CHAN_EN_WE_SHIFT; 198 else 199 val |= BIT(chan->id) << DMAC_CHAN_EN_SHIFT | 200 BIT(chan->id) << DMAC_CHAN_EN2_WE_SHIFT; 201 axi_dma_iowrite32(chan->chip, DMAC_CHEN, val); 202 } 203 204 static inline bool axi_chan_is_hw_enable(struct axi_dma_chan *chan) 205 { 206 u32 val; 207 208 val = axi_dma_ioread32(chan->chip, DMAC_CHEN); 209 210 return !!(val & (BIT(chan->id) << DMAC_CHAN_EN_SHIFT)); 211 } 212 213 static void axi_dma_hw_init(struct axi_dma_chip *chip) 214 { 215 int ret; 216 u32 i; 217 218 for (i = 0; i < chip->dw->hdata->nr_channels; i++) { 219 axi_chan_irq_disable(&chip->dw->chan[i], DWAXIDMAC_IRQ_ALL); 220 axi_chan_disable(&chip->dw->chan[i]); 221 } 222 ret = dma_set_mask_and_coherent(chip->dev, DMA_BIT_MASK(64)); 223 if (ret) 224 dev_warn(chip->dev, "Unable to set coherent mask\n"); 225 } 226 227 static u32 axi_chan_get_xfer_width(struct axi_dma_chan *chan, dma_addr_t src, 228 dma_addr_t dst, size_t len) 229 { 230 u32 max_width = chan->chip->dw->hdata->m_data_width; 231 232 return __ffs(src | dst | len | BIT(max_width)); 233 } 234 235 static inline const char *axi_chan_name(struct axi_dma_chan *chan) 236 { 237 return dma_chan_name(&chan->vc.chan); 238 } 239 240 static struct axi_dma_desc *axi_desc_alloc(u32 num) 241 { 242 struct axi_dma_desc *desc; 243 244 desc = kzalloc(sizeof(*desc), GFP_NOWAIT); 245 if (!desc) 246 return NULL; 247 248 desc->hw_desc = kcalloc(num, sizeof(*desc->hw_desc), GFP_NOWAIT); 249 if (!desc->hw_desc) { 250 kfree(desc); 251 return NULL; 252 } 253 254 return desc; 255 } 256 257 static struct axi_dma_lli *axi_desc_get(struct axi_dma_chan *chan, 258 dma_addr_t *addr) 259 { 260 struct axi_dma_lli *lli; 261 dma_addr_t phys; 262 263 lli = dma_pool_zalloc(chan->desc_pool, GFP_NOWAIT, &phys); 264 if (unlikely(!lli)) { 265 dev_err(chan2dev(chan), "%s: not enough descriptors available\n", 266 axi_chan_name(chan)); 267 return NULL; 268 } 269 270 atomic_inc(&chan->descs_allocated); 271 *addr = phys; 272 273 return lli; 274 } 275 276 static void axi_desc_put(struct axi_dma_desc *desc) 277 { 278 struct axi_dma_chan *chan = desc->chan; 279 int count = atomic_read(&chan->descs_allocated); 280 struct axi_dma_hw_desc *hw_desc; 281 int descs_put; 282 283 for (descs_put = 0; descs_put < count; descs_put++) { 284 hw_desc = &desc->hw_desc[descs_put]; 285 dma_pool_free(chan->desc_pool, hw_desc->lli, hw_desc->llp); 286 } 287 288 kfree(desc->hw_desc); 289 kfree(desc); 290 atomic_sub(descs_put, &chan->descs_allocated); 291 dev_vdbg(chan2dev(chan), "%s: %d descs put, %d still allocated\n", 292 axi_chan_name(chan), descs_put, 293 atomic_read(&chan->descs_allocated)); 294 } 295 296 static void vchan_desc_put(struct virt_dma_desc *vdesc) 297 { 298 axi_desc_put(vd_to_axi_desc(vdesc)); 299 } 300 301 static enum dma_status 302 dma_chan_tx_status(struct dma_chan *dchan, dma_cookie_t cookie, 303 struct dma_tx_state *txstate) 304 { 305 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); 306 struct virt_dma_desc *vdesc; 307 enum dma_status status; 308 u32 completed_length; 309 unsigned long flags; 310 u32 completed_blocks; 311 size_t bytes = 0; 312 u32 length; 313 u32 len; 314 315 status = dma_cookie_status(dchan, cookie, txstate); 316 if (status == DMA_COMPLETE || !txstate) 317 return status; 318 319 spin_lock_irqsave(&chan->vc.lock, flags); 320 321 vdesc = vchan_find_desc(&chan->vc, cookie); 322 if (vdesc) { 323 length = vd_to_axi_desc(vdesc)->length; 324 completed_blocks = vd_to_axi_desc(vdesc)->completed_blocks; 325 len = vd_to_axi_desc(vdesc)->hw_desc[0].len; 326 completed_length = completed_blocks * len; 327 bytes = length - completed_length; 328 } else { 329 bytes = vd_to_axi_desc(vdesc)->length; 330 } 331 332 spin_unlock_irqrestore(&chan->vc.lock, flags); 333 dma_set_residue(txstate, bytes); 334 335 return status; 336 } 337 338 static void write_desc_llp(struct axi_dma_hw_desc *desc, dma_addr_t adr) 339 { 340 desc->lli->llp = cpu_to_le64(adr); 341 } 342 343 static void write_chan_llp(struct axi_dma_chan *chan, dma_addr_t adr) 344 { 345 axi_chan_iowrite64(chan, CH_LLP, adr); 346 } 347 348 static void dw_axi_dma_set_byte_halfword(struct axi_dma_chan *chan, bool set) 349 { 350 u32 offset = DMAC_APB_BYTE_WR_CH_EN; 351 u32 reg_width, val; 352 353 if (!chan->chip->apb_regs) { 354 dev_dbg(chan->chip->dev, "apb_regs not initialized\n"); 355 return; 356 } 357 358 reg_width = __ffs(chan->config.dst_addr_width); 359 if (reg_width == DWAXIDMAC_TRANS_WIDTH_16) 360 offset = DMAC_APB_HALFWORD_WR_CH_EN; 361 362 val = ioread32(chan->chip->apb_regs + offset); 363 364 if (set) 365 val |= BIT(chan->id); 366 else 367 val &= ~BIT(chan->id); 368 369 iowrite32(val, chan->chip->apb_regs + offset); 370 } 371 /* Called in chan locked context */ 372 static void axi_chan_block_xfer_start(struct axi_dma_chan *chan, 373 struct axi_dma_desc *first) 374 { 375 u32 priority = chan->chip->dw->hdata->priority[chan->id]; 376 struct axi_dma_chan_config config = {}; 377 u32 irq_mask; 378 u8 lms = 0; /* Select AXI0 master for LLI fetching */ 379 380 if (unlikely(axi_chan_is_hw_enable(chan))) { 381 dev_err(chan2dev(chan), "%s is non-idle!\n", 382 axi_chan_name(chan)); 383 384 return; 385 } 386 387 axi_dma_enable(chan->chip); 388 389 config.dst_multblk_type = DWAXIDMAC_MBLK_TYPE_LL; 390 config.src_multblk_type = DWAXIDMAC_MBLK_TYPE_LL; 391 config.tt_fc = DWAXIDMAC_TT_FC_MEM_TO_MEM_DMAC; 392 config.prior = priority; 393 config.hs_sel_dst = DWAXIDMAC_HS_SEL_HW; 394 config.hs_sel_src = DWAXIDMAC_HS_SEL_HW; 395 switch (chan->direction) { 396 case DMA_MEM_TO_DEV: 397 dw_axi_dma_set_byte_halfword(chan, true); 398 config.tt_fc = chan->config.device_fc ? 399 DWAXIDMAC_TT_FC_MEM_TO_PER_DST : 400 DWAXIDMAC_TT_FC_MEM_TO_PER_DMAC; 401 if (chan->chip->apb_regs) 402 config.dst_per = chan->id; 403 else 404 config.dst_per = chan->hw_handshake_num; 405 break; 406 case DMA_DEV_TO_MEM: 407 config.tt_fc = chan->config.device_fc ? 408 DWAXIDMAC_TT_FC_PER_TO_MEM_SRC : 409 DWAXIDMAC_TT_FC_PER_TO_MEM_DMAC; 410 if (chan->chip->apb_regs) 411 config.src_per = chan->id; 412 else 413 config.src_per = chan->hw_handshake_num; 414 break; 415 default: 416 break; 417 } 418 axi_chan_config_write(chan, &config); 419 420 write_chan_llp(chan, first->hw_desc[0].llp | lms); 421 422 irq_mask = DWAXIDMAC_IRQ_DMA_TRF | DWAXIDMAC_IRQ_ALL_ERR; 423 axi_chan_irq_sig_set(chan, irq_mask); 424 425 /* Generate 'suspend' status but don't generate interrupt */ 426 irq_mask |= DWAXIDMAC_IRQ_SUSPENDED; 427 axi_chan_irq_set(chan, irq_mask); 428 429 axi_chan_enable(chan); 430 } 431 432 static void axi_chan_start_first_queued(struct axi_dma_chan *chan) 433 { 434 struct axi_dma_desc *desc; 435 struct virt_dma_desc *vd; 436 437 vd = vchan_next_desc(&chan->vc); 438 if (!vd) 439 return; 440 441 desc = vd_to_axi_desc(vd); 442 dev_vdbg(chan2dev(chan), "%s: started %u\n", axi_chan_name(chan), 443 vd->tx.cookie); 444 axi_chan_block_xfer_start(chan, desc); 445 } 446 447 static void dma_chan_issue_pending(struct dma_chan *dchan) 448 { 449 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); 450 unsigned long flags; 451 452 spin_lock_irqsave(&chan->vc.lock, flags); 453 if (vchan_issue_pending(&chan->vc)) 454 axi_chan_start_first_queued(chan); 455 spin_unlock_irqrestore(&chan->vc.lock, flags); 456 } 457 458 static void dw_axi_dma_synchronize(struct dma_chan *dchan) 459 { 460 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); 461 462 vchan_synchronize(&chan->vc); 463 } 464 465 static int dma_chan_alloc_chan_resources(struct dma_chan *dchan) 466 { 467 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); 468 469 /* ASSERT: channel is idle */ 470 if (axi_chan_is_hw_enable(chan)) { 471 dev_err(chan2dev(chan), "%s is non-idle!\n", 472 axi_chan_name(chan)); 473 return -EBUSY; 474 } 475 476 /* LLI address must be aligned to a 64-byte boundary */ 477 chan->desc_pool = dma_pool_create(dev_name(chan2dev(chan)), 478 chan->chip->dev, 479 sizeof(struct axi_dma_lli), 480 64, 0); 481 if (!chan->desc_pool) { 482 dev_err(chan2dev(chan), "No memory for descriptors\n"); 483 return -ENOMEM; 484 } 485 dev_vdbg(dchan2dev(dchan), "%s: allocating\n", axi_chan_name(chan)); 486 487 pm_runtime_get(chan->chip->dev); 488 489 return 0; 490 } 491 492 static void dma_chan_free_chan_resources(struct dma_chan *dchan) 493 { 494 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); 495 496 /* ASSERT: channel is idle */ 497 if (axi_chan_is_hw_enable(chan)) 498 dev_err(dchan2dev(dchan), "%s is non-idle!\n", 499 axi_chan_name(chan)); 500 501 axi_chan_disable(chan); 502 axi_chan_irq_disable(chan, DWAXIDMAC_IRQ_ALL); 503 504 vchan_free_chan_resources(&chan->vc); 505 506 dma_pool_destroy(chan->desc_pool); 507 chan->desc_pool = NULL; 508 dev_vdbg(dchan2dev(dchan), 509 "%s: free resources, descriptor still allocated: %u\n", 510 axi_chan_name(chan), atomic_read(&chan->descs_allocated)); 511 512 pm_runtime_put(chan->chip->dev); 513 } 514 515 static void dw_axi_dma_set_hw_channel(struct axi_dma_chan *chan, bool set) 516 { 517 struct axi_dma_chip *chip = chan->chip; 518 unsigned long reg_value, val; 519 520 if (!chip->apb_regs) { 521 dev_err(chip->dev, "apb_regs not initialized\n"); 522 return; 523 } 524 525 /* 526 * An unused DMA channel has a default value of 0x3F. 527 * Lock the DMA channel by assign a handshake number to the channel. 528 * Unlock the DMA channel by assign 0x3F to the channel. 529 */ 530 if (set) 531 val = chan->hw_handshake_num; 532 else 533 val = UNUSED_CHANNEL; 534 535 reg_value = lo_hi_readq(chip->apb_regs + DMAC_APB_HW_HS_SEL_0); 536 537 /* Channel is already allocated, set handshake as per channel ID */ 538 /* 64 bit write should handle for 8 channels */ 539 540 reg_value &= ~(DMA_APB_HS_SEL_MASK << 541 (chan->id * DMA_APB_HS_SEL_BIT_SIZE)); 542 reg_value |= (val << (chan->id * DMA_APB_HS_SEL_BIT_SIZE)); 543 lo_hi_writeq(reg_value, chip->apb_regs + DMAC_APB_HW_HS_SEL_0); 544 545 return; 546 } 547 548 /* 549 * If DW_axi_dmac sees CHx_CTL.ShadowReg_Or_LLI_Last bit of the fetched LLI 550 * as 1, it understands that the current block is the final block in the 551 * transfer and completes the DMA transfer operation at the end of current 552 * block transfer. 553 */ 554 static void set_desc_last(struct axi_dma_hw_desc *desc) 555 { 556 u32 val; 557 558 val = le32_to_cpu(desc->lli->ctl_hi); 559 val |= CH_CTL_H_LLI_LAST; 560 desc->lli->ctl_hi = cpu_to_le32(val); 561 } 562 563 static void write_desc_sar(struct axi_dma_hw_desc *desc, dma_addr_t adr) 564 { 565 desc->lli->sar = cpu_to_le64(adr); 566 } 567 568 static void write_desc_dar(struct axi_dma_hw_desc *desc, dma_addr_t adr) 569 { 570 desc->lli->dar = cpu_to_le64(adr); 571 } 572 573 static void set_desc_src_master(struct axi_dma_hw_desc *desc) 574 { 575 u32 val; 576 577 /* Select AXI0 for source master */ 578 val = le32_to_cpu(desc->lli->ctl_lo); 579 val &= ~CH_CTL_L_SRC_MAST; 580 desc->lli->ctl_lo = cpu_to_le32(val); 581 } 582 583 static void set_desc_dest_master(struct axi_dma_hw_desc *hw_desc, 584 struct axi_dma_desc *desc) 585 { 586 u32 val; 587 588 /* Select AXI1 for source master if available */ 589 val = le32_to_cpu(hw_desc->lli->ctl_lo); 590 if (desc->chan->chip->dw->hdata->nr_masters > 1) 591 val |= CH_CTL_L_DST_MAST; 592 else 593 val &= ~CH_CTL_L_DST_MAST; 594 595 hw_desc->lli->ctl_lo = cpu_to_le32(val); 596 } 597 598 static int dw_axi_dma_set_hw_desc(struct axi_dma_chan *chan, 599 struct axi_dma_hw_desc *hw_desc, 600 dma_addr_t mem_addr, size_t len) 601 { 602 unsigned int data_width = BIT(chan->chip->dw->hdata->m_data_width); 603 unsigned int reg_width; 604 unsigned int mem_width; 605 dma_addr_t device_addr; 606 size_t axi_block_ts; 607 size_t block_ts; 608 u32 ctllo, ctlhi; 609 u32 burst_len; 610 611 axi_block_ts = chan->chip->dw->hdata->block_size[chan->id]; 612 613 mem_width = __ffs(data_width | mem_addr | len); 614 if (mem_width > DWAXIDMAC_TRANS_WIDTH_32) 615 mem_width = DWAXIDMAC_TRANS_WIDTH_32; 616 617 if (!IS_ALIGNED(mem_addr, 4)) { 618 dev_err(chan->chip->dev, "invalid buffer alignment\n"); 619 return -EINVAL; 620 } 621 622 switch (chan->direction) { 623 case DMA_MEM_TO_DEV: 624 reg_width = __ffs(chan->config.dst_addr_width); 625 device_addr = chan->config.dst_addr; 626 ctllo = reg_width << CH_CTL_L_DST_WIDTH_POS | 627 mem_width << CH_CTL_L_SRC_WIDTH_POS | 628 DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_DST_INC_POS | 629 DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_SRC_INC_POS; 630 block_ts = len >> mem_width; 631 break; 632 case DMA_DEV_TO_MEM: 633 reg_width = __ffs(chan->config.src_addr_width); 634 device_addr = chan->config.src_addr; 635 ctllo = reg_width << CH_CTL_L_SRC_WIDTH_POS | 636 mem_width << CH_CTL_L_DST_WIDTH_POS | 637 DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_DST_INC_POS | 638 DWAXIDMAC_CH_CTL_L_NOINC << CH_CTL_L_SRC_INC_POS; 639 block_ts = len >> reg_width; 640 break; 641 default: 642 return -EINVAL; 643 } 644 645 if (block_ts > axi_block_ts) 646 return -EINVAL; 647 648 hw_desc->lli = axi_desc_get(chan, &hw_desc->llp); 649 if (unlikely(!hw_desc->lli)) 650 return -ENOMEM; 651 652 ctlhi = CH_CTL_H_LLI_VALID; 653 654 if (chan->chip->dw->hdata->restrict_axi_burst_len) { 655 burst_len = chan->chip->dw->hdata->axi_rw_burst_len; 656 ctlhi |= CH_CTL_H_ARLEN_EN | CH_CTL_H_AWLEN_EN | 657 burst_len << CH_CTL_H_ARLEN_POS | 658 burst_len << CH_CTL_H_AWLEN_POS; 659 } 660 661 hw_desc->lli->ctl_hi = cpu_to_le32(ctlhi); 662 663 if (chan->direction == DMA_MEM_TO_DEV) { 664 write_desc_sar(hw_desc, mem_addr); 665 write_desc_dar(hw_desc, device_addr); 666 } else { 667 write_desc_sar(hw_desc, device_addr); 668 write_desc_dar(hw_desc, mem_addr); 669 } 670 671 hw_desc->lli->block_ts_lo = cpu_to_le32(block_ts - 1); 672 673 ctllo |= DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_DST_MSIZE_POS | 674 DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_SRC_MSIZE_POS; 675 hw_desc->lli->ctl_lo = cpu_to_le32(ctllo); 676 677 set_desc_src_master(hw_desc); 678 679 hw_desc->len = len; 680 return 0; 681 } 682 683 static size_t calculate_block_len(struct axi_dma_chan *chan, 684 dma_addr_t dma_addr, size_t buf_len, 685 enum dma_transfer_direction direction) 686 { 687 u32 data_width, reg_width, mem_width; 688 size_t axi_block_ts, block_len; 689 690 axi_block_ts = chan->chip->dw->hdata->block_size[chan->id]; 691 692 switch (direction) { 693 case DMA_MEM_TO_DEV: 694 data_width = BIT(chan->chip->dw->hdata->m_data_width); 695 mem_width = __ffs(data_width | dma_addr | buf_len); 696 if (mem_width > DWAXIDMAC_TRANS_WIDTH_32) 697 mem_width = DWAXIDMAC_TRANS_WIDTH_32; 698 699 block_len = axi_block_ts << mem_width; 700 break; 701 case DMA_DEV_TO_MEM: 702 reg_width = __ffs(chan->config.src_addr_width); 703 block_len = axi_block_ts << reg_width; 704 break; 705 default: 706 block_len = 0; 707 } 708 709 return block_len; 710 } 711 712 static struct dma_async_tx_descriptor * 713 dw_axi_dma_chan_prep_cyclic(struct dma_chan *dchan, dma_addr_t dma_addr, 714 size_t buf_len, size_t period_len, 715 enum dma_transfer_direction direction, 716 unsigned long flags) 717 { 718 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); 719 struct axi_dma_hw_desc *hw_desc = NULL; 720 struct axi_dma_desc *desc = NULL; 721 dma_addr_t src_addr = dma_addr; 722 u32 num_periods, num_segments; 723 size_t axi_block_len; 724 u32 total_segments; 725 u32 segment_len; 726 unsigned int i; 727 int status; 728 u64 llp = 0; 729 u8 lms = 0; /* Select AXI0 master for LLI fetching */ 730 731 num_periods = buf_len / period_len; 732 733 axi_block_len = calculate_block_len(chan, dma_addr, buf_len, direction); 734 if (axi_block_len == 0) 735 return NULL; 736 737 num_segments = DIV_ROUND_UP(period_len, axi_block_len); 738 segment_len = DIV_ROUND_UP(period_len, num_segments); 739 740 total_segments = num_periods * num_segments; 741 742 desc = axi_desc_alloc(total_segments); 743 if (unlikely(!desc)) 744 goto err_desc_get; 745 746 chan->direction = direction; 747 desc->chan = chan; 748 chan->cyclic = true; 749 desc->length = 0; 750 desc->period_len = period_len; 751 752 for (i = 0; i < total_segments; i++) { 753 hw_desc = &desc->hw_desc[i]; 754 755 status = dw_axi_dma_set_hw_desc(chan, hw_desc, src_addr, 756 segment_len); 757 if (status < 0) 758 goto err_desc_get; 759 760 desc->length += hw_desc->len; 761 /* Set end-of-link to the linked descriptor, so that cyclic 762 * callback function can be triggered during interrupt. 763 */ 764 set_desc_last(hw_desc); 765 766 src_addr += segment_len; 767 } 768 769 llp = desc->hw_desc[0].llp; 770 771 /* Managed transfer list */ 772 do { 773 hw_desc = &desc->hw_desc[--total_segments]; 774 write_desc_llp(hw_desc, llp | lms); 775 llp = hw_desc->llp; 776 } while (total_segments); 777 778 dw_axi_dma_set_hw_channel(chan, true); 779 780 return vchan_tx_prep(&chan->vc, &desc->vd, flags); 781 782 err_desc_get: 783 if (desc) 784 axi_desc_put(desc); 785 786 return NULL; 787 } 788 789 static struct dma_async_tx_descriptor * 790 dw_axi_dma_chan_prep_slave_sg(struct dma_chan *dchan, struct scatterlist *sgl, 791 unsigned int sg_len, 792 enum dma_transfer_direction direction, 793 unsigned long flags, void *context) 794 { 795 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); 796 struct axi_dma_hw_desc *hw_desc = NULL; 797 struct axi_dma_desc *desc = NULL; 798 u32 num_segments, segment_len; 799 unsigned int loop = 0; 800 struct scatterlist *sg; 801 size_t axi_block_len; 802 u32 len, num_sgs = 0; 803 unsigned int i; 804 dma_addr_t mem; 805 int status; 806 u64 llp = 0; 807 u8 lms = 0; /* Select AXI0 master for LLI fetching */ 808 809 if (unlikely(!is_slave_direction(direction) || !sg_len)) 810 return NULL; 811 812 mem = sg_dma_address(sgl); 813 len = sg_dma_len(sgl); 814 815 axi_block_len = calculate_block_len(chan, mem, len, direction); 816 if (axi_block_len == 0) 817 return NULL; 818 819 for_each_sg(sgl, sg, sg_len, i) 820 num_sgs += DIV_ROUND_UP(sg_dma_len(sg), axi_block_len); 821 822 desc = axi_desc_alloc(num_sgs); 823 if (unlikely(!desc)) 824 goto err_desc_get; 825 826 desc->chan = chan; 827 desc->length = 0; 828 chan->direction = direction; 829 830 for_each_sg(sgl, sg, sg_len, i) { 831 mem = sg_dma_address(sg); 832 len = sg_dma_len(sg); 833 num_segments = DIV_ROUND_UP(sg_dma_len(sg), axi_block_len); 834 segment_len = DIV_ROUND_UP(sg_dma_len(sg), num_segments); 835 836 do { 837 hw_desc = &desc->hw_desc[loop++]; 838 status = dw_axi_dma_set_hw_desc(chan, hw_desc, mem, segment_len); 839 if (status < 0) 840 goto err_desc_get; 841 842 desc->length += hw_desc->len; 843 len -= segment_len; 844 mem += segment_len; 845 } while (len >= segment_len); 846 } 847 848 /* Set end-of-link to the last link descriptor of list */ 849 set_desc_last(&desc->hw_desc[num_sgs - 1]); 850 851 /* Managed transfer list */ 852 do { 853 hw_desc = &desc->hw_desc[--num_sgs]; 854 write_desc_llp(hw_desc, llp | lms); 855 llp = hw_desc->llp; 856 } while (num_sgs); 857 858 dw_axi_dma_set_hw_channel(chan, true); 859 860 return vchan_tx_prep(&chan->vc, &desc->vd, flags); 861 862 err_desc_get: 863 if (desc) 864 axi_desc_put(desc); 865 866 return NULL; 867 } 868 869 static struct dma_async_tx_descriptor * 870 dma_chan_prep_dma_memcpy(struct dma_chan *dchan, dma_addr_t dst_adr, 871 dma_addr_t src_adr, size_t len, unsigned long flags) 872 { 873 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); 874 size_t block_ts, max_block_ts, xfer_len; 875 struct axi_dma_hw_desc *hw_desc = NULL; 876 struct axi_dma_desc *desc = NULL; 877 u32 xfer_width, reg, num; 878 u64 llp = 0; 879 u8 lms = 0; /* Select AXI0 master for LLI fetching */ 880 881 dev_dbg(chan2dev(chan), "%s: memcpy: src: %pad dst: %pad length: %zd flags: %#lx", 882 axi_chan_name(chan), &src_adr, &dst_adr, len, flags); 883 884 max_block_ts = chan->chip->dw->hdata->block_size[chan->id]; 885 xfer_width = axi_chan_get_xfer_width(chan, src_adr, dst_adr, len); 886 num = DIV_ROUND_UP(len, max_block_ts << xfer_width); 887 desc = axi_desc_alloc(num); 888 if (unlikely(!desc)) 889 goto err_desc_get; 890 891 desc->chan = chan; 892 num = 0; 893 desc->length = 0; 894 while (len) { 895 xfer_len = len; 896 897 hw_desc = &desc->hw_desc[num]; 898 /* 899 * Take care for the alignment. 900 * Actually source and destination widths can be different, but 901 * make them same to be simpler. 902 */ 903 xfer_width = axi_chan_get_xfer_width(chan, src_adr, dst_adr, xfer_len); 904 905 /* 906 * block_ts indicates the total number of data of width 907 * to be transferred in a DMA block transfer. 908 * BLOCK_TS register should be set to block_ts - 1 909 */ 910 block_ts = xfer_len >> xfer_width; 911 if (block_ts > max_block_ts) { 912 block_ts = max_block_ts; 913 xfer_len = max_block_ts << xfer_width; 914 } 915 916 hw_desc->lli = axi_desc_get(chan, &hw_desc->llp); 917 if (unlikely(!hw_desc->lli)) 918 goto err_desc_get; 919 920 write_desc_sar(hw_desc, src_adr); 921 write_desc_dar(hw_desc, dst_adr); 922 hw_desc->lli->block_ts_lo = cpu_to_le32(block_ts - 1); 923 924 reg = CH_CTL_H_LLI_VALID; 925 if (chan->chip->dw->hdata->restrict_axi_burst_len) { 926 u32 burst_len = chan->chip->dw->hdata->axi_rw_burst_len; 927 928 reg |= (CH_CTL_H_ARLEN_EN | 929 burst_len << CH_CTL_H_ARLEN_POS | 930 CH_CTL_H_AWLEN_EN | 931 burst_len << CH_CTL_H_AWLEN_POS); 932 } 933 hw_desc->lli->ctl_hi = cpu_to_le32(reg); 934 935 reg = (DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_DST_MSIZE_POS | 936 DWAXIDMAC_BURST_TRANS_LEN_4 << CH_CTL_L_SRC_MSIZE_POS | 937 xfer_width << CH_CTL_L_DST_WIDTH_POS | 938 xfer_width << CH_CTL_L_SRC_WIDTH_POS | 939 DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_DST_INC_POS | 940 DWAXIDMAC_CH_CTL_L_INC << CH_CTL_L_SRC_INC_POS); 941 hw_desc->lli->ctl_lo = cpu_to_le32(reg); 942 943 set_desc_src_master(hw_desc); 944 set_desc_dest_master(hw_desc, desc); 945 946 hw_desc->len = xfer_len; 947 desc->length += hw_desc->len; 948 /* update the length and addresses for the next loop cycle */ 949 len -= xfer_len; 950 dst_adr += xfer_len; 951 src_adr += xfer_len; 952 num++; 953 } 954 955 /* Set end-of-link to the last link descriptor of list */ 956 set_desc_last(&desc->hw_desc[num - 1]); 957 /* Managed transfer list */ 958 do { 959 hw_desc = &desc->hw_desc[--num]; 960 write_desc_llp(hw_desc, llp | lms); 961 llp = hw_desc->llp; 962 } while (num); 963 964 return vchan_tx_prep(&chan->vc, &desc->vd, flags); 965 966 err_desc_get: 967 if (desc) 968 axi_desc_put(desc); 969 return NULL; 970 } 971 972 static int dw_axi_dma_chan_slave_config(struct dma_chan *dchan, 973 struct dma_slave_config *config) 974 { 975 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); 976 977 memcpy(&chan->config, config, sizeof(*config)); 978 979 return 0; 980 } 981 982 static void axi_chan_dump_lli(struct axi_dma_chan *chan, 983 struct axi_dma_hw_desc *desc) 984 { 985 if (!desc->lli) { 986 dev_err(dchan2dev(&chan->vc.chan), "NULL LLI\n"); 987 return; 988 } 989 990 dev_err(dchan2dev(&chan->vc.chan), 991 "SAR: 0x%llx DAR: 0x%llx LLP: 0x%llx BTS 0x%x CTL: 0x%x:%08x", 992 le64_to_cpu(desc->lli->sar), 993 le64_to_cpu(desc->lli->dar), 994 le64_to_cpu(desc->lli->llp), 995 le32_to_cpu(desc->lli->block_ts_lo), 996 le32_to_cpu(desc->lli->ctl_hi), 997 le32_to_cpu(desc->lli->ctl_lo)); 998 } 999 1000 static void axi_chan_list_dump_lli(struct axi_dma_chan *chan, 1001 struct axi_dma_desc *desc_head) 1002 { 1003 int count = atomic_read(&chan->descs_allocated); 1004 int i; 1005 1006 for (i = 0; i < count; i++) 1007 axi_chan_dump_lli(chan, &desc_head->hw_desc[i]); 1008 } 1009 1010 static noinline void axi_chan_handle_err(struct axi_dma_chan *chan, u32 status) 1011 { 1012 struct virt_dma_desc *vd; 1013 unsigned long flags; 1014 1015 spin_lock_irqsave(&chan->vc.lock, flags); 1016 1017 axi_chan_disable(chan); 1018 1019 /* The bad descriptor currently is in the head of vc list */ 1020 vd = vchan_next_desc(&chan->vc); 1021 /* Remove the completed descriptor from issued list */ 1022 list_del(&vd->node); 1023 1024 /* WARN about bad descriptor */ 1025 dev_err(chan2dev(chan), 1026 "Bad descriptor submitted for %s, cookie: %d, irq: 0x%08x\n", 1027 axi_chan_name(chan), vd->tx.cookie, status); 1028 axi_chan_list_dump_lli(chan, vd_to_axi_desc(vd)); 1029 1030 vchan_cookie_complete(vd); 1031 1032 /* Try to restart the controller */ 1033 axi_chan_start_first_queued(chan); 1034 1035 spin_unlock_irqrestore(&chan->vc.lock, flags); 1036 } 1037 1038 static void axi_chan_block_xfer_complete(struct axi_dma_chan *chan) 1039 { 1040 int count = atomic_read(&chan->descs_allocated); 1041 struct axi_dma_hw_desc *hw_desc; 1042 struct axi_dma_desc *desc; 1043 struct virt_dma_desc *vd; 1044 unsigned long flags; 1045 u64 llp; 1046 int i; 1047 1048 spin_lock_irqsave(&chan->vc.lock, flags); 1049 if (unlikely(axi_chan_is_hw_enable(chan))) { 1050 dev_err(chan2dev(chan), "BUG: %s caught DWAXIDMAC_IRQ_DMA_TRF, but channel not idle!\n", 1051 axi_chan_name(chan)); 1052 axi_chan_disable(chan); 1053 } 1054 1055 /* The completed descriptor currently is in the head of vc list */ 1056 vd = vchan_next_desc(&chan->vc); 1057 if (!vd) { 1058 dev_err(chan2dev(chan), "BUG: %s, IRQ with no descriptors\n", 1059 axi_chan_name(chan)); 1060 goto out; 1061 } 1062 1063 if (chan->cyclic) { 1064 desc = vd_to_axi_desc(vd); 1065 if (desc) { 1066 llp = lo_hi_readq(chan->chan_regs + CH_LLP); 1067 for (i = 0; i < count; i++) { 1068 hw_desc = &desc->hw_desc[i]; 1069 if (hw_desc->llp == llp) { 1070 axi_chan_irq_clear(chan, hw_desc->lli->status_lo); 1071 hw_desc->lli->ctl_hi |= CH_CTL_H_LLI_VALID; 1072 desc->completed_blocks = i; 1073 1074 if (((hw_desc->len * (i + 1)) % desc->period_len) == 0) 1075 vchan_cyclic_callback(vd); 1076 break; 1077 } 1078 } 1079 1080 axi_chan_enable(chan); 1081 } 1082 } else { 1083 /* Remove the completed descriptor from issued list before completing */ 1084 list_del(&vd->node); 1085 vchan_cookie_complete(vd); 1086 1087 /* Submit queued descriptors after processing the completed ones */ 1088 axi_chan_start_first_queued(chan); 1089 } 1090 1091 out: 1092 spin_unlock_irqrestore(&chan->vc.lock, flags); 1093 } 1094 1095 static irqreturn_t dw_axi_dma_interrupt(int irq, void *dev_id) 1096 { 1097 struct axi_dma_chip *chip = dev_id; 1098 struct dw_axi_dma *dw = chip->dw; 1099 struct axi_dma_chan *chan; 1100 1101 u32 status, i; 1102 1103 /* Disable DMAC interrupts. We'll enable them after processing channels */ 1104 axi_dma_irq_disable(chip); 1105 1106 /* Poll, clear and process every channel interrupt status */ 1107 for (i = 0; i < dw->hdata->nr_channels; i++) { 1108 chan = &dw->chan[i]; 1109 status = axi_chan_irq_read(chan); 1110 axi_chan_irq_clear(chan, status); 1111 1112 dev_vdbg(chip->dev, "%s %u IRQ status: 0x%08x\n", 1113 axi_chan_name(chan), i, status); 1114 1115 if (status & DWAXIDMAC_IRQ_ALL_ERR) 1116 axi_chan_handle_err(chan, status); 1117 else if (status & DWAXIDMAC_IRQ_DMA_TRF) 1118 axi_chan_block_xfer_complete(chan); 1119 } 1120 1121 /* Re-enable interrupts */ 1122 axi_dma_irq_enable(chip); 1123 1124 return IRQ_HANDLED; 1125 } 1126 1127 static int dma_chan_terminate_all(struct dma_chan *dchan) 1128 { 1129 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); 1130 u32 chan_active = BIT(chan->id) << DMAC_CHAN_EN_SHIFT; 1131 unsigned long flags; 1132 u32 val; 1133 int ret; 1134 LIST_HEAD(head); 1135 1136 axi_chan_disable(chan); 1137 1138 ret = readl_poll_timeout_atomic(chan->chip->regs + DMAC_CHEN, val, 1139 !(val & chan_active), 1000, 10000); 1140 if (ret == -ETIMEDOUT) 1141 dev_warn(dchan2dev(dchan), 1142 "%s failed to stop\n", axi_chan_name(chan)); 1143 1144 if (chan->direction != DMA_MEM_TO_MEM) 1145 dw_axi_dma_set_hw_channel(chan, false); 1146 if (chan->direction == DMA_MEM_TO_DEV) 1147 dw_axi_dma_set_byte_halfword(chan, false); 1148 1149 spin_lock_irqsave(&chan->vc.lock, flags); 1150 1151 vchan_get_all_descriptors(&chan->vc, &head); 1152 1153 chan->cyclic = false; 1154 spin_unlock_irqrestore(&chan->vc.lock, flags); 1155 1156 vchan_dma_desc_free_list(&chan->vc, &head); 1157 1158 dev_vdbg(dchan2dev(dchan), "terminated: %s\n", axi_chan_name(chan)); 1159 1160 return 0; 1161 } 1162 1163 static int dma_chan_pause(struct dma_chan *dchan) 1164 { 1165 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); 1166 unsigned long flags; 1167 unsigned int timeout = 20; /* timeout iterations */ 1168 u32 val; 1169 1170 spin_lock_irqsave(&chan->vc.lock, flags); 1171 1172 if (chan->chip->dw->hdata->reg_map_8_channels) { 1173 val = axi_dma_ioread32(chan->chip, DMAC_CHEN); 1174 val |= BIT(chan->id) << DMAC_CHAN_SUSP_SHIFT | 1175 BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT; 1176 axi_dma_iowrite32(chan->chip, DMAC_CHEN, val); 1177 } else { 1178 val = axi_dma_ioread32(chan->chip, DMAC_CHSUSPREG); 1179 val |= BIT(chan->id) << DMAC_CHAN_SUSP2_SHIFT | 1180 BIT(chan->id) << DMAC_CHAN_SUSP2_WE_SHIFT; 1181 axi_dma_iowrite32(chan->chip, DMAC_CHSUSPREG, val); 1182 } 1183 1184 do { 1185 if (axi_chan_irq_read(chan) & DWAXIDMAC_IRQ_SUSPENDED) 1186 break; 1187 1188 udelay(2); 1189 } while (--timeout); 1190 1191 axi_chan_irq_clear(chan, DWAXIDMAC_IRQ_SUSPENDED); 1192 1193 chan->is_paused = true; 1194 1195 spin_unlock_irqrestore(&chan->vc.lock, flags); 1196 1197 return timeout ? 0 : -EAGAIN; 1198 } 1199 1200 /* Called in chan locked context */ 1201 static inline void axi_chan_resume(struct axi_dma_chan *chan) 1202 { 1203 u32 val; 1204 1205 if (chan->chip->dw->hdata->reg_map_8_channels) { 1206 val = axi_dma_ioread32(chan->chip, DMAC_CHEN); 1207 val &= ~(BIT(chan->id) << DMAC_CHAN_SUSP_SHIFT); 1208 val |= (BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT); 1209 axi_dma_iowrite32(chan->chip, DMAC_CHEN, val); 1210 } else { 1211 val = axi_dma_ioread32(chan->chip, DMAC_CHSUSPREG); 1212 val &= ~(BIT(chan->id) << DMAC_CHAN_SUSP2_SHIFT); 1213 val |= (BIT(chan->id) << DMAC_CHAN_SUSP2_WE_SHIFT); 1214 axi_dma_iowrite32(chan->chip, DMAC_CHSUSPREG, val); 1215 } 1216 1217 chan->is_paused = false; 1218 } 1219 1220 static int dma_chan_resume(struct dma_chan *dchan) 1221 { 1222 struct axi_dma_chan *chan = dchan_to_axi_dma_chan(dchan); 1223 unsigned long flags; 1224 1225 spin_lock_irqsave(&chan->vc.lock, flags); 1226 1227 if (chan->is_paused) 1228 axi_chan_resume(chan); 1229 1230 spin_unlock_irqrestore(&chan->vc.lock, flags); 1231 1232 return 0; 1233 } 1234 1235 static int axi_dma_suspend(struct axi_dma_chip *chip) 1236 { 1237 axi_dma_irq_disable(chip); 1238 axi_dma_disable(chip); 1239 1240 clk_disable_unprepare(chip->core_clk); 1241 clk_disable_unprepare(chip->cfgr_clk); 1242 1243 return 0; 1244 } 1245 1246 static int axi_dma_resume(struct axi_dma_chip *chip) 1247 { 1248 int ret; 1249 1250 ret = clk_prepare_enable(chip->cfgr_clk); 1251 if (ret < 0) 1252 return ret; 1253 1254 ret = clk_prepare_enable(chip->core_clk); 1255 if (ret < 0) 1256 return ret; 1257 1258 axi_dma_enable(chip); 1259 axi_dma_irq_enable(chip); 1260 1261 return 0; 1262 } 1263 1264 static int __maybe_unused axi_dma_runtime_suspend(struct device *dev) 1265 { 1266 struct axi_dma_chip *chip = dev_get_drvdata(dev); 1267 1268 return axi_dma_suspend(chip); 1269 } 1270 1271 static int __maybe_unused axi_dma_runtime_resume(struct device *dev) 1272 { 1273 struct axi_dma_chip *chip = dev_get_drvdata(dev); 1274 1275 return axi_dma_resume(chip); 1276 } 1277 1278 static struct dma_chan *dw_axi_dma_of_xlate(struct of_phandle_args *dma_spec, 1279 struct of_dma *ofdma) 1280 { 1281 struct dw_axi_dma *dw = ofdma->of_dma_data; 1282 struct axi_dma_chan *chan; 1283 struct dma_chan *dchan; 1284 1285 dchan = dma_get_any_slave_channel(&dw->dma); 1286 if (!dchan) 1287 return NULL; 1288 1289 chan = dchan_to_axi_dma_chan(dchan); 1290 chan->hw_handshake_num = dma_spec->args[0]; 1291 return dchan; 1292 } 1293 1294 static int parse_device_properties(struct axi_dma_chip *chip) 1295 { 1296 struct device *dev = chip->dev; 1297 u32 tmp, carr[DMAC_MAX_CHANNELS]; 1298 int ret; 1299 1300 ret = device_property_read_u32(dev, "dma-channels", &tmp); 1301 if (ret) 1302 return ret; 1303 if (tmp == 0 || tmp > DMAC_MAX_CHANNELS) 1304 return -EINVAL; 1305 1306 chip->dw->hdata->nr_channels = tmp; 1307 if (tmp <= DMA_REG_MAP_CH_REF) 1308 chip->dw->hdata->reg_map_8_channels = true; 1309 1310 ret = device_property_read_u32(dev, "snps,dma-masters", &tmp); 1311 if (ret) 1312 return ret; 1313 if (tmp == 0 || tmp > DMAC_MAX_MASTERS) 1314 return -EINVAL; 1315 1316 chip->dw->hdata->nr_masters = tmp; 1317 1318 ret = device_property_read_u32(dev, "snps,data-width", &tmp); 1319 if (ret) 1320 return ret; 1321 if (tmp > DWAXIDMAC_TRANS_WIDTH_MAX) 1322 return -EINVAL; 1323 1324 chip->dw->hdata->m_data_width = tmp; 1325 1326 ret = device_property_read_u32_array(dev, "snps,block-size", carr, 1327 chip->dw->hdata->nr_channels); 1328 if (ret) 1329 return ret; 1330 for (tmp = 0; tmp < chip->dw->hdata->nr_channels; tmp++) { 1331 if (carr[tmp] == 0 || carr[tmp] > DMAC_MAX_BLK_SIZE) 1332 return -EINVAL; 1333 1334 chip->dw->hdata->block_size[tmp] = carr[tmp]; 1335 } 1336 1337 ret = device_property_read_u32_array(dev, "snps,priority", carr, 1338 chip->dw->hdata->nr_channels); 1339 if (ret) 1340 return ret; 1341 /* Priority value must be programmed within [0:nr_channels-1] range */ 1342 for (tmp = 0; tmp < chip->dw->hdata->nr_channels; tmp++) { 1343 if (carr[tmp] >= chip->dw->hdata->nr_channels) 1344 return -EINVAL; 1345 1346 chip->dw->hdata->priority[tmp] = carr[tmp]; 1347 } 1348 1349 /* axi-max-burst-len is optional property */ 1350 ret = device_property_read_u32(dev, "snps,axi-max-burst-len", &tmp); 1351 if (!ret) { 1352 if (tmp > DWAXIDMAC_ARWLEN_MAX + 1) 1353 return -EINVAL; 1354 if (tmp < DWAXIDMAC_ARWLEN_MIN + 1) 1355 return -EINVAL; 1356 1357 chip->dw->hdata->restrict_axi_burst_len = true; 1358 chip->dw->hdata->axi_rw_burst_len = tmp; 1359 } 1360 1361 return 0; 1362 } 1363 1364 static int dw_probe(struct platform_device *pdev) 1365 { 1366 struct device_node *node = pdev->dev.of_node; 1367 struct axi_dma_chip *chip; 1368 struct resource *mem; 1369 struct dw_axi_dma *dw; 1370 struct dw_axi_dma_hcfg *hdata; 1371 u32 i; 1372 int ret; 1373 1374 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 1375 if (!chip) 1376 return -ENOMEM; 1377 1378 dw = devm_kzalloc(&pdev->dev, sizeof(*dw), GFP_KERNEL); 1379 if (!dw) 1380 return -ENOMEM; 1381 1382 hdata = devm_kzalloc(&pdev->dev, sizeof(*hdata), GFP_KERNEL); 1383 if (!hdata) 1384 return -ENOMEM; 1385 1386 chip->dw = dw; 1387 chip->dev = &pdev->dev; 1388 chip->dw->hdata = hdata; 1389 1390 chip->irq = platform_get_irq(pdev, 0); 1391 if (chip->irq < 0) 1392 return chip->irq; 1393 1394 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1395 chip->regs = devm_ioremap_resource(chip->dev, mem); 1396 if (IS_ERR(chip->regs)) 1397 return PTR_ERR(chip->regs); 1398 1399 if (of_device_is_compatible(node, "intel,kmb-axi-dma")) { 1400 chip->apb_regs = devm_platform_ioremap_resource(pdev, 1); 1401 if (IS_ERR(chip->apb_regs)) 1402 return PTR_ERR(chip->apb_regs); 1403 } 1404 1405 chip->core_clk = devm_clk_get(chip->dev, "core-clk"); 1406 if (IS_ERR(chip->core_clk)) 1407 return PTR_ERR(chip->core_clk); 1408 1409 chip->cfgr_clk = devm_clk_get(chip->dev, "cfgr-clk"); 1410 if (IS_ERR(chip->cfgr_clk)) 1411 return PTR_ERR(chip->cfgr_clk); 1412 1413 ret = parse_device_properties(chip); 1414 if (ret) 1415 return ret; 1416 1417 dw->chan = devm_kcalloc(chip->dev, hdata->nr_channels, 1418 sizeof(*dw->chan), GFP_KERNEL); 1419 if (!dw->chan) 1420 return -ENOMEM; 1421 1422 ret = devm_request_irq(chip->dev, chip->irq, dw_axi_dma_interrupt, 1423 IRQF_SHARED, KBUILD_MODNAME, chip); 1424 if (ret) 1425 return ret; 1426 1427 INIT_LIST_HEAD(&dw->dma.channels); 1428 for (i = 0; i < hdata->nr_channels; i++) { 1429 struct axi_dma_chan *chan = &dw->chan[i]; 1430 1431 chan->chip = chip; 1432 chan->id = i; 1433 chan->chan_regs = chip->regs + COMMON_REG_LEN + i * CHAN_REG_LEN; 1434 atomic_set(&chan->descs_allocated, 0); 1435 1436 chan->vc.desc_free = vchan_desc_put; 1437 vchan_init(&chan->vc, &dw->dma); 1438 } 1439 1440 /* Set capabilities */ 1441 dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask); 1442 dma_cap_set(DMA_SLAVE, dw->dma.cap_mask); 1443 dma_cap_set(DMA_CYCLIC, dw->dma.cap_mask); 1444 1445 /* DMA capabilities */ 1446 dw->dma.chancnt = hdata->nr_channels; 1447 dw->dma.max_burst = hdata->axi_rw_burst_len; 1448 dw->dma.src_addr_widths = AXI_DMA_BUSWIDTHS; 1449 dw->dma.dst_addr_widths = AXI_DMA_BUSWIDTHS; 1450 dw->dma.directions = BIT(DMA_MEM_TO_MEM); 1451 dw->dma.directions |= BIT(DMA_MEM_TO_DEV) | BIT(DMA_DEV_TO_MEM); 1452 dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; 1453 1454 dw->dma.dev = chip->dev; 1455 dw->dma.device_tx_status = dma_chan_tx_status; 1456 dw->dma.device_issue_pending = dma_chan_issue_pending; 1457 dw->dma.device_terminate_all = dma_chan_terminate_all; 1458 dw->dma.device_pause = dma_chan_pause; 1459 dw->dma.device_resume = dma_chan_resume; 1460 1461 dw->dma.device_alloc_chan_resources = dma_chan_alloc_chan_resources; 1462 dw->dma.device_free_chan_resources = dma_chan_free_chan_resources; 1463 1464 dw->dma.device_prep_dma_memcpy = dma_chan_prep_dma_memcpy; 1465 dw->dma.device_synchronize = dw_axi_dma_synchronize; 1466 dw->dma.device_config = dw_axi_dma_chan_slave_config; 1467 dw->dma.device_prep_slave_sg = dw_axi_dma_chan_prep_slave_sg; 1468 dw->dma.device_prep_dma_cyclic = dw_axi_dma_chan_prep_cyclic; 1469 1470 /* 1471 * Synopsis DesignWare AxiDMA datasheet mentioned Maximum 1472 * supported blocks is 1024. Device register width is 4 bytes. 1473 * Therefore, set constraint to 1024 * 4. 1474 */ 1475 dw->dma.dev->dma_parms = &dw->dma_parms; 1476 dma_set_max_seg_size(&pdev->dev, MAX_BLOCK_SIZE); 1477 platform_set_drvdata(pdev, chip); 1478 1479 pm_runtime_enable(chip->dev); 1480 1481 /* 1482 * We can't just call pm_runtime_get here instead of 1483 * pm_runtime_get_noresume + axi_dma_resume because we need 1484 * driver to work also without Runtime PM. 1485 */ 1486 pm_runtime_get_noresume(chip->dev); 1487 ret = axi_dma_resume(chip); 1488 if (ret < 0) 1489 goto err_pm_disable; 1490 1491 axi_dma_hw_init(chip); 1492 1493 pm_runtime_put(chip->dev); 1494 1495 ret = dmaenginem_async_device_register(&dw->dma); 1496 if (ret) 1497 goto err_pm_disable; 1498 1499 /* Register with OF helpers for DMA lookups */ 1500 ret = of_dma_controller_register(pdev->dev.of_node, 1501 dw_axi_dma_of_xlate, dw); 1502 if (ret < 0) 1503 dev_warn(&pdev->dev, 1504 "Failed to register OF DMA controller, fallback to MEM_TO_MEM mode\n"); 1505 1506 dev_info(chip->dev, "DesignWare AXI DMA Controller, %d channels\n", 1507 dw->hdata->nr_channels); 1508 1509 return 0; 1510 1511 err_pm_disable: 1512 pm_runtime_disable(chip->dev); 1513 1514 return ret; 1515 } 1516 1517 static int dw_remove(struct platform_device *pdev) 1518 { 1519 struct axi_dma_chip *chip = platform_get_drvdata(pdev); 1520 struct dw_axi_dma *dw = chip->dw; 1521 struct axi_dma_chan *chan, *_chan; 1522 u32 i; 1523 1524 /* Enable clk before accessing to registers */ 1525 clk_prepare_enable(chip->cfgr_clk); 1526 clk_prepare_enable(chip->core_clk); 1527 axi_dma_irq_disable(chip); 1528 for (i = 0; i < dw->hdata->nr_channels; i++) { 1529 axi_chan_disable(&chip->dw->chan[i]); 1530 axi_chan_irq_disable(&chip->dw->chan[i], DWAXIDMAC_IRQ_ALL); 1531 } 1532 axi_dma_disable(chip); 1533 1534 pm_runtime_disable(chip->dev); 1535 axi_dma_suspend(chip); 1536 1537 devm_free_irq(chip->dev, chip->irq, chip); 1538 1539 of_dma_controller_free(chip->dev->of_node); 1540 1541 list_for_each_entry_safe(chan, _chan, &dw->dma.channels, 1542 vc.chan.device_node) { 1543 list_del(&chan->vc.chan.device_node); 1544 tasklet_kill(&chan->vc.task); 1545 } 1546 1547 return 0; 1548 } 1549 1550 static const struct dev_pm_ops dw_axi_dma_pm_ops = { 1551 SET_RUNTIME_PM_OPS(axi_dma_runtime_suspend, axi_dma_runtime_resume, NULL) 1552 }; 1553 1554 static const struct of_device_id dw_dma_of_id_table[] = { 1555 { .compatible = "snps,axi-dma-1.01a" }, 1556 { .compatible = "intel,kmb-axi-dma" }, 1557 {} 1558 }; 1559 MODULE_DEVICE_TABLE(of, dw_dma_of_id_table); 1560 1561 static struct platform_driver dw_driver = { 1562 .probe = dw_probe, 1563 .remove = dw_remove, 1564 .driver = { 1565 .name = KBUILD_MODNAME, 1566 .of_match_table = dw_dma_of_id_table, 1567 .pm = &dw_axi_dma_pm_ops, 1568 }, 1569 }; 1570 module_platform_driver(dw_driver); 1571 1572 MODULE_LICENSE("GPL v2"); 1573 MODULE_DESCRIPTION("Synopsys DesignWare AXI DMA Controller platform driver"); 1574 MODULE_AUTHOR("Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>"); 1575