xref: /openbmc/linux/drivers/dma/dmatest.c (revision f1432cd2)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * DMA Engine test module
4  *
5  * Copyright (C) 2007 Atmel Corporation
6  * Copyright (C) 2013 Intel Corporation
7  */
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9 
10 #include <linux/err.h>
11 #include <linux/delay.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/dmaengine.h>
14 #include <linux/freezer.h>
15 #include <linux/init.h>
16 #include <linux/kthread.h>
17 #include <linux/sched/task.h>
18 #include <linux/module.h>
19 #include <linux/moduleparam.h>
20 #include <linux/random.h>
21 #include <linux/slab.h>
22 #include <linux/wait.h>
23 
24 static unsigned int test_buf_size = 16384;
25 module_param(test_buf_size, uint, S_IRUGO | S_IWUSR);
26 MODULE_PARM_DESC(test_buf_size, "Size of the memcpy test buffer");
27 
28 static char test_device[32];
29 module_param_string(device, test_device, sizeof(test_device),
30 		S_IRUGO | S_IWUSR);
31 MODULE_PARM_DESC(device, "Bus ID of the DMA Engine to test (default: any)");
32 
33 static unsigned int threads_per_chan = 1;
34 module_param(threads_per_chan, uint, S_IRUGO | S_IWUSR);
35 MODULE_PARM_DESC(threads_per_chan,
36 		"Number of threads to start per channel (default: 1)");
37 
38 static unsigned int max_channels;
39 module_param(max_channels, uint, S_IRUGO | S_IWUSR);
40 MODULE_PARM_DESC(max_channels,
41 		"Maximum number of channels to use (default: all)");
42 
43 static unsigned int iterations;
44 module_param(iterations, uint, S_IRUGO | S_IWUSR);
45 MODULE_PARM_DESC(iterations,
46 		"Iterations before stopping test (default: infinite)");
47 
48 static unsigned int dmatest;
49 module_param(dmatest, uint, S_IRUGO | S_IWUSR);
50 MODULE_PARM_DESC(dmatest,
51 		"dmatest 0-memcpy 1-memset (default: 0)");
52 
53 static unsigned int xor_sources = 3;
54 module_param(xor_sources, uint, S_IRUGO | S_IWUSR);
55 MODULE_PARM_DESC(xor_sources,
56 		"Number of xor source buffers (default: 3)");
57 
58 static unsigned int pq_sources = 3;
59 module_param(pq_sources, uint, S_IRUGO | S_IWUSR);
60 MODULE_PARM_DESC(pq_sources,
61 		"Number of p+q source buffers (default: 3)");
62 
63 static int timeout = 3000;
64 module_param(timeout, int, S_IRUGO | S_IWUSR);
65 MODULE_PARM_DESC(timeout, "Transfer Timeout in msec (default: 3000), "
66 		 "Pass -1 for infinite timeout");
67 
68 static bool noverify;
69 module_param(noverify, bool, S_IRUGO | S_IWUSR);
70 MODULE_PARM_DESC(noverify, "Disable data verification (default: verify)");
71 
72 static bool norandom;
73 module_param(norandom, bool, 0644);
74 MODULE_PARM_DESC(norandom, "Disable random offset setup (default: random)");
75 
76 static bool verbose;
77 module_param(verbose, bool, S_IRUGO | S_IWUSR);
78 MODULE_PARM_DESC(verbose, "Enable \"success\" result messages (default: off)");
79 
80 static int alignment = -1;
81 module_param(alignment, int, 0644);
82 MODULE_PARM_DESC(alignment, "Custom data address alignment taken as 2^(alignment) (default: not used (-1))");
83 
84 static unsigned int transfer_size;
85 module_param(transfer_size, uint, 0644);
86 MODULE_PARM_DESC(transfer_size, "Optional custom transfer size in bytes (default: not used (0))");
87 
88 static bool polled;
89 module_param(polled, bool, S_IRUGO | S_IWUSR);
90 MODULE_PARM_DESC(polled, "Use polling for completion instead of interrupts");
91 
92 /**
93  * struct dmatest_params - test parameters.
94  * @buf_size:		size of the memcpy test buffer
95  * @channel:		bus ID of the channel to test
96  * @device:		bus ID of the DMA Engine to test
97  * @threads_per_chan:	number of threads to start per channel
98  * @max_channels:	maximum number of channels to use
99  * @iterations:		iterations before stopping test
100  * @xor_sources:	number of xor source buffers
101  * @pq_sources:		number of p+q source buffers
102  * @timeout:		transfer timeout in msec, -1 for infinite timeout
103  * @noverify:		disable data verification
104  * @norandom:		disable random offset setup
105  * @alignment:		custom data address alignment taken as 2^alignment
106  * @transfer_size:	custom transfer size in bytes
107  * @polled:		use polling for completion instead of interrupts
108  */
109 struct dmatest_params {
110 	unsigned int	buf_size;
111 	char		channel[20];
112 	char		device[32];
113 	unsigned int	threads_per_chan;
114 	unsigned int	max_channels;
115 	unsigned int	iterations;
116 	unsigned int	xor_sources;
117 	unsigned int	pq_sources;
118 	int		timeout;
119 	bool		noverify;
120 	bool		norandom;
121 	int		alignment;
122 	unsigned int	transfer_size;
123 	bool		polled;
124 };
125 
126 /**
127  * struct dmatest_info - test information.
128  * @params:		test parameters
129  * @channels:		channels under test
130  * @nr_channels:	number of channels under test
131  * @lock:		access protection to the fields of this structure
132  * @did_init:		module has been initialized completely
133  * @last_error:		test has faced configuration issues
134  */
135 static struct dmatest_info {
136 	/* Test parameters */
137 	struct dmatest_params	params;
138 
139 	/* Internal state */
140 	struct list_head	channels;
141 	unsigned int		nr_channels;
142 	int			last_error;
143 	struct mutex		lock;
144 	bool			did_init;
145 } test_info = {
146 	.channels = LIST_HEAD_INIT(test_info.channels),
147 	.lock = __MUTEX_INITIALIZER(test_info.lock),
148 };
149 
150 static int dmatest_run_set(const char *val, const struct kernel_param *kp);
151 static int dmatest_run_get(char *val, const struct kernel_param *kp);
152 static const struct kernel_param_ops run_ops = {
153 	.set = dmatest_run_set,
154 	.get = dmatest_run_get,
155 };
156 static bool dmatest_run;
157 module_param_cb(run, &run_ops, &dmatest_run, S_IRUGO | S_IWUSR);
158 MODULE_PARM_DESC(run, "Run the test (default: false)");
159 
160 static int dmatest_chan_set(const char *val, const struct kernel_param *kp);
161 static int dmatest_chan_get(char *val, const struct kernel_param *kp);
162 static const struct kernel_param_ops multi_chan_ops = {
163 	.set = dmatest_chan_set,
164 	.get = dmatest_chan_get,
165 };
166 
167 static char test_channel[20];
168 static struct kparam_string newchan_kps = {
169 	.string = test_channel,
170 	.maxlen = 20,
171 };
172 module_param_cb(channel, &multi_chan_ops, &newchan_kps, 0644);
173 MODULE_PARM_DESC(channel, "Bus ID of the channel to test (default: any)");
174 
175 static int dmatest_test_list_get(char *val, const struct kernel_param *kp);
176 static const struct kernel_param_ops test_list_ops = {
177 	.get = dmatest_test_list_get,
178 };
179 module_param_cb(test_list, &test_list_ops, NULL, 0444);
180 MODULE_PARM_DESC(test_list, "Print current test list");
181 
182 /* Maximum amount of mismatched bytes in buffer to print */
183 #define MAX_ERROR_COUNT		32
184 
185 /*
186  * Initialization patterns. All bytes in the source buffer has bit 7
187  * set, all bytes in the destination buffer has bit 7 cleared.
188  *
189  * Bit 6 is set for all bytes which are to be copied by the DMA
190  * engine. Bit 5 is set for all bytes which are to be overwritten by
191  * the DMA engine.
192  *
193  * The remaining bits are the inverse of a counter which increments by
194  * one for each byte address.
195  */
196 #define PATTERN_SRC		0x80
197 #define PATTERN_DST		0x00
198 #define PATTERN_COPY		0x40
199 #define PATTERN_OVERWRITE	0x20
200 #define PATTERN_COUNT_MASK	0x1f
201 #define PATTERN_MEMSET_IDX	0x01
202 
203 /* Fixed point arithmetic ops */
204 #define FIXPT_SHIFT		8
205 #define FIXPNT_MASK		0xFF
206 #define FIXPT_TO_INT(a)	((a) >> FIXPT_SHIFT)
207 #define INT_TO_FIXPT(a)	((a) << FIXPT_SHIFT)
208 #define FIXPT_GET_FRAC(a)	((((a) & FIXPNT_MASK) * 100) >> FIXPT_SHIFT)
209 
210 /* poor man's completion - we want to use wait_event_freezable() on it */
211 struct dmatest_done {
212 	bool			done;
213 	wait_queue_head_t	*wait;
214 };
215 
216 struct dmatest_data {
217 	u8		**raw;
218 	u8		**aligned;
219 	unsigned int	cnt;
220 	unsigned int	off;
221 };
222 
223 struct dmatest_thread {
224 	struct list_head	node;
225 	struct dmatest_info	*info;
226 	struct task_struct	*task;
227 	struct dma_chan		*chan;
228 	struct dmatest_data	src;
229 	struct dmatest_data	dst;
230 	enum dma_transaction_type type;
231 	wait_queue_head_t done_wait;
232 	struct dmatest_done test_done;
233 	bool			done;
234 	bool			pending;
235 };
236 
237 struct dmatest_chan {
238 	struct list_head	node;
239 	struct dma_chan		*chan;
240 	struct list_head	threads;
241 };
242 
243 static DECLARE_WAIT_QUEUE_HEAD(thread_wait);
244 static bool wait;
245 
246 static bool is_threaded_test_run(struct dmatest_info *info)
247 {
248 	struct dmatest_chan *dtc;
249 
250 	list_for_each_entry(dtc, &info->channels, node) {
251 		struct dmatest_thread *thread;
252 
253 		list_for_each_entry(thread, &dtc->threads, node) {
254 			if (!thread->done && !thread->pending)
255 				return true;
256 		}
257 	}
258 
259 	return false;
260 }
261 
262 static bool is_threaded_test_pending(struct dmatest_info *info)
263 {
264 	struct dmatest_chan *dtc;
265 
266 	list_for_each_entry(dtc, &info->channels, node) {
267 		struct dmatest_thread *thread;
268 
269 		list_for_each_entry(thread, &dtc->threads, node) {
270 			if (thread->pending)
271 				return true;
272 		}
273 	}
274 
275 	return false;
276 }
277 
278 static int dmatest_wait_get(char *val, const struct kernel_param *kp)
279 {
280 	struct dmatest_info *info = &test_info;
281 	struct dmatest_params *params = &info->params;
282 
283 	if (params->iterations)
284 		wait_event(thread_wait, !is_threaded_test_run(info));
285 	wait = true;
286 	return param_get_bool(val, kp);
287 }
288 
289 static const struct kernel_param_ops wait_ops = {
290 	.get = dmatest_wait_get,
291 	.set = param_set_bool,
292 };
293 module_param_cb(wait, &wait_ops, &wait, S_IRUGO);
294 MODULE_PARM_DESC(wait, "Wait for tests to complete (default: false)");
295 
296 static bool dmatest_match_channel(struct dmatest_params *params,
297 		struct dma_chan *chan)
298 {
299 	if (params->channel[0] == '\0')
300 		return true;
301 	return strcmp(dma_chan_name(chan), params->channel) == 0;
302 }
303 
304 static bool dmatest_match_device(struct dmatest_params *params,
305 		struct dma_device *device)
306 {
307 	if (params->device[0] == '\0')
308 		return true;
309 	return strcmp(dev_name(device->dev), params->device) == 0;
310 }
311 
312 static unsigned long dmatest_random(void)
313 {
314 	unsigned long buf;
315 
316 	prandom_bytes(&buf, sizeof(buf));
317 	return buf;
318 }
319 
320 static inline u8 gen_inv_idx(u8 index, bool is_memset)
321 {
322 	u8 val = is_memset ? PATTERN_MEMSET_IDX : index;
323 
324 	return ~val & PATTERN_COUNT_MASK;
325 }
326 
327 static inline u8 gen_src_value(u8 index, bool is_memset)
328 {
329 	return PATTERN_SRC | gen_inv_idx(index, is_memset);
330 }
331 
332 static inline u8 gen_dst_value(u8 index, bool is_memset)
333 {
334 	return PATTERN_DST | gen_inv_idx(index, is_memset);
335 }
336 
337 static void dmatest_init_srcs(u8 **bufs, unsigned int start, unsigned int len,
338 		unsigned int buf_size, bool is_memset)
339 {
340 	unsigned int i;
341 	u8 *buf;
342 
343 	for (; (buf = *bufs); bufs++) {
344 		for (i = 0; i < start; i++)
345 			buf[i] = gen_src_value(i, is_memset);
346 		for ( ; i < start + len; i++)
347 			buf[i] = gen_src_value(i, is_memset) | PATTERN_COPY;
348 		for ( ; i < buf_size; i++)
349 			buf[i] = gen_src_value(i, is_memset);
350 		buf++;
351 	}
352 }
353 
354 static void dmatest_init_dsts(u8 **bufs, unsigned int start, unsigned int len,
355 		unsigned int buf_size, bool is_memset)
356 {
357 	unsigned int i;
358 	u8 *buf;
359 
360 	for (; (buf = *bufs); bufs++) {
361 		for (i = 0; i < start; i++)
362 			buf[i] = gen_dst_value(i, is_memset);
363 		for ( ; i < start + len; i++)
364 			buf[i] = gen_dst_value(i, is_memset) |
365 						PATTERN_OVERWRITE;
366 		for ( ; i < buf_size; i++)
367 			buf[i] = gen_dst_value(i, is_memset);
368 	}
369 }
370 
371 static void dmatest_mismatch(u8 actual, u8 pattern, unsigned int index,
372 		unsigned int counter, bool is_srcbuf, bool is_memset)
373 {
374 	u8		diff = actual ^ pattern;
375 	u8		expected = pattern | gen_inv_idx(counter, is_memset);
376 	const char	*thread_name = current->comm;
377 
378 	if (is_srcbuf)
379 		pr_warn("%s: srcbuf[0x%x] overwritten! Expected %02x, got %02x\n",
380 			thread_name, index, expected, actual);
381 	else if ((pattern & PATTERN_COPY)
382 			&& (diff & (PATTERN_COPY | PATTERN_OVERWRITE)))
383 		pr_warn("%s: dstbuf[0x%x] not copied! Expected %02x, got %02x\n",
384 			thread_name, index, expected, actual);
385 	else if (diff & PATTERN_SRC)
386 		pr_warn("%s: dstbuf[0x%x] was copied! Expected %02x, got %02x\n",
387 			thread_name, index, expected, actual);
388 	else
389 		pr_warn("%s: dstbuf[0x%x] mismatch! Expected %02x, got %02x\n",
390 			thread_name, index, expected, actual);
391 }
392 
393 static unsigned int dmatest_verify(u8 **bufs, unsigned int start,
394 		unsigned int end, unsigned int counter, u8 pattern,
395 		bool is_srcbuf, bool is_memset)
396 {
397 	unsigned int i;
398 	unsigned int error_count = 0;
399 	u8 actual;
400 	u8 expected;
401 	u8 *buf;
402 	unsigned int counter_orig = counter;
403 
404 	for (; (buf = *bufs); bufs++) {
405 		counter = counter_orig;
406 		for (i = start; i < end; i++) {
407 			actual = buf[i];
408 			expected = pattern | gen_inv_idx(counter, is_memset);
409 			if (actual != expected) {
410 				if (error_count < MAX_ERROR_COUNT)
411 					dmatest_mismatch(actual, pattern, i,
412 							 counter, is_srcbuf,
413 							 is_memset);
414 				error_count++;
415 			}
416 			counter++;
417 		}
418 	}
419 
420 	if (error_count > MAX_ERROR_COUNT)
421 		pr_warn("%s: %u errors suppressed\n",
422 			current->comm, error_count - MAX_ERROR_COUNT);
423 
424 	return error_count;
425 }
426 
427 
428 static void dmatest_callback(void *arg)
429 {
430 	struct dmatest_done *done = arg;
431 	struct dmatest_thread *thread =
432 		container_of(done, struct dmatest_thread, test_done);
433 	if (!thread->done) {
434 		done->done = true;
435 		wake_up_all(done->wait);
436 	} else {
437 		/*
438 		 * If thread->done, it means that this callback occurred
439 		 * after the parent thread has cleaned up. This can
440 		 * happen in the case that driver doesn't implement
441 		 * the terminate_all() functionality and a dma operation
442 		 * did not occur within the timeout period
443 		 */
444 		WARN(1, "dmatest: Kernel memory may be corrupted!!\n");
445 	}
446 }
447 
448 static unsigned int min_odd(unsigned int x, unsigned int y)
449 {
450 	unsigned int val = min(x, y);
451 
452 	return val % 2 ? val : val - 1;
453 }
454 
455 static void result(const char *err, unsigned int n, unsigned int src_off,
456 		   unsigned int dst_off, unsigned int len, unsigned long data)
457 {
458 	if (IS_ERR_VALUE(data)) {
459 		pr_info("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%ld)\n",
460 			current->comm, n, err, src_off, dst_off, len, data);
461 	} else {
462 		pr_info("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n",
463 			current->comm, n, err, src_off, dst_off, len, data);
464 	}
465 }
466 
467 static void dbg_result(const char *err, unsigned int n, unsigned int src_off,
468 		       unsigned int dst_off, unsigned int len,
469 		       unsigned long data)
470 {
471 	pr_debug("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n",
472 		 current->comm, n, err, src_off, dst_off, len, data);
473 }
474 
475 #define verbose_result(err, n, src_off, dst_off, len, data) ({	\
476 	if (verbose)						\
477 		result(err, n, src_off, dst_off, len, data);	\
478 	else							\
479 		dbg_result(err, n, src_off, dst_off, len, data);\
480 })
481 
482 static unsigned long long dmatest_persec(s64 runtime, unsigned int val)
483 {
484 	unsigned long long per_sec = 1000000;
485 
486 	if (runtime <= 0)
487 		return 0;
488 
489 	/* drop precision until runtime is 32-bits */
490 	while (runtime > UINT_MAX) {
491 		runtime >>= 1;
492 		per_sec <<= 1;
493 	}
494 
495 	per_sec *= val;
496 	per_sec = INT_TO_FIXPT(per_sec);
497 	do_div(per_sec, runtime);
498 
499 	return per_sec;
500 }
501 
502 static unsigned long long dmatest_KBs(s64 runtime, unsigned long long len)
503 {
504 	return FIXPT_TO_INT(dmatest_persec(runtime, len >> 10));
505 }
506 
507 static void __dmatest_free_test_data(struct dmatest_data *d, unsigned int cnt)
508 {
509 	unsigned int i;
510 
511 	for (i = 0; i < cnt; i++)
512 		kfree(d->raw[i]);
513 
514 	kfree(d->aligned);
515 	kfree(d->raw);
516 }
517 
518 static void dmatest_free_test_data(struct dmatest_data *d)
519 {
520 	__dmatest_free_test_data(d, d->cnt);
521 }
522 
523 static int dmatest_alloc_test_data(struct dmatest_data *d,
524 		unsigned int buf_size, u8 align)
525 {
526 	unsigned int i = 0;
527 
528 	d->raw = kcalloc(d->cnt + 1, sizeof(u8 *), GFP_KERNEL);
529 	if (!d->raw)
530 		return -ENOMEM;
531 
532 	d->aligned = kcalloc(d->cnt + 1, sizeof(u8 *), GFP_KERNEL);
533 	if (!d->aligned)
534 		goto err;
535 
536 	for (i = 0; i < d->cnt; i++) {
537 		d->raw[i] = kmalloc(buf_size + align, GFP_KERNEL);
538 		if (!d->raw[i])
539 			goto err;
540 
541 		/* align to alignment restriction */
542 		if (align)
543 			d->aligned[i] = PTR_ALIGN(d->raw[i], align);
544 		else
545 			d->aligned[i] = d->raw[i];
546 	}
547 
548 	return 0;
549 err:
550 	__dmatest_free_test_data(d, i);
551 	return -ENOMEM;
552 }
553 
554 /*
555  * This function repeatedly tests DMA transfers of various lengths and
556  * offsets for a given operation type until it is told to exit by
557  * kthread_stop(). There may be multiple threads running this function
558  * in parallel for a single channel, and there may be multiple channels
559  * being tested in parallel.
560  *
561  * Before each test, the source and destination buffer is initialized
562  * with a known pattern. This pattern is different depending on
563  * whether it's in an area which is supposed to be copied or
564  * overwritten, and different in the source and destination buffers.
565  * So if the DMA engine doesn't copy exactly what we tell it to copy,
566  * we'll notice.
567  */
568 static int dmatest_func(void *data)
569 {
570 	struct dmatest_thread	*thread = data;
571 	struct dmatest_done	*done = &thread->test_done;
572 	struct dmatest_info	*info;
573 	struct dmatest_params	*params;
574 	struct dma_chan		*chan;
575 	struct dma_device	*dev;
576 	struct device		*dma_dev;
577 	unsigned int		error_count;
578 	unsigned int		failed_tests = 0;
579 	unsigned int		total_tests = 0;
580 	dma_cookie_t		cookie;
581 	enum dma_status		status;
582 	enum dma_ctrl_flags 	flags;
583 	u8			*pq_coefs = NULL;
584 	int			ret;
585 	unsigned int 		buf_size;
586 	struct dmatest_data	*src;
587 	struct dmatest_data	*dst;
588 	int			i;
589 	ktime_t			ktime, start, diff;
590 	ktime_t			filltime = 0;
591 	ktime_t			comparetime = 0;
592 	s64			runtime = 0;
593 	unsigned long long	total_len = 0;
594 	unsigned long long	iops = 0;
595 	u8			align = 0;
596 	bool			is_memset = false;
597 	dma_addr_t		*srcs;
598 	dma_addr_t		*dma_pq;
599 
600 	set_freezable();
601 
602 	ret = -ENOMEM;
603 
604 	smp_rmb();
605 	thread->pending = false;
606 	info = thread->info;
607 	params = &info->params;
608 	chan = thread->chan;
609 	dev = chan->device;
610 	dma_dev = dmaengine_get_dma_device(chan);
611 
612 	src = &thread->src;
613 	dst = &thread->dst;
614 	if (thread->type == DMA_MEMCPY) {
615 		align = params->alignment < 0 ? dev->copy_align :
616 						params->alignment;
617 		src->cnt = dst->cnt = 1;
618 	} else if (thread->type == DMA_MEMSET) {
619 		align = params->alignment < 0 ? dev->fill_align :
620 						params->alignment;
621 		src->cnt = dst->cnt = 1;
622 		is_memset = true;
623 	} else if (thread->type == DMA_XOR) {
624 		/* force odd to ensure dst = src */
625 		src->cnt = min_odd(params->xor_sources | 1, dev->max_xor);
626 		dst->cnt = 1;
627 		align = params->alignment < 0 ? dev->xor_align :
628 						params->alignment;
629 	} else if (thread->type == DMA_PQ) {
630 		/* force odd to ensure dst = src */
631 		src->cnt = min_odd(params->pq_sources | 1, dma_maxpq(dev, 0));
632 		dst->cnt = 2;
633 		align = params->alignment < 0 ? dev->pq_align :
634 						params->alignment;
635 
636 		pq_coefs = kmalloc(params->pq_sources + 1, GFP_KERNEL);
637 		if (!pq_coefs)
638 			goto err_thread_type;
639 
640 		for (i = 0; i < src->cnt; i++)
641 			pq_coefs[i] = 1;
642 	} else
643 		goto err_thread_type;
644 
645 	/* Check if buffer count fits into map count variable (u8) */
646 	if ((src->cnt + dst->cnt) >= 255) {
647 		pr_err("too many buffers (%d of 255 supported)\n",
648 		       src->cnt + dst->cnt);
649 		goto err_free_coefs;
650 	}
651 
652 	buf_size = params->buf_size;
653 	if (1 << align > buf_size) {
654 		pr_err("%u-byte buffer too small for %d-byte alignment\n",
655 		       buf_size, 1 << align);
656 		goto err_free_coefs;
657 	}
658 
659 	if (dmatest_alloc_test_data(src, buf_size, align) < 0)
660 		goto err_free_coefs;
661 
662 	if (dmatest_alloc_test_data(dst, buf_size, align) < 0)
663 		goto err_src;
664 
665 	set_user_nice(current, 10);
666 
667 	srcs = kcalloc(src->cnt, sizeof(dma_addr_t), GFP_KERNEL);
668 	if (!srcs)
669 		goto err_dst;
670 
671 	dma_pq = kcalloc(dst->cnt, sizeof(dma_addr_t), GFP_KERNEL);
672 	if (!dma_pq)
673 		goto err_srcs_array;
674 
675 	/*
676 	 * src and dst buffers are freed by ourselves below
677 	 */
678 	if (params->polled) {
679 		flags = DMA_CTRL_ACK;
680 	} else {
681 		if (dma_has_cap(DMA_INTERRUPT, dev->cap_mask)) {
682 			flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
683 		} else {
684 			pr_err("Channel does not support interrupt!\n");
685 			goto err_pq_array;
686 		}
687 	}
688 
689 	ktime = ktime_get();
690 	while (!(kthread_should_stop() ||
691 	       (params->iterations && total_tests >= params->iterations))) {
692 		struct dma_async_tx_descriptor *tx = NULL;
693 		struct dmaengine_unmap_data *um;
694 		dma_addr_t *dsts;
695 		unsigned int len;
696 
697 		total_tests++;
698 
699 		if (params->transfer_size) {
700 			if (params->transfer_size >= buf_size) {
701 				pr_err("%u-byte transfer size must be lower than %u-buffer size\n",
702 				       params->transfer_size, buf_size);
703 				break;
704 			}
705 			len = params->transfer_size;
706 		} else if (params->norandom) {
707 			len = buf_size;
708 		} else {
709 			len = dmatest_random() % buf_size + 1;
710 		}
711 
712 		/* Do not alter transfer size explicitly defined by user */
713 		if (!params->transfer_size) {
714 			len = (len >> align) << align;
715 			if (!len)
716 				len = 1 << align;
717 		}
718 		total_len += len;
719 
720 		if (params->norandom) {
721 			src->off = 0;
722 			dst->off = 0;
723 		} else {
724 			src->off = dmatest_random() % (buf_size - len + 1);
725 			dst->off = dmatest_random() % (buf_size - len + 1);
726 
727 			src->off = (src->off >> align) << align;
728 			dst->off = (dst->off >> align) << align;
729 		}
730 
731 		if (!params->noverify) {
732 			start = ktime_get();
733 			dmatest_init_srcs(src->aligned, src->off, len,
734 					  buf_size, is_memset);
735 			dmatest_init_dsts(dst->aligned, dst->off, len,
736 					  buf_size, is_memset);
737 
738 			diff = ktime_sub(ktime_get(), start);
739 			filltime = ktime_add(filltime, diff);
740 		}
741 
742 		um = dmaengine_get_unmap_data(dma_dev, src->cnt + dst->cnt,
743 					      GFP_KERNEL);
744 		if (!um) {
745 			failed_tests++;
746 			result("unmap data NULL", total_tests,
747 			       src->off, dst->off, len, ret);
748 			continue;
749 		}
750 
751 		um->len = buf_size;
752 		for (i = 0; i < src->cnt; i++) {
753 			void *buf = src->aligned[i];
754 			struct page *pg = virt_to_page(buf);
755 			unsigned long pg_off = offset_in_page(buf);
756 
757 			um->addr[i] = dma_map_page(dma_dev, pg, pg_off,
758 						   um->len, DMA_TO_DEVICE);
759 			srcs[i] = um->addr[i] + src->off;
760 			ret = dma_mapping_error(dma_dev, um->addr[i]);
761 			if (ret) {
762 				result("src mapping error", total_tests,
763 				       src->off, dst->off, len, ret);
764 				goto error_unmap_continue;
765 			}
766 			um->to_cnt++;
767 		}
768 		/* map with DMA_BIDIRECTIONAL to force writeback/invalidate */
769 		dsts = &um->addr[src->cnt];
770 		for (i = 0; i < dst->cnt; i++) {
771 			void *buf = dst->aligned[i];
772 			struct page *pg = virt_to_page(buf);
773 			unsigned long pg_off = offset_in_page(buf);
774 
775 			dsts[i] = dma_map_page(dma_dev, pg, pg_off, um->len,
776 					       DMA_BIDIRECTIONAL);
777 			ret = dma_mapping_error(dma_dev, dsts[i]);
778 			if (ret) {
779 				result("dst mapping error", total_tests,
780 				       src->off, dst->off, len, ret);
781 				goto error_unmap_continue;
782 			}
783 			um->bidi_cnt++;
784 		}
785 
786 		if (thread->type == DMA_MEMCPY)
787 			tx = dev->device_prep_dma_memcpy(chan,
788 							 dsts[0] + dst->off,
789 							 srcs[0], len, flags);
790 		else if (thread->type == DMA_MEMSET)
791 			tx = dev->device_prep_dma_memset(chan,
792 						dsts[0] + dst->off,
793 						*(src->aligned[0] + src->off),
794 						len, flags);
795 		else if (thread->type == DMA_XOR)
796 			tx = dev->device_prep_dma_xor(chan,
797 						      dsts[0] + dst->off,
798 						      srcs, src->cnt,
799 						      len, flags);
800 		else if (thread->type == DMA_PQ) {
801 			for (i = 0; i < dst->cnt; i++)
802 				dma_pq[i] = dsts[i] + dst->off;
803 			tx = dev->device_prep_dma_pq(chan, dma_pq, srcs,
804 						     src->cnt, pq_coefs,
805 						     len, flags);
806 		}
807 
808 		if (!tx) {
809 			result("prep error", total_tests, src->off,
810 			       dst->off, len, ret);
811 			msleep(100);
812 			goto error_unmap_continue;
813 		}
814 
815 		done->done = false;
816 		if (!params->polled) {
817 			tx->callback = dmatest_callback;
818 			tx->callback_param = done;
819 		}
820 		cookie = tx->tx_submit(tx);
821 
822 		if (dma_submit_error(cookie)) {
823 			result("submit error", total_tests, src->off,
824 			       dst->off, len, ret);
825 			msleep(100);
826 			goto error_unmap_continue;
827 		}
828 
829 		if (params->polled) {
830 			status = dma_sync_wait(chan, cookie);
831 			dmaengine_terminate_sync(chan);
832 			if (status == DMA_COMPLETE)
833 				done->done = true;
834 		} else {
835 			dma_async_issue_pending(chan);
836 
837 			wait_event_freezable_timeout(thread->done_wait,
838 					done->done,
839 					msecs_to_jiffies(params->timeout));
840 
841 			status = dma_async_is_tx_complete(chan, cookie, NULL,
842 							  NULL);
843 		}
844 
845 		if (!done->done) {
846 			result("test timed out", total_tests, src->off, dst->off,
847 			       len, 0);
848 			goto error_unmap_continue;
849 		} else if (status != DMA_COMPLETE &&
850 			   !(dma_has_cap(DMA_COMPLETION_NO_ORDER,
851 					 dev->cap_mask) &&
852 			     status == DMA_OUT_OF_ORDER)) {
853 			result(status == DMA_ERROR ?
854 			       "completion error status" :
855 			       "completion busy status", total_tests, src->off,
856 			       dst->off, len, ret);
857 			goto error_unmap_continue;
858 		}
859 
860 		dmaengine_unmap_put(um);
861 
862 		if (params->noverify) {
863 			verbose_result("test passed", total_tests, src->off,
864 				       dst->off, len, 0);
865 			continue;
866 		}
867 
868 		start = ktime_get();
869 		pr_debug("%s: verifying source buffer...\n", current->comm);
870 		error_count = dmatest_verify(src->aligned, 0, src->off,
871 				0, PATTERN_SRC, true, is_memset);
872 		error_count += dmatest_verify(src->aligned, src->off,
873 				src->off + len, src->off,
874 				PATTERN_SRC | PATTERN_COPY, true, is_memset);
875 		error_count += dmatest_verify(src->aligned, src->off + len,
876 				buf_size, src->off + len,
877 				PATTERN_SRC, true, is_memset);
878 
879 		pr_debug("%s: verifying dest buffer...\n", current->comm);
880 		error_count += dmatest_verify(dst->aligned, 0, dst->off,
881 				0, PATTERN_DST, false, is_memset);
882 
883 		error_count += dmatest_verify(dst->aligned, dst->off,
884 				dst->off + len, src->off,
885 				PATTERN_SRC | PATTERN_COPY, false, is_memset);
886 
887 		error_count += dmatest_verify(dst->aligned, dst->off + len,
888 				buf_size, dst->off + len,
889 				PATTERN_DST, false, is_memset);
890 
891 		diff = ktime_sub(ktime_get(), start);
892 		comparetime = ktime_add(comparetime, diff);
893 
894 		if (error_count) {
895 			result("data error", total_tests, src->off, dst->off,
896 			       len, error_count);
897 			failed_tests++;
898 		} else {
899 			verbose_result("test passed", total_tests, src->off,
900 				       dst->off, len, 0);
901 		}
902 
903 		continue;
904 
905 error_unmap_continue:
906 		dmaengine_unmap_put(um);
907 		failed_tests++;
908 	}
909 	ktime = ktime_sub(ktime_get(), ktime);
910 	ktime = ktime_sub(ktime, comparetime);
911 	ktime = ktime_sub(ktime, filltime);
912 	runtime = ktime_to_us(ktime);
913 
914 	ret = 0;
915 err_pq_array:
916 	kfree(dma_pq);
917 err_srcs_array:
918 	kfree(srcs);
919 err_dst:
920 	dmatest_free_test_data(dst);
921 err_src:
922 	dmatest_free_test_data(src);
923 err_free_coefs:
924 	kfree(pq_coefs);
925 err_thread_type:
926 	iops = dmatest_persec(runtime, total_tests);
927 	pr_info("%s: summary %u tests, %u failures %llu.%02llu iops %llu KB/s (%d)\n",
928 		current->comm, total_tests, failed_tests,
929 		FIXPT_TO_INT(iops), FIXPT_GET_FRAC(iops),
930 		dmatest_KBs(runtime, total_len), ret);
931 
932 	/* terminate all transfers on specified channels */
933 	if (ret || failed_tests)
934 		dmaengine_terminate_sync(chan);
935 
936 	thread->done = true;
937 	wake_up(&thread_wait);
938 
939 	return ret;
940 }
941 
942 static void dmatest_cleanup_channel(struct dmatest_chan *dtc)
943 {
944 	struct dmatest_thread	*thread;
945 	struct dmatest_thread	*_thread;
946 	int			ret;
947 
948 	list_for_each_entry_safe(thread, _thread, &dtc->threads, node) {
949 		ret = kthread_stop(thread->task);
950 		pr_debug("thread %s exited with status %d\n",
951 			 thread->task->comm, ret);
952 		list_del(&thread->node);
953 		put_task_struct(thread->task);
954 		kfree(thread);
955 	}
956 
957 	/* terminate all transfers on specified channels */
958 	dmaengine_terminate_sync(dtc->chan);
959 
960 	kfree(dtc);
961 }
962 
963 static int dmatest_add_threads(struct dmatest_info *info,
964 		struct dmatest_chan *dtc, enum dma_transaction_type type)
965 {
966 	struct dmatest_params *params = &info->params;
967 	struct dmatest_thread *thread;
968 	struct dma_chan *chan = dtc->chan;
969 	char *op;
970 	unsigned int i;
971 
972 	if (type == DMA_MEMCPY)
973 		op = "copy";
974 	else if (type == DMA_MEMSET)
975 		op = "set";
976 	else if (type == DMA_XOR)
977 		op = "xor";
978 	else if (type == DMA_PQ)
979 		op = "pq";
980 	else
981 		return -EINVAL;
982 
983 	for (i = 0; i < params->threads_per_chan; i++) {
984 		thread = kzalloc(sizeof(struct dmatest_thread), GFP_KERNEL);
985 		if (!thread) {
986 			pr_warn("No memory for %s-%s%u\n",
987 				dma_chan_name(chan), op, i);
988 			break;
989 		}
990 		thread->info = info;
991 		thread->chan = dtc->chan;
992 		thread->type = type;
993 		thread->test_done.wait = &thread->done_wait;
994 		init_waitqueue_head(&thread->done_wait);
995 		smp_wmb();
996 		thread->task = kthread_create(dmatest_func, thread, "%s-%s%u",
997 				dma_chan_name(chan), op, i);
998 		if (IS_ERR(thread->task)) {
999 			pr_warn("Failed to create thread %s-%s%u\n",
1000 				dma_chan_name(chan), op, i);
1001 			kfree(thread);
1002 			break;
1003 		}
1004 
1005 		/* srcbuf and dstbuf are allocated by the thread itself */
1006 		get_task_struct(thread->task);
1007 		list_add_tail(&thread->node, &dtc->threads);
1008 		thread->pending = true;
1009 	}
1010 
1011 	return i;
1012 }
1013 
1014 static int dmatest_add_channel(struct dmatest_info *info,
1015 		struct dma_chan *chan)
1016 {
1017 	struct dmatest_chan	*dtc;
1018 	struct dma_device	*dma_dev = chan->device;
1019 	unsigned int		thread_count = 0;
1020 	int cnt;
1021 
1022 	dtc = kmalloc(sizeof(struct dmatest_chan), GFP_KERNEL);
1023 	if (!dtc) {
1024 		pr_warn("No memory for %s\n", dma_chan_name(chan));
1025 		return -ENOMEM;
1026 	}
1027 
1028 	dtc->chan = chan;
1029 	INIT_LIST_HEAD(&dtc->threads);
1030 
1031 	if (dma_has_cap(DMA_COMPLETION_NO_ORDER, dma_dev->cap_mask) &&
1032 	    info->params.polled) {
1033 		info->params.polled = false;
1034 		pr_warn("DMA_COMPLETION_NO_ORDER, polled disabled\n");
1035 	}
1036 
1037 	if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) {
1038 		if (dmatest == 0) {
1039 			cnt = dmatest_add_threads(info, dtc, DMA_MEMCPY);
1040 			thread_count += cnt > 0 ? cnt : 0;
1041 		}
1042 	}
1043 
1044 	if (dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)) {
1045 		if (dmatest == 1) {
1046 			cnt = dmatest_add_threads(info, dtc, DMA_MEMSET);
1047 			thread_count += cnt > 0 ? cnt : 0;
1048 		}
1049 	}
1050 
1051 	if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) {
1052 		cnt = dmatest_add_threads(info, dtc, DMA_XOR);
1053 		thread_count += cnt > 0 ? cnt : 0;
1054 	}
1055 	if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) {
1056 		cnt = dmatest_add_threads(info, dtc, DMA_PQ);
1057 		thread_count += cnt > 0 ? cnt : 0;
1058 	}
1059 
1060 	pr_info("Added %u threads using %s\n",
1061 		thread_count, dma_chan_name(chan));
1062 
1063 	list_add_tail(&dtc->node, &info->channels);
1064 	info->nr_channels++;
1065 
1066 	return 0;
1067 }
1068 
1069 static bool filter(struct dma_chan *chan, void *param)
1070 {
1071 	return dmatest_match_channel(param, chan) && dmatest_match_device(param, chan->device);
1072 }
1073 
1074 static void request_channels(struct dmatest_info *info,
1075 			     enum dma_transaction_type type)
1076 {
1077 	dma_cap_mask_t mask;
1078 
1079 	dma_cap_zero(mask);
1080 	dma_cap_set(type, mask);
1081 	for (;;) {
1082 		struct dmatest_params *params = &info->params;
1083 		struct dma_chan *chan;
1084 
1085 		chan = dma_request_channel(mask, filter, params);
1086 		if (chan) {
1087 			if (dmatest_add_channel(info, chan)) {
1088 				dma_release_channel(chan);
1089 				break; /* add_channel failed, punt */
1090 			}
1091 		} else
1092 			break; /* no more channels available */
1093 		if (params->max_channels &&
1094 		    info->nr_channels >= params->max_channels)
1095 			break; /* we have all we need */
1096 	}
1097 }
1098 
1099 static void add_threaded_test(struct dmatest_info *info)
1100 {
1101 	struct dmatest_params *params = &info->params;
1102 
1103 	/* Copy test parameters */
1104 	params->buf_size = test_buf_size;
1105 	strlcpy(params->channel, strim(test_channel), sizeof(params->channel));
1106 	strlcpy(params->device, strim(test_device), sizeof(params->device));
1107 	params->threads_per_chan = threads_per_chan;
1108 	params->max_channels = max_channels;
1109 	params->iterations = iterations;
1110 	params->xor_sources = xor_sources;
1111 	params->pq_sources = pq_sources;
1112 	params->timeout = timeout;
1113 	params->noverify = noverify;
1114 	params->norandom = norandom;
1115 	params->alignment = alignment;
1116 	params->transfer_size = transfer_size;
1117 	params->polled = polled;
1118 
1119 	request_channels(info, DMA_MEMCPY);
1120 	request_channels(info, DMA_MEMSET);
1121 	request_channels(info, DMA_XOR);
1122 	request_channels(info, DMA_PQ);
1123 }
1124 
1125 static void run_pending_tests(struct dmatest_info *info)
1126 {
1127 	struct dmatest_chan *dtc;
1128 	unsigned int thread_count = 0;
1129 
1130 	list_for_each_entry(dtc, &info->channels, node) {
1131 		struct dmatest_thread *thread;
1132 
1133 		thread_count = 0;
1134 		list_for_each_entry(thread, &dtc->threads, node) {
1135 			wake_up_process(thread->task);
1136 			thread_count++;
1137 		}
1138 		pr_info("Started %u threads using %s\n",
1139 			thread_count, dma_chan_name(dtc->chan));
1140 	}
1141 }
1142 
1143 static void stop_threaded_test(struct dmatest_info *info)
1144 {
1145 	struct dmatest_chan *dtc, *_dtc;
1146 	struct dma_chan *chan;
1147 
1148 	list_for_each_entry_safe(dtc, _dtc, &info->channels, node) {
1149 		list_del(&dtc->node);
1150 		chan = dtc->chan;
1151 		dmatest_cleanup_channel(dtc);
1152 		pr_debug("dropped channel %s\n", dma_chan_name(chan));
1153 		dma_release_channel(chan);
1154 	}
1155 
1156 	info->nr_channels = 0;
1157 }
1158 
1159 static void start_threaded_tests(struct dmatest_info *info)
1160 {
1161 	/* we might be called early to set run=, defer running until all
1162 	 * parameters have been evaluated
1163 	 */
1164 	if (!info->did_init)
1165 		return;
1166 
1167 	run_pending_tests(info);
1168 }
1169 
1170 static int dmatest_run_get(char *val, const struct kernel_param *kp)
1171 {
1172 	struct dmatest_info *info = &test_info;
1173 
1174 	mutex_lock(&info->lock);
1175 	if (is_threaded_test_run(info)) {
1176 		dmatest_run = true;
1177 	} else {
1178 		if (!is_threaded_test_pending(info))
1179 			stop_threaded_test(info);
1180 		dmatest_run = false;
1181 	}
1182 	mutex_unlock(&info->lock);
1183 
1184 	return param_get_bool(val, kp);
1185 }
1186 
1187 static int dmatest_run_set(const char *val, const struct kernel_param *kp)
1188 {
1189 	struct dmatest_info *info = &test_info;
1190 	int ret;
1191 
1192 	mutex_lock(&info->lock);
1193 	ret = param_set_bool(val, kp);
1194 	if (ret) {
1195 		mutex_unlock(&info->lock);
1196 		return ret;
1197 	} else if (dmatest_run) {
1198 		if (!is_threaded_test_pending(info)) {
1199 			/*
1200 			 * We have nothing to run. This can be due to:
1201 			 */
1202 			ret = info->last_error;
1203 			if (ret) {
1204 				/* 1) Misconfiguration */
1205 				pr_err("Channel misconfigured, can't continue\n");
1206 				mutex_unlock(&info->lock);
1207 				return ret;
1208 			} else {
1209 				/* 2) We rely on defaults */
1210 				pr_info("No channels configured, continue with any\n");
1211 				if (!is_threaded_test_run(info))
1212 					stop_threaded_test(info);
1213 				add_threaded_test(info);
1214 			}
1215 		}
1216 		start_threaded_tests(info);
1217 	} else {
1218 		stop_threaded_test(info);
1219 	}
1220 
1221 	mutex_unlock(&info->lock);
1222 
1223 	return ret;
1224 }
1225 
1226 static int dmatest_chan_set(const char *val, const struct kernel_param *kp)
1227 {
1228 	struct dmatest_info *info = &test_info;
1229 	struct dmatest_chan *dtc;
1230 	char chan_reset_val[20];
1231 	int ret;
1232 
1233 	mutex_lock(&info->lock);
1234 	ret = param_set_copystring(val, kp);
1235 	if (ret) {
1236 		mutex_unlock(&info->lock);
1237 		return ret;
1238 	}
1239 	/*Clear any previously run threads */
1240 	if (!is_threaded_test_run(info) && !is_threaded_test_pending(info))
1241 		stop_threaded_test(info);
1242 	/* Reject channels that are already registered */
1243 	if (is_threaded_test_pending(info)) {
1244 		list_for_each_entry(dtc, &info->channels, node) {
1245 			if (strcmp(dma_chan_name(dtc->chan),
1246 				   strim(test_channel)) == 0) {
1247 				dtc = list_last_entry(&info->channels,
1248 						      struct dmatest_chan,
1249 						      node);
1250 				strlcpy(chan_reset_val,
1251 					dma_chan_name(dtc->chan),
1252 					sizeof(chan_reset_val));
1253 				ret = -EBUSY;
1254 				goto add_chan_err;
1255 			}
1256 		}
1257 	}
1258 
1259 	add_threaded_test(info);
1260 
1261 	/* Check if channel was added successfully */
1262 	if (!list_empty(&info->channels)) {
1263 		/*
1264 		 * if new channel was not successfully added, revert the
1265 		 * "test_channel" string to the name of the last successfully
1266 		 * added channel. exception for when users issues empty string
1267 		 * to channel parameter.
1268 		 */
1269 		dtc = list_last_entry(&info->channels, struct dmatest_chan, node);
1270 		if ((strcmp(dma_chan_name(dtc->chan), strim(test_channel)) != 0)
1271 		    && (strcmp("", strim(test_channel)) != 0)) {
1272 			ret = -EINVAL;
1273 			strlcpy(chan_reset_val, dma_chan_name(dtc->chan),
1274 				sizeof(chan_reset_val));
1275 			goto add_chan_err;
1276 		}
1277 
1278 	} else {
1279 		/* Clear test_channel if no channels were added successfully */
1280 		strlcpy(chan_reset_val, "", sizeof(chan_reset_val));
1281 		ret = -EBUSY;
1282 		goto add_chan_err;
1283 	}
1284 
1285 	info->last_error = ret;
1286 	mutex_unlock(&info->lock);
1287 
1288 	return ret;
1289 
1290 add_chan_err:
1291 	param_set_copystring(chan_reset_val, kp);
1292 	info->last_error = ret;
1293 	mutex_unlock(&info->lock);
1294 
1295 	return ret;
1296 }
1297 
1298 static int dmatest_chan_get(char *val, const struct kernel_param *kp)
1299 {
1300 	struct dmatest_info *info = &test_info;
1301 
1302 	mutex_lock(&info->lock);
1303 	if (!is_threaded_test_run(info) && !is_threaded_test_pending(info)) {
1304 		stop_threaded_test(info);
1305 		strlcpy(test_channel, "", sizeof(test_channel));
1306 	}
1307 	mutex_unlock(&info->lock);
1308 
1309 	return param_get_string(val, kp);
1310 }
1311 
1312 static int dmatest_test_list_get(char *val, const struct kernel_param *kp)
1313 {
1314 	struct dmatest_info *info = &test_info;
1315 	struct dmatest_chan *dtc;
1316 	unsigned int thread_count = 0;
1317 
1318 	list_for_each_entry(dtc, &info->channels, node) {
1319 		struct dmatest_thread *thread;
1320 
1321 		thread_count = 0;
1322 		list_for_each_entry(thread, &dtc->threads, node) {
1323 			thread_count++;
1324 		}
1325 		pr_info("%u threads using %s\n",
1326 			thread_count, dma_chan_name(dtc->chan));
1327 	}
1328 
1329 	return 0;
1330 }
1331 
1332 static int __init dmatest_init(void)
1333 {
1334 	struct dmatest_info *info = &test_info;
1335 	struct dmatest_params *params = &info->params;
1336 
1337 	if (dmatest_run) {
1338 		mutex_lock(&info->lock);
1339 		add_threaded_test(info);
1340 		run_pending_tests(info);
1341 		mutex_unlock(&info->lock);
1342 	}
1343 
1344 	if (params->iterations && wait)
1345 		wait_event(thread_wait, !is_threaded_test_run(info));
1346 
1347 	/* module parameters are stable, inittime tests are started,
1348 	 * let userspace take over 'run' control
1349 	 */
1350 	info->did_init = true;
1351 
1352 	return 0;
1353 }
1354 /* when compiled-in wait for drivers to load first */
1355 late_initcall(dmatest_init);
1356 
1357 static void __exit dmatest_exit(void)
1358 {
1359 	struct dmatest_info *info = &test_info;
1360 
1361 	mutex_lock(&info->lock);
1362 	stop_threaded_test(info);
1363 	mutex_unlock(&info->lock);
1364 }
1365 module_exit(dmatest_exit);
1366 
1367 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
1368 MODULE_LICENSE("GPL v2");
1369