1 /* 2 * DMA Engine test module 3 * 4 * Copyright (C) 2007 Atmel Corporation 5 * Copyright (C) 2013 Intel Corporation 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 12 13 #include <linux/delay.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/dmaengine.h> 16 #include <linux/freezer.h> 17 #include <linux/init.h> 18 #include <linux/kthread.h> 19 #include <linux/module.h> 20 #include <linux/moduleparam.h> 21 #include <linux/random.h> 22 #include <linux/slab.h> 23 #include <linux/wait.h> 24 25 static unsigned int test_buf_size = 16384; 26 module_param(test_buf_size, uint, S_IRUGO | S_IWUSR); 27 MODULE_PARM_DESC(test_buf_size, "Size of the memcpy test buffer"); 28 29 static char test_channel[20]; 30 module_param_string(channel, test_channel, sizeof(test_channel), 31 S_IRUGO | S_IWUSR); 32 MODULE_PARM_DESC(channel, "Bus ID of the channel to test (default: any)"); 33 34 static char test_device[32]; 35 module_param_string(device, test_device, sizeof(test_device), 36 S_IRUGO | S_IWUSR); 37 MODULE_PARM_DESC(device, "Bus ID of the DMA Engine to test (default: any)"); 38 39 static unsigned int threads_per_chan = 1; 40 module_param(threads_per_chan, uint, S_IRUGO | S_IWUSR); 41 MODULE_PARM_DESC(threads_per_chan, 42 "Number of threads to start per channel (default: 1)"); 43 44 static unsigned int max_channels; 45 module_param(max_channels, uint, S_IRUGO | S_IWUSR); 46 MODULE_PARM_DESC(max_channels, 47 "Maximum number of channels to use (default: all)"); 48 49 static unsigned int iterations; 50 module_param(iterations, uint, S_IRUGO | S_IWUSR); 51 MODULE_PARM_DESC(iterations, 52 "Iterations before stopping test (default: infinite)"); 53 54 static unsigned int sg_buffers = 1; 55 module_param(sg_buffers, uint, S_IRUGO | S_IWUSR); 56 MODULE_PARM_DESC(sg_buffers, 57 "Number of scatter gather buffers (default: 1)"); 58 59 static unsigned int dmatest; 60 module_param(dmatest, uint, S_IRUGO | S_IWUSR); 61 MODULE_PARM_DESC(dmatest, 62 "dmatest 0-memcpy 1-slave_sg (default: 0)"); 63 64 static unsigned int xor_sources = 3; 65 module_param(xor_sources, uint, S_IRUGO | S_IWUSR); 66 MODULE_PARM_DESC(xor_sources, 67 "Number of xor source buffers (default: 3)"); 68 69 static unsigned int pq_sources = 3; 70 module_param(pq_sources, uint, S_IRUGO | S_IWUSR); 71 MODULE_PARM_DESC(pq_sources, 72 "Number of p+q source buffers (default: 3)"); 73 74 static int timeout = 3000; 75 module_param(timeout, uint, S_IRUGO | S_IWUSR); 76 MODULE_PARM_DESC(timeout, "Transfer Timeout in msec (default: 3000), " 77 "Pass -1 for infinite timeout"); 78 79 static bool noverify; 80 module_param(noverify, bool, S_IRUGO | S_IWUSR); 81 MODULE_PARM_DESC(noverify, "Disable random data setup and verification"); 82 83 static bool verbose; 84 module_param(verbose, bool, S_IRUGO | S_IWUSR); 85 MODULE_PARM_DESC(verbose, "Enable \"success\" result messages (default: off)"); 86 87 /** 88 * struct dmatest_params - test parameters. 89 * @buf_size: size of the memcpy test buffer 90 * @channel: bus ID of the channel to test 91 * @device: bus ID of the DMA Engine to test 92 * @threads_per_chan: number of threads to start per channel 93 * @max_channels: maximum number of channels to use 94 * @iterations: iterations before stopping test 95 * @xor_sources: number of xor source buffers 96 * @pq_sources: number of p+q source buffers 97 * @timeout: transfer timeout in msec, -1 for infinite timeout 98 */ 99 struct dmatest_params { 100 unsigned int buf_size; 101 char channel[20]; 102 char device[32]; 103 unsigned int threads_per_chan; 104 unsigned int max_channels; 105 unsigned int iterations; 106 unsigned int xor_sources; 107 unsigned int pq_sources; 108 int timeout; 109 bool noverify; 110 }; 111 112 /** 113 * struct dmatest_info - test information. 114 * @params: test parameters 115 * @lock: access protection to the fields of this structure 116 */ 117 static struct dmatest_info { 118 /* Test parameters */ 119 struct dmatest_params params; 120 121 /* Internal state */ 122 struct list_head channels; 123 unsigned int nr_channels; 124 struct mutex lock; 125 bool did_init; 126 } test_info = { 127 .channels = LIST_HEAD_INIT(test_info.channels), 128 .lock = __MUTEX_INITIALIZER(test_info.lock), 129 }; 130 131 static int dmatest_run_set(const char *val, const struct kernel_param *kp); 132 static int dmatest_run_get(char *val, const struct kernel_param *kp); 133 static const struct kernel_param_ops run_ops = { 134 .set = dmatest_run_set, 135 .get = dmatest_run_get, 136 }; 137 static bool dmatest_run; 138 module_param_cb(run, &run_ops, &dmatest_run, S_IRUGO | S_IWUSR); 139 MODULE_PARM_DESC(run, "Run the test (default: false)"); 140 141 /* Maximum amount of mismatched bytes in buffer to print */ 142 #define MAX_ERROR_COUNT 32 143 144 /* 145 * Initialization patterns. All bytes in the source buffer has bit 7 146 * set, all bytes in the destination buffer has bit 7 cleared. 147 * 148 * Bit 6 is set for all bytes which are to be copied by the DMA 149 * engine. Bit 5 is set for all bytes which are to be overwritten by 150 * the DMA engine. 151 * 152 * The remaining bits are the inverse of a counter which increments by 153 * one for each byte address. 154 */ 155 #define PATTERN_SRC 0x80 156 #define PATTERN_DST 0x00 157 #define PATTERN_COPY 0x40 158 #define PATTERN_OVERWRITE 0x20 159 #define PATTERN_COUNT_MASK 0x1f 160 161 struct dmatest_thread { 162 struct list_head node; 163 struct dmatest_info *info; 164 struct task_struct *task; 165 struct dma_chan *chan; 166 u8 **srcs; 167 u8 **dsts; 168 enum dma_transaction_type type; 169 bool done; 170 }; 171 172 struct dmatest_chan { 173 struct list_head node; 174 struct dma_chan *chan; 175 struct list_head threads; 176 }; 177 178 static DECLARE_WAIT_QUEUE_HEAD(thread_wait); 179 static bool wait; 180 181 static bool is_threaded_test_run(struct dmatest_info *info) 182 { 183 struct dmatest_chan *dtc; 184 185 list_for_each_entry(dtc, &info->channels, node) { 186 struct dmatest_thread *thread; 187 188 list_for_each_entry(thread, &dtc->threads, node) { 189 if (!thread->done) 190 return true; 191 } 192 } 193 194 return false; 195 } 196 197 static int dmatest_wait_get(char *val, const struct kernel_param *kp) 198 { 199 struct dmatest_info *info = &test_info; 200 struct dmatest_params *params = &info->params; 201 202 if (params->iterations) 203 wait_event(thread_wait, !is_threaded_test_run(info)); 204 wait = true; 205 return param_get_bool(val, kp); 206 } 207 208 static const struct kernel_param_ops wait_ops = { 209 .get = dmatest_wait_get, 210 .set = param_set_bool, 211 }; 212 module_param_cb(wait, &wait_ops, &wait, S_IRUGO); 213 MODULE_PARM_DESC(wait, "Wait for tests to complete (default: false)"); 214 215 static bool dmatest_match_channel(struct dmatest_params *params, 216 struct dma_chan *chan) 217 { 218 if (params->channel[0] == '\0') 219 return true; 220 return strcmp(dma_chan_name(chan), params->channel) == 0; 221 } 222 223 static bool dmatest_match_device(struct dmatest_params *params, 224 struct dma_device *device) 225 { 226 if (params->device[0] == '\0') 227 return true; 228 return strcmp(dev_name(device->dev), params->device) == 0; 229 } 230 231 static unsigned long dmatest_random(void) 232 { 233 unsigned long buf; 234 235 prandom_bytes(&buf, sizeof(buf)); 236 return buf; 237 } 238 239 static void dmatest_init_srcs(u8 **bufs, unsigned int start, unsigned int len, 240 unsigned int buf_size) 241 { 242 unsigned int i; 243 u8 *buf; 244 245 for (; (buf = *bufs); bufs++) { 246 for (i = 0; i < start; i++) 247 buf[i] = PATTERN_SRC | (~i & PATTERN_COUNT_MASK); 248 for ( ; i < start + len; i++) 249 buf[i] = PATTERN_SRC | PATTERN_COPY 250 | (~i & PATTERN_COUNT_MASK); 251 for ( ; i < buf_size; i++) 252 buf[i] = PATTERN_SRC | (~i & PATTERN_COUNT_MASK); 253 buf++; 254 } 255 } 256 257 static void dmatest_init_dsts(u8 **bufs, unsigned int start, unsigned int len, 258 unsigned int buf_size) 259 { 260 unsigned int i; 261 u8 *buf; 262 263 for (; (buf = *bufs); bufs++) { 264 for (i = 0; i < start; i++) 265 buf[i] = PATTERN_DST | (~i & PATTERN_COUNT_MASK); 266 for ( ; i < start + len; i++) 267 buf[i] = PATTERN_DST | PATTERN_OVERWRITE 268 | (~i & PATTERN_COUNT_MASK); 269 for ( ; i < buf_size; i++) 270 buf[i] = PATTERN_DST | (~i & PATTERN_COUNT_MASK); 271 } 272 } 273 274 static void dmatest_mismatch(u8 actual, u8 pattern, unsigned int index, 275 unsigned int counter, bool is_srcbuf) 276 { 277 u8 diff = actual ^ pattern; 278 u8 expected = pattern | (~counter & PATTERN_COUNT_MASK); 279 const char *thread_name = current->comm; 280 281 if (is_srcbuf) 282 pr_warn("%s: srcbuf[0x%x] overwritten! Expected %02x, got %02x\n", 283 thread_name, index, expected, actual); 284 else if ((pattern & PATTERN_COPY) 285 && (diff & (PATTERN_COPY | PATTERN_OVERWRITE))) 286 pr_warn("%s: dstbuf[0x%x] not copied! Expected %02x, got %02x\n", 287 thread_name, index, expected, actual); 288 else if (diff & PATTERN_SRC) 289 pr_warn("%s: dstbuf[0x%x] was copied! Expected %02x, got %02x\n", 290 thread_name, index, expected, actual); 291 else 292 pr_warn("%s: dstbuf[0x%x] mismatch! Expected %02x, got %02x\n", 293 thread_name, index, expected, actual); 294 } 295 296 static unsigned int dmatest_verify(u8 **bufs, unsigned int start, 297 unsigned int end, unsigned int counter, u8 pattern, 298 bool is_srcbuf) 299 { 300 unsigned int i; 301 unsigned int error_count = 0; 302 u8 actual; 303 u8 expected; 304 u8 *buf; 305 unsigned int counter_orig = counter; 306 307 for (; (buf = *bufs); bufs++) { 308 counter = counter_orig; 309 for (i = start; i < end; i++) { 310 actual = buf[i]; 311 expected = pattern | (~counter & PATTERN_COUNT_MASK); 312 if (actual != expected) { 313 if (error_count < MAX_ERROR_COUNT) 314 dmatest_mismatch(actual, pattern, i, 315 counter, is_srcbuf); 316 error_count++; 317 } 318 counter++; 319 } 320 } 321 322 if (error_count > MAX_ERROR_COUNT) 323 pr_warn("%s: %u errors suppressed\n", 324 current->comm, error_count - MAX_ERROR_COUNT); 325 326 return error_count; 327 } 328 329 /* poor man's completion - we want to use wait_event_freezable() on it */ 330 struct dmatest_done { 331 bool done; 332 wait_queue_head_t *wait; 333 }; 334 335 static void dmatest_callback(void *arg) 336 { 337 struct dmatest_done *done = arg; 338 339 done->done = true; 340 wake_up_all(done->wait); 341 } 342 343 static unsigned int min_odd(unsigned int x, unsigned int y) 344 { 345 unsigned int val = min(x, y); 346 347 return val % 2 ? val : val - 1; 348 } 349 350 static void result(const char *err, unsigned int n, unsigned int src_off, 351 unsigned int dst_off, unsigned int len, unsigned long data) 352 { 353 pr_info("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n", 354 current->comm, n, err, src_off, dst_off, len, data); 355 } 356 357 static void dbg_result(const char *err, unsigned int n, unsigned int src_off, 358 unsigned int dst_off, unsigned int len, 359 unsigned long data) 360 { 361 pr_debug("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n", 362 current->comm, n, err, src_off, dst_off, len, data); 363 } 364 365 #define verbose_result(err, n, src_off, dst_off, len, data) ({ \ 366 if (verbose) \ 367 result(err, n, src_off, dst_off, len, data); \ 368 else \ 369 dbg_result(err, n, src_off, dst_off, len, data);\ 370 }) 371 372 static unsigned long long dmatest_persec(s64 runtime, unsigned int val) 373 { 374 unsigned long long per_sec = 1000000; 375 376 if (runtime <= 0) 377 return 0; 378 379 /* drop precision until runtime is 32-bits */ 380 while (runtime > UINT_MAX) { 381 runtime >>= 1; 382 per_sec <<= 1; 383 } 384 385 per_sec *= val; 386 do_div(per_sec, runtime); 387 return per_sec; 388 } 389 390 static unsigned long long dmatest_KBs(s64 runtime, unsigned long long len) 391 { 392 return dmatest_persec(runtime, len >> 10); 393 } 394 395 /* 396 * This function repeatedly tests DMA transfers of various lengths and 397 * offsets for a given operation type until it is told to exit by 398 * kthread_stop(). There may be multiple threads running this function 399 * in parallel for a single channel, and there may be multiple channels 400 * being tested in parallel. 401 * 402 * Before each test, the source and destination buffer is initialized 403 * with a known pattern. This pattern is different depending on 404 * whether it's in an area which is supposed to be copied or 405 * overwritten, and different in the source and destination buffers. 406 * So if the DMA engine doesn't copy exactly what we tell it to copy, 407 * we'll notice. 408 */ 409 static int dmatest_func(void *data) 410 { 411 DECLARE_WAIT_QUEUE_HEAD_ONSTACK(done_wait); 412 struct dmatest_thread *thread = data; 413 struct dmatest_done done = { .wait = &done_wait }; 414 struct dmatest_info *info; 415 struct dmatest_params *params; 416 struct dma_chan *chan; 417 struct dma_device *dev; 418 unsigned int error_count; 419 unsigned int failed_tests = 0; 420 unsigned int total_tests = 0; 421 dma_cookie_t cookie; 422 enum dma_status status; 423 enum dma_ctrl_flags flags; 424 u8 *pq_coefs = NULL; 425 int ret; 426 int src_cnt; 427 int dst_cnt; 428 int i; 429 ktime_t ktime, start, diff; 430 ktime_t filltime = ktime_set(0, 0); 431 ktime_t comparetime = ktime_set(0, 0); 432 s64 runtime = 0; 433 unsigned long long total_len = 0; 434 435 set_freezable(); 436 437 ret = -ENOMEM; 438 439 smp_rmb(); 440 info = thread->info; 441 params = &info->params; 442 chan = thread->chan; 443 dev = chan->device; 444 if (thread->type == DMA_MEMCPY) 445 src_cnt = dst_cnt = 1; 446 else if (thread->type == DMA_SG) 447 src_cnt = dst_cnt = sg_buffers; 448 else if (thread->type == DMA_XOR) { 449 /* force odd to ensure dst = src */ 450 src_cnt = min_odd(params->xor_sources | 1, dev->max_xor); 451 dst_cnt = 1; 452 } else if (thread->type == DMA_PQ) { 453 /* force odd to ensure dst = src */ 454 src_cnt = min_odd(params->pq_sources | 1, dma_maxpq(dev, 0)); 455 dst_cnt = 2; 456 457 pq_coefs = kmalloc(params->pq_sources+1, GFP_KERNEL); 458 if (!pq_coefs) 459 goto err_thread_type; 460 461 for (i = 0; i < src_cnt; i++) 462 pq_coefs[i] = 1; 463 } else 464 goto err_thread_type; 465 466 thread->srcs = kcalloc(src_cnt+1, sizeof(u8 *), GFP_KERNEL); 467 if (!thread->srcs) 468 goto err_srcs; 469 for (i = 0; i < src_cnt; i++) { 470 thread->srcs[i] = kmalloc(params->buf_size, GFP_KERNEL); 471 if (!thread->srcs[i]) 472 goto err_srcbuf; 473 } 474 thread->srcs[i] = NULL; 475 476 thread->dsts = kcalloc(dst_cnt+1, sizeof(u8 *), GFP_KERNEL); 477 if (!thread->dsts) 478 goto err_dsts; 479 for (i = 0; i < dst_cnt; i++) { 480 thread->dsts[i] = kmalloc(params->buf_size, GFP_KERNEL); 481 if (!thread->dsts[i]) 482 goto err_dstbuf; 483 } 484 thread->dsts[i] = NULL; 485 486 set_user_nice(current, 10); 487 488 /* 489 * src and dst buffers are freed by ourselves below 490 */ 491 flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; 492 493 ktime = ktime_get(); 494 while (!kthread_should_stop() 495 && !(params->iterations && total_tests >= params->iterations)) { 496 struct dma_async_tx_descriptor *tx = NULL; 497 struct dmaengine_unmap_data *um; 498 dma_addr_t srcs[src_cnt]; 499 dma_addr_t *dsts; 500 unsigned int src_off, dst_off, len; 501 u8 align = 0; 502 struct scatterlist tx_sg[src_cnt]; 503 struct scatterlist rx_sg[src_cnt]; 504 505 total_tests++; 506 507 /* honor alignment restrictions */ 508 if (thread->type == DMA_MEMCPY || thread->type == DMA_SG) 509 align = dev->copy_align; 510 else if (thread->type == DMA_XOR) 511 align = dev->xor_align; 512 else if (thread->type == DMA_PQ) 513 align = dev->pq_align; 514 515 if (1 << align > params->buf_size) { 516 pr_err("%u-byte buffer too small for %d-byte alignment\n", 517 params->buf_size, 1 << align); 518 break; 519 } 520 521 if (params->noverify) 522 len = params->buf_size; 523 else 524 len = dmatest_random() % params->buf_size + 1; 525 526 len = (len >> align) << align; 527 if (!len) 528 len = 1 << align; 529 530 total_len += len; 531 532 if (params->noverify) { 533 src_off = 0; 534 dst_off = 0; 535 } else { 536 start = ktime_get(); 537 src_off = dmatest_random() % (params->buf_size - len + 1); 538 dst_off = dmatest_random() % (params->buf_size - len + 1); 539 540 src_off = (src_off >> align) << align; 541 dst_off = (dst_off >> align) << align; 542 543 dmatest_init_srcs(thread->srcs, src_off, len, 544 params->buf_size); 545 dmatest_init_dsts(thread->dsts, dst_off, len, 546 params->buf_size); 547 548 diff = ktime_sub(ktime_get(), start); 549 filltime = ktime_add(filltime, diff); 550 } 551 552 um = dmaengine_get_unmap_data(dev->dev, src_cnt+dst_cnt, 553 GFP_KERNEL); 554 if (!um) { 555 failed_tests++; 556 result("unmap data NULL", total_tests, 557 src_off, dst_off, len, ret); 558 continue; 559 } 560 561 um->len = params->buf_size; 562 for (i = 0; i < src_cnt; i++) { 563 void *buf = thread->srcs[i]; 564 struct page *pg = virt_to_page(buf); 565 unsigned pg_off = (unsigned long) buf & ~PAGE_MASK; 566 567 um->addr[i] = dma_map_page(dev->dev, pg, pg_off, 568 um->len, DMA_TO_DEVICE); 569 srcs[i] = um->addr[i] + src_off; 570 ret = dma_mapping_error(dev->dev, um->addr[i]); 571 if (ret) { 572 dmaengine_unmap_put(um); 573 result("src mapping error", total_tests, 574 src_off, dst_off, len, ret); 575 failed_tests++; 576 continue; 577 } 578 um->to_cnt++; 579 } 580 /* map with DMA_BIDIRECTIONAL to force writeback/invalidate */ 581 dsts = &um->addr[src_cnt]; 582 for (i = 0; i < dst_cnt; i++) { 583 void *buf = thread->dsts[i]; 584 struct page *pg = virt_to_page(buf); 585 unsigned pg_off = (unsigned long) buf & ~PAGE_MASK; 586 587 dsts[i] = dma_map_page(dev->dev, pg, pg_off, um->len, 588 DMA_BIDIRECTIONAL); 589 ret = dma_mapping_error(dev->dev, dsts[i]); 590 if (ret) { 591 dmaengine_unmap_put(um); 592 result("dst mapping error", total_tests, 593 src_off, dst_off, len, ret); 594 failed_tests++; 595 continue; 596 } 597 um->bidi_cnt++; 598 } 599 600 sg_init_table(tx_sg, src_cnt); 601 sg_init_table(rx_sg, src_cnt); 602 for (i = 0; i < src_cnt; i++) { 603 sg_dma_address(&rx_sg[i]) = srcs[i]; 604 sg_dma_address(&tx_sg[i]) = dsts[i] + dst_off; 605 sg_dma_len(&tx_sg[i]) = len; 606 sg_dma_len(&rx_sg[i]) = len; 607 } 608 609 if (thread->type == DMA_MEMCPY) 610 tx = dev->device_prep_dma_memcpy(chan, 611 dsts[0] + dst_off, 612 srcs[0], len, flags); 613 else if (thread->type == DMA_SG) 614 tx = dev->device_prep_dma_sg(chan, tx_sg, src_cnt, 615 rx_sg, src_cnt, flags); 616 else if (thread->type == DMA_XOR) 617 tx = dev->device_prep_dma_xor(chan, 618 dsts[0] + dst_off, 619 srcs, src_cnt, 620 len, flags); 621 else if (thread->type == DMA_PQ) { 622 dma_addr_t dma_pq[dst_cnt]; 623 624 for (i = 0; i < dst_cnt; i++) 625 dma_pq[i] = dsts[i] + dst_off; 626 tx = dev->device_prep_dma_pq(chan, dma_pq, srcs, 627 src_cnt, pq_coefs, 628 len, flags); 629 } 630 631 if (!tx) { 632 dmaengine_unmap_put(um); 633 result("prep error", total_tests, src_off, 634 dst_off, len, ret); 635 msleep(100); 636 failed_tests++; 637 continue; 638 } 639 640 done.done = false; 641 tx->callback = dmatest_callback; 642 tx->callback_param = &done; 643 cookie = tx->tx_submit(tx); 644 645 if (dma_submit_error(cookie)) { 646 dmaengine_unmap_put(um); 647 result("submit error", total_tests, src_off, 648 dst_off, len, ret); 649 msleep(100); 650 failed_tests++; 651 continue; 652 } 653 dma_async_issue_pending(chan); 654 655 wait_event_freezable_timeout(done_wait, done.done, 656 msecs_to_jiffies(params->timeout)); 657 658 status = dma_async_is_tx_complete(chan, cookie, NULL, NULL); 659 660 if (!done.done) { 661 /* 662 * We're leaving the timed out dma operation with 663 * dangling pointer to done_wait. To make this 664 * correct, we'll need to allocate wait_done for 665 * each test iteration and perform "who's gonna 666 * free it this time?" dancing. For now, just 667 * leave it dangling. 668 */ 669 dmaengine_unmap_put(um); 670 result("test timed out", total_tests, src_off, dst_off, 671 len, 0); 672 failed_tests++; 673 continue; 674 } else if (status != DMA_COMPLETE) { 675 dmaengine_unmap_put(um); 676 result(status == DMA_ERROR ? 677 "completion error status" : 678 "completion busy status", total_tests, src_off, 679 dst_off, len, ret); 680 failed_tests++; 681 continue; 682 } 683 684 dmaengine_unmap_put(um); 685 686 if (params->noverify) { 687 verbose_result("test passed", total_tests, src_off, 688 dst_off, len, 0); 689 continue; 690 } 691 692 start = ktime_get(); 693 pr_debug("%s: verifying source buffer...\n", current->comm); 694 error_count = dmatest_verify(thread->srcs, 0, src_off, 695 0, PATTERN_SRC, true); 696 error_count += dmatest_verify(thread->srcs, src_off, 697 src_off + len, src_off, 698 PATTERN_SRC | PATTERN_COPY, true); 699 error_count += dmatest_verify(thread->srcs, src_off + len, 700 params->buf_size, src_off + len, 701 PATTERN_SRC, true); 702 703 pr_debug("%s: verifying dest buffer...\n", current->comm); 704 error_count += dmatest_verify(thread->dsts, 0, dst_off, 705 0, PATTERN_DST, false); 706 error_count += dmatest_verify(thread->dsts, dst_off, 707 dst_off + len, src_off, 708 PATTERN_SRC | PATTERN_COPY, false); 709 error_count += dmatest_verify(thread->dsts, dst_off + len, 710 params->buf_size, dst_off + len, 711 PATTERN_DST, false); 712 713 diff = ktime_sub(ktime_get(), start); 714 comparetime = ktime_add(comparetime, diff); 715 716 if (error_count) { 717 result("data error", total_tests, src_off, dst_off, 718 len, error_count); 719 failed_tests++; 720 } else { 721 verbose_result("test passed", total_tests, src_off, 722 dst_off, len, 0); 723 } 724 } 725 ktime = ktime_sub(ktime_get(), ktime); 726 ktime = ktime_sub(ktime, comparetime); 727 ktime = ktime_sub(ktime, filltime); 728 runtime = ktime_to_us(ktime); 729 730 ret = 0; 731 err_dstbuf: 732 for (i = 0; thread->dsts[i]; i++) 733 kfree(thread->dsts[i]); 734 kfree(thread->dsts); 735 err_dsts: 736 err_srcbuf: 737 for (i = 0; thread->srcs[i]; i++) 738 kfree(thread->srcs[i]); 739 kfree(thread->srcs); 740 err_srcs: 741 kfree(pq_coefs); 742 err_thread_type: 743 pr_info("%s: summary %u tests, %u failures %llu iops %llu KB/s (%d)\n", 744 current->comm, total_tests, failed_tests, 745 dmatest_persec(runtime, total_tests), 746 dmatest_KBs(runtime, total_len), ret); 747 748 /* terminate all transfers on specified channels */ 749 if (ret) 750 dmaengine_terminate_all(chan); 751 752 thread->done = true; 753 wake_up(&thread_wait); 754 755 return ret; 756 } 757 758 static void dmatest_cleanup_channel(struct dmatest_chan *dtc) 759 { 760 struct dmatest_thread *thread; 761 struct dmatest_thread *_thread; 762 int ret; 763 764 list_for_each_entry_safe(thread, _thread, &dtc->threads, node) { 765 ret = kthread_stop(thread->task); 766 pr_debug("thread %s exited with status %d\n", 767 thread->task->comm, ret); 768 list_del(&thread->node); 769 put_task_struct(thread->task); 770 kfree(thread); 771 } 772 773 /* terminate all transfers on specified channels */ 774 dmaengine_terminate_all(dtc->chan); 775 776 kfree(dtc); 777 } 778 779 static int dmatest_add_threads(struct dmatest_info *info, 780 struct dmatest_chan *dtc, enum dma_transaction_type type) 781 { 782 struct dmatest_params *params = &info->params; 783 struct dmatest_thread *thread; 784 struct dma_chan *chan = dtc->chan; 785 char *op; 786 unsigned int i; 787 788 if (type == DMA_MEMCPY) 789 op = "copy"; 790 else if (type == DMA_SG) 791 op = "sg"; 792 else if (type == DMA_XOR) 793 op = "xor"; 794 else if (type == DMA_PQ) 795 op = "pq"; 796 else 797 return -EINVAL; 798 799 for (i = 0; i < params->threads_per_chan; i++) { 800 thread = kzalloc(sizeof(struct dmatest_thread), GFP_KERNEL); 801 if (!thread) { 802 pr_warn("No memory for %s-%s%u\n", 803 dma_chan_name(chan), op, i); 804 break; 805 } 806 thread->info = info; 807 thread->chan = dtc->chan; 808 thread->type = type; 809 smp_wmb(); 810 thread->task = kthread_create(dmatest_func, thread, "%s-%s%u", 811 dma_chan_name(chan), op, i); 812 if (IS_ERR(thread->task)) { 813 pr_warn("Failed to create thread %s-%s%u\n", 814 dma_chan_name(chan), op, i); 815 kfree(thread); 816 break; 817 } 818 819 /* srcbuf and dstbuf are allocated by the thread itself */ 820 get_task_struct(thread->task); 821 list_add_tail(&thread->node, &dtc->threads); 822 wake_up_process(thread->task); 823 } 824 825 return i; 826 } 827 828 static int dmatest_add_channel(struct dmatest_info *info, 829 struct dma_chan *chan) 830 { 831 struct dmatest_chan *dtc; 832 struct dma_device *dma_dev = chan->device; 833 unsigned int thread_count = 0; 834 int cnt; 835 836 dtc = kmalloc(sizeof(struct dmatest_chan), GFP_KERNEL); 837 if (!dtc) { 838 pr_warn("No memory for %s\n", dma_chan_name(chan)); 839 return -ENOMEM; 840 } 841 842 dtc->chan = chan; 843 INIT_LIST_HEAD(&dtc->threads); 844 845 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) { 846 if (dmatest == 0) { 847 cnt = dmatest_add_threads(info, dtc, DMA_MEMCPY); 848 thread_count += cnt > 0 ? cnt : 0; 849 } 850 } 851 852 if (dma_has_cap(DMA_SG, dma_dev->cap_mask)) { 853 if (dmatest == 1) { 854 cnt = dmatest_add_threads(info, dtc, DMA_SG); 855 thread_count += cnt > 0 ? cnt : 0; 856 } 857 } 858 859 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) { 860 cnt = dmatest_add_threads(info, dtc, DMA_XOR); 861 thread_count += cnt > 0 ? cnt : 0; 862 } 863 if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) { 864 cnt = dmatest_add_threads(info, dtc, DMA_PQ); 865 thread_count += cnt > 0 ? cnt : 0; 866 } 867 868 pr_info("Started %u threads using %s\n", 869 thread_count, dma_chan_name(chan)); 870 871 list_add_tail(&dtc->node, &info->channels); 872 info->nr_channels++; 873 874 return 0; 875 } 876 877 static bool filter(struct dma_chan *chan, void *param) 878 { 879 struct dmatest_params *params = param; 880 881 if (!dmatest_match_channel(params, chan) || 882 !dmatest_match_device(params, chan->device)) 883 return false; 884 else 885 return true; 886 } 887 888 static void request_channels(struct dmatest_info *info, 889 enum dma_transaction_type type) 890 { 891 dma_cap_mask_t mask; 892 893 dma_cap_zero(mask); 894 dma_cap_set(type, mask); 895 for (;;) { 896 struct dmatest_params *params = &info->params; 897 struct dma_chan *chan; 898 899 chan = dma_request_channel(mask, filter, params); 900 if (chan) { 901 if (dmatest_add_channel(info, chan)) { 902 dma_release_channel(chan); 903 break; /* add_channel failed, punt */ 904 } 905 } else 906 break; /* no more channels available */ 907 if (params->max_channels && 908 info->nr_channels >= params->max_channels) 909 break; /* we have all we need */ 910 } 911 } 912 913 static void run_threaded_test(struct dmatest_info *info) 914 { 915 struct dmatest_params *params = &info->params; 916 917 /* Copy test parameters */ 918 params->buf_size = test_buf_size; 919 strlcpy(params->channel, strim(test_channel), sizeof(params->channel)); 920 strlcpy(params->device, strim(test_device), sizeof(params->device)); 921 params->threads_per_chan = threads_per_chan; 922 params->max_channels = max_channels; 923 params->iterations = iterations; 924 params->xor_sources = xor_sources; 925 params->pq_sources = pq_sources; 926 params->timeout = timeout; 927 params->noverify = noverify; 928 929 request_channels(info, DMA_MEMCPY); 930 request_channels(info, DMA_XOR); 931 request_channels(info, DMA_SG); 932 request_channels(info, DMA_PQ); 933 } 934 935 static void stop_threaded_test(struct dmatest_info *info) 936 { 937 struct dmatest_chan *dtc, *_dtc; 938 struct dma_chan *chan; 939 940 list_for_each_entry_safe(dtc, _dtc, &info->channels, node) { 941 list_del(&dtc->node); 942 chan = dtc->chan; 943 dmatest_cleanup_channel(dtc); 944 pr_debug("dropped channel %s\n", dma_chan_name(chan)); 945 dma_release_channel(chan); 946 } 947 948 info->nr_channels = 0; 949 } 950 951 static void restart_threaded_test(struct dmatest_info *info, bool run) 952 { 953 /* we might be called early to set run=, defer running until all 954 * parameters have been evaluated 955 */ 956 if (!info->did_init) 957 return; 958 959 /* Stop any running test first */ 960 stop_threaded_test(info); 961 962 /* Run test with new parameters */ 963 run_threaded_test(info); 964 } 965 966 static int dmatest_run_get(char *val, const struct kernel_param *kp) 967 { 968 struct dmatest_info *info = &test_info; 969 970 mutex_lock(&info->lock); 971 if (is_threaded_test_run(info)) { 972 dmatest_run = true; 973 } else { 974 stop_threaded_test(info); 975 dmatest_run = false; 976 } 977 mutex_unlock(&info->lock); 978 979 return param_get_bool(val, kp); 980 } 981 982 static int dmatest_run_set(const char *val, const struct kernel_param *kp) 983 { 984 struct dmatest_info *info = &test_info; 985 int ret; 986 987 mutex_lock(&info->lock); 988 ret = param_set_bool(val, kp); 989 if (ret) { 990 mutex_unlock(&info->lock); 991 return ret; 992 } 993 994 if (is_threaded_test_run(info)) 995 ret = -EBUSY; 996 else if (dmatest_run) 997 restart_threaded_test(info, dmatest_run); 998 999 mutex_unlock(&info->lock); 1000 1001 return ret; 1002 } 1003 1004 static int __init dmatest_init(void) 1005 { 1006 struct dmatest_info *info = &test_info; 1007 struct dmatest_params *params = &info->params; 1008 1009 if (dmatest_run) { 1010 mutex_lock(&info->lock); 1011 run_threaded_test(info); 1012 mutex_unlock(&info->lock); 1013 } 1014 1015 if (params->iterations && wait) 1016 wait_event(thread_wait, !is_threaded_test_run(info)); 1017 1018 /* module parameters are stable, inittime tests are started, 1019 * let userspace take over 'run' control 1020 */ 1021 info->did_init = true; 1022 1023 return 0; 1024 } 1025 /* when compiled-in wait for drivers to load first */ 1026 late_initcall(dmatest_init); 1027 1028 static void __exit dmatest_exit(void) 1029 { 1030 struct dmatest_info *info = &test_info; 1031 1032 mutex_lock(&info->lock); 1033 stop_threaded_test(info); 1034 mutex_unlock(&info->lock); 1035 } 1036 module_exit(dmatest_exit); 1037 1038 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); 1039 MODULE_LICENSE("GPL v2"); 1040