1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * DMA Engine test module 4 * 5 * Copyright (C) 2007 Atmel Corporation 6 * Copyright (C) 2013 Intel Corporation 7 */ 8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 9 10 #include <linux/err.h> 11 #include <linux/delay.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/dmaengine.h> 14 #include <linux/freezer.h> 15 #include <linux/init.h> 16 #include <linux/kthread.h> 17 #include <linux/sched/task.h> 18 #include <linux/module.h> 19 #include <linux/moduleparam.h> 20 #include <linux/random.h> 21 #include <linux/slab.h> 22 #include <linux/wait.h> 23 24 static unsigned int test_buf_size = 16384; 25 module_param(test_buf_size, uint, S_IRUGO | S_IWUSR); 26 MODULE_PARM_DESC(test_buf_size, "Size of the memcpy test buffer"); 27 28 static char test_device[32]; 29 module_param_string(device, test_device, sizeof(test_device), 30 S_IRUGO | S_IWUSR); 31 MODULE_PARM_DESC(device, "Bus ID of the DMA Engine to test (default: any)"); 32 33 static unsigned int threads_per_chan = 1; 34 module_param(threads_per_chan, uint, S_IRUGO | S_IWUSR); 35 MODULE_PARM_DESC(threads_per_chan, 36 "Number of threads to start per channel (default: 1)"); 37 38 static unsigned int max_channels; 39 module_param(max_channels, uint, S_IRUGO | S_IWUSR); 40 MODULE_PARM_DESC(max_channels, 41 "Maximum number of channels to use (default: all)"); 42 43 static unsigned int iterations; 44 module_param(iterations, uint, S_IRUGO | S_IWUSR); 45 MODULE_PARM_DESC(iterations, 46 "Iterations before stopping test (default: infinite)"); 47 48 static unsigned int dmatest; 49 module_param(dmatest, uint, S_IRUGO | S_IWUSR); 50 MODULE_PARM_DESC(dmatest, 51 "dmatest 0-memcpy 1-memset (default: 0)"); 52 53 static unsigned int xor_sources = 3; 54 module_param(xor_sources, uint, S_IRUGO | S_IWUSR); 55 MODULE_PARM_DESC(xor_sources, 56 "Number of xor source buffers (default: 3)"); 57 58 static unsigned int pq_sources = 3; 59 module_param(pq_sources, uint, S_IRUGO | S_IWUSR); 60 MODULE_PARM_DESC(pq_sources, 61 "Number of p+q source buffers (default: 3)"); 62 63 static int timeout = 3000; 64 module_param(timeout, int, S_IRUGO | S_IWUSR); 65 MODULE_PARM_DESC(timeout, "Transfer Timeout in msec (default: 3000), " 66 "Pass -1 for infinite timeout"); 67 68 static bool noverify; 69 module_param(noverify, bool, S_IRUGO | S_IWUSR); 70 MODULE_PARM_DESC(noverify, "Disable data verification (default: verify)"); 71 72 static bool norandom; 73 module_param(norandom, bool, 0644); 74 MODULE_PARM_DESC(norandom, "Disable random offset setup (default: random)"); 75 76 static bool verbose; 77 module_param(verbose, bool, S_IRUGO | S_IWUSR); 78 MODULE_PARM_DESC(verbose, "Enable \"success\" result messages (default: off)"); 79 80 static int alignment = -1; 81 module_param(alignment, int, 0644); 82 MODULE_PARM_DESC(alignment, "Custom data address alignment taken as 2^(alignment) (default: not used (-1))"); 83 84 static unsigned int transfer_size; 85 module_param(transfer_size, uint, 0644); 86 MODULE_PARM_DESC(transfer_size, "Optional custom transfer size in bytes (default: not used (0))"); 87 88 static bool polled; 89 module_param(polled, bool, S_IRUGO | S_IWUSR); 90 MODULE_PARM_DESC(polled, "Use polling for completion instead of interrupts"); 91 92 /** 93 * struct dmatest_params - test parameters. 94 * @buf_size: size of the memcpy test buffer 95 * @channel: bus ID of the channel to test 96 * @device: bus ID of the DMA Engine to test 97 * @threads_per_chan: number of threads to start per channel 98 * @max_channels: maximum number of channels to use 99 * @iterations: iterations before stopping test 100 * @xor_sources: number of xor source buffers 101 * @pq_sources: number of p+q source buffers 102 * @timeout: transfer timeout in msec, -1 for infinite timeout 103 * @noverify: disable data verification 104 * @norandom: disable random offset setup 105 * @alignment: custom data address alignment taken as 2^alignment 106 * @transfer_size: custom transfer size in bytes 107 * @polled: use polling for completion instead of interrupts 108 */ 109 struct dmatest_params { 110 unsigned int buf_size; 111 char channel[20]; 112 char device[32]; 113 unsigned int threads_per_chan; 114 unsigned int max_channels; 115 unsigned int iterations; 116 unsigned int xor_sources; 117 unsigned int pq_sources; 118 int timeout; 119 bool noverify; 120 bool norandom; 121 int alignment; 122 unsigned int transfer_size; 123 bool polled; 124 }; 125 126 /** 127 * struct dmatest_info - test information. 128 * @params: test parameters 129 * @channels: channels under test 130 * @nr_channels: number of channels under test 131 * @lock: access protection to the fields of this structure 132 * @did_init: module has been initialized completely 133 * @last_error: test has faced configuration issues 134 */ 135 static struct dmatest_info { 136 /* Test parameters */ 137 struct dmatest_params params; 138 139 /* Internal state */ 140 struct list_head channels; 141 unsigned int nr_channels; 142 int last_error; 143 struct mutex lock; 144 bool did_init; 145 } test_info = { 146 .channels = LIST_HEAD_INIT(test_info.channels), 147 .lock = __MUTEX_INITIALIZER(test_info.lock), 148 }; 149 150 static int dmatest_run_set(const char *val, const struct kernel_param *kp); 151 static int dmatest_run_get(char *val, const struct kernel_param *kp); 152 static const struct kernel_param_ops run_ops = { 153 .set = dmatest_run_set, 154 .get = dmatest_run_get, 155 }; 156 static bool dmatest_run; 157 module_param_cb(run, &run_ops, &dmatest_run, S_IRUGO | S_IWUSR); 158 MODULE_PARM_DESC(run, "Run the test (default: false)"); 159 160 static int dmatest_chan_set(const char *val, const struct kernel_param *kp); 161 static int dmatest_chan_get(char *val, const struct kernel_param *kp); 162 static const struct kernel_param_ops multi_chan_ops = { 163 .set = dmatest_chan_set, 164 .get = dmatest_chan_get, 165 }; 166 167 static char test_channel[20]; 168 static struct kparam_string newchan_kps = { 169 .string = test_channel, 170 .maxlen = 20, 171 }; 172 module_param_cb(channel, &multi_chan_ops, &newchan_kps, 0644); 173 MODULE_PARM_DESC(channel, "Bus ID of the channel to test (default: any)"); 174 175 static int dmatest_test_list_get(char *val, const struct kernel_param *kp); 176 static const struct kernel_param_ops test_list_ops = { 177 .get = dmatest_test_list_get, 178 }; 179 module_param_cb(test_list, &test_list_ops, NULL, 0444); 180 MODULE_PARM_DESC(test_list, "Print current test list"); 181 182 /* Maximum amount of mismatched bytes in buffer to print */ 183 #define MAX_ERROR_COUNT 32 184 185 /* 186 * Initialization patterns. All bytes in the source buffer has bit 7 187 * set, all bytes in the destination buffer has bit 7 cleared. 188 * 189 * Bit 6 is set for all bytes which are to be copied by the DMA 190 * engine. Bit 5 is set for all bytes which are to be overwritten by 191 * the DMA engine. 192 * 193 * The remaining bits are the inverse of a counter which increments by 194 * one for each byte address. 195 */ 196 #define PATTERN_SRC 0x80 197 #define PATTERN_DST 0x00 198 #define PATTERN_COPY 0x40 199 #define PATTERN_OVERWRITE 0x20 200 #define PATTERN_COUNT_MASK 0x1f 201 #define PATTERN_MEMSET_IDX 0x01 202 203 /* Fixed point arithmetic ops */ 204 #define FIXPT_SHIFT 8 205 #define FIXPNT_MASK 0xFF 206 #define FIXPT_TO_INT(a) ((a) >> FIXPT_SHIFT) 207 #define INT_TO_FIXPT(a) ((a) << FIXPT_SHIFT) 208 #define FIXPT_GET_FRAC(a) ((((a) & FIXPNT_MASK) * 100) >> FIXPT_SHIFT) 209 210 /* poor man's completion - we want to use wait_event_freezable() on it */ 211 struct dmatest_done { 212 bool done; 213 wait_queue_head_t *wait; 214 }; 215 216 struct dmatest_data { 217 u8 **raw; 218 u8 **aligned; 219 unsigned int cnt; 220 unsigned int off; 221 }; 222 223 struct dmatest_thread { 224 struct list_head node; 225 struct dmatest_info *info; 226 struct task_struct *task; 227 struct dma_chan *chan; 228 struct dmatest_data src; 229 struct dmatest_data dst; 230 enum dma_transaction_type type; 231 wait_queue_head_t done_wait; 232 struct dmatest_done test_done; 233 bool done; 234 bool pending; 235 }; 236 237 struct dmatest_chan { 238 struct list_head node; 239 struct dma_chan *chan; 240 struct list_head threads; 241 }; 242 243 static DECLARE_WAIT_QUEUE_HEAD(thread_wait); 244 static bool wait; 245 246 static bool is_threaded_test_run(struct dmatest_info *info) 247 { 248 struct dmatest_chan *dtc; 249 250 list_for_each_entry(dtc, &info->channels, node) { 251 struct dmatest_thread *thread; 252 253 list_for_each_entry(thread, &dtc->threads, node) { 254 if (!thread->done && !thread->pending) 255 return true; 256 } 257 } 258 259 return false; 260 } 261 262 static bool is_threaded_test_pending(struct dmatest_info *info) 263 { 264 struct dmatest_chan *dtc; 265 266 list_for_each_entry(dtc, &info->channels, node) { 267 struct dmatest_thread *thread; 268 269 list_for_each_entry(thread, &dtc->threads, node) { 270 if (thread->pending) 271 return true; 272 } 273 } 274 275 return false; 276 } 277 278 static int dmatest_wait_get(char *val, const struct kernel_param *kp) 279 { 280 struct dmatest_info *info = &test_info; 281 struct dmatest_params *params = &info->params; 282 283 if (params->iterations) 284 wait_event(thread_wait, !is_threaded_test_run(info)); 285 wait = true; 286 return param_get_bool(val, kp); 287 } 288 289 static const struct kernel_param_ops wait_ops = { 290 .get = dmatest_wait_get, 291 .set = param_set_bool, 292 }; 293 module_param_cb(wait, &wait_ops, &wait, S_IRUGO); 294 MODULE_PARM_DESC(wait, "Wait for tests to complete (default: false)"); 295 296 static bool dmatest_match_channel(struct dmatest_params *params, 297 struct dma_chan *chan) 298 { 299 if (params->channel[0] == '\0') 300 return true; 301 return strcmp(dma_chan_name(chan), params->channel) == 0; 302 } 303 304 static bool dmatest_match_device(struct dmatest_params *params, 305 struct dma_device *device) 306 { 307 if (params->device[0] == '\0') 308 return true; 309 return strcmp(dev_name(device->dev), params->device) == 0; 310 } 311 312 static unsigned long dmatest_random(void) 313 { 314 unsigned long buf; 315 316 prandom_bytes(&buf, sizeof(buf)); 317 return buf; 318 } 319 320 static inline u8 gen_inv_idx(u8 index, bool is_memset) 321 { 322 u8 val = is_memset ? PATTERN_MEMSET_IDX : index; 323 324 return ~val & PATTERN_COUNT_MASK; 325 } 326 327 static inline u8 gen_src_value(u8 index, bool is_memset) 328 { 329 return PATTERN_SRC | gen_inv_idx(index, is_memset); 330 } 331 332 static inline u8 gen_dst_value(u8 index, bool is_memset) 333 { 334 return PATTERN_DST | gen_inv_idx(index, is_memset); 335 } 336 337 static void dmatest_init_srcs(u8 **bufs, unsigned int start, unsigned int len, 338 unsigned int buf_size, bool is_memset) 339 { 340 unsigned int i; 341 u8 *buf; 342 343 for (; (buf = *bufs); bufs++) { 344 for (i = 0; i < start; i++) 345 buf[i] = gen_src_value(i, is_memset); 346 for ( ; i < start + len; i++) 347 buf[i] = gen_src_value(i, is_memset) | PATTERN_COPY; 348 for ( ; i < buf_size; i++) 349 buf[i] = gen_src_value(i, is_memset); 350 buf++; 351 } 352 } 353 354 static void dmatest_init_dsts(u8 **bufs, unsigned int start, unsigned int len, 355 unsigned int buf_size, bool is_memset) 356 { 357 unsigned int i; 358 u8 *buf; 359 360 for (; (buf = *bufs); bufs++) { 361 for (i = 0; i < start; i++) 362 buf[i] = gen_dst_value(i, is_memset); 363 for ( ; i < start + len; i++) 364 buf[i] = gen_dst_value(i, is_memset) | 365 PATTERN_OVERWRITE; 366 for ( ; i < buf_size; i++) 367 buf[i] = gen_dst_value(i, is_memset); 368 } 369 } 370 371 static void dmatest_mismatch(u8 actual, u8 pattern, unsigned int index, 372 unsigned int counter, bool is_srcbuf, bool is_memset) 373 { 374 u8 diff = actual ^ pattern; 375 u8 expected = pattern | gen_inv_idx(counter, is_memset); 376 const char *thread_name = current->comm; 377 378 if (is_srcbuf) 379 pr_warn("%s: srcbuf[0x%x] overwritten! Expected %02x, got %02x\n", 380 thread_name, index, expected, actual); 381 else if ((pattern & PATTERN_COPY) 382 && (diff & (PATTERN_COPY | PATTERN_OVERWRITE))) 383 pr_warn("%s: dstbuf[0x%x] not copied! Expected %02x, got %02x\n", 384 thread_name, index, expected, actual); 385 else if (diff & PATTERN_SRC) 386 pr_warn("%s: dstbuf[0x%x] was copied! Expected %02x, got %02x\n", 387 thread_name, index, expected, actual); 388 else 389 pr_warn("%s: dstbuf[0x%x] mismatch! Expected %02x, got %02x\n", 390 thread_name, index, expected, actual); 391 } 392 393 static unsigned int dmatest_verify(u8 **bufs, unsigned int start, 394 unsigned int end, unsigned int counter, u8 pattern, 395 bool is_srcbuf, bool is_memset) 396 { 397 unsigned int i; 398 unsigned int error_count = 0; 399 u8 actual; 400 u8 expected; 401 u8 *buf; 402 unsigned int counter_orig = counter; 403 404 for (; (buf = *bufs); bufs++) { 405 counter = counter_orig; 406 for (i = start; i < end; i++) { 407 actual = buf[i]; 408 expected = pattern | gen_inv_idx(counter, is_memset); 409 if (actual != expected) { 410 if (error_count < MAX_ERROR_COUNT) 411 dmatest_mismatch(actual, pattern, i, 412 counter, is_srcbuf, 413 is_memset); 414 error_count++; 415 } 416 counter++; 417 } 418 } 419 420 if (error_count > MAX_ERROR_COUNT) 421 pr_warn("%s: %u errors suppressed\n", 422 current->comm, error_count - MAX_ERROR_COUNT); 423 424 return error_count; 425 } 426 427 428 static void dmatest_callback(void *arg) 429 { 430 struct dmatest_done *done = arg; 431 struct dmatest_thread *thread = 432 container_of(done, struct dmatest_thread, test_done); 433 if (!thread->done) { 434 done->done = true; 435 wake_up_all(done->wait); 436 } else { 437 /* 438 * If thread->done, it means that this callback occurred 439 * after the parent thread has cleaned up. This can 440 * happen in the case that driver doesn't implement 441 * the terminate_all() functionality and a dma operation 442 * did not occur within the timeout period 443 */ 444 WARN(1, "dmatest: Kernel memory may be corrupted!!\n"); 445 } 446 } 447 448 static unsigned int min_odd(unsigned int x, unsigned int y) 449 { 450 unsigned int val = min(x, y); 451 452 return val % 2 ? val : val - 1; 453 } 454 455 static void result(const char *err, unsigned int n, unsigned int src_off, 456 unsigned int dst_off, unsigned int len, unsigned long data) 457 { 458 if (IS_ERR_VALUE(data)) { 459 pr_info("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%ld)\n", 460 current->comm, n, err, src_off, dst_off, len, data); 461 } else { 462 pr_info("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n", 463 current->comm, n, err, src_off, dst_off, len, data); 464 } 465 } 466 467 static void dbg_result(const char *err, unsigned int n, unsigned int src_off, 468 unsigned int dst_off, unsigned int len, 469 unsigned long data) 470 { 471 pr_debug("%s: result #%u: '%s' with src_off=0x%x dst_off=0x%x len=0x%x (%lu)\n", 472 current->comm, n, err, src_off, dst_off, len, data); 473 } 474 475 #define verbose_result(err, n, src_off, dst_off, len, data) ({ \ 476 if (verbose) \ 477 result(err, n, src_off, dst_off, len, data); \ 478 else \ 479 dbg_result(err, n, src_off, dst_off, len, data);\ 480 }) 481 482 static unsigned long long dmatest_persec(s64 runtime, unsigned int val) 483 { 484 unsigned long long per_sec = 1000000; 485 486 if (runtime <= 0) 487 return 0; 488 489 /* drop precision until runtime is 32-bits */ 490 while (runtime > UINT_MAX) { 491 runtime >>= 1; 492 per_sec <<= 1; 493 } 494 495 per_sec *= val; 496 per_sec = INT_TO_FIXPT(per_sec); 497 do_div(per_sec, runtime); 498 499 return per_sec; 500 } 501 502 static unsigned long long dmatest_KBs(s64 runtime, unsigned long long len) 503 { 504 return FIXPT_TO_INT(dmatest_persec(runtime, len >> 10)); 505 } 506 507 static void __dmatest_free_test_data(struct dmatest_data *d, unsigned int cnt) 508 { 509 unsigned int i; 510 511 for (i = 0; i < cnt; i++) 512 kfree(d->raw[i]); 513 514 kfree(d->aligned); 515 kfree(d->raw); 516 } 517 518 static void dmatest_free_test_data(struct dmatest_data *d) 519 { 520 __dmatest_free_test_data(d, d->cnt); 521 } 522 523 static int dmatest_alloc_test_data(struct dmatest_data *d, 524 unsigned int buf_size, u8 align) 525 { 526 unsigned int i = 0; 527 528 d->raw = kcalloc(d->cnt + 1, sizeof(u8 *), GFP_KERNEL); 529 if (!d->raw) 530 return -ENOMEM; 531 532 d->aligned = kcalloc(d->cnt + 1, sizeof(u8 *), GFP_KERNEL); 533 if (!d->aligned) 534 goto err; 535 536 for (i = 0; i < d->cnt; i++) { 537 d->raw[i] = kmalloc(buf_size + align, GFP_KERNEL); 538 if (!d->raw[i]) 539 goto err; 540 541 /* align to alignment restriction */ 542 if (align) 543 d->aligned[i] = PTR_ALIGN(d->raw[i], align); 544 else 545 d->aligned[i] = d->raw[i]; 546 } 547 548 return 0; 549 err: 550 __dmatest_free_test_data(d, i); 551 return -ENOMEM; 552 } 553 554 /* 555 * This function repeatedly tests DMA transfers of various lengths and 556 * offsets for a given operation type until it is told to exit by 557 * kthread_stop(). There may be multiple threads running this function 558 * in parallel for a single channel, and there may be multiple channels 559 * being tested in parallel. 560 * 561 * Before each test, the source and destination buffer is initialized 562 * with a known pattern. This pattern is different depending on 563 * whether it's in an area which is supposed to be copied or 564 * overwritten, and different in the source and destination buffers. 565 * So if the DMA engine doesn't copy exactly what we tell it to copy, 566 * we'll notice. 567 */ 568 static int dmatest_func(void *data) 569 { 570 struct dmatest_thread *thread = data; 571 struct dmatest_done *done = &thread->test_done; 572 struct dmatest_info *info; 573 struct dmatest_params *params; 574 struct dma_chan *chan; 575 struct dma_device *dev; 576 unsigned int error_count; 577 unsigned int failed_tests = 0; 578 unsigned int total_tests = 0; 579 dma_cookie_t cookie; 580 enum dma_status status; 581 enum dma_ctrl_flags flags; 582 u8 *pq_coefs = NULL; 583 int ret; 584 unsigned int buf_size; 585 struct dmatest_data *src; 586 struct dmatest_data *dst; 587 int i; 588 ktime_t ktime, start, diff; 589 ktime_t filltime = 0; 590 ktime_t comparetime = 0; 591 s64 runtime = 0; 592 unsigned long long total_len = 0; 593 unsigned long long iops = 0; 594 u8 align = 0; 595 bool is_memset = false; 596 dma_addr_t *srcs; 597 dma_addr_t *dma_pq; 598 599 set_freezable(); 600 601 ret = -ENOMEM; 602 603 smp_rmb(); 604 thread->pending = false; 605 info = thread->info; 606 params = &info->params; 607 chan = thread->chan; 608 dev = chan->device; 609 src = &thread->src; 610 dst = &thread->dst; 611 if (thread->type == DMA_MEMCPY) { 612 align = params->alignment < 0 ? dev->copy_align : 613 params->alignment; 614 src->cnt = dst->cnt = 1; 615 } else if (thread->type == DMA_MEMSET) { 616 align = params->alignment < 0 ? dev->fill_align : 617 params->alignment; 618 src->cnt = dst->cnt = 1; 619 is_memset = true; 620 } else if (thread->type == DMA_XOR) { 621 /* force odd to ensure dst = src */ 622 src->cnt = min_odd(params->xor_sources | 1, dev->max_xor); 623 dst->cnt = 1; 624 align = params->alignment < 0 ? dev->xor_align : 625 params->alignment; 626 } else if (thread->type == DMA_PQ) { 627 /* force odd to ensure dst = src */ 628 src->cnt = min_odd(params->pq_sources | 1, dma_maxpq(dev, 0)); 629 dst->cnt = 2; 630 align = params->alignment < 0 ? dev->pq_align : 631 params->alignment; 632 633 pq_coefs = kmalloc(params->pq_sources + 1, GFP_KERNEL); 634 if (!pq_coefs) 635 goto err_thread_type; 636 637 for (i = 0; i < src->cnt; i++) 638 pq_coefs[i] = 1; 639 } else 640 goto err_thread_type; 641 642 /* Check if buffer count fits into map count variable (u8) */ 643 if ((src->cnt + dst->cnt) >= 255) { 644 pr_err("too many buffers (%d of 255 supported)\n", 645 src->cnt + dst->cnt); 646 goto err_free_coefs; 647 } 648 649 buf_size = params->buf_size; 650 if (1 << align > buf_size) { 651 pr_err("%u-byte buffer too small for %d-byte alignment\n", 652 buf_size, 1 << align); 653 goto err_free_coefs; 654 } 655 656 if (dmatest_alloc_test_data(src, buf_size, align) < 0) 657 goto err_free_coefs; 658 659 if (dmatest_alloc_test_data(dst, buf_size, align) < 0) 660 goto err_src; 661 662 set_user_nice(current, 10); 663 664 srcs = kcalloc(src->cnt, sizeof(dma_addr_t), GFP_KERNEL); 665 if (!srcs) 666 goto err_dst; 667 668 dma_pq = kcalloc(dst->cnt, sizeof(dma_addr_t), GFP_KERNEL); 669 if (!dma_pq) 670 goto err_srcs_array; 671 672 /* 673 * src and dst buffers are freed by ourselves below 674 */ 675 if (params->polled) 676 flags = DMA_CTRL_ACK; 677 else 678 flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; 679 680 ktime = ktime_get(); 681 while (!(kthread_should_stop() || 682 (params->iterations && total_tests >= params->iterations))) { 683 struct dma_async_tx_descriptor *tx = NULL; 684 struct dmaengine_unmap_data *um; 685 dma_addr_t *dsts; 686 unsigned int len; 687 688 total_tests++; 689 690 if (params->transfer_size) { 691 if (params->transfer_size >= buf_size) { 692 pr_err("%u-byte transfer size must be lower than %u-buffer size\n", 693 params->transfer_size, buf_size); 694 break; 695 } 696 len = params->transfer_size; 697 } else if (params->norandom) { 698 len = buf_size; 699 } else { 700 len = dmatest_random() % buf_size + 1; 701 } 702 703 /* Do not alter transfer size explicitly defined by user */ 704 if (!params->transfer_size) { 705 len = (len >> align) << align; 706 if (!len) 707 len = 1 << align; 708 } 709 total_len += len; 710 711 if (params->norandom) { 712 src->off = 0; 713 dst->off = 0; 714 } else { 715 src->off = dmatest_random() % (buf_size - len + 1); 716 dst->off = dmatest_random() % (buf_size - len + 1); 717 718 src->off = (src->off >> align) << align; 719 dst->off = (dst->off >> align) << align; 720 } 721 722 if (!params->noverify) { 723 start = ktime_get(); 724 dmatest_init_srcs(src->aligned, src->off, len, 725 buf_size, is_memset); 726 dmatest_init_dsts(dst->aligned, dst->off, len, 727 buf_size, is_memset); 728 729 diff = ktime_sub(ktime_get(), start); 730 filltime = ktime_add(filltime, diff); 731 } 732 733 um = dmaengine_get_unmap_data(dev->dev, src->cnt + dst->cnt, 734 GFP_KERNEL); 735 if (!um) { 736 failed_tests++; 737 result("unmap data NULL", total_tests, 738 src->off, dst->off, len, ret); 739 continue; 740 } 741 742 um->len = buf_size; 743 for (i = 0; i < src->cnt; i++) { 744 void *buf = src->aligned[i]; 745 struct page *pg = virt_to_page(buf); 746 unsigned long pg_off = offset_in_page(buf); 747 748 um->addr[i] = dma_map_page(dev->dev, pg, pg_off, 749 um->len, DMA_TO_DEVICE); 750 srcs[i] = um->addr[i] + src->off; 751 ret = dma_mapping_error(dev->dev, um->addr[i]); 752 if (ret) { 753 result("src mapping error", total_tests, 754 src->off, dst->off, len, ret); 755 goto error_unmap_continue; 756 } 757 um->to_cnt++; 758 } 759 /* map with DMA_BIDIRECTIONAL to force writeback/invalidate */ 760 dsts = &um->addr[src->cnt]; 761 for (i = 0; i < dst->cnt; i++) { 762 void *buf = dst->aligned[i]; 763 struct page *pg = virt_to_page(buf); 764 unsigned long pg_off = offset_in_page(buf); 765 766 dsts[i] = dma_map_page(dev->dev, pg, pg_off, um->len, 767 DMA_BIDIRECTIONAL); 768 ret = dma_mapping_error(dev->dev, dsts[i]); 769 if (ret) { 770 result("dst mapping error", total_tests, 771 src->off, dst->off, len, ret); 772 goto error_unmap_continue; 773 } 774 um->bidi_cnt++; 775 } 776 777 if (thread->type == DMA_MEMCPY) 778 tx = dev->device_prep_dma_memcpy(chan, 779 dsts[0] + dst->off, 780 srcs[0], len, flags); 781 else if (thread->type == DMA_MEMSET) 782 tx = dev->device_prep_dma_memset(chan, 783 dsts[0] + dst->off, 784 *(src->aligned[0] + src->off), 785 len, flags); 786 else if (thread->type == DMA_XOR) 787 tx = dev->device_prep_dma_xor(chan, 788 dsts[0] + dst->off, 789 srcs, src->cnt, 790 len, flags); 791 else if (thread->type == DMA_PQ) { 792 for (i = 0; i < dst->cnt; i++) 793 dma_pq[i] = dsts[i] + dst->off; 794 tx = dev->device_prep_dma_pq(chan, dma_pq, srcs, 795 src->cnt, pq_coefs, 796 len, flags); 797 } 798 799 if (!tx) { 800 result("prep error", total_tests, src->off, 801 dst->off, len, ret); 802 msleep(100); 803 goto error_unmap_continue; 804 } 805 806 done->done = false; 807 if (!params->polled) { 808 tx->callback = dmatest_callback; 809 tx->callback_param = done; 810 } 811 cookie = tx->tx_submit(tx); 812 813 if (dma_submit_error(cookie)) { 814 result("submit error", total_tests, src->off, 815 dst->off, len, ret); 816 msleep(100); 817 goto error_unmap_continue; 818 } 819 820 if (params->polled) { 821 status = dma_sync_wait(chan, cookie); 822 dmaengine_terminate_sync(chan); 823 if (status == DMA_COMPLETE) 824 done->done = true; 825 } else { 826 dma_async_issue_pending(chan); 827 828 wait_event_freezable_timeout(thread->done_wait, 829 done->done, 830 msecs_to_jiffies(params->timeout)); 831 832 status = dma_async_is_tx_complete(chan, cookie, NULL, 833 NULL); 834 } 835 836 if (!done->done) { 837 result("test timed out", total_tests, src->off, dst->off, 838 len, 0); 839 goto error_unmap_continue; 840 } else if (status != DMA_COMPLETE && 841 !(dma_has_cap(DMA_COMPLETION_NO_ORDER, 842 dev->cap_mask) && 843 status == DMA_OUT_OF_ORDER)) { 844 result(status == DMA_ERROR ? 845 "completion error status" : 846 "completion busy status", total_tests, src->off, 847 dst->off, len, ret); 848 goto error_unmap_continue; 849 } 850 851 dmaengine_unmap_put(um); 852 853 if (params->noverify) { 854 verbose_result("test passed", total_tests, src->off, 855 dst->off, len, 0); 856 continue; 857 } 858 859 start = ktime_get(); 860 pr_debug("%s: verifying source buffer...\n", current->comm); 861 error_count = dmatest_verify(src->aligned, 0, src->off, 862 0, PATTERN_SRC, true, is_memset); 863 error_count += dmatest_verify(src->aligned, src->off, 864 src->off + len, src->off, 865 PATTERN_SRC | PATTERN_COPY, true, is_memset); 866 error_count += dmatest_verify(src->aligned, src->off + len, 867 buf_size, src->off + len, 868 PATTERN_SRC, true, is_memset); 869 870 pr_debug("%s: verifying dest buffer...\n", current->comm); 871 error_count += dmatest_verify(dst->aligned, 0, dst->off, 872 0, PATTERN_DST, false, is_memset); 873 874 error_count += dmatest_verify(dst->aligned, dst->off, 875 dst->off + len, src->off, 876 PATTERN_SRC | PATTERN_COPY, false, is_memset); 877 878 error_count += dmatest_verify(dst->aligned, dst->off + len, 879 buf_size, dst->off + len, 880 PATTERN_DST, false, is_memset); 881 882 diff = ktime_sub(ktime_get(), start); 883 comparetime = ktime_add(comparetime, diff); 884 885 if (error_count) { 886 result("data error", total_tests, src->off, dst->off, 887 len, error_count); 888 failed_tests++; 889 } else { 890 verbose_result("test passed", total_tests, src->off, 891 dst->off, len, 0); 892 } 893 894 continue; 895 896 error_unmap_continue: 897 dmaengine_unmap_put(um); 898 failed_tests++; 899 } 900 ktime = ktime_sub(ktime_get(), ktime); 901 ktime = ktime_sub(ktime, comparetime); 902 ktime = ktime_sub(ktime, filltime); 903 runtime = ktime_to_us(ktime); 904 905 ret = 0; 906 kfree(dma_pq); 907 err_srcs_array: 908 kfree(srcs); 909 err_dst: 910 dmatest_free_test_data(dst); 911 err_src: 912 dmatest_free_test_data(src); 913 err_free_coefs: 914 kfree(pq_coefs); 915 err_thread_type: 916 iops = dmatest_persec(runtime, total_tests); 917 pr_info("%s: summary %u tests, %u failures %llu.%02llu iops %llu KB/s (%d)\n", 918 current->comm, total_tests, failed_tests, 919 FIXPT_TO_INT(iops), FIXPT_GET_FRAC(iops), 920 dmatest_KBs(runtime, total_len), ret); 921 922 /* terminate all transfers on specified channels */ 923 if (ret || failed_tests) 924 dmaengine_terminate_sync(chan); 925 926 thread->done = true; 927 wake_up(&thread_wait); 928 929 return ret; 930 } 931 932 static void dmatest_cleanup_channel(struct dmatest_chan *dtc) 933 { 934 struct dmatest_thread *thread; 935 struct dmatest_thread *_thread; 936 int ret; 937 938 list_for_each_entry_safe(thread, _thread, &dtc->threads, node) { 939 ret = kthread_stop(thread->task); 940 pr_debug("thread %s exited with status %d\n", 941 thread->task->comm, ret); 942 list_del(&thread->node); 943 put_task_struct(thread->task); 944 kfree(thread); 945 } 946 947 /* terminate all transfers on specified channels */ 948 dmaengine_terminate_sync(dtc->chan); 949 950 kfree(dtc); 951 } 952 953 static int dmatest_add_threads(struct dmatest_info *info, 954 struct dmatest_chan *dtc, enum dma_transaction_type type) 955 { 956 struct dmatest_params *params = &info->params; 957 struct dmatest_thread *thread; 958 struct dma_chan *chan = dtc->chan; 959 char *op; 960 unsigned int i; 961 962 if (type == DMA_MEMCPY) 963 op = "copy"; 964 else if (type == DMA_MEMSET) 965 op = "set"; 966 else if (type == DMA_XOR) 967 op = "xor"; 968 else if (type == DMA_PQ) 969 op = "pq"; 970 else 971 return -EINVAL; 972 973 for (i = 0; i < params->threads_per_chan; i++) { 974 thread = kzalloc(sizeof(struct dmatest_thread), GFP_KERNEL); 975 if (!thread) { 976 pr_warn("No memory for %s-%s%u\n", 977 dma_chan_name(chan), op, i); 978 break; 979 } 980 thread->info = info; 981 thread->chan = dtc->chan; 982 thread->type = type; 983 thread->test_done.wait = &thread->done_wait; 984 init_waitqueue_head(&thread->done_wait); 985 smp_wmb(); 986 thread->task = kthread_create(dmatest_func, thread, "%s-%s%u", 987 dma_chan_name(chan), op, i); 988 if (IS_ERR(thread->task)) { 989 pr_warn("Failed to create thread %s-%s%u\n", 990 dma_chan_name(chan), op, i); 991 kfree(thread); 992 break; 993 } 994 995 /* srcbuf and dstbuf are allocated by the thread itself */ 996 get_task_struct(thread->task); 997 list_add_tail(&thread->node, &dtc->threads); 998 thread->pending = true; 999 } 1000 1001 return i; 1002 } 1003 1004 static int dmatest_add_channel(struct dmatest_info *info, 1005 struct dma_chan *chan) 1006 { 1007 struct dmatest_chan *dtc; 1008 struct dma_device *dma_dev = chan->device; 1009 unsigned int thread_count = 0; 1010 int cnt; 1011 1012 dtc = kmalloc(sizeof(struct dmatest_chan), GFP_KERNEL); 1013 if (!dtc) { 1014 pr_warn("No memory for %s\n", dma_chan_name(chan)); 1015 return -ENOMEM; 1016 } 1017 1018 dtc->chan = chan; 1019 INIT_LIST_HEAD(&dtc->threads); 1020 1021 if (dma_has_cap(DMA_COMPLETION_NO_ORDER, dma_dev->cap_mask) && 1022 info->params.polled) { 1023 info->params.polled = false; 1024 pr_warn("DMA_COMPLETION_NO_ORDER, polled disabled\n"); 1025 } 1026 1027 if (dma_has_cap(DMA_MEMCPY, dma_dev->cap_mask)) { 1028 if (dmatest == 0) { 1029 cnt = dmatest_add_threads(info, dtc, DMA_MEMCPY); 1030 thread_count += cnt > 0 ? cnt : 0; 1031 } 1032 } 1033 1034 if (dma_has_cap(DMA_MEMSET, dma_dev->cap_mask)) { 1035 if (dmatest == 1) { 1036 cnt = dmatest_add_threads(info, dtc, DMA_MEMSET); 1037 thread_count += cnt > 0 ? cnt : 0; 1038 } 1039 } 1040 1041 if (dma_has_cap(DMA_XOR, dma_dev->cap_mask)) { 1042 cnt = dmatest_add_threads(info, dtc, DMA_XOR); 1043 thread_count += cnt > 0 ? cnt : 0; 1044 } 1045 if (dma_has_cap(DMA_PQ, dma_dev->cap_mask)) { 1046 cnt = dmatest_add_threads(info, dtc, DMA_PQ); 1047 thread_count += cnt > 0 ? cnt : 0; 1048 } 1049 1050 pr_info("Added %u threads using %s\n", 1051 thread_count, dma_chan_name(chan)); 1052 1053 list_add_tail(&dtc->node, &info->channels); 1054 info->nr_channels++; 1055 1056 return 0; 1057 } 1058 1059 static bool filter(struct dma_chan *chan, void *param) 1060 { 1061 return dmatest_match_channel(param, chan) && dmatest_match_device(param, chan->device); 1062 } 1063 1064 static void request_channels(struct dmatest_info *info, 1065 enum dma_transaction_type type) 1066 { 1067 dma_cap_mask_t mask; 1068 1069 dma_cap_zero(mask); 1070 dma_cap_set(type, mask); 1071 for (;;) { 1072 struct dmatest_params *params = &info->params; 1073 struct dma_chan *chan; 1074 1075 chan = dma_request_channel(mask, filter, params); 1076 if (chan) { 1077 if (dmatest_add_channel(info, chan)) { 1078 dma_release_channel(chan); 1079 break; /* add_channel failed, punt */ 1080 } 1081 } else 1082 break; /* no more channels available */ 1083 if (params->max_channels && 1084 info->nr_channels >= params->max_channels) 1085 break; /* we have all we need */ 1086 } 1087 } 1088 1089 static void add_threaded_test(struct dmatest_info *info) 1090 { 1091 struct dmatest_params *params = &info->params; 1092 1093 /* Copy test parameters */ 1094 params->buf_size = test_buf_size; 1095 strlcpy(params->channel, strim(test_channel), sizeof(params->channel)); 1096 strlcpy(params->device, strim(test_device), sizeof(params->device)); 1097 params->threads_per_chan = threads_per_chan; 1098 params->max_channels = max_channels; 1099 params->iterations = iterations; 1100 params->xor_sources = xor_sources; 1101 params->pq_sources = pq_sources; 1102 params->timeout = timeout; 1103 params->noverify = noverify; 1104 params->norandom = norandom; 1105 params->alignment = alignment; 1106 params->transfer_size = transfer_size; 1107 params->polled = polled; 1108 1109 request_channels(info, DMA_MEMCPY); 1110 request_channels(info, DMA_MEMSET); 1111 request_channels(info, DMA_XOR); 1112 request_channels(info, DMA_PQ); 1113 } 1114 1115 static void run_pending_tests(struct dmatest_info *info) 1116 { 1117 struct dmatest_chan *dtc; 1118 unsigned int thread_count = 0; 1119 1120 list_for_each_entry(dtc, &info->channels, node) { 1121 struct dmatest_thread *thread; 1122 1123 thread_count = 0; 1124 list_for_each_entry(thread, &dtc->threads, node) { 1125 wake_up_process(thread->task); 1126 thread_count++; 1127 } 1128 pr_info("Started %u threads using %s\n", 1129 thread_count, dma_chan_name(dtc->chan)); 1130 } 1131 } 1132 1133 static void stop_threaded_test(struct dmatest_info *info) 1134 { 1135 struct dmatest_chan *dtc, *_dtc; 1136 struct dma_chan *chan; 1137 1138 list_for_each_entry_safe(dtc, _dtc, &info->channels, node) { 1139 list_del(&dtc->node); 1140 chan = dtc->chan; 1141 dmatest_cleanup_channel(dtc); 1142 pr_debug("dropped channel %s\n", dma_chan_name(chan)); 1143 dma_release_channel(chan); 1144 } 1145 1146 info->nr_channels = 0; 1147 } 1148 1149 static void start_threaded_tests(struct dmatest_info *info) 1150 { 1151 /* we might be called early to set run=, defer running until all 1152 * parameters have been evaluated 1153 */ 1154 if (!info->did_init) 1155 return; 1156 1157 run_pending_tests(info); 1158 } 1159 1160 static int dmatest_run_get(char *val, const struct kernel_param *kp) 1161 { 1162 struct dmatest_info *info = &test_info; 1163 1164 mutex_lock(&info->lock); 1165 if (is_threaded_test_run(info)) { 1166 dmatest_run = true; 1167 } else { 1168 if (!is_threaded_test_pending(info)) 1169 stop_threaded_test(info); 1170 dmatest_run = false; 1171 } 1172 mutex_unlock(&info->lock); 1173 1174 return param_get_bool(val, kp); 1175 } 1176 1177 static int dmatest_run_set(const char *val, const struct kernel_param *kp) 1178 { 1179 struct dmatest_info *info = &test_info; 1180 int ret; 1181 1182 mutex_lock(&info->lock); 1183 ret = param_set_bool(val, kp); 1184 if (ret) { 1185 mutex_unlock(&info->lock); 1186 return ret; 1187 } else if (dmatest_run) { 1188 if (!is_threaded_test_pending(info)) { 1189 /* 1190 * We have nothing to run. This can be due to: 1191 */ 1192 ret = info->last_error; 1193 if (ret) { 1194 /* 1) Misconfiguration */ 1195 pr_err("Channel misconfigured, can't continue\n"); 1196 mutex_unlock(&info->lock); 1197 return ret; 1198 } else { 1199 /* 2) We rely on defaults */ 1200 pr_info("No channels configured, continue with any\n"); 1201 if (!is_threaded_test_run(info)) 1202 stop_threaded_test(info); 1203 add_threaded_test(info); 1204 } 1205 } 1206 start_threaded_tests(info); 1207 } else { 1208 stop_threaded_test(info); 1209 } 1210 1211 mutex_unlock(&info->lock); 1212 1213 return ret; 1214 } 1215 1216 static int dmatest_chan_set(const char *val, const struct kernel_param *kp) 1217 { 1218 struct dmatest_info *info = &test_info; 1219 struct dmatest_chan *dtc; 1220 char chan_reset_val[20]; 1221 int ret; 1222 1223 mutex_lock(&info->lock); 1224 ret = param_set_copystring(val, kp); 1225 if (ret) { 1226 mutex_unlock(&info->lock); 1227 return ret; 1228 } 1229 /*Clear any previously run threads */ 1230 if (!is_threaded_test_run(info) && !is_threaded_test_pending(info)) 1231 stop_threaded_test(info); 1232 /* Reject channels that are already registered */ 1233 if (is_threaded_test_pending(info)) { 1234 list_for_each_entry(dtc, &info->channels, node) { 1235 if (strcmp(dma_chan_name(dtc->chan), 1236 strim(test_channel)) == 0) { 1237 dtc = list_last_entry(&info->channels, 1238 struct dmatest_chan, 1239 node); 1240 strlcpy(chan_reset_val, 1241 dma_chan_name(dtc->chan), 1242 sizeof(chan_reset_val)); 1243 ret = -EBUSY; 1244 goto add_chan_err; 1245 } 1246 } 1247 } 1248 1249 add_threaded_test(info); 1250 1251 /* Check if channel was added successfully */ 1252 if (!list_empty(&info->channels)) { 1253 /* 1254 * if new channel was not successfully added, revert the 1255 * "test_channel" string to the name of the last successfully 1256 * added channel. exception for when users issues empty string 1257 * to channel parameter. 1258 */ 1259 dtc = list_last_entry(&info->channels, struct dmatest_chan, node); 1260 if ((strcmp(dma_chan_name(dtc->chan), strim(test_channel)) != 0) 1261 && (strcmp("", strim(test_channel)) != 0)) { 1262 ret = -EINVAL; 1263 strlcpy(chan_reset_val, dma_chan_name(dtc->chan), 1264 sizeof(chan_reset_val)); 1265 goto add_chan_err; 1266 } 1267 1268 } else { 1269 /* Clear test_channel if no channels were added successfully */ 1270 strlcpy(chan_reset_val, "", sizeof(chan_reset_val)); 1271 ret = -EBUSY; 1272 goto add_chan_err; 1273 } 1274 1275 info->last_error = ret; 1276 mutex_unlock(&info->lock); 1277 1278 return ret; 1279 1280 add_chan_err: 1281 param_set_copystring(chan_reset_val, kp); 1282 info->last_error = ret; 1283 mutex_unlock(&info->lock); 1284 1285 return ret; 1286 } 1287 1288 static int dmatest_chan_get(char *val, const struct kernel_param *kp) 1289 { 1290 struct dmatest_info *info = &test_info; 1291 1292 mutex_lock(&info->lock); 1293 if (!is_threaded_test_run(info) && !is_threaded_test_pending(info)) { 1294 stop_threaded_test(info); 1295 strlcpy(test_channel, "", sizeof(test_channel)); 1296 } 1297 mutex_unlock(&info->lock); 1298 1299 return param_get_string(val, kp); 1300 } 1301 1302 static int dmatest_test_list_get(char *val, const struct kernel_param *kp) 1303 { 1304 struct dmatest_info *info = &test_info; 1305 struct dmatest_chan *dtc; 1306 unsigned int thread_count = 0; 1307 1308 list_for_each_entry(dtc, &info->channels, node) { 1309 struct dmatest_thread *thread; 1310 1311 thread_count = 0; 1312 list_for_each_entry(thread, &dtc->threads, node) { 1313 thread_count++; 1314 } 1315 pr_info("%u threads using %s\n", 1316 thread_count, dma_chan_name(dtc->chan)); 1317 } 1318 1319 return 0; 1320 } 1321 1322 static int __init dmatest_init(void) 1323 { 1324 struct dmatest_info *info = &test_info; 1325 struct dmatest_params *params = &info->params; 1326 1327 if (dmatest_run) { 1328 mutex_lock(&info->lock); 1329 add_threaded_test(info); 1330 run_pending_tests(info); 1331 mutex_unlock(&info->lock); 1332 } 1333 1334 if (params->iterations && wait) 1335 wait_event(thread_wait, !is_threaded_test_run(info)); 1336 1337 /* module parameters are stable, inittime tests are started, 1338 * let userspace take over 'run' control 1339 */ 1340 info->did_init = true; 1341 1342 return 0; 1343 } 1344 /* when compiled-in wait for drivers to load first */ 1345 late_initcall(dmatest_init); 1346 1347 static void __exit dmatest_exit(void) 1348 { 1349 struct dmatest_info *info = &test_info; 1350 1351 mutex_lock(&info->lock); 1352 stop_threaded_test(info); 1353 mutex_unlock(&info->lock); 1354 } 1355 module_exit(dmatest_exit); 1356 1357 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)"); 1358 MODULE_LICENSE("GPL v2"); 1359