12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2d894fc60SAlex Smith /* 3d894fc60SAlex Smith * Ingenic JZ4780 DMA controller 4d894fc60SAlex Smith * 5d894fc60SAlex Smith * Copyright (c) 2015 Imagination Technologies 6d894fc60SAlex Smith * Author: Alex Smith <alex@alex-smith.me.uk> 7d894fc60SAlex Smith */ 8d894fc60SAlex Smith 9d894fc60SAlex Smith #include <linux/clk.h> 10d894fc60SAlex Smith #include <linux/dmapool.h> 11d894fc60SAlex Smith #include <linux/init.h> 12d894fc60SAlex Smith #include <linux/interrupt.h> 13d894fc60SAlex Smith #include <linux/module.h> 14d894fc60SAlex Smith #include <linux/of.h> 156147b032SPaul Cercueil #include <linux/of_device.h> 16d894fc60SAlex Smith #include <linux/of_dma.h> 17d894fc60SAlex Smith #include <linux/platform_device.h> 18d894fc60SAlex Smith #include <linux/slab.h> 19d894fc60SAlex Smith 20d894fc60SAlex Smith #include "dmaengine.h" 21d894fc60SAlex Smith #include "virt-dma.h" 22d894fc60SAlex Smith 23d894fc60SAlex Smith /* Global registers. */ 2433633583SPaul Cercueil #define JZ_DMA_REG_DMAC 0x00 2533633583SPaul Cercueil #define JZ_DMA_REG_DIRQP 0x04 2633633583SPaul Cercueil #define JZ_DMA_REG_DDR 0x08 2733633583SPaul Cercueil #define JZ_DMA_REG_DDRS 0x0c 2829870eb7SPaul Cercueil #define JZ_DMA_REG_DCKE 0x10 2929870eb7SPaul Cercueil #define JZ_DMA_REG_DCKES 0x14 3029870eb7SPaul Cercueil #define JZ_DMA_REG_DCKEC 0x18 3133633583SPaul Cercueil #define JZ_DMA_REG_DMACP 0x1c 3233633583SPaul Cercueil #define JZ_DMA_REG_DSIRQP 0x20 3333633583SPaul Cercueil #define JZ_DMA_REG_DSIRQM 0x24 3433633583SPaul Cercueil #define JZ_DMA_REG_DCIRQP 0x28 3533633583SPaul Cercueil #define JZ_DMA_REG_DCIRQM 0x2c 36d894fc60SAlex Smith 37d894fc60SAlex Smith /* Per-channel registers. */ 38d894fc60SAlex Smith #define JZ_DMA_REG_CHAN(n) (n * 0x20) 3933633583SPaul Cercueil #define JZ_DMA_REG_DSA 0x00 4033633583SPaul Cercueil #define JZ_DMA_REG_DTA 0x04 4133633583SPaul Cercueil #define JZ_DMA_REG_DTC 0x08 4233633583SPaul Cercueil #define JZ_DMA_REG_DRT 0x0c 4333633583SPaul Cercueil #define JZ_DMA_REG_DCS 0x10 4433633583SPaul Cercueil #define JZ_DMA_REG_DCM 0x14 4533633583SPaul Cercueil #define JZ_DMA_REG_DDA 0x18 4633633583SPaul Cercueil #define JZ_DMA_REG_DSD 0x1c 47d894fc60SAlex Smith 48d894fc60SAlex Smith #define JZ_DMA_DMAC_DMAE BIT(0) 49d894fc60SAlex Smith #define JZ_DMA_DMAC_AR BIT(2) 50d894fc60SAlex Smith #define JZ_DMA_DMAC_HLT BIT(3) 5117a8e30eSPaul Cercueil #define JZ_DMA_DMAC_FAIC BIT(27) 52d894fc60SAlex Smith #define JZ_DMA_DMAC_FMSC BIT(31) 53d894fc60SAlex Smith 54d894fc60SAlex Smith #define JZ_DMA_DRT_AUTO 0x8 55d894fc60SAlex Smith 56d894fc60SAlex Smith #define JZ_DMA_DCS_CTE BIT(0) 57d894fc60SAlex Smith #define JZ_DMA_DCS_HLT BIT(2) 58d894fc60SAlex Smith #define JZ_DMA_DCS_TT BIT(3) 59d894fc60SAlex Smith #define JZ_DMA_DCS_AR BIT(4) 60d894fc60SAlex Smith #define JZ_DMA_DCS_DES8 BIT(30) 61d894fc60SAlex Smith 62d894fc60SAlex Smith #define JZ_DMA_DCM_LINK BIT(0) 63d894fc60SAlex Smith #define JZ_DMA_DCM_TIE BIT(1) 64d894fc60SAlex Smith #define JZ_DMA_DCM_STDE BIT(2) 65d894fc60SAlex Smith #define JZ_DMA_DCM_TSZ_SHIFT 8 66d894fc60SAlex Smith #define JZ_DMA_DCM_TSZ_MASK (0x7 << JZ_DMA_DCM_TSZ_SHIFT) 67d894fc60SAlex Smith #define JZ_DMA_DCM_DP_SHIFT 12 68d894fc60SAlex Smith #define JZ_DMA_DCM_SP_SHIFT 14 69d894fc60SAlex Smith #define JZ_DMA_DCM_DAI BIT(22) 70d894fc60SAlex Smith #define JZ_DMA_DCM_SAI BIT(23) 71d894fc60SAlex Smith 72d894fc60SAlex Smith #define JZ_DMA_SIZE_4_BYTE 0x0 73d894fc60SAlex Smith #define JZ_DMA_SIZE_1_BYTE 0x1 74d894fc60SAlex Smith #define JZ_DMA_SIZE_2_BYTE 0x2 75d894fc60SAlex Smith #define JZ_DMA_SIZE_16_BYTE 0x3 76d894fc60SAlex Smith #define JZ_DMA_SIZE_32_BYTE 0x4 77d894fc60SAlex Smith #define JZ_DMA_SIZE_64_BYTE 0x5 78d894fc60SAlex Smith #define JZ_DMA_SIZE_128_BYTE 0x6 79d894fc60SAlex Smith 80d894fc60SAlex Smith #define JZ_DMA_WIDTH_32_BIT 0x0 81d894fc60SAlex Smith #define JZ_DMA_WIDTH_8_BIT 0x1 82d894fc60SAlex Smith #define JZ_DMA_WIDTH_16_BIT 0x2 83d894fc60SAlex Smith 84d894fc60SAlex Smith #define JZ_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ 85d894fc60SAlex Smith BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ 86d894fc60SAlex Smith BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)) 87d894fc60SAlex Smith 8833633583SPaul Cercueil #define JZ4780_DMA_CTRL_OFFSET 0x1000 8933633583SPaul Cercueil 9029870eb7SPaul Cercueil /* macros for use with jz4780_dma_soc_data.flags */ 9129870eb7SPaul Cercueil #define JZ_SOC_DATA_ALLOW_LEGACY_DT BIT(0) 9229870eb7SPaul Cercueil #define JZ_SOC_DATA_PROGRAMMABLE_DMA BIT(1) 9329870eb7SPaul Cercueil #define JZ_SOC_DATA_PER_CHAN_PM BIT(2) 94ae9156b6SPaul Cercueil #define JZ_SOC_DATA_NO_DCKES_DCKEC BIT(3) 95f4c255f1SPaul Cercueil #define JZ_SOC_DATA_BREAK_LINKS BIT(4) 9629870eb7SPaul Cercueil 97d894fc60SAlex Smith /** 98d894fc60SAlex Smith * struct jz4780_dma_hwdesc - descriptor structure read by the DMA controller. 99d894fc60SAlex Smith * @dcm: value for the DCM (channel command) register 100d894fc60SAlex Smith * @dsa: source address 101d894fc60SAlex Smith * @dta: target address 102d894fc60SAlex Smith * @dtc: transfer count (number of blocks of the transfer size specified in DCM 103d894fc60SAlex Smith * to transfer) in the low 24 bits, offset of the next descriptor from the 104d894fc60SAlex Smith * descriptor base address in the upper 8 bits. 105d894fc60SAlex Smith */ 106d894fc60SAlex Smith struct jz4780_dma_hwdesc { 107d894fc60SAlex Smith uint32_t dcm; 108d894fc60SAlex Smith uint32_t dsa; 109d894fc60SAlex Smith uint32_t dta; 110d894fc60SAlex Smith uint32_t dtc; 111d894fc60SAlex Smith }; 112d894fc60SAlex Smith 113d894fc60SAlex Smith /* Size of allocations for hardware descriptor blocks. */ 114d894fc60SAlex Smith #define JZ_DMA_DESC_BLOCK_SIZE PAGE_SIZE 115d894fc60SAlex Smith #define JZ_DMA_MAX_DESC \ 116d894fc60SAlex Smith (JZ_DMA_DESC_BLOCK_SIZE / sizeof(struct jz4780_dma_hwdesc)) 117d894fc60SAlex Smith 118d894fc60SAlex Smith struct jz4780_dma_desc { 119d894fc60SAlex Smith struct virt_dma_desc vdesc; 120d894fc60SAlex Smith 121d894fc60SAlex Smith struct jz4780_dma_hwdesc *desc; 122d894fc60SAlex Smith dma_addr_t desc_phys; 123d894fc60SAlex Smith unsigned int count; 124d894fc60SAlex Smith enum dma_transaction_type type; 125d894fc60SAlex Smith uint32_t status; 126d894fc60SAlex Smith }; 127d894fc60SAlex Smith 128d894fc60SAlex Smith struct jz4780_dma_chan { 129d894fc60SAlex Smith struct virt_dma_chan vchan; 130d894fc60SAlex Smith unsigned int id; 131d894fc60SAlex Smith struct dma_pool *desc_pool; 132d894fc60SAlex Smith 133d894fc60SAlex Smith uint32_t transfer_type; 134d894fc60SAlex Smith uint32_t transfer_shift; 135d894fc60SAlex Smith struct dma_slave_config config; 136d894fc60SAlex Smith 137d894fc60SAlex Smith struct jz4780_dma_desc *desc; 138d894fc60SAlex Smith unsigned int curr_hwdesc; 139d894fc60SAlex Smith }; 140d894fc60SAlex Smith 1416147b032SPaul Cercueil struct jz4780_dma_soc_data { 1426147b032SPaul Cercueil unsigned int nb_channels; 14329870eb7SPaul Cercueil unsigned int transfer_ord_max; 14429870eb7SPaul Cercueil unsigned long flags; 1456147b032SPaul Cercueil }; 1466147b032SPaul Cercueil 147d894fc60SAlex Smith struct jz4780_dma_dev { 148d894fc60SAlex Smith struct dma_device dma_device; 14933633583SPaul Cercueil void __iomem *chn_base; 15033633583SPaul Cercueil void __iomem *ctrl_base; 151d894fc60SAlex Smith struct clk *clk; 152d894fc60SAlex Smith unsigned int irq; 1536147b032SPaul Cercueil const struct jz4780_dma_soc_data *soc_data; 154d894fc60SAlex Smith 155d894fc60SAlex Smith uint32_t chan_reserved; 1566147b032SPaul Cercueil struct jz4780_dma_chan chan[]; 157d894fc60SAlex Smith }; 158d894fc60SAlex Smith 159026fd406SAlex Smith struct jz4780_dma_filter_data { 160d894fc60SAlex Smith uint32_t transfer_type; 161d894fc60SAlex Smith int channel; 162d894fc60SAlex Smith }; 163d894fc60SAlex Smith 164d894fc60SAlex Smith static inline struct jz4780_dma_chan *to_jz4780_dma_chan(struct dma_chan *chan) 165d894fc60SAlex Smith { 166d894fc60SAlex Smith return container_of(chan, struct jz4780_dma_chan, vchan.chan); 167d894fc60SAlex Smith } 168d894fc60SAlex Smith 169d894fc60SAlex Smith static inline struct jz4780_dma_desc *to_jz4780_dma_desc( 170d894fc60SAlex Smith struct virt_dma_desc *vdesc) 171d894fc60SAlex Smith { 172d894fc60SAlex Smith return container_of(vdesc, struct jz4780_dma_desc, vdesc); 173d894fc60SAlex Smith } 174d894fc60SAlex Smith 175d894fc60SAlex Smith static inline struct jz4780_dma_dev *jz4780_dma_chan_parent( 176d894fc60SAlex Smith struct jz4780_dma_chan *jzchan) 177d894fc60SAlex Smith { 178d894fc60SAlex Smith return container_of(jzchan->vchan.chan.device, struct jz4780_dma_dev, 179d894fc60SAlex Smith dma_device); 180d894fc60SAlex Smith } 181d894fc60SAlex Smith 18233633583SPaul Cercueil static inline uint32_t jz4780_dma_chn_readl(struct jz4780_dma_dev *jzdma, 18333633583SPaul Cercueil unsigned int chn, unsigned int reg) 184d894fc60SAlex Smith { 18533633583SPaul Cercueil return readl(jzdma->chn_base + reg + JZ_DMA_REG_CHAN(chn)); 186d894fc60SAlex Smith } 187d894fc60SAlex Smith 18833633583SPaul Cercueil static inline void jz4780_dma_chn_writel(struct jz4780_dma_dev *jzdma, 18933633583SPaul Cercueil unsigned int chn, unsigned int reg, uint32_t val) 19033633583SPaul Cercueil { 19133633583SPaul Cercueil writel(val, jzdma->chn_base + reg + JZ_DMA_REG_CHAN(chn)); 19233633583SPaul Cercueil } 19333633583SPaul Cercueil 19433633583SPaul Cercueil static inline uint32_t jz4780_dma_ctrl_readl(struct jz4780_dma_dev *jzdma, 19533633583SPaul Cercueil unsigned int reg) 19633633583SPaul Cercueil { 19733633583SPaul Cercueil return readl(jzdma->ctrl_base + reg); 19833633583SPaul Cercueil } 19933633583SPaul Cercueil 20033633583SPaul Cercueil static inline void jz4780_dma_ctrl_writel(struct jz4780_dma_dev *jzdma, 201d894fc60SAlex Smith unsigned int reg, uint32_t val) 202d894fc60SAlex Smith { 20333633583SPaul Cercueil writel(val, jzdma->ctrl_base + reg); 204d894fc60SAlex Smith } 205d894fc60SAlex Smith 20629870eb7SPaul Cercueil static inline void jz4780_dma_chan_enable(struct jz4780_dma_dev *jzdma, 20729870eb7SPaul Cercueil unsigned int chn) 20829870eb7SPaul Cercueil { 209ae9156b6SPaul Cercueil if (jzdma->soc_data->flags & JZ_SOC_DATA_PER_CHAN_PM) { 210ae9156b6SPaul Cercueil unsigned int reg; 211ae9156b6SPaul Cercueil 212ae9156b6SPaul Cercueil if (jzdma->soc_data->flags & JZ_SOC_DATA_NO_DCKES_DCKEC) 213ae9156b6SPaul Cercueil reg = JZ_DMA_REG_DCKE; 214ae9156b6SPaul Cercueil else 215ae9156b6SPaul Cercueil reg = JZ_DMA_REG_DCKES; 216ae9156b6SPaul Cercueil 217ae9156b6SPaul Cercueil jz4780_dma_ctrl_writel(jzdma, reg, BIT(chn)); 218ae9156b6SPaul Cercueil } 21929870eb7SPaul Cercueil } 22029870eb7SPaul Cercueil 22129870eb7SPaul Cercueil static inline void jz4780_dma_chan_disable(struct jz4780_dma_dev *jzdma, 22229870eb7SPaul Cercueil unsigned int chn) 22329870eb7SPaul Cercueil { 224ae9156b6SPaul Cercueil if ((jzdma->soc_data->flags & JZ_SOC_DATA_PER_CHAN_PM) && 225ae9156b6SPaul Cercueil !(jzdma->soc_data->flags & JZ_SOC_DATA_NO_DCKES_DCKEC)) 22629870eb7SPaul Cercueil jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DCKEC, BIT(chn)); 227d894fc60SAlex Smith } 228d894fc60SAlex Smith 229d894fc60SAlex Smith static struct jz4780_dma_desc *jz4780_dma_desc_alloc( 230d894fc60SAlex Smith struct jz4780_dma_chan *jzchan, unsigned int count, 231d894fc60SAlex Smith enum dma_transaction_type type) 232d894fc60SAlex Smith { 233d894fc60SAlex Smith struct jz4780_dma_desc *desc; 234d894fc60SAlex Smith 235d894fc60SAlex Smith if (count > JZ_DMA_MAX_DESC) 236d894fc60SAlex Smith return NULL; 237d894fc60SAlex Smith 238d894fc60SAlex Smith desc = kzalloc(sizeof(*desc), GFP_NOWAIT); 239d894fc60SAlex Smith if (!desc) 240d894fc60SAlex Smith return NULL; 241d894fc60SAlex Smith 242d894fc60SAlex Smith desc->desc = dma_pool_alloc(jzchan->desc_pool, GFP_NOWAIT, 243d894fc60SAlex Smith &desc->desc_phys); 244d894fc60SAlex Smith if (!desc->desc) { 245d894fc60SAlex Smith kfree(desc); 246d894fc60SAlex Smith return NULL; 247d894fc60SAlex Smith } 248d894fc60SAlex Smith 249d894fc60SAlex Smith desc->count = count; 250d894fc60SAlex Smith desc->type = type; 251d894fc60SAlex Smith return desc; 252d894fc60SAlex Smith } 253d894fc60SAlex Smith 254d894fc60SAlex Smith static void jz4780_dma_desc_free(struct virt_dma_desc *vdesc) 255d894fc60SAlex Smith { 256d894fc60SAlex Smith struct jz4780_dma_desc *desc = to_jz4780_dma_desc(vdesc); 257d894fc60SAlex Smith struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(vdesc->tx.chan); 258d894fc60SAlex Smith 259d894fc60SAlex Smith dma_pool_free(jzchan->desc_pool, desc->desc, desc->desc_phys); 260d894fc60SAlex Smith kfree(desc); 261d894fc60SAlex Smith } 262d894fc60SAlex Smith 26329870eb7SPaul Cercueil static uint32_t jz4780_dma_transfer_size(struct jz4780_dma_chan *jzchan, 26429870eb7SPaul Cercueil unsigned long val, uint32_t *shift) 265d894fc60SAlex Smith { 26629870eb7SPaul Cercueil struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan); 267dc578f31SAlex Smith int ord = ffs(val) - 1; 268d894fc60SAlex Smith 269dc578f31SAlex Smith /* 270dc578f31SAlex Smith * 8 byte transfer sizes unsupported so fall back on 4. If it's larger 271dc578f31SAlex Smith * than the maximum, just limit it. It is perfectly safe to fall back 272dc578f31SAlex Smith * in this way since we won't exceed the maximum burst size supported 273dc578f31SAlex Smith * by the device, the only effect is reduced efficiency. This is better 274dc578f31SAlex Smith * than refusing to perform the request at all. 275dc578f31SAlex Smith */ 276dc578f31SAlex Smith if (ord == 3) 277dc578f31SAlex Smith ord = 2; 27829870eb7SPaul Cercueil else if (ord > jzdma->soc_data->transfer_ord_max) 27929870eb7SPaul Cercueil ord = jzdma->soc_data->transfer_ord_max; 280dc578f31SAlex Smith 281dc578f31SAlex Smith *shift = ord; 282dc578f31SAlex Smith 283dc578f31SAlex Smith switch (ord) { 284d894fc60SAlex Smith case 0: 285d894fc60SAlex Smith return JZ_DMA_SIZE_1_BYTE; 286d894fc60SAlex Smith case 1: 287d894fc60SAlex Smith return JZ_DMA_SIZE_2_BYTE; 288d894fc60SAlex Smith case 2: 289d894fc60SAlex Smith return JZ_DMA_SIZE_4_BYTE; 290d894fc60SAlex Smith case 4: 291d894fc60SAlex Smith return JZ_DMA_SIZE_16_BYTE; 292d894fc60SAlex Smith case 5: 293d894fc60SAlex Smith return JZ_DMA_SIZE_32_BYTE; 294d894fc60SAlex Smith case 6: 295d894fc60SAlex Smith return JZ_DMA_SIZE_64_BYTE; 296d894fc60SAlex Smith default: 297dc578f31SAlex Smith return JZ_DMA_SIZE_128_BYTE; 298d894fc60SAlex Smith } 299d894fc60SAlex Smith } 300d894fc60SAlex Smith 301839896efSAlex Smith static int jz4780_dma_setup_hwdesc(struct jz4780_dma_chan *jzchan, 302d894fc60SAlex Smith struct jz4780_dma_hwdesc *desc, dma_addr_t addr, size_t len, 303d894fc60SAlex Smith enum dma_transfer_direction direction) 304d894fc60SAlex Smith { 305d894fc60SAlex Smith struct dma_slave_config *config = &jzchan->config; 306d894fc60SAlex Smith uint32_t width, maxburst, tsz; 307d894fc60SAlex Smith 308d894fc60SAlex Smith if (direction == DMA_MEM_TO_DEV) { 309d894fc60SAlex Smith desc->dcm = JZ_DMA_DCM_SAI; 310d894fc60SAlex Smith desc->dsa = addr; 311d894fc60SAlex Smith desc->dta = config->dst_addr; 312d894fc60SAlex Smith 313d894fc60SAlex Smith width = config->dst_addr_width; 314d894fc60SAlex Smith maxburst = config->dst_maxburst; 315d894fc60SAlex Smith } else { 316d894fc60SAlex Smith desc->dcm = JZ_DMA_DCM_DAI; 317d894fc60SAlex Smith desc->dsa = config->src_addr; 318d894fc60SAlex Smith desc->dta = addr; 319d894fc60SAlex Smith 320d894fc60SAlex Smith width = config->src_addr_width; 321d894fc60SAlex Smith maxburst = config->src_maxburst; 322d894fc60SAlex Smith } 323d894fc60SAlex Smith 324d894fc60SAlex Smith /* 325d894fc60SAlex Smith * This calculates the maximum transfer size that can be used with the 326d894fc60SAlex Smith * given address, length, width and maximum burst size. The address 327d894fc60SAlex Smith * must be aligned to the transfer size, the total length must be 328d894fc60SAlex Smith * divisible by the transfer size, and we must not use more than the 329d894fc60SAlex Smith * maximum burst specified by the user. 330d894fc60SAlex Smith */ 33129870eb7SPaul Cercueil tsz = jz4780_dma_transfer_size(jzchan, addr | len | (width * maxburst), 332dc578f31SAlex Smith &jzchan->transfer_shift); 333d894fc60SAlex Smith 334d894fc60SAlex Smith switch (width) { 335d894fc60SAlex Smith case DMA_SLAVE_BUSWIDTH_1_BYTE: 336d894fc60SAlex Smith case DMA_SLAVE_BUSWIDTH_2_BYTES: 337d894fc60SAlex Smith break; 338d894fc60SAlex Smith case DMA_SLAVE_BUSWIDTH_4_BYTES: 339d894fc60SAlex Smith width = JZ_DMA_WIDTH_32_BIT; 340d894fc60SAlex Smith break; 341d894fc60SAlex Smith default: 342d894fc60SAlex Smith return -EINVAL; 343d894fc60SAlex Smith } 344d894fc60SAlex Smith 345d894fc60SAlex Smith desc->dcm |= tsz << JZ_DMA_DCM_TSZ_SHIFT; 346d894fc60SAlex Smith desc->dcm |= width << JZ_DMA_DCM_SP_SHIFT; 347d894fc60SAlex Smith desc->dcm |= width << JZ_DMA_DCM_DP_SHIFT; 348d894fc60SAlex Smith 349dc578f31SAlex Smith desc->dtc = len >> jzchan->transfer_shift; 350839896efSAlex Smith return 0; 351d894fc60SAlex Smith } 352d894fc60SAlex Smith 353d894fc60SAlex Smith static struct dma_async_tx_descriptor *jz4780_dma_prep_slave_sg( 354d894fc60SAlex Smith struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, 35546fa5168SAlex Smith enum dma_transfer_direction direction, unsigned long flags, 35646fa5168SAlex Smith void *context) 357d894fc60SAlex Smith { 358d894fc60SAlex Smith struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan); 359f4c255f1SPaul Cercueil struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan); 360d894fc60SAlex Smith struct jz4780_dma_desc *desc; 361d894fc60SAlex Smith unsigned int i; 362d894fc60SAlex Smith int err; 363d894fc60SAlex Smith 364d894fc60SAlex Smith desc = jz4780_dma_desc_alloc(jzchan, sg_len, DMA_SLAVE); 365d894fc60SAlex Smith if (!desc) 366d894fc60SAlex Smith return NULL; 367d894fc60SAlex Smith 368d894fc60SAlex Smith for (i = 0; i < sg_len; i++) { 369d894fc60SAlex Smith err = jz4780_dma_setup_hwdesc(jzchan, &desc->desc[i], 370d894fc60SAlex Smith sg_dma_address(&sgl[i]), 371d894fc60SAlex Smith sg_dma_len(&sgl[i]), 372d894fc60SAlex Smith direction); 373fc878efeSColin Ian King if (err < 0) { 374fc878efeSColin Ian King jz4780_dma_desc_free(&jzchan->desc->vdesc); 375839896efSAlex Smith return NULL; 376fc878efeSColin Ian King } 377d894fc60SAlex Smith 378d894fc60SAlex Smith desc->desc[i].dcm |= JZ_DMA_DCM_TIE; 379d894fc60SAlex Smith 380f4c255f1SPaul Cercueil if (i != (sg_len - 1) && 381f4c255f1SPaul Cercueil !(jzdma->soc_data->flags & JZ_SOC_DATA_BREAK_LINKS)) { 382d894fc60SAlex Smith /* Automatically proceeed to the next descriptor. */ 383d894fc60SAlex Smith desc->desc[i].dcm |= JZ_DMA_DCM_LINK; 384d894fc60SAlex Smith 385d894fc60SAlex Smith /* 386d894fc60SAlex Smith * The upper 8 bits of the DTC field in the descriptor 387d894fc60SAlex Smith * must be set to (offset from descriptor base of next 388d894fc60SAlex Smith * descriptor >> 4). 389d894fc60SAlex Smith */ 390d894fc60SAlex Smith desc->desc[i].dtc |= 391d894fc60SAlex Smith (((i + 1) * sizeof(*desc->desc)) >> 4) << 24; 392d894fc60SAlex Smith } 393d894fc60SAlex Smith } 394d894fc60SAlex Smith 395d894fc60SAlex Smith return vchan_tx_prep(&jzchan->vchan, &desc->vdesc, flags); 396d894fc60SAlex Smith } 397d894fc60SAlex Smith 398d894fc60SAlex Smith static struct dma_async_tx_descriptor *jz4780_dma_prep_dma_cyclic( 399d894fc60SAlex Smith struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, 400d894fc60SAlex Smith size_t period_len, enum dma_transfer_direction direction, 401d894fc60SAlex Smith unsigned long flags) 402d894fc60SAlex Smith { 403d894fc60SAlex Smith struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan); 404d894fc60SAlex Smith struct jz4780_dma_desc *desc; 405d894fc60SAlex Smith unsigned int periods, i; 406d894fc60SAlex Smith int err; 407d894fc60SAlex Smith 408d894fc60SAlex Smith if (buf_len % period_len) 409d894fc60SAlex Smith return NULL; 410d894fc60SAlex Smith 411d894fc60SAlex Smith periods = buf_len / period_len; 412d894fc60SAlex Smith 413d894fc60SAlex Smith desc = jz4780_dma_desc_alloc(jzchan, periods, DMA_CYCLIC); 414d894fc60SAlex Smith if (!desc) 415d894fc60SAlex Smith return NULL; 416d894fc60SAlex Smith 417d894fc60SAlex Smith for (i = 0; i < periods; i++) { 418d894fc60SAlex Smith err = jz4780_dma_setup_hwdesc(jzchan, &desc->desc[i], buf_addr, 419d894fc60SAlex Smith period_len, direction); 420fc878efeSColin Ian King if (err < 0) { 421fc878efeSColin Ian King jz4780_dma_desc_free(&jzchan->desc->vdesc); 422839896efSAlex Smith return NULL; 423fc878efeSColin Ian King } 424d894fc60SAlex Smith 425d894fc60SAlex Smith buf_addr += period_len; 426d894fc60SAlex Smith 427d894fc60SAlex Smith /* 428d894fc60SAlex Smith * Set the link bit to indicate that the controller should 429d894fc60SAlex Smith * automatically proceed to the next descriptor. In 430d894fc60SAlex Smith * jz4780_dma_begin(), this will be cleared if we need to issue 431d894fc60SAlex Smith * an interrupt after each period. 432d894fc60SAlex Smith */ 433d894fc60SAlex Smith desc->desc[i].dcm |= JZ_DMA_DCM_TIE | JZ_DMA_DCM_LINK; 434d894fc60SAlex Smith 435d894fc60SAlex Smith /* 436d894fc60SAlex Smith * The upper 8 bits of the DTC field in the descriptor must be 437d894fc60SAlex Smith * set to (offset from descriptor base of next descriptor >> 4). 438d894fc60SAlex Smith * If this is the last descriptor, link it back to the first, 439d894fc60SAlex Smith * i.e. leave offset set to 0, otherwise point to the next one. 440d894fc60SAlex Smith */ 441d894fc60SAlex Smith if (i != (periods - 1)) { 442d894fc60SAlex Smith desc->desc[i].dtc |= 443d894fc60SAlex Smith (((i + 1) * sizeof(*desc->desc)) >> 4) << 24; 444d894fc60SAlex Smith } 445d894fc60SAlex Smith } 446d894fc60SAlex Smith 447d894fc60SAlex Smith return vchan_tx_prep(&jzchan->vchan, &desc->vdesc, flags); 448d894fc60SAlex Smith } 449d894fc60SAlex Smith 4504f5db8c8SVinod Koul static struct dma_async_tx_descriptor *jz4780_dma_prep_dma_memcpy( 451d894fc60SAlex Smith struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, 452d894fc60SAlex Smith size_t len, unsigned long flags) 453d894fc60SAlex Smith { 454d894fc60SAlex Smith struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan); 455d894fc60SAlex Smith struct jz4780_dma_desc *desc; 456d894fc60SAlex Smith uint32_t tsz; 457d894fc60SAlex Smith 458d894fc60SAlex Smith desc = jz4780_dma_desc_alloc(jzchan, 1, DMA_MEMCPY); 459d894fc60SAlex Smith if (!desc) 460d894fc60SAlex Smith return NULL; 461d894fc60SAlex Smith 46229870eb7SPaul Cercueil tsz = jz4780_dma_transfer_size(jzchan, dest | src | len, 463dc578f31SAlex Smith &jzchan->transfer_shift); 464d894fc60SAlex Smith 4655eed7d84SPaul Cercueil jzchan->transfer_type = JZ_DMA_DRT_AUTO; 4665eed7d84SPaul Cercueil 467d894fc60SAlex Smith desc->desc[0].dsa = src; 468d894fc60SAlex Smith desc->desc[0].dta = dest; 469d894fc60SAlex Smith desc->desc[0].dcm = JZ_DMA_DCM_TIE | JZ_DMA_DCM_SAI | JZ_DMA_DCM_DAI | 470d894fc60SAlex Smith tsz << JZ_DMA_DCM_TSZ_SHIFT | 471d894fc60SAlex Smith JZ_DMA_WIDTH_32_BIT << JZ_DMA_DCM_SP_SHIFT | 472d894fc60SAlex Smith JZ_DMA_WIDTH_32_BIT << JZ_DMA_DCM_DP_SHIFT; 473839896efSAlex Smith desc->desc[0].dtc = len >> jzchan->transfer_shift; 474d894fc60SAlex Smith 475d894fc60SAlex Smith return vchan_tx_prep(&jzchan->vchan, &desc->vdesc, flags); 476d894fc60SAlex Smith } 477d894fc60SAlex Smith 478d894fc60SAlex Smith static void jz4780_dma_begin(struct jz4780_dma_chan *jzchan) 479d894fc60SAlex Smith { 480d894fc60SAlex Smith struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan); 481d894fc60SAlex Smith struct virt_dma_desc *vdesc; 482d894fc60SAlex Smith unsigned int i; 483d894fc60SAlex Smith dma_addr_t desc_phys; 484d894fc60SAlex Smith 485d894fc60SAlex Smith if (!jzchan->desc) { 486d894fc60SAlex Smith vdesc = vchan_next_desc(&jzchan->vchan); 487d894fc60SAlex Smith if (!vdesc) 488d894fc60SAlex Smith return; 489d894fc60SAlex Smith 490d894fc60SAlex Smith list_del(&vdesc->node); 491d894fc60SAlex Smith 492d894fc60SAlex Smith jzchan->desc = to_jz4780_dma_desc(vdesc); 493d894fc60SAlex Smith jzchan->curr_hwdesc = 0; 494d894fc60SAlex Smith 495d894fc60SAlex Smith if (jzchan->desc->type == DMA_CYCLIC && vdesc->tx.callback) { 496d894fc60SAlex Smith /* 497d894fc60SAlex Smith * The DMA controller doesn't support triggering an 498d894fc60SAlex Smith * interrupt after processing each descriptor, only 499d894fc60SAlex Smith * after processing an entire terminated list of 500d894fc60SAlex Smith * descriptors. For a cyclic DMA setup the list of 501d894fc60SAlex Smith * descriptors is not terminated so we can never get an 502d894fc60SAlex Smith * interrupt. 503d894fc60SAlex Smith * 504d894fc60SAlex Smith * If the user requested a callback for a cyclic DMA 505d894fc60SAlex Smith * setup then we workaround this hardware limitation 506d894fc60SAlex Smith * here by degrading to a set of unlinked descriptors 507d894fc60SAlex Smith * which we will submit in sequence in response to the 508d894fc60SAlex Smith * completion of processing the previous descriptor. 509d894fc60SAlex Smith */ 510d894fc60SAlex Smith for (i = 0; i < jzchan->desc->count; i++) 511d894fc60SAlex Smith jzchan->desc->desc[i].dcm &= ~JZ_DMA_DCM_LINK; 512d894fc60SAlex Smith } 513d894fc60SAlex Smith } else { 514d894fc60SAlex Smith /* 515d894fc60SAlex Smith * There is an existing transfer, therefore this must be one 516d894fc60SAlex Smith * for which we unlinked the descriptors above. Advance to the 517d894fc60SAlex Smith * next one in the list. 518d894fc60SAlex Smith */ 519d894fc60SAlex Smith jzchan->curr_hwdesc = 520d894fc60SAlex Smith (jzchan->curr_hwdesc + 1) % jzchan->desc->count; 521d894fc60SAlex Smith } 522d894fc60SAlex Smith 52329870eb7SPaul Cercueil /* Enable the channel's clock. */ 52429870eb7SPaul Cercueil jz4780_dma_chan_enable(jzdma, jzchan->id); 52529870eb7SPaul Cercueil 5265eed7d84SPaul Cercueil /* Use 4-word descriptors. */ 5275eed7d84SPaul Cercueil jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DCS, 0); 5285eed7d84SPaul Cercueil 5295eed7d84SPaul Cercueil /* Set transfer type. */ 5305eed7d84SPaul Cercueil jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DRT, 5315eed7d84SPaul Cercueil jzchan->transfer_type); 532d894fc60SAlex Smith 5339e4e3a4cSDaniel Silsby /* 5349e4e3a4cSDaniel Silsby * Set the transfer count. This is redundant for a descriptor-driven 5359e4e3a4cSDaniel Silsby * transfer. However, there can be a delay between the transfer start 5369e4e3a4cSDaniel Silsby * time and when DTCn reg contains the new transfer count. Setting 5379e4e3a4cSDaniel Silsby * it explicitly ensures residue is computed correctly at all times. 5389e4e3a4cSDaniel Silsby */ 5399e4e3a4cSDaniel Silsby jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DTC, 5409e4e3a4cSDaniel Silsby jzchan->desc->desc[jzchan->curr_hwdesc].dtc); 541d894fc60SAlex Smith 542d894fc60SAlex Smith /* Write descriptor address and initiate descriptor fetch. */ 543d894fc60SAlex Smith desc_phys = jzchan->desc->desc_phys + 544d894fc60SAlex Smith (jzchan->curr_hwdesc * sizeof(*jzchan->desc->desc)); 54533633583SPaul Cercueil jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DDA, desc_phys); 54633633583SPaul Cercueil jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DDRS, BIT(jzchan->id)); 547d894fc60SAlex Smith 548d894fc60SAlex Smith /* Enable the channel. */ 54933633583SPaul Cercueil jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DCS, 5505eed7d84SPaul Cercueil JZ_DMA_DCS_CTE); 551d894fc60SAlex Smith } 552d894fc60SAlex Smith 553d894fc60SAlex Smith static void jz4780_dma_issue_pending(struct dma_chan *chan) 554d894fc60SAlex Smith { 555d894fc60SAlex Smith struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan); 556d894fc60SAlex Smith unsigned long flags; 557d894fc60SAlex Smith 558d894fc60SAlex Smith spin_lock_irqsave(&jzchan->vchan.lock, flags); 559d894fc60SAlex Smith 560d894fc60SAlex Smith if (vchan_issue_pending(&jzchan->vchan) && !jzchan->desc) 561d894fc60SAlex Smith jz4780_dma_begin(jzchan); 562d894fc60SAlex Smith 563d894fc60SAlex Smith spin_unlock_irqrestore(&jzchan->vchan.lock, flags); 564d894fc60SAlex Smith } 565d894fc60SAlex Smith 56646fa5168SAlex Smith static int jz4780_dma_terminate_all(struct dma_chan *chan) 567d894fc60SAlex Smith { 56846fa5168SAlex Smith struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan); 569d894fc60SAlex Smith struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan); 570d894fc60SAlex Smith unsigned long flags; 571d894fc60SAlex Smith LIST_HEAD(head); 572d894fc60SAlex Smith 573d894fc60SAlex Smith spin_lock_irqsave(&jzchan->vchan.lock, flags); 574d894fc60SAlex Smith 575d894fc60SAlex Smith /* Clear the DMA status and stop the transfer. */ 57633633583SPaul Cercueil jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DCS, 0); 577d894fc60SAlex Smith if (jzchan->desc) { 578f0dd52c8SPeter Ujfalusi vchan_terminate_vdesc(&jzchan->desc->vdesc); 579d894fc60SAlex Smith jzchan->desc = NULL; 580d894fc60SAlex Smith } 581d894fc60SAlex Smith 58229870eb7SPaul Cercueil jz4780_dma_chan_disable(jzdma, jzchan->id); 58329870eb7SPaul Cercueil 584d894fc60SAlex Smith vchan_get_all_descriptors(&jzchan->vchan, &head); 585d894fc60SAlex Smith 586d894fc60SAlex Smith spin_unlock_irqrestore(&jzchan->vchan.lock, flags); 587d894fc60SAlex Smith 588d894fc60SAlex Smith vchan_dma_desc_free_list(&jzchan->vchan, &head); 589d894fc60SAlex Smith return 0; 590d894fc60SAlex Smith } 591d894fc60SAlex Smith 592f0dd52c8SPeter Ujfalusi static void jz4780_dma_synchronize(struct dma_chan *chan) 593f0dd52c8SPeter Ujfalusi { 594f0dd52c8SPeter Ujfalusi struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan); 59529870eb7SPaul Cercueil struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan); 596f0dd52c8SPeter Ujfalusi 597f0dd52c8SPeter Ujfalusi vchan_synchronize(&jzchan->vchan); 59829870eb7SPaul Cercueil jz4780_dma_chan_disable(jzdma, jzchan->id); 599f0dd52c8SPeter Ujfalusi } 600f0dd52c8SPeter Ujfalusi 60146fa5168SAlex Smith static int jz4780_dma_config(struct dma_chan *chan, 60246fa5168SAlex Smith struct dma_slave_config *config) 603d894fc60SAlex Smith { 60446fa5168SAlex Smith struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan); 60546fa5168SAlex Smith 606d894fc60SAlex Smith if ((config->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES) 607d894fc60SAlex Smith || (config->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)) 608d894fc60SAlex Smith return -EINVAL; 609d894fc60SAlex Smith 610d894fc60SAlex Smith /* Copy the reset of the slave configuration, it is used later. */ 611d894fc60SAlex Smith memcpy(&jzchan->config, config, sizeof(jzchan->config)); 612d894fc60SAlex Smith 613d894fc60SAlex Smith return 0; 614d894fc60SAlex Smith } 615d894fc60SAlex Smith 616d894fc60SAlex Smith static size_t jz4780_dma_desc_residue(struct jz4780_dma_chan *jzchan, 617d894fc60SAlex Smith struct jz4780_dma_desc *desc, unsigned int next_sg) 618d894fc60SAlex Smith { 619d894fc60SAlex Smith struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan); 620f3c045dfSDaniel Silsby unsigned int count = 0; 621d894fc60SAlex Smith unsigned int i; 622d894fc60SAlex Smith 623d894fc60SAlex Smith for (i = next_sg; i < desc->count; i++) 624f3c045dfSDaniel Silsby count += desc->desc[i].dtc & GENMASK(23, 0); 625d894fc60SAlex Smith 626f3c045dfSDaniel Silsby if (next_sg != 0) 627f3c045dfSDaniel Silsby count += jz4780_dma_chn_readl(jzdma, jzchan->id, 62833633583SPaul Cercueil JZ_DMA_REG_DTC); 629d894fc60SAlex Smith 630f3c045dfSDaniel Silsby return count << jzchan->transfer_shift; 631d894fc60SAlex Smith } 632d894fc60SAlex Smith 633d894fc60SAlex Smith static enum dma_status jz4780_dma_tx_status(struct dma_chan *chan, 634d894fc60SAlex Smith dma_cookie_t cookie, struct dma_tx_state *txstate) 635d894fc60SAlex Smith { 636d894fc60SAlex Smith struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan); 637d894fc60SAlex Smith struct virt_dma_desc *vdesc; 638d894fc60SAlex Smith enum dma_status status; 639d894fc60SAlex Smith unsigned long flags; 6401f0b0f23SDaniel Silsby unsigned long residue = 0; 641d894fc60SAlex Smith 642baf6fd97SPaul Cercueil spin_lock_irqsave(&jzchan->vchan.lock, flags); 643baf6fd97SPaul Cercueil 644d894fc60SAlex Smith status = dma_cookie_status(chan, cookie, txstate); 645d894fc60SAlex Smith if ((status == DMA_COMPLETE) || (txstate == NULL)) 646baf6fd97SPaul Cercueil goto out_unlock_irqrestore; 647d894fc60SAlex Smith 648d894fc60SAlex Smith vdesc = vchan_find_desc(&jzchan->vchan, cookie); 649d894fc60SAlex Smith if (vdesc) { 650d894fc60SAlex Smith /* On the issued list, so hasn't been processed yet */ 6511f0b0f23SDaniel Silsby residue = jz4780_dma_desc_residue(jzchan, 652d894fc60SAlex Smith to_jz4780_dma_desc(vdesc), 0); 653d894fc60SAlex Smith } else if (cookie == jzchan->desc->vdesc.tx.cookie) { 6541f0b0f23SDaniel Silsby residue = jz4780_dma_desc_residue(jzchan, jzchan->desc, 65583ef4fb7SDaniel Silsby jzchan->curr_hwdesc + 1); 6561f0b0f23SDaniel Silsby } 6571f0b0f23SDaniel Silsby dma_set_residue(txstate, residue); 658d894fc60SAlex Smith 659d894fc60SAlex Smith if (vdesc && jzchan->desc && vdesc == &jzchan->desc->vdesc 660d894fc60SAlex Smith && jzchan->desc->status & (JZ_DMA_DCS_AR | JZ_DMA_DCS_HLT)) 661d894fc60SAlex Smith status = DMA_ERROR; 662d894fc60SAlex Smith 663baf6fd97SPaul Cercueil out_unlock_irqrestore: 664d894fc60SAlex Smith spin_unlock_irqrestore(&jzchan->vchan.lock, flags); 665d894fc60SAlex Smith return status; 666d894fc60SAlex Smith } 667d894fc60SAlex Smith 6684e4106f5SPaul Cercueil static bool jz4780_dma_chan_irq(struct jz4780_dma_dev *jzdma, 669d894fc60SAlex Smith struct jz4780_dma_chan *jzchan) 670d894fc60SAlex Smith { 671f4c255f1SPaul Cercueil const unsigned int soc_flags = jzdma->soc_data->flags; 672f4c255f1SPaul Cercueil struct jz4780_dma_desc *desc = jzchan->desc; 673d894fc60SAlex Smith uint32_t dcs; 6744e4106f5SPaul Cercueil bool ack = true; 675d894fc60SAlex Smith 676d894fc60SAlex Smith spin_lock(&jzchan->vchan.lock); 677d894fc60SAlex Smith 67833633583SPaul Cercueil dcs = jz4780_dma_chn_readl(jzdma, jzchan->id, JZ_DMA_REG_DCS); 67933633583SPaul Cercueil jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DCS, 0); 680d894fc60SAlex Smith 681d894fc60SAlex Smith if (dcs & JZ_DMA_DCS_AR) { 682d894fc60SAlex Smith dev_warn(&jzchan->vchan.chan.dev->device, 683d894fc60SAlex Smith "address error (DCS=0x%x)\n", dcs); 684d894fc60SAlex Smith } 685d894fc60SAlex Smith 686d894fc60SAlex Smith if (dcs & JZ_DMA_DCS_HLT) { 687d894fc60SAlex Smith dev_warn(&jzchan->vchan.chan.dev->device, 688d894fc60SAlex Smith "channel halt (DCS=0x%x)\n", dcs); 689d894fc60SAlex Smith } 690d894fc60SAlex Smith 691d894fc60SAlex Smith if (jzchan->desc) { 692d894fc60SAlex Smith jzchan->desc->status = dcs; 693d894fc60SAlex Smith 694d894fc60SAlex Smith if ((dcs & (JZ_DMA_DCS_AR | JZ_DMA_DCS_HLT)) == 0) { 695d894fc60SAlex Smith if (jzchan->desc->type == DMA_CYCLIC) { 696d894fc60SAlex Smith vchan_cyclic_callback(&jzchan->desc->vdesc); 697d894fc60SAlex Smith 698d894fc60SAlex Smith jz4780_dma_begin(jzchan); 6994e4106f5SPaul Cercueil } else if (dcs & JZ_DMA_DCS_TT) { 700f4c255f1SPaul Cercueil if (!(soc_flags & JZ_SOC_DATA_BREAK_LINKS) || 701f4c255f1SPaul Cercueil (jzchan->curr_hwdesc + 1 == desc->count)) { 702f4c255f1SPaul Cercueil vchan_cookie_complete(&desc->vdesc); 7034e4106f5SPaul Cercueil jzchan->desc = NULL; 704f4c255f1SPaul Cercueil } 7054e4106f5SPaul Cercueil 7064e4106f5SPaul Cercueil jz4780_dma_begin(jzchan); 7074e4106f5SPaul Cercueil } else { 7084e4106f5SPaul Cercueil /* False positive - continue the transfer */ 7094e4106f5SPaul Cercueil ack = false; 7104e4106f5SPaul Cercueil jz4780_dma_chn_writel(jzdma, jzchan->id, 7114e4106f5SPaul Cercueil JZ_DMA_REG_DCS, 7124e4106f5SPaul Cercueil JZ_DMA_DCS_CTE); 7134e4106f5SPaul Cercueil } 714d894fc60SAlex Smith } 715d894fc60SAlex Smith } else { 716d894fc60SAlex Smith dev_err(&jzchan->vchan.chan.dev->device, 717d894fc60SAlex Smith "channel IRQ with no active transfer\n"); 718d894fc60SAlex Smith } 719d894fc60SAlex Smith 720d894fc60SAlex Smith spin_unlock(&jzchan->vchan.lock); 7214e4106f5SPaul Cercueil 7224e4106f5SPaul Cercueil return ack; 723d894fc60SAlex Smith } 724d894fc60SAlex Smith 725d894fc60SAlex Smith static irqreturn_t jz4780_dma_irq_handler(int irq, void *data) 726d894fc60SAlex Smith { 727d894fc60SAlex Smith struct jz4780_dma_dev *jzdma = data; 7284e4106f5SPaul Cercueil unsigned int nb_channels = jzdma->soc_data->nb_channels; 7294c89cc73SDan Carpenter unsigned long pending; 7304c89cc73SDan Carpenter uint32_t dmac; 731d894fc60SAlex Smith int i; 732d894fc60SAlex Smith 73333633583SPaul Cercueil pending = jz4780_dma_ctrl_readl(jzdma, JZ_DMA_REG_DIRQP); 734d894fc60SAlex Smith 7354c89cc73SDan Carpenter for_each_set_bit(i, &pending, nb_channels) { 7364e4106f5SPaul Cercueil if (jz4780_dma_chan_irq(jzdma, &jzdma->chan[i])) 7374e4106f5SPaul Cercueil pending &= ~BIT(i); 738d894fc60SAlex Smith } 739d894fc60SAlex Smith 740d894fc60SAlex Smith /* Clear halt and address error status of all channels. */ 74133633583SPaul Cercueil dmac = jz4780_dma_ctrl_readl(jzdma, JZ_DMA_REG_DMAC); 742d894fc60SAlex Smith dmac &= ~(JZ_DMA_DMAC_HLT | JZ_DMA_DMAC_AR); 74333633583SPaul Cercueil jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DMAC, dmac); 744d894fc60SAlex Smith 745d894fc60SAlex Smith /* Clear interrupt pending status. */ 7464e4106f5SPaul Cercueil jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DIRQP, pending); 747d894fc60SAlex Smith 748d894fc60SAlex Smith return IRQ_HANDLED; 749d894fc60SAlex Smith } 750d894fc60SAlex Smith 751d894fc60SAlex Smith static int jz4780_dma_alloc_chan_resources(struct dma_chan *chan) 752d894fc60SAlex Smith { 753d894fc60SAlex Smith struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan); 754d894fc60SAlex Smith 755d894fc60SAlex Smith jzchan->desc_pool = dma_pool_create(dev_name(&chan->dev->device), 756d894fc60SAlex Smith chan->device->dev, 757d894fc60SAlex Smith JZ_DMA_DESC_BLOCK_SIZE, 758d894fc60SAlex Smith PAGE_SIZE, 0); 759d894fc60SAlex Smith if (!jzchan->desc_pool) { 760d894fc60SAlex Smith dev_err(&chan->dev->device, 761d894fc60SAlex Smith "failed to allocate descriptor pool\n"); 762d894fc60SAlex Smith return -ENOMEM; 763d894fc60SAlex Smith } 764d894fc60SAlex Smith 765d894fc60SAlex Smith return 0; 766d894fc60SAlex Smith } 767d894fc60SAlex Smith 768d894fc60SAlex Smith static void jz4780_dma_free_chan_resources(struct dma_chan *chan) 769d894fc60SAlex Smith { 770d894fc60SAlex Smith struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan); 771d894fc60SAlex Smith 772d894fc60SAlex Smith vchan_free_chan_resources(&jzchan->vchan); 773d894fc60SAlex Smith dma_pool_destroy(jzchan->desc_pool); 774d894fc60SAlex Smith jzchan->desc_pool = NULL; 775d894fc60SAlex Smith } 776d894fc60SAlex Smith 777d894fc60SAlex Smith static bool jz4780_dma_filter_fn(struct dma_chan *chan, void *param) 778d894fc60SAlex Smith { 779d894fc60SAlex Smith struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan); 780d894fc60SAlex Smith struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan); 781026fd406SAlex Smith struct jz4780_dma_filter_data *data = param; 782026fd406SAlex Smith 783d894fc60SAlex Smith 784d894fc60SAlex Smith if (data->channel > -1) { 785d894fc60SAlex Smith if (data->channel != jzchan->id) 786d894fc60SAlex Smith return false; 787d894fc60SAlex Smith } else if (jzdma->chan_reserved & BIT(jzchan->id)) { 788d894fc60SAlex Smith return false; 789d894fc60SAlex Smith } 790d894fc60SAlex Smith 791d894fc60SAlex Smith jzchan->transfer_type = data->transfer_type; 792d894fc60SAlex Smith 793d894fc60SAlex Smith return true; 794d894fc60SAlex Smith } 795d894fc60SAlex Smith 796d894fc60SAlex Smith static struct dma_chan *jz4780_of_dma_xlate(struct of_phandle_args *dma_spec, 797d894fc60SAlex Smith struct of_dma *ofdma) 798d894fc60SAlex Smith { 799d894fc60SAlex Smith struct jz4780_dma_dev *jzdma = ofdma->of_dma_data; 800d894fc60SAlex Smith dma_cap_mask_t mask = jzdma->dma_device.cap_mask; 801026fd406SAlex Smith struct jz4780_dma_filter_data data; 802d894fc60SAlex Smith 803d894fc60SAlex Smith if (dma_spec->args_count != 2) 804d894fc60SAlex Smith return NULL; 805d894fc60SAlex Smith 806d894fc60SAlex Smith data.transfer_type = dma_spec->args[0]; 807d894fc60SAlex Smith data.channel = dma_spec->args[1]; 808d894fc60SAlex Smith 809d894fc60SAlex Smith if (data.channel > -1) { 8106147b032SPaul Cercueil if (data.channel >= jzdma->soc_data->nb_channels) { 811d894fc60SAlex Smith dev_err(jzdma->dma_device.dev, 812d894fc60SAlex Smith "device requested non-existent channel %u\n", 813d894fc60SAlex Smith data.channel); 814d894fc60SAlex Smith return NULL; 815d894fc60SAlex Smith } 816d894fc60SAlex Smith 817d894fc60SAlex Smith /* Can only select a channel marked as reserved. */ 818d894fc60SAlex Smith if (!(jzdma->chan_reserved & BIT(data.channel))) { 819d894fc60SAlex Smith dev_err(jzdma->dma_device.dev, 820d894fc60SAlex Smith "device requested unreserved channel %u\n", 821d894fc60SAlex Smith data.channel); 822d894fc60SAlex Smith return NULL; 823d894fc60SAlex Smith } 824d894fc60SAlex Smith 825d3273e10SAlex Smith jzdma->chan[data.channel].transfer_type = data.transfer_type; 826d3273e10SAlex Smith 827d3273e10SAlex Smith return dma_get_slave_channel( 828d3273e10SAlex Smith &jzdma->chan[data.channel].vchan.chan); 829d3273e10SAlex Smith } else { 830c88ba7b9SBaolin Wang return __dma_request_channel(&mask, jz4780_dma_filter_fn, &data, 831c88ba7b9SBaolin Wang ofdma->of_node); 832d894fc60SAlex Smith } 833d3273e10SAlex Smith } 834d894fc60SAlex Smith 835d894fc60SAlex Smith static int jz4780_dma_probe(struct platform_device *pdev) 836d894fc60SAlex Smith { 837d894fc60SAlex Smith struct device *dev = &pdev->dev; 8386147b032SPaul Cercueil const struct jz4780_dma_soc_data *soc_data; 839d894fc60SAlex Smith struct jz4780_dma_dev *jzdma; 840d894fc60SAlex Smith struct jz4780_dma_chan *jzchan; 841d894fc60SAlex Smith struct dma_device *dd; 842d894fc60SAlex Smith struct resource *res; 843d894fc60SAlex Smith int i, ret; 844d894fc60SAlex Smith 84554f919a0SPaul Cercueil if (!dev->of_node) { 84654f919a0SPaul Cercueil dev_err(dev, "This driver must be probed from devicetree\n"); 84754f919a0SPaul Cercueil return -EINVAL; 84854f919a0SPaul Cercueil } 84954f919a0SPaul Cercueil 8506147b032SPaul Cercueil soc_data = device_get_match_data(dev); 8516147b032SPaul Cercueil if (!soc_data) 8526147b032SPaul Cercueil return -EINVAL; 8536147b032SPaul Cercueil 854ed414d58SGustavo A. R. Silva jzdma = devm_kzalloc(dev, struct_size(jzdma, chan, 855ed414d58SGustavo A. R. Silva soc_data->nb_channels), GFP_KERNEL); 856d894fc60SAlex Smith if (!jzdma) 857d894fc60SAlex Smith return -ENOMEM; 858d894fc60SAlex Smith 8596147b032SPaul Cercueil jzdma->soc_data = soc_data; 860d894fc60SAlex Smith platform_set_drvdata(pdev, jzdma); 861d894fc60SAlex Smith 8621148ac67SMarkus Elfring jzdma->chn_base = devm_platform_ioremap_resource(pdev, 0); 86333633583SPaul Cercueil if (IS_ERR(jzdma->chn_base)) 86433633583SPaul Cercueil return PTR_ERR(jzdma->chn_base); 86533633583SPaul Cercueil 86633633583SPaul Cercueil res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 86733633583SPaul Cercueil if (res) { 86833633583SPaul Cercueil jzdma->ctrl_base = devm_ioremap_resource(dev, res); 86933633583SPaul Cercueil if (IS_ERR(jzdma->ctrl_base)) 87033633583SPaul Cercueil return PTR_ERR(jzdma->ctrl_base); 87129870eb7SPaul Cercueil } else if (soc_data->flags & JZ_SOC_DATA_ALLOW_LEGACY_DT) { 87233633583SPaul Cercueil /* 87333633583SPaul Cercueil * On JZ4780, if the second memory resource was not supplied, 87433633583SPaul Cercueil * assume we're using an old devicetree, and calculate the 87533633583SPaul Cercueil * offset to the control registers. 87633633583SPaul Cercueil */ 87733633583SPaul Cercueil jzdma->ctrl_base = jzdma->chn_base + JZ4780_DMA_CTRL_OFFSET; 87829870eb7SPaul Cercueil } else { 87929870eb7SPaul Cercueil dev_err(dev, "failed to get I/O memory\n"); 88029870eb7SPaul Cercueil return -EINVAL; 88133633583SPaul Cercueil } 882d894fc60SAlex Smith 883d894fc60SAlex Smith jzdma->clk = devm_clk_get(dev, NULL); 884d894fc60SAlex Smith if (IS_ERR(jzdma->clk)) { 885d894fc60SAlex Smith dev_err(dev, "failed to get clock\n"); 886d509a83cSAlex Smith ret = PTR_ERR(jzdma->clk); 8876d6018fcSMadhuparna Bhowmik return ret; 888d894fc60SAlex Smith } 889d894fc60SAlex Smith 890d894fc60SAlex Smith clk_prepare_enable(jzdma->clk); 891d894fc60SAlex Smith 892d894fc60SAlex Smith /* Property is optional, if it doesn't exist the value will remain 0. */ 893d894fc60SAlex Smith of_property_read_u32_index(dev->of_node, "ingenic,reserved-channels", 894d894fc60SAlex Smith 0, &jzdma->chan_reserved); 895d894fc60SAlex Smith 896d894fc60SAlex Smith dd = &jzdma->dma_device; 897d894fc60SAlex Smith 898d894fc60SAlex Smith dma_cap_set(DMA_MEMCPY, dd->cap_mask); 899d894fc60SAlex Smith dma_cap_set(DMA_SLAVE, dd->cap_mask); 900d894fc60SAlex Smith dma_cap_set(DMA_CYCLIC, dd->cap_mask); 901d894fc60SAlex Smith 902d894fc60SAlex Smith dd->dev = dev; 90377a68e56SMaxime Ripard dd->copy_align = DMAENGINE_ALIGN_4_BYTES; 904d894fc60SAlex Smith dd->device_alloc_chan_resources = jz4780_dma_alloc_chan_resources; 905d894fc60SAlex Smith dd->device_free_chan_resources = jz4780_dma_free_chan_resources; 906d894fc60SAlex Smith dd->device_prep_slave_sg = jz4780_dma_prep_slave_sg; 907d894fc60SAlex Smith dd->device_prep_dma_cyclic = jz4780_dma_prep_dma_cyclic; 908d894fc60SAlex Smith dd->device_prep_dma_memcpy = jz4780_dma_prep_dma_memcpy; 90946fa5168SAlex Smith dd->device_config = jz4780_dma_config; 910d894fc60SAlex Smith dd->device_terminate_all = jz4780_dma_terminate_all; 911f0dd52c8SPeter Ujfalusi dd->device_synchronize = jz4780_dma_synchronize; 912d894fc60SAlex Smith dd->device_tx_status = jz4780_dma_tx_status; 913d894fc60SAlex Smith dd->device_issue_pending = jz4780_dma_issue_pending; 914d894fc60SAlex Smith dd->src_addr_widths = JZ_DMA_BUSWIDTHS; 915d894fc60SAlex Smith dd->dst_addr_widths = JZ_DMA_BUSWIDTHS; 916d894fc60SAlex Smith dd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); 917d894fc60SAlex Smith dd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; 918d894fc60SAlex Smith 919d894fc60SAlex Smith /* 920d894fc60SAlex Smith * Enable DMA controller, mark all channels as not programmable. 921d894fc60SAlex Smith * Also set the FMSC bit - it increases MSC performance, so it makes 922d894fc60SAlex Smith * little sense not to enable it. 923d894fc60SAlex Smith */ 92417a8e30eSPaul Cercueil jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DMAC, JZ_DMA_DMAC_DMAE | 92517a8e30eSPaul Cercueil JZ_DMA_DMAC_FAIC | JZ_DMA_DMAC_FMSC); 92629870eb7SPaul Cercueil 92729870eb7SPaul Cercueil if (soc_data->flags & JZ_SOC_DATA_PROGRAMMABLE_DMA) 92833633583SPaul Cercueil jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DMACP, 0); 929d894fc60SAlex Smith 930d894fc60SAlex Smith INIT_LIST_HEAD(&dd->channels); 931d894fc60SAlex Smith 9326147b032SPaul Cercueil for (i = 0; i < soc_data->nb_channels; i++) { 933d894fc60SAlex Smith jzchan = &jzdma->chan[i]; 934d894fc60SAlex Smith jzchan->id = i; 935d894fc60SAlex Smith 936d894fc60SAlex Smith vchan_init(&jzchan->vchan, dd); 937d894fc60SAlex Smith jzchan->vchan.desc_free = jz4780_dma_desc_free; 938d894fc60SAlex Smith } 939d894fc60SAlex Smith 9406d6018fcSMadhuparna Bhowmik ret = platform_get_irq(pdev, 0); 9416d6018fcSMadhuparna Bhowmik if (ret < 0) 9426d6018fcSMadhuparna Bhowmik goto err_disable_clk; 9436d6018fcSMadhuparna Bhowmik 9446d6018fcSMadhuparna Bhowmik jzdma->irq = ret; 9456d6018fcSMadhuparna Bhowmik 9466d6018fcSMadhuparna Bhowmik ret = request_irq(jzdma->irq, jz4780_dma_irq_handler, 0, dev_name(dev), 9476d6018fcSMadhuparna Bhowmik jzdma); 9486d6018fcSMadhuparna Bhowmik if (ret) { 9496d6018fcSMadhuparna Bhowmik dev_err(dev, "failed to request IRQ %u!\n", jzdma->irq); 9506d6018fcSMadhuparna Bhowmik goto err_disable_clk; 9516d6018fcSMadhuparna Bhowmik } 9526d6018fcSMadhuparna Bhowmik 9530f5a5e57SHuang Shijie ret = dmaenginem_async_device_register(dd); 954d894fc60SAlex Smith if (ret) { 955d894fc60SAlex Smith dev_err(dev, "failed to register device\n"); 9566d6018fcSMadhuparna Bhowmik goto err_free_irq; 957d894fc60SAlex Smith } 958d894fc60SAlex Smith 959d894fc60SAlex Smith /* Register with OF DMA helpers. */ 960d894fc60SAlex Smith ret = of_dma_controller_register(dev->of_node, jz4780_of_dma_xlate, 961d894fc60SAlex Smith jzdma); 962d894fc60SAlex Smith if (ret) { 963d894fc60SAlex Smith dev_err(dev, "failed to register OF DMA controller\n"); 9646d6018fcSMadhuparna Bhowmik goto err_free_irq; 965d894fc60SAlex Smith } 966d894fc60SAlex Smith 967d894fc60SAlex Smith dev_info(dev, "JZ4780 DMA controller initialised\n"); 968d894fc60SAlex Smith return 0; 969d894fc60SAlex Smith 970d509a83cSAlex Smith err_free_irq: 971d509a83cSAlex Smith free_irq(jzdma->irq, jzdma); 9726d6018fcSMadhuparna Bhowmik 9736d6018fcSMadhuparna Bhowmik err_disable_clk: 9746d6018fcSMadhuparna Bhowmik clk_disable_unprepare(jzdma->clk); 975d894fc60SAlex Smith return ret; 976d894fc60SAlex Smith } 977d894fc60SAlex Smith 978d894fc60SAlex Smith static int jz4780_dma_remove(struct platform_device *pdev) 979d894fc60SAlex Smith { 980d894fc60SAlex Smith struct jz4780_dma_dev *jzdma = platform_get_drvdata(pdev); 981ae9c02b4SAlex Smith int i; 982d894fc60SAlex Smith 983d894fc60SAlex Smith of_dma_controller_free(pdev->dev.of_node); 984ae9c02b4SAlex Smith 9859568fedaSChuhong Yuan clk_disable_unprepare(jzdma->clk); 986d509a83cSAlex Smith free_irq(jzdma->irq, jzdma); 987ae9c02b4SAlex Smith 9886147b032SPaul Cercueil for (i = 0; i < jzdma->soc_data->nb_channels; i++) 989ae9c02b4SAlex Smith tasklet_kill(&jzdma->chan[i].vchan.task); 990ae9c02b4SAlex Smith 991d894fc60SAlex Smith return 0; 992d894fc60SAlex Smith } 993d894fc60SAlex Smith 994ffaaa8ccSPaul Cercueil static const struct jz4780_dma_soc_data jz4740_dma_soc_data = { 995ffaaa8ccSPaul Cercueil .nb_channels = 6, 996ffaaa8ccSPaul Cercueil .transfer_ord_max = 5, 997f4c255f1SPaul Cercueil .flags = JZ_SOC_DATA_BREAK_LINKS, 998ffaaa8ccSPaul Cercueil }; 999ffaaa8ccSPaul Cercueil 1000ae9156b6SPaul Cercueil static const struct jz4780_dma_soc_data jz4725b_dma_soc_data = { 1001ae9156b6SPaul Cercueil .nb_channels = 6, 1002ae9156b6SPaul Cercueil .transfer_ord_max = 5, 1003a40c94beSPaul Cercueil .flags = JZ_SOC_DATA_PER_CHAN_PM | JZ_SOC_DATA_NO_DCKES_DCKEC | 1004a40c94beSPaul Cercueil JZ_SOC_DATA_BREAK_LINKS, 1005ae9156b6SPaul Cercueil }; 1006ae9156b6SPaul Cercueil 1007*d2852a3eSPaul Cercueil static const struct jz4780_dma_soc_data jz4760_dma_soc_data = { 1008*d2852a3eSPaul Cercueil .nb_channels = 5, 1009*d2852a3eSPaul Cercueil .transfer_ord_max = 6, 1010*d2852a3eSPaul Cercueil .flags = JZ_SOC_DATA_PER_CHAN_PM | JZ_SOC_DATA_NO_DCKES_DCKEC, 1011*d2852a3eSPaul Cercueil }; 1012*d2852a3eSPaul Cercueil 1013*d2852a3eSPaul Cercueil static const struct jz4780_dma_soc_data jz4760b_dma_soc_data = { 1014*d2852a3eSPaul Cercueil .nb_channels = 5, 1015*d2852a3eSPaul Cercueil .transfer_ord_max = 6, 1016*d2852a3eSPaul Cercueil .flags = JZ_SOC_DATA_PER_CHAN_PM, 1017*d2852a3eSPaul Cercueil }; 1018*d2852a3eSPaul Cercueil 101929870eb7SPaul Cercueil static const struct jz4780_dma_soc_data jz4770_dma_soc_data = { 102029870eb7SPaul Cercueil .nb_channels = 6, 102129870eb7SPaul Cercueil .transfer_ord_max = 6, 102229870eb7SPaul Cercueil .flags = JZ_SOC_DATA_PER_CHAN_PM, 102329870eb7SPaul Cercueil }; 102429870eb7SPaul Cercueil 10256147b032SPaul Cercueil static const struct jz4780_dma_soc_data jz4780_dma_soc_data = { 10266147b032SPaul Cercueil .nb_channels = 32, 102729870eb7SPaul Cercueil .transfer_ord_max = 7, 102829870eb7SPaul Cercueil .flags = JZ_SOC_DATA_ALLOW_LEGACY_DT | JZ_SOC_DATA_PROGRAMMABLE_DMA, 10296147b032SPaul Cercueil }; 10306147b032SPaul Cercueil 1031fee175e4SZhou Yanjie static const struct jz4780_dma_soc_data x1000_dma_soc_data = { 1032fee175e4SZhou Yanjie .nb_channels = 8, 1033fee175e4SZhou Yanjie .transfer_ord_max = 7, 1034fee175e4SZhou Yanjie .flags = JZ_SOC_DATA_PROGRAMMABLE_DMA, 1035fee175e4SZhou Yanjie }; 1036fee175e4SZhou Yanjie 103720f5a659S周琰杰 (Zhou Yanjie) static const struct jz4780_dma_soc_data x1830_dma_soc_data = { 103820f5a659S周琰杰 (Zhou Yanjie) .nb_channels = 32, 103920f5a659S周琰杰 (Zhou Yanjie) .transfer_ord_max = 7, 104020f5a659S周琰杰 (Zhou Yanjie) .flags = JZ_SOC_DATA_PROGRAMMABLE_DMA, 104120f5a659S周琰杰 (Zhou Yanjie) }; 104220f5a659S周琰杰 (Zhou Yanjie) 1043d894fc60SAlex Smith static const struct of_device_id jz4780_dma_dt_match[] = { 1044ffaaa8ccSPaul Cercueil { .compatible = "ingenic,jz4740-dma", .data = &jz4740_dma_soc_data }, 1045ae9156b6SPaul Cercueil { .compatible = "ingenic,jz4725b-dma", .data = &jz4725b_dma_soc_data }, 1046*d2852a3eSPaul Cercueil { .compatible = "ingenic,jz4760-dma", .data = &jz4760_dma_soc_data }, 1047*d2852a3eSPaul Cercueil { .compatible = "ingenic,jz4760b-dma", .data = &jz4760b_dma_soc_data }, 104829870eb7SPaul Cercueil { .compatible = "ingenic,jz4770-dma", .data = &jz4770_dma_soc_data }, 10496147b032SPaul Cercueil { .compatible = "ingenic,jz4780-dma", .data = &jz4780_dma_soc_data }, 1050fee175e4SZhou Yanjie { .compatible = "ingenic,x1000-dma", .data = &x1000_dma_soc_data }, 105120f5a659S周琰杰 (Zhou Yanjie) { .compatible = "ingenic,x1830-dma", .data = &x1830_dma_soc_data }, 1052d894fc60SAlex Smith {}, 1053d894fc60SAlex Smith }; 1054d894fc60SAlex Smith MODULE_DEVICE_TABLE(of, jz4780_dma_dt_match); 1055d894fc60SAlex Smith 1056d894fc60SAlex Smith static struct platform_driver jz4780_dma_driver = { 1057d894fc60SAlex Smith .probe = jz4780_dma_probe, 1058d894fc60SAlex Smith .remove = jz4780_dma_remove, 1059d894fc60SAlex Smith .driver = { 1060d894fc60SAlex Smith .name = "jz4780-dma", 1061255c2cc8SKrzysztof Kozlowski .of_match_table = jz4780_dma_dt_match, 1062d894fc60SAlex Smith }, 1063d894fc60SAlex Smith }; 1064d894fc60SAlex Smith 1065d894fc60SAlex Smith static int __init jz4780_dma_init(void) 1066d894fc60SAlex Smith { 1067d894fc60SAlex Smith return platform_driver_register(&jz4780_dma_driver); 1068d894fc60SAlex Smith } 1069d894fc60SAlex Smith subsys_initcall(jz4780_dma_init); 1070d894fc60SAlex Smith 1071d894fc60SAlex Smith static void __exit jz4780_dma_exit(void) 1072d894fc60SAlex Smith { 1073d894fc60SAlex Smith platform_driver_unregister(&jz4780_dma_driver); 1074d894fc60SAlex Smith } 1075d894fc60SAlex Smith module_exit(jz4780_dma_exit); 1076d894fc60SAlex Smith 1077d894fc60SAlex Smith MODULE_AUTHOR("Alex Smith <alex@alex-smith.me.uk>"); 1078d894fc60SAlex Smith MODULE_DESCRIPTION("Ingenic JZ4780 DMA controller driver"); 1079d894fc60SAlex Smith MODULE_LICENSE("GPL"); 1080