1d894fc60SAlex Smith /* 2d894fc60SAlex Smith * Ingenic JZ4780 DMA controller 3d894fc60SAlex Smith * 4d894fc60SAlex Smith * Copyright (c) 2015 Imagination Technologies 5d894fc60SAlex Smith * Author: Alex Smith <alex@alex-smith.me.uk> 6d894fc60SAlex Smith * 7d894fc60SAlex Smith * This program is free software; you can redistribute it and/or modify it 8d894fc60SAlex Smith * under the terms of the GNU General Public License as published by the 9d894fc60SAlex Smith * Free Software Foundation; either version 2 of the License, or (at your 10d894fc60SAlex Smith * option) any later version. 11d894fc60SAlex Smith */ 12d894fc60SAlex Smith 13d894fc60SAlex Smith #include <linux/clk.h> 14d894fc60SAlex Smith #include <linux/dmapool.h> 15d894fc60SAlex Smith #include <linux/init.h> 16d894fc60SAlex Smith #include <linux/interrupt.h> 17d894fc60SAlex Smith #include <linux/module.h> 18d894fc60SAlex Smith #include <linux/of.h> 196147b032SPaul Cercueil #include <linux/of_device.h> 20d894fc60SAlex Smith #include <linux/of_dma.h> 21d894fc60SAlex Smith #include <linux/platform_device.h> 22d894fc60SAlex Smith #include <linux/slab.h> 23d894fc60SAlex Smith 24d894fc60SAlex Smith #include "dmaengine.h" 25d894fc60SAlex Smith #include "virt-dma.h" 26d894fc60SAlex Smith 27d894fc60SAlex Smith /* Global registers. */ 28d894fc60SAlex Smith #define JZ_DMA_REG_DMAC 0x1000 29d894fc60SAlex Smith #define JZ_DMA_REG_DIRQP 0x1004 30d894fc60SAlex Smith #define JZ_DMA_REG_DDR 0x1008 31d894fc60SAlex Smith #define JZ_DMA_REG_DDRS 0x100c 32d894fc60SAlex Smith #define JZ_DMA_REG_DMACP 0x101c 33d894fc60SAlex Smith #define JZ_DMA_REG_DSIRQP 0x1020 34d894fc60SAlex Smith #define JZ_DMA_REG_DSIRQM 0x1024 35d894fc60SAlex Smith #define JZ_DMA_REG_DCIRQP 0x1028 36d894fc60SAlex Smith #define JZ_DMA_REG_DCIRQM 0x102c 37d894fc60SAlex Smith 38d894fc60SAlex Smith /* Per-channel registers. */ 39d894fc60SAlex Smith #define JZ_DMA_REG_CHAN(n) (n * 0x20) 40d894fc60SAlex Smith #define JZ_DMA_REG_DSA(n) (0x00 + JZ_DMA_REG_CHAN(n)) 41d894fc60SAlex Smith #define JZ_DMA_REG_DTA(n) (0x04 + JZ_DMA_REG_CHAN(n)) 42d894fc60SAlex Smith #define JZ_DMA_REG_DTC(n) (0x08 + JZ_DMA_REG_CHAN(n)) 43d894fc60SAlex Smith #define JZ_DMA_REG_DRT(n) (0x0c + JZ_DMA_REG_CHAN(n)) 44d894fc60SAlex Smith #define JZ_DMA_REG_DCS(n) (0x10 + JZ_DMA_REG_CHAN(n)) 45d894fc60SAlex Smith #define JZ_DMA_REG_DCM(n) (0x14 + JZ_DMA_REG_CHAN(n)) 46d894fc60SAlex Smith #define JZ_DMA_REG_DDA(n) (0x18 + JZ_DMA_REG_CHAN(n)) 47d894fc60SAlex Smith #define JZ_DMA_REG_DSD(n) (0x1c + JZ_DMA_REG_CHAN(n)) 48d894fc60SAlex Smith 49d894fc60SAlex Smith #define JZ_DMA_DMAC_DMAE BIT(0) 50d894fc60SAlex Smith #define JZ_DMA_DMAC_AR BIT(2) 51d894fc60SAlex Smith #define JZ_DMA_DMAC_HLT BIT(3) 52d894fc60SAlex Smith #define JZ_DMA_DMAC_FMSC BIT(31) 53d894fc60SAlex Smith 54d894fc60SAlex Smith #define JZ_DMA_DRT_AUTO 0x8 55d894fc60SAlex Smith 56d894fc60SAlex Smith #define JZ_DMA_DCS_CTE BIT(0) 57d894fc60SAlex Smith #define JZ_DMA_DCS_HLT BIT(2) 58d894fc60SAlex Smith #define JZ_DMA_DCS_TT BIT(3) 59d894fc60SAlex Smith #define JZ_DMA_DCS_AR BIT(4) 60d894fc60SAlex Smith #define JZ_DMA_DCS_DES8 BIT(30) 61d894fc60SAlex Smith 62d894fc60SAlex Smith #define JZ_DMA_DCM_LINK BIT(0) 63d894fc60SAlex Smith #define JZ_DMA_DCM_TIE BIT(1) 64d894fc60SAlex Smith #define JZ_DMA_DCM_STDE BIT(2) 65d894fc60SAlex Smith #define JZ_DMA_DCM_TSZ_SHIFT 8 66d894fc60SAlex Smith #define JZ_DMA_DCM_TSZ_MASK (0x7 << JZ_DMA_DCM_TSZ_SHIFT) 67d894fc60SAlex Smith #define JZ_DMA_DCM_DP_SHIFT 12 68d894fc60SAlex Smith #define JZ_DMA_DCM_SP_SHIFT 14 69d894fc60SAlex Smith #define JZ_DMA_DCM_DAI BIT(22) 70d894fc60SAlex Smith #define JZ_DMA_DCM_SAI BIT(23) 71d894fc60SAlex Smith 72d894fc60SAlex Smith #define JZ_DMA_SIZE_4_BYTE 0x0 73d894fc60SAlex Smith #define JZ_DMA_SIZE_1_BYTE 0x1 74d894fc60SAlex Smith #define JZ_DMA_SIZE_2_BYTE 0x2 75d894fc60SAlex Smith #define JZ_DMA_SIZE_16_BYTE 0x3 76d894fc60SAlex Smith #define JZ_DMA_SIZE_32_BYTE 0x4 77d894fc60SAlex Smith #define JZ_DMA_SIZE_64_BYTE 0x5 78d894fc60SAlex Smith #define JZ_DMA_SIZE_128_BYTE 0x6 79d894fc60SAlex Smith 80d894fc60SAlex Smith #define JZ_DMA_WIDTH_32_BIT 0x0 81d894fc60SAlex Smith #define JZ_DMA_WIDTH_8_BIT 0x1 82d894fc60SAlex Smith #define JZ_DMA_WIDTH_16_BIT 0x2 83d894fc60SAlex Smith 84d894fc60SAlex Smith #define JZ_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ 85d894fc60SAlex Smith BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ 86d894fc60SAlex Smith BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)) 87d894fc60SAlex Smith 88d894fc60SAlex Smith /** 89d894fc60SAlex Smith * struct jz4780_dma_hwdesc - descriptor structure read by the DMA controller. 90d894fc60SAlex Smith * @dcm: value for the DCM (channel command) register 91d894fc60SAlex Smith * @dsa: source address 92d894fc60SAlex Smith * @dta: target address 93d894fc60SAlex Smith * @dtc: transfer count (number of blocks of the transfer size specified in DCM 94d894fc60SAlex Smith * to transfer) in the low 24 bits, offset of the next descriptor from the 95d894fc60SAlex Smith * descriptor base address in the upper 8 bits. 96d894fc60SAlex Smith * @sd: target/source stride difference (in stride transfer mode). 97d894fc60SAlex Smith * @drt: request type 98d894fc60SAlex Smith */ 99d894fc60SAlex Smith struct jz4780_dma_hwdesc { 100d894fc60SAlex Smith uint32_t dcm; 101d894fc60SAlex Smith uint32_t dsa; 102d894fc60SAlex Smith uint32_t dta; 103d894fc60SAlex Smith uint32_t dtc; 104d894fc60SAlex Smith uint32_t sd; 105d894fc60SAlex Smith uint32_t drt; 106d894fc60SAlex Smith uint32_t reserved[2]; 107d894fc60SAlex Smith }; 108d894fc60SAlex Smith 109d894fc60SAlex Smith /* Size of allocations for hardware descriptor blocks. */ 110d894fc60SAlex Smith #define JZ_DMA_DESC_BLOCK_SIZE PAGE_SIZE 111d894fc60SAlex Smith #define JZ_DMA_MAX_DESC \ 112d894fc60SAlex Smith (JZ_DMA_DESC_BLOCK_SIZE / sizeof(struct jz4780_dma_hwdesc)) 113d894fc60SAlex Smith 114d894fc60SAlex Smith struct jz4780_dma_desc { 115d894fc60SAlex Smith struct virt_dma_desc vdesc; 116d894fc60SAlex Smith 117d894fc60SAlex Smith struct jz4780_dma_hwdesc *desc; 118d894fc60SAlex Smith dma_addr_t desc_phys; 119d894fc60SAlex Smith unsigned int count; 120d894fc60SAlex Smith enum dma_transaction_type type; 121d894fc60SAlex Smith uint32_t status; 122d894fc60SAlex Smith }; 123d894fc60SAlex Smith 124d894fc60SAlex Smith struct jz4780_dma_chan { 125d894fc60SAlex Smith struct virt_dma_chan vchan; 126d894fc60SAlex Smith unsigned int id; 127d894fc60SAlex Smith struct dma_pool *desc_pool; 128d894fc60SAlex Smith 129d894fc60SAlex Smith uint32_t transfer_type; 130d894fc60SAlex Smith uint32_t transfer_shift; 131d894fc60SAlex Smith struct dma_slave_config config; 132d894fc60SAlex Smith 133d894fc60SAlex Smith struct jz4780_dma_desc *desc; 134d894fc60SAlex Smith unsigned int curr_hwdesc; 135d894fc60SAlex Smith }; 136d894fc60SAlex Smith 1376147b032SPaul Cercueil struct jz4780_dma_soc_data { 1386147b032SPaul Cercueil unsigned int nb_channels; 1396147b032SPaul Cercueil }; 1406147b032SPaul Cercueil 141d894fc60SAlex Smith struct jz4780_dma_dev { 142d894fc60SAlex Smith struct dma_device dma_device; 143d894fc60SAlex Smith void __iomem *base; 144d894fc60SAlex Smith struct clk *clk; 145d894fc60SAlex Smith unsigned int irq; 1466147b032SPaul Cercueil const struct jz4780_dma_soc_data *soc_data; 147d894fc60SAlex Smith 148d894fc60SAlex Smith uint32_t chan_reserved; 1496147b032SPaul Cercueil struct jz4780_dma_chan chan[]; 150d894fc60SAlex Smith }; 151d894fc60SAlex Smith 152026fd406SAlex Smith struct jz4780_dma_filter_data { 153026fd406SAlex Smith struct device_node *of_node; 154d894fc60SAlex Smith uint32_t transfer_type; 155d894fc60SAlex Smith int channel; 156d894fc60SAlex Smith }; 157d894fc60SAlex Smith 158d894fc60SAlex Smith static inline struct jz4780_dma_chan *to_jz4780_dma_chan(struct dma_chan *chan) 159d894fc60SAlex Smith { 160d894fc60SAlex Smith return container_of(chan, struct jz4780_dma_chan, vchan.chan); 161d894fc60SAlex Smith } 162d894fc60SAlex Smith 163d894fc60SAlex Smith static inline struct jz4780_dma_desc *to_jz4780_dma_desc( 164d894fc60SAlex Smith struct virt_dma_desc *vdesc) 165d894fc60SAlex Smith { 166d894fc60SAlex Smith return container_of(vdesc, struct jz4780_dma_desc, vdesc); 167d894fc60SAlex Smith } 168d894fc60SAlex Smith 169d894fc60SAlex Smith static inline struct jz4780_dma_dev *jz4780_dma_chan_parent( 170d894fc60SAlex Smith struct jz4780_dma_chan *jzchan) 171d894fc60SAlex Smith { 172d894fc60SAlex Smith return container_of(jzchan->vchan.chan.device, struct jz4780_dma_dev, 173d894fc60SAlex Smith dma_device); 174d894fc60SAlex Smith } 175d894fc60SAlex Smith 176d894fc60SAlex Smith static inline uint32_t jz4780_dma_readl(struct jz4780_dma_dev *jzdma, 177d894fc60SAlex Smith unsigned int reg) 178d894fc60SAlex Smith { 179d894fc60SAlex Smith return readl(jzdma->base + reg); 180d894fc60SAlex Smith } 181d894fc60SAlex Smith 182d894fc60SAlex Smith static inline void jz4780_dma_writel(struct jz4780_dma_dev *jzdma, 183d894fc60SAlex Smith unsigned int reg, uint32_t val) 184d894fc60SAlex Smith { 185d894fc60SAlex Smith writel(val, jzdma->base + reg); 186d894fc60SAlex Smith } 187d894fc60SAlex Smith 188d894fc60SAlex Smith static struct jz4780_dma_desc *jz4780_dma_desc_alloc( 189d894fc60SAlex Smith struct jz4780_dma_chan *jzchan, unsigned int count, 190d894fc60SAlex Smith enum dma_transaction_type type) 191d894fc60SAlex Smith { 192d894fc60SAlex Smith struct jz4780_dma_desc *desc; 193d894fc60SAlex Smith 194d894fc60SAlex Smith if (count > JZ_DMA_MAX_DESC) 195d894fc60SAlex Smith return NULL; 196d894fc60SAlex Smith 197d894fc60SAlex Smith desc = kzalloc(sizeof(*desc), GFP_NOWAIT); 198d894fc60SAlex Smith if (!desc) 199d894fc60SAlex Smith return NULL; 200d894fc60SAlex Smith 201d894fc60SAlex Smith desc->desc = dma_pool_alloc(jzchan->desc_pool, GFP_NOWAIT, 202d894fc60SAlex Smith &desc->desc_phys); 203d894fc60SAlex Smith if (!desc->desc) { 204d894fc60SAlex Smith kfree(desc); 205d894fc60SAlex Smith return NULL; 206d894fc60SAlex Smith } 207d894fc60SAlex Smith 208d894fc60SAlex Smith desc->count = count; 209d894fc60SAlex Smith desc->type = type; 210d894fc60SAlex Smith return desc; 211d894fc60SAlex Smith } 212d894fc60SAlex Smith 213d894fc60SAlex Smith static void jz4780_dma_desc_free(struct virt_dma_desc *vdesc) 214d894fc60SAlex Smith { 215d894fc60SAlex Smith struct jz4780_dma_desc *desc = to_jz4780_dma_desc(vdesc); 216d894fc60SAlex Smith struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(vdesc->tx.chan); 217d894fc60SAlex Smith 218d894fc60SAlex Smith dma_pool_free(jzchan->desc_pool, desc->desc, desc->desc_phys); 219d894fc60SAlex Smith kfree(desc); 220d894fc60SAlex Smith } 221d894fc60SAlex Smith 222dc578f31SAlex Smith static uint32_t jz4780_dma_transfer_size(unsigned long val, uint32_t *shift) 223d894fc60SAlex Smith { 224dc578f31SAlex Smith int ord = ffs(val) - 1; 225d894fc60SAlex Smith 226dc578f31SAlex Smith /* 227dc578f31SAlex Smith * 8 byte transfer sizes unsupported so fall back on 4. If it's larger 228dc578f31SAlex Smith * than the maximum, just limit it. It is perfectly safe to fall back 229dc578f31SAlex Smith * in this way since we won't exceed the maximum burst size supported 230dc578f31SAlex Smith * by the device, the only effect is reduced efficiency. This is better 231dc578f31SAlex Smith * than refusing to perform the request at all. 232dc578f31SAlex Smith */ 233dc578f31SAlex Smith if (ord == 3) 234dc578f31SAlex Smith ord = 2; 235dc578f31SAlex Smith else if (ord > 7) 236dc578f31SAlex Smith ord = 7; 237dc578f31SAlex Smith 238dc578f31SAlex Smith *shift = ord; 239dc578f31SAlex Smith 240dc578f31SAlex Smith switch (ord) { 241d894fc60SAlex Smith case 0: 242d894fc60SAlex Smith return JZ_DMA_SIZE_1_BYTE; 243d894fc60SAlex Smith case 1: 244d894fc60SAlex Smith return JZ_DMA_SIZE_2_BYTE; 245d894fc60SAlex Smith case 2: 246d894fc60SAlex Smith return JZ_DMA_SIZE_4_BYTE; 247d894fc60SAlex Smith case 4: 248d894fc60SAlex Smith return JZ_DMA_SIZE_16_BYTE; 249d894fc60SAlex Smith case 5: 250d894fc60SAlex Smith return JZ_DMA_SIZE_32_BYTE; 251d894fc60SAlex Smith case 6: 252d894fc60SAlex Smith return JZ_DMA_SIZE_64_BYTE; 253d894fc60SAlex Smith default: 254dc578f31SAlex Smith return JZ_DMA_SIZE_128_BYTE; 255d894fc60SAlex Smith } 256d894fc60SAlex Smith } 257d894fc60SAlex Smith 258839896efSAlex Smith static int jz4780_dma_setup_hwdesc(struct jz4780_dma_chan *jzchan, 259d894fc60SAlex Smith struct jz4780_dma_hwdesc *desc, dma_addr_t addr, size_t len, 260d894fc60SAlex Smith enum dma_transfer_direction direction) 261d894fc60SAlex Smith { 262d894fc60SAlex Smith struct dma_slave_config *config = &jzchan->config; 263d894fc60SAlex Smith uint32_t width, maxburst, tsz; 264d894fc60SAlex Smith 265d894fc60SAlex Smith if (direction == DMA_MEM_TO_DEV) { 266d894fc60SAlex Smith desc->dcm = JZ_DMA_DCM_SAI; 267d894fc60SAlex Smith desc->dsa = addr; 268d894fc60SAlex Smith desc->dta = config->dst_addr; 269d894fc60SAlex Smith desc->drt = jzchan->transfer_type; 270d894fc60SAlex Smith 271d894fc60SAlex Smith width = config->dst_addr_width; 272d894fc60SAlex Smith maxburst = config->dst_maxburst; 273d894fc60SAlex Smith } else { 274d894fc60SAlex Smith desc->dcm = JZ_DMA_DCM_DAI; 275d894fc60SAlex Smith desc->dsa = config->src_addr; 276d894fc60SAlex Smith desc->dta = addr; 277d894fc60SAlex Smith desc->drt = jzchan->transfer_type; 278d894fc60SAlex Smith 279d894fc60SAlex Smith width = config->src_addr_width; 280d894fc60SAlex Smith maxburst = config->src_maxburst; 281d894fc60SAlex Smith } 282d894fc60SAlex Smith 283d894fc60SAlex Smith /* 284d894fc60SAlex Smith * This calculates the maximum transfer size that can be used with the 285d894fc60SAlex Smith * given address, length, width and maximum burst size. The address 286d894fc60SAlex Smith * must be aligned to the transfer size, the total length must be 287d894fc60SAlex Smith * divisible by the transfer size, and we must not use more than the 288d894fc60SAlex Smith * maximum burst specified by the user. 289d894fc60SAlex Smith */ 290dc578f31SAlex Smith tsz = jz4780_dma_transfer_size(addr | len | (width * maxburst), 291dc578f31SAlex Smith &jzchan->transfer_shift); 292d894fc60SAlex Smith 293d894fc60SAlex Smith switch (width) { 294d894fc60SAlex Smith case DMA_SLAVE_BUSWIDTH_1_BYTE: 295d894fc60SAlex Smith case DMA_SLAVE_BUSWIDTH_2_BYTES: 296d894fc60SAlex Smith break; 297d894fc60SAlex Smith case DMA_SLAVE_BUSWIDTH_4_BYTES: 298d894fc60SAlex Smith width = JZ_DMA_WIDTH_32_BIT; 299d894fc60SAlex Smith break; 300d894fc60SAlex Smith default: 301d894fc60SAlex Smith return -EINVAL; 302d894fc60SAlex Smith } 303d894fc60SAlex Smith 304d894fc60SAlex Smith desc->dcm |= tsz << JZ_DMA_DCM_TSZ_SHIFT; 305d894fc60SAlex Smith desc->dcm |= width << JZ_DMA_DCM_SP_SHIFT; 306d894fc60SAlex Smith desc->dcm |= width << JZ_DMA_DCM_DP_SHIFT; 307d894fc60SAlex Smith 308dc578f31SAlex Smith desc->dtc = len >> jzchan->transfer_shift; 309839896efSAlex Smith return 0; 310d894fc60SAlex Smith } 311d894fc60SAlex Smith 312d894fc60SAlex Smith static struct dma_async_tx_descriptor *jz4780_dma_prep_slave_sg( 313d894fc60SAlex Smith struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, 31446fa5168SAlex Smith enum dma_transfer_direction direction, unsigned long flags, 31546fa5168SAlex Smith void *context) 316d894fc60SAlex Smith { 317d894fc60SAlex Smith struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan); 318d894fc60SAlex Smith struct jz4780_dma_desc *desc; 319d894fc60SAlex Smith unsigned int i; 320d894fc60SAlex Smith int err; 321d894fc60SAlex Smith 322d894fc60SAlex Smith desc = jz4780_dma_desc_alloc(jzchan, sg_len, DMA_SLAVE); 323d894fc60SAlex Smith if (!desc) 324d894fc60SAlex Smith return NULL; 325d894fc60SAlex Smith 326d894fc60SAlex Smith for (i = 0; i < sg_len; i++) { 327d894fc60SAlex Smith err = jz4780_dma_setup_hwdesc(jzchan, &desc->desc[i], 328d894fc60SAlex Smith sg_dma_address(&sgl[i]), 329d894fc60SAlex Smith sg_dma_len(&sgl[i]), 330d894fc60SAlex Smith direction); 331fc878efeSColin Ian King if (err < 0) { 332fc878efeSColin Ian King jz4780_dma_desc_free(&jzchan->desc->vdesc); 333839896efSAlex Smith return NULL; 334fc878efeSColin Ian King } 335d894fc60SAlex Smith 336d894fc60SAlex Smith desc->desc[i].dcm |= JZ_DMA_DCM_TIE; 337d894fc60SAlex Smith 338d894fc60SAlex Smith if (i != (sg_len - 1)) { 339d894fc60SAlex Smith /* Automatically proceeed to the next descriptor. */ 340d894fc60SAlex Smith desc->desc[i].dcm |= JZ_DMA_DCM_LINK; 341d894fc60SAlex Smith 342d894fc60SAlex Smith /* 343d894fc60SAlex Smith * The upper 8 bits of the DTC field in the descriptor 344d894fc60SAlex Smith * must be set to (offset from descriptor base of next 345d894fc60SAlex Smith * descriptor >> 4). 346d894fc60SAlex Smith */ 347d894fc60SAlex Smith desc->desc[i].dtc |= 348d894fc60SAlex Smith (((i + 1) * sizeof(*desc->desc)) >> 4) << 24; 349d894fc60SAlex Smith } 350d894fc60SAlex Smith } 351d894fc60SAlex Smith 352d894fc60SAlex Smith return vchan_tx_prep(&jzchan->vchan, &desc->vdesc, flags); 353d894fc60SAlex Smith } 354d894fc60SAlex Smith 355d894fc60SAlex Smith static struct dma_async_tx_descriptor *jz4780_dma_prep_dma_cyclic( 356d894fc60SAlex Smith struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, 357d894fc60SAlex Smith size_t period_len, enum dma_transfer_direction direction, 358d894fc60SAlex Smith unsigned long flags) 359d894fc60SAlex Smith { 360d894fc60SAlex Smith struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan); 361d894fc60SAlex Smith struct jz4780_dma_desc *desc; 362d894fc60SAlex Smith unsigned int periods, i; 363d894fc60SAlex Smith int err; 364d894fc60SAlex Smith 365d894fc60SAlex Smith if (buf_len % period_len) 366d894fc60SAlex Smith return NULL; 367d894fc60SAlex Smith 368d894fc60SAlex Smith periods = buf_len / period_len; 369d894fc60SAlex Smith 370d894fc60SAlex Smith desc = jz4780_dma_desc_alloc(jzchan, periods, DMA_CYCLIC); 371d894fc60SAlex Smith if (!desc) 372d894fc60SAlex Smith return NULL; 373d894fc60SAlex Smith 374d894fc60SAlex Smith for (i = 0; i < periods; i++) { 375d894fc60SAlex Smith err = jz4780_dma_setup_hwdesc(jzchan, &desc->desc[i], buf_addr, 376d894fc60SAlex Smith period_len, direction); 377fc878efeSColin Ian King if (err < 0) { 378fc878efeSColin Ian King jz4780_dma_desc_free(&jzchan->desc->vdesc); 379839896efSAlex Smith return NULL; 380fc878efeSColin Ian King } 381d894fc60SAlex Smith 382d894fc60SAlex Smith buf_addr += period_len; 383d894fc60SAlex Smith 384d894fc60SAlex Smith /* 385d894fc60SAlex Smith * Set the link bit to indicate that the controller should 386d894fc60SAlex Smith * automatically proceed to the next descriptor. In 387d894fc60SAlex Smith * jz4780_dma_begin(), this will be cleared if we need to issue 388d894fc60SAlex Smith * an interrupt after each period. 389d894fc60SAlex Smith */ 390d894fc60SAlex Smith desc->desc[i].dcm |= JZ_DMA_DCM_TIE | JZ_DMA_DCM_LINK; 391d894fc60SAlex Smith 392d894fc60SAlex Smith /* 393d894fc60SAlex Smith * The upper 8 bits of the DTC field in the descriptor must be 394d894fc60SAlex Smith * set to (offset from descriptor base of next descriptor >> 4). 395d894fc60SAlex Smith * If this is the last descriptor, link it back to the first, 396d894fc60SAlex Smith * i.e. leave offset set to 0, otherwise point to the next one. 397d894fc60SAlex Smith */ 398d894fc60SAlex Smith if (i != (periods - 1)) { 399d894fc60SAlex Smith desc->desc[i].dtc |= 400d894fc60SAlex Smith (((i + 1) * sizeof(*desc->desc)) >> 4) << 24; 401d894fc60SAlex Smith } 402d894fc60SAlex Smith } 403d894fc60SAlex Smith 404d894fc60SAlex Smith return vchan_tx_prep(&jzchan->vchan, &desc->vdesc, flags); 405d894fc60SAlex Smith } 406d894fc60SAlex Smith 4074f5db8c8SVinod Koul static struct dma_async_tx_descriptor *jz4780_dma_prep_dma_memcpy( 408d894fc60SAlex Smith struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, 409d894fc60SAlex Smith size_t len, unsigned long flags) 410d894fc60SAlex Smith { 411d894fc60SAlex Smith struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan); 412d894fc60SAlex Smith struct jz4780_dma_desc *desc; 413d894fc60SAlex Smith uint32_t tsz; 414d894fc60SAlex Smith 415d894fc60SAlex Smith desc = jz4780_dma_desc_alloc(jzchan, 1, DMA_MEMCPY); 416d894fc60SAlex Smith if (!desc) 417d894fc60SAlex Smith return NULL; 418d894fc60SAlex Smith 419dc578f31SAlex Smith tsz = jz4780_dma_transfer_size(dest | src | len, 420dc578f31SAlex Smith &jzchan->transfer_shift); 421d894fc60SAlex Smith 422d894fc60SAlex Smith desc->desc[0].dsa = src; 423d894fc60SAlex Smith desc->desc[0].dta = dest; 424d894fc60SAlex Smith desc->desc[0].drt = JZ_DMA_DRT_AUTO; 425d894fc60SAlex Smith desc->desc[0].dcm = JZ_DMA_DCM_TIE | JZ_DMA_DCM_SAI | JZ_DMA_DCM_DAI | 426d894fc60SAlex Smith tsz << JZ_DMA_DCM_TSZ_SHIFT | 427d894fc60SAlex Smith JZ_DMA_WIDTH_32_BIT << JZ_DMA_DCM_SP_SHIFT | 428d894fc60SAlex Smith JZ_DMA_WIDTH_32_BIT << JZ_DMA_DCM_DP_SHIFT; 429839896efSAlex Smith desc->desc[0].dtc = len >> jzchan->transfer_shift; 430d894fc60SAlex Smith 431d894fc60SAlex Smith return vchan_tx_prep(&jzchan->vchan, &desc->vdesc, flags); 432d894fc60SAlex Smith } 433d894fc60SAlex Smith 434d894fc60SAlex Smith static void jz4780_dma_begin(struct jz4780_dma_chan *jzchan) 435d894fc60SAlex Smith { 436d894fc60SAlex Smith struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan); 437d894fc60SAlex Smith struct virt_dma_desc *vdesc; 438d894fc60SAlex Smith unsigned int i; 439d894fc60SAlex Smith dma_addr_t desc_phys; 440d894fc60SAlex Smith 441d894fc60SAlex Smith if (!jzchan->desc) { 442d894fc60SAlex Smith vdesc = vchan_next_desc(&jzchan->vchan); 443d894fc60SAlex Smith if (!vdesc) 444d894fc60SAlex Smith return; 445d894fc60SAlex Smith 446d894fc60SAlex Smith list_del(&vdesc->node); 447d894fc60SAlex Smith 448d894fc60SAlex Smith jzchan->desc = to_jz4780_dma_desc(vdesc); 449d894fc60SAlex Smith jzchan->curr_hwdesc = 0; 450d894fc60SAlex Smith 451d894fc60SAlex Smith if (jzchan->desc->type == DMA_CYCLIC && vdesc->tx.callback) { 452d894fc60SAlex Smith /* 453d894fc60SAlex Smith * The DMA controller doesn't support triggering an 454d894fc60SAlex Smith * interrupt after processing each descriptor, only 455d894fc60SAlex Smith * after processing an entire terminated list of 456d894fc60SAlex Smith * descriptors. For a cyclic DMA setup the list of 457d894fc60SAlex Smith * descriptors is not terminated so we can never get an 458d894fc60SAlex Smith * interrupt. 459d894fc60SAlex Smith * 460d894fc60SAlex Smith * If the user requested a callback for a cyclic DMA 461d894fc60SAlex Smith * setup then we workaround this hardware limitation 462d894fc60SAlex Smith * here by degrading to a set of unlinked descriptors 463d894fc60SAlex Smith * which we will submit in sequence in response to the 464d894fc60SAlex Smith * completion of processing the previous descriptor. 465d894fc60SAlex Smith */ 466d894fc60SAlex Smith for (i = 0; i < jzchan->desc->count; i++) 467d894fc60SAlex Smith jzchan->desc->desc[i].dcm &= ~JZ_DMA_DCM_LINK; 468d894fc60SAlex Smith } 469d894fc60SAlex Smith } else { 470d894fc60SAlex Smith /* 471d894fc60SAlex Smith * There is an existing transfer, therefore this must be one 472d894fc60SAlex Smith * for which we unlinked the descriptors above. Advance to the 473d894fc60SAlex Smith * next one in the list. 474d894fc60SAlex Smith */ 475d894fc60SAlex Smith jzchan->curr_hwdesc = 476d894fc60SAlex Smith (jzchan->curr_hwdesc + 1) % jzchan->desc->count; 477d894fc60SAlex Smith } 478d894fc60SAlex Smith 479d894fc60SAlex Smith /* Use 8-word descriptors. */ 480d894fc60SAlex Smith jz4780_dma_writel(jzdma, JZ_DMA_REG_DCS(jzchan->id), JZ_DMA_DCS_DES8); 481d894fc60SAlex Smith 482d894fc60SAlex Smith /* Write descriptor address and initiate descriptor fetch. */ 483d894fc60SAlex Smith desc_phys = jzchan->desc->desc_phys + 484d894fc60SAlex Smith (jzchan->curr_hwdesc * sizeof(*jzchan->desc->desc)); 485d894fc60SAlex Smith jz4780_dma_writel(jzdma, JZ_DMA_REG_DDA(jzchan->id), desc_phys); 486d894fc60SAlex Smith jz4780_dma_writel(jzdma, JZ_DMA_REG_DDRS, BIT(jzchan->id)); 487d894fc60SAlex Smith 488d894fc60SAlex Smith /* Enable the channel. */ 489d894fc60SAlex Smith jz4780_dma_writel(jzdma, JZ_DMA_REG_DCS(jzchan->id), 490d894fc60SAlex Smith JZ_DMA_DCS_DES8 | JZ_DMA_DCS_CTE); 491d894fc60SAlex Smith } 492d894fc60SAlex Smith 493d894fc60SAlex Smith static void jz4780_dma_issue_pending(struct dma_chan *chan) 494d894fc60SAlex Smith { 495d894fc60SAlex Smith struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan); 496d894fc60SAlex Smith unsigned long flags; 497d894fc60SAlex Smith 498d894fc60SAlex Smith spin_lock_irqsave(&jzchan->vchan.lock, flags); 499d894fc60SAlex Smith 500d894fc60SAlex Smith if (vchan_issue_pending(&jzchan->vchan) && !jzchan->desc) 501d894fc60SAlex Smith jz4780_dma_begin(jzchan); 502d894fc60SAlex Smith 503d894fc60SAlex Smith spin_unlock_irqrestore(&jzchan->vchan.lock, flags); 504d894fc60SAlex Smith } 505d894fc60SAlex Smith 50646fa5168SAlex Smith static int jz4780_dma_terminate_all(struct dma_chan *chan) 507d894fc60SAlex Smith { 50846fa5168SAlex Smith struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan); 509d894fc60SAlex Smith struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan); 510d894fc60SAlex Smith unsigned long flags; 511d894fc60SAlex Smith LIST_HEAD(head); 512d894fc60SAlex Smith 513d894fc60SAlex Smith spin_lock_irqsave(&jzchan->vchan.lock, flags); 514d894fc60SAlex Smith 515d894fc60SAlex Smith /* Clear the DMA status and stop the transfer. */ 516d894fc60SAlex Smith jz4780_dma_writel(jzdma, JZ_DMA_REG_DCS(jzchan->id), 0); 517d894fc60SAlex Smith if (jzchan->desc) { 518f0dd52c8SPeter Ujfalusi vchan_terminate_vdesc(&jzchan->desc->vdesc); 519d894fc60SAlex Smith jzchan->desc = NULL; 520d894fc60SAlex Smith } 521d894fc60SAlex Smith 522d894fc60SAlex Smith vchan_get_all_descriptors(&jzchan->vchan, &head); 523d894fc60SAlex Smith 524d894fc60SAlex Smith spin_unlock_irqrestore(&jzchan->vchan.lock, flags); 525d894fc60SAlex Smith 526d894fc60SAlex Smith vchan_dma_desc_free_list(&jzchan->vchan, &head); 527d894fc60SAlex Smith return 0; 528d894fc60SAlex Smith } 529d894fc60SAlex Smith 530f0dd52c8SPeter Ujfalusi static void jz4780_dma_synchronize(struct dma_chan *chan) 531f0dd52c8SPeter Ujfalusi { 532f0dd52c8SPeter Ujfalusi struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan); 533f0dd52c8SPeter Ujfalusi 534f0dd52c8SPeter Ujfalusi vchan_synchronize(&jzchan->vchan); 535f0dd52c8SPeter Ujfalusi } 536f0dd52c8SPeter Ujfalusi 53746fa5168SAlex Smith static int jz4780_dma_config(struct dma_chan *chan, 53846fa5168SAlex Smith struct dma_slave_config *config) 539d894fc60SAlex Smith { 54046fa5168SAlex Smith struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan); 54146fa5168SAlex Smith 542d894fc60SAlex Smith if ((config->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES) 543d894fc60SAlex Smith || (config->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)) 544d894fc60SAlex Smith return -EINVAL; 545d894fc60SAlex Smith 546d894fc60SAlex Smith /* Copy the reset of the slave configuration, it is used later. */ 547d894fc60SAlex Smith memcpy(&jzchan->config, config, sizeof(jzchan->config)); 548d894fc60SAlex Smith 549d894fc60SAlex Smith return 0; 550d894fc60SAlex Smith } 551d894fc60SAlex Smith 552d894fc60SAlex Smith static size_t jz4780_dma_desc_residue(struct jz4780_dma_chan *jzchan, 553d894fc60SAlex Smith struct jz4780_dma_desc *desc, unsigned int next_sg) 554d894fc60SAlex Smith { 555d894fc60SAlex Smith struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan); 556d894fc60SAlex Smith unsigned int residue, count; 557d894fc60SAlex Smith unsigned int i; 558d894fc60SAlex Smith 559d894fc60SAlex Smith residue = 0; 560d894fc60SAlex Smith 561d894fc60SAlex Smith for (i = next_sg; i < desc->count; i++) 562d894fc60SAlex Smith residue += desc->desc[i].dtc << jzchan->transfer_shift; 563d894fc60SAlex Smith 564d894fc60SAlex Smith if (next_sg != 0) { 565d894fc60SAlex Smith count = jz4780_dma_readl(jzdma, 566d894fc60SAlex Smith JZ_DMA_REG_DTC(jzchan->id)); 567d894fc60SAlex Smith residue += count << jzchan->transfer_shift; 568d894fc60SAlex Smith } 569d894fc60SAlex Smith 570d894fc60SAlex Smith return residue; 571d894fc60SAlex Smith } 572d894fc60SAlex Smith 573d894fc60SAlex Smith static enum dma_status jz4780_dma_tx_status(struct dma_chan *chan, 574d894fc60SAlex Smith dma_cookie_t cookie, struct dma_tx_state *txstate) 575d894fc60SAlex Smith { 576d894fc60SAlex Smith struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan); 577d894fc60SAlex Smith struct virt_dma_desc *vdesc; 578d894fc60SAlex Smith enum dma_status status; 579d894fc60SAlex Smith unsigned long flags; 580d894fc60SAlex Smith 581d894fc60SAlex Smith status = dma_cookie_status(chan, cookie, txstate); 582d894fc60SAlex Smith if ((status == DMA_COMPLETE) || (txstate == NULL)) 583d894fc60SAlex Smith return status; 584d894fc60SAlex Smith 585d894fc60SAlex Smith spin_lock_irqsave(&jzchan->vchan.lock, flags); 586d894fc60SAlex Smith 587d894fc60SAlex Smith vdesc = vchan_find_desc(&jzchan->vchan, cookie); 588d894fc60SAlex Smith if (vdesc) { 589d894fc60SAlex Smith /* On the issued list, so hasn't been processed yet */ 590d894fc60SAlex Smith txstate->residue = jz4780_dma_desc_residue(jzchan, 591d894fc60SAlex Smith to_jz4780_dma_desc(vdesc), 0); 592d894fc60SAlex Smith } else if (cookie == jzchan->desc->vdesc.tx.cookie) { 593d894fc60SAlex Smith txstate->residue = jz4780_dma_desc_residue(jzchan, jzchan->desc, 594d894fc60SAlex Smith (jzchan->curr_hwdesc + 1) % jzchan->desc->count); 595d894fc60SAlex Smith } else 596d894fc60SAlex Smith txstate->residue = 0; 597d894fc60SAlex Smith 598d894fc60SAlex Smith if (vdesc && jzchan->desc && vdesc == &jzchan->desc->vdesc 599d894fc60SAlex Smith && jzchan->desc->status & (JZ_DMA_DCS_AR | JZ_DMA_DCS_HLT)) 600d894fc60SAlex Smith status = DMA_ERROR; 601d894fc60SAlex Smith 602d894fc60SAlex Smith spin_unlock_irqrestore(&jzchan->vchan.lock, flags); 603d894fc60SAlex Smith return status; 604d894fc60SAlex Smith } 605d894fc60SAlex Smith 606d894fc60SAlex Smith static void jz4780_dma_chan_irq(struct jz4780_dma_dev *jzdma, 607d894fc60SAlex Smith struct jz4780_dma_chan *jzchan) 608d894fc60SAlex Smith { 609d894fc60SAlex Smith uint32_t dcs; 610d894fc60SAlex Smith 611d894fc60SAlex Smith spin_lock(&jzchan->vchan.lock); 612d894fc60SAlex Smith 613d894fc60SAlex Smith dcs = jz4780_dma_readl(jzdma, JZ_DMA_REG_DCS(jzchan->id)); 614d894fc60SAlex Smith jz4780_dma_writel(jzdma, JZ_DMA_REG_DCS(jzchan->id), 0); 615d894fc60SAlex Smith 616d894fc60SAlex Smith if (dcs & JZ_DMA_DCS_AR) { 617d894fc60SAlex Smith dev_warn(&jzchan->vchan.chan.dev->device, 618d894fc60SAlex Smith "address error (DCS=0x%x)\n", dcs); 619d894fc60SAlex Smith } 620d894fc60SAlex Smith 621d894fc60SAlex Smith if (dcs & JZ_DMA_DCS_HLT) { 622d894fc60SAlex Smith dev_warn(&jzchan->vchan.chan.dev->device, 623d894fc60SAlex Smith "channel halt (DCS=0x%x)\n", dcs); 624d894fc60SAlex Smith } 625d894fc60SAlex Smith 626d894fc60SAlex Smith if (jzchan->desc) { 627d894fc60SAlex Smith jzchan->desc->status = dcs; 628d894fc60SAlex Smith 629d894fc60SAlex Smith if ((dcs & (JZ_DMA_DCS_AR | JZ_DMA_DCS_HLT)) == 0) { 630d894fc60SAlex Smith if (jzchan->desc->type == DMA_CYCLIC) { 631d894fc60SAlex Smith vchan_cyclic_callback(&jzchan->desc->vdesc); 632d894fc60SAlex Smith } else { 633d894fc60SAlex Smith vchan_cookie_complete(&jzchan->desc->vdesc); 634d894fc60SAlex Smith jzchan->desc = NULL; 635d894fc60SAlex Smith } 636d894fc60SAlex Smith 637d894fc60SAlex Smith jz4780_dma_begin(jzchan); 638d894fc60SAlex Smith } 639d894fc60SAlex Smith } else { 640d894fc60SAlex Smith dev_err(&jzchan->vchan.chan.dev->device, 641d894fc60SAlex Smith "channel IRQ with no active transfer\n"); 642d894fc60SAlex Smith } 643d894fc60SAlex Smith 644d894fc60SAlex Smith spin_unlock(&jzchan->vchan.lock); 645d894fc60SAlex Smith } 646d894fc60SAlex Smith 647d894fc60SAlex Smith static irqreturn_t jz4780_dma_irq_handler(int irq, void *data) 648d894fc60SAlex Smith { 649d894fc60SAlex Smith struct jz4780_dma_dev *jzdma = data; 650d894fc60SAlex Smith uint32_t pending, dmac; 651d894fc60SAlex Smith int i; 652d894fc60SAlex Smith 653d894fc60SAlex Smith pending = jz4780_dma_readl(jzdma, JZ_DMA_REG_DIRQP); 654d894fc60SAlex Smith 6556147b032SPaul Cercueil for (i = 0; i < jzdma->soc_data->nb_channels; i++) { 656d894fc60SAlex Smith if (!(pending & (1<<i))) 657d894fc60SAlex Smith continue; 658d894fc60SAlex Smith 659d894fc60SAlex Smith jz4780_dma_chan_irq(jzdma, &jzdma->chan[i]); 660d894fc60SAlex Smith } 661d894fc60SAlex Smith 662d894fc60SAlex Smith /* Clear halt and address error status of all channels. */ 663d894fc60SAlex Smith dmac = jz4780_dma_readl(jzdma, JZ_DMA_REG_DMAC); 664d894fc60SAlex Smith dmac &= ~(JZ_DMA_DMAC_HLT | JZ_DMA_DMAC_AR); 665d894fc60SAlex Smith jz4780_dma_writel(jzdma, JZ_DMA_REG_DMAC, dmac); 666d894fc60SAlex Smith 667d894fc60SAlex Smith /* Clear interrupt pending status. */ 668d894fc60SAlex Smith jz4780_dma_writel(jzdma, JZ_DMA_REG_DIRQP, 0); 669d894fc60SAlex Smith 670d894fc60SAlex Smith return IRQ_HANDLED; 671d894fc60SAlex Smith } 672d894fc60SAlex Smith 673d894fc60SAlex Smith static int jz4780_dma_alloc_chan_resources(struct dma_chan *chan) 674d894fc60SAlex Smith { 675d894fc60SAlex Smith struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan); 676d894fc60SAlex Smith 677d894fc60SAlex Smith jzchan->desc_pool = dma_pool_create(dev_name(&chan->dev->device), 678d894fc60SAlex Smith chan->device->dev, 679d894fc60SAlex Smith JZ_DMA_DESC_BLOCK_SIZE, 680d894fc60SAlex Smith PAGE_SIZE, 0); 681d894fc60SAlex Smith if (!jzchan->desc_pool) { 682d894fc60SAlex Smith dev_err(&chan->dev->device, 683d894fc60SAlex Smith "failed to allocate descriptor pool\n"); 684d894fc60SAlex Smith return -ENOMEM; 685d894fc60SAlex Smith } 686d894fc60SAlex Smith 687d894fc60SAlex Smith return 0; 688d894fc60SAlex Smith } 689d894fc60SAlex Smith 690d894fc60SAlex Smith static void jz4780_dma_free_chan_resources(struct dma_chan *chan) 691d894fc60SAlex Smith { 692d894fc60SAlex Smith struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan); 693d894fc60SAlex Smith 694d894fc60SAlex Smith vchan_free_chan_resources(&jzchan->vchan); 695d894fc60SAlex Smith dma_pool_destroy(jzchan->desc_pool); 696d894fc60SAlex Smith jzchan->desc_pool = NULL; 697d894fc60SAlex Smith } 698d894fc60SAlex Smith 699d894fc60SAlex Smith static bool jz4780_dma_filter_fn(struct dma_chan *chan, void *param) 700d894fc60SAlex Smith { 701d894fc60SAlex Smith struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan); 702d894fc60SAlex Smith struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan); 703026fd406SAlex Smith struct jz4780_dma_filter_data *data = param; 704026fd406SAlex Smith 705026fd406SAlex Smith if (jzdma->dma_device.dev->of_node != data->of_node) 706026fd406SAlex Smith return false; 707d894fc60SAlex Smith 708d894fc60SAlex Smith if (data->channel > -1) { 709d894fc60SAlex Smith if (data->channel != jzchan->id) 710d894fc60SAlex Smith return false; 711d894fc60SAlex Smith } else if (jzdma->chan_reserved & BIT(jzchan->id)) { 712d894fc60SAlex Smith return false; 713d894fc60SAlex Smith } 714d894fc60SAlex Smith 715d894fc60SAlex Smith jzchan->transfer_type = data->transfer_type; 716d894fc60SAlex Smith 717d894fc60SAlex Smith return true; 718d894fc60SAlex Smith } 719d894fc60SAlex Smith 720d894fc60SAlex Smith static struct dma_chan *jz4780_of_dma_xlate(struct of_phandle_args *dma_spec, 721d894fc60SAlex Smith struct of_dma *ofdma) 722d894fc60SAlex Smith { 723d894fc60SAlex Smith struct jz4780_dma_dev *jzdma = ofdma->of_dma_data; 724d894fc60SAlex Smith dma_cap_mask_t mask = jzdma->dma_device.cap_mask; 725026fd406SAlex Smith struct jz4780_dma_filter_data data; 726d894fc60SAlex Smith 727d894fc60SAlex Smith if (dma_spec->args_count != 2) 728d894fc60SAlex Smith return NULL; 729d894fc60SAlex Smith 730026fd406SAlex Smith data.of_node = ofdma->of_node; 731d894fc60SAlex Smith data.transfer_type = dma_spec->args[0]; 732d894fc60SAlex Smith data.channel = dma_spec->args[1]; 733d894fc60SAlex Smith 734d894fc60SAlex Smith if (data.channel > -1) { 7356147b032SPaul Cercueil if (data.channel >= jzdma->soc_data->nb_channels) { 736d894fc60SAlex Smith dev_err(jzdma->dma_device.dev, 737d894fc60SAlex Smith "device requested non-existent channel %u\n", 738d894fc60SAlex Smith data.channel); 739d894fc60SAlex Smith return NULL; 740d894fc60SAlex Smith } 741d894fc60SAlex Smith 742d894fc60SAlex Smith /* Can only select a channel marked as reserved. */ 743d894fc60SAlex Smith if (!(jzdma->chan_reserved & BIT(data.channel))) { 744d894fc60SAlex Smith dev_err(jzdma->dma_device.dev, 745d894fc60SAlex Smith "device requested unreserved channel %u\n", 746d894fc60SAlex Smith data.channel); 747d894fc60SAlex Smith return NULL; 748d894fc60SAlex Smith } 749d894fc60SAlex Smith 750d3273e10SAlex Smith jzdma->chan[data.channel].transfer_type = data.transfer_type; 751d3273e10SAlex Smith 752d3273e10SAlex Smith return dma_get_slave_channel( 753d3273e10SAlex Smith &jzdma->chan[data.channel].vchan.chan); 754d3273e10SAlex Smith } else { 755d894fc60SAlex Smith return dma_request_channel(mask, jz4780_dma_filter_fn, &data); 756d894fc60SAlex Smith } 757d3273e10SAlex Smith } 758d894fc60SAlex Smith 759d894fc60SAlex Smith static int jz4780_dma_probe(struct platform_device *pdev) 760d894fc60SAlex Smith { 761d894fc60SAlex Smith struct device *dev = &pdev->dev; 7626147b032SPaul Cercueil const struct jz4780_dma_soc_data *soc_data; 763d894fc60SAlex Smith struct jz4780_dma_dev *jzdma; 764d894fc60SAlex Smith struct jz4780_dma_chan *jzchan; 765d894fc60SAlex Smith struct dma_device *dd; 766d894fc60SAlex Smith struct resource *res; 767d894fc60SAlex Smith int i, ret; 768d894fc60SAlex Smith 76954f919a0SPaul Cercueil if (!dev->of_node) { 77054f919a0SPaul Cercueil dev_err(dev, "This driver must be probed from devicetree\n"); 77154f919a0SPaul Cercueil return -EINVAL; 77254f919a0SPaul Cercueil } 77354f919a0SPaul Cercueil 7746147b032SPaul Cercueil soc_data = device_get_match_data(dev); 7756147b032SPaul Cercueil if (!soc_data) 7766147b032SPaul Cercueil return -EINVAL; 7776147b032SPaul Cercueil 7786147b032SPaul Cercueil jzdma = devm_kzalloc(dev, sizeof(*jzdma) 7796147b032SPaul Cercueil + sizeof(*jzdma->chan) * soc_data->nb_channels, 7806147b032SPaul Cercueil GFP_KERNEL); 781d894fc60SAlex Smith if (!jzdma) 782d894fc60SAlex Smith return -ENOMEM; 783d894fc60SAlex Smith 7846147b032SPaul Cercueil jzdma->soc_data = soc_data; 785d894fc60SAlex Smith platform_set_drvdata(pdev, jzdma); 786d894fc60SAlex Smith 787d894fc60SAlex Smith res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 788d894fc60SAlex Smith if (!res) { 789d894fc60SAlex Smith dev_err(dev, "failed to get I/O memory\n"); 790d894fc60SAlex Smith return -EINVAL; 791d894fc60SAlex Smith } 792d894fc60SAlex Smith 793d894fc60SAlex Smith jzdma->base = devm_ioremap_resource(dev, res); 794d894fc60SAlex Smith if (IS_ERR(jzdma->base)) 795d894fc60SAlex Smith return PTR_ERR(jzdma->base); 796d894fc60SAlex Smith 797839896efSAlex Smith ret = platform_get_irq(pdev, 0); 798839896efSAlex Smith if (ret < 0) { 799d894fc60SAlex Smith dev_err(dev, "failed to get IRQ: %d\n", ret); 800839896efSAlex Smith return ret; 801d894fc60SAlex Smith } 802d894fc60SAlex Smith 803839896efSAlex Smith jzdma->irq = ret; 804839896efSAlex Smith 805d509a83cSAlex Smith ret = request_irq(jzdma->irq, jz4780_dma_irq_handler, 0, dev_name(dev), 806d509a83cSAlex Smith jzdma); 807d894fc60SAlex Smith if (ret) { 808d894fc60SAlex Smith dev_err(dev, "failed to request IRQ %u!\n", jzdma->irq); 809839896efSAlex Smith return ret; 810d894fc60SAlex Smith } 811d894fc60SAlex Smith 812d894fc60SAlex Smith jzdma->clk = devm_clk_get(dev, NULL); 813d894fc60SAlex Smith if (IS_ERR(jzdma->clk)) { 814d894fc60SAlex Smith dev_err(dev, "failed to get clock\n"); 815d509a83cSAlex Smith ret = PTR_ERR(jzdma->clk); 816d509a83cSAlex Smith goto err_free_irq; 817d894fc60SAlex Smith } 818d894fc60SAlex Smith 819d894fc60SAlex Smith clk_prepare_enable(jzdma->clk); 820d894fc60SAlex Smith 821d894fc60SAlex Smith /* Property is optional, if it doesn't exist the value will remain 0. */ 822d894fc60SAlex Smith of_property_read_u32_index(dev->of_node, "ingenic,reserved-channels", 823d894fc60SAlex Smith 0, &jzdma->chan_reserved); 824d894fc60SAlex Smith 825d894fc60SAlex Smith dd = &jzdma->dma_device; 826d894fc60SAlex Smith 827d894fc60SAlex Smith dma_cap_set(DMA_MEMCPY, dd->cap_mask); 828d894fc60SAlex Smith dma_cap_set(DMA_SLAVE, dd->cap_mask); 829d894fc60SAlex Smith dma_cap_set(DMA_CYCLIC, dd->cap_mask); 830d894fc60SAlex Smith 831d894fc60SAlex Smith dd->dev = dev; 83277a68e56SMaxime Ripard dd->copy_align = DMAENGINE_ALIGN_4_BYTES; 833d894fc60SAlex Smith dd->device_alloc_chan_resources = jz4780_dma_alloc_chan_resources; 834d894fc60SAlex Smith dd->device_free_chan_resources = jz4780_dma_free_chan_resources; 835d894fc60SAlex Smith dd->device_prep_slave_sg = jz4780_dma_prep_slave_sg; 836d894fc60SAlex Smith dd->device_prep_dma_cyclic = jz4780_dma_prep_dma_cyclic; 837d894fc60SAlex Smith dd->device_prep_dma_memcpy = jz4780_dma_prep_dma_memcpy; 83846fa5168SAlex Smith dd->device_config = jz4780_dma_config; 839d894fc60SAlex Smith dd->device_terminate_all = jz4780_dma_terminate_all; 840f0dd52c8SPeter Ujfalusi dd->device_synchronize = jz4780_dma_synchronize; 841d894fc60SAlex Smith dd->device_tx_status = jz4780_dma_tx_status; 842d894fc60SAlex Smith dd->device_issue_pending = jz4780_dma_issue_pending; 843d894fc60SAlex Smith dd->src_addr_widths = JZ_DMA_BUSWIDTHS; 844d894fc60SAlex Smith dd->dst_addr_widths = JZ_DMA_BUSWIDTHS; 845d894fc60SAlex Smith dd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); 846d894fc60SAlex Smith dd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; 847d894fc60SAlex Smith 848d894fc60SAlex Smith /* 849d894fc60SAlex Smith * Enable DMA controller, mark all channels as not programmable. 850d894fc60SAlex Smith * Also set the FMSC bit - it increases MSC performance, so it makes 851d894fc60SAlex Smith * little sense not to enable it. 852d894fc60SAlex Smith */ 853d894fc60SAlex Smith jz4780_dma_writel(jzdma, JZ_DMA_REG_DMAC, 854d894fc60SAlex Smith JZ_DMA_DMAC_DMAE | JZ_DMA_DMAC_FMSC); 855d894fc60SAlex Smith jz4780_dma_writel(jzdma, JZ_DMA_REG_DMACP, 0); 856d894fc60SAlex Smith 857d894fc60SAlex Smith INIT_LIST_HEAD(&dd->channels); 858d894fc60SAlex Smith 8596147b032SPaul Cercueil for (i = 0; i < soc_data->nb_channels; i++) { 860d894fc60SAlex Smith jzchan = &jzdma->chan[i]; 861d894fc60SAlex Smith jzchan->id = i; 862d894fc60SAlex Smith 863d894fc60SAlex Smith vchan_init(&jzchan->vchan, dd); 864d894fc60SAlex Smith jzchan->vchan.desc_free = jz4780_dma_desc_free; 865d894fc60SAlex Smith } 866d894fc60SAlex Smith 867d894fc60SAlex Smith ret = dma_async_device_register(dd); 868d894fc60SAlex Smith if (ret) { 869d894fc60SAlex Smith dev_err(dev, "failed to register device\n"); 870d894fc60SAlex Smith goto err_disable_clk; 871d894fc60SAlex Smith } 872d894fc60SAlex Smith 873d894fc60SAlex Smith /* Register with OF DMA helpers. */ 874d894fc60SAlex Smith ret = of_dma_controller_register(dev->of_node, jz4780_of_dma_xlate, 875d894fc60SAlex Smith jzdma); 876d894fc60SAlex Smith if (ret) { 877d894fc60SAlex Smith dev_err(dev, "failed to register OF DMA controller\n"); 878d894fc60SAlex Smith goto err_unregister_dev; 879d894fc60SAlex Smith } 880d894fc60SAlex Smith 881d894fc60SAlex Smith dev_info(dev, "JZ4780 DMA controller initialised\n"); 882d894fc60SAlex Smith return 0; 883d894fc60SAlex Smith 884d894fc60SAlex Smith err_unregister_dev: 885d894fc60SAlex Smith dma_async_device_unregister(dd); 886d894fc60SAlex Smith 887d894fc60SAlex Smith err_disable_clk: 888d894fc60SAlex Smith clk_disable_unprepare(jzdma->clk); 889d509a83cSAlex Smith 890d509a83cSAlex Smith err_free_irq: 891d509a83cSAlex Smith free_irq(jzdma->irq, jzdma); 892d894fc60SAlex Smith return ret; 893d894fc60SAlex Smith } 894d894fc60SAlex Smith 895d894fc60SAlex Smith static int jz4780_dma_remove(struct platform_device *pdev) 896d894fc60SAlex Smith { 897d894fc60SAlex Smith struct jz4780_dma_dev *jzdma = platform_get_drvdata(pdev); 898ae9c02b4SAlex Smith int i; 899d894fc60SAlex Smith 900d894fc60SAlex Smith of_dma_controller_free(pdev->dev.of_node); 901ae9c02b4SAlex Smith 902d509a83cSAlex Smith free_irq(jzdma->irq, jzdma); 903ae9c02b4SAlex Smith 9046147b032SPaul Cercueil for (i = 0; i < jzdma->soc_data->nb_channels; i++) 905ae9c02b4SAlex Smith tasklet_kill(&jzdma->chan[i].vchan.task); 906ae9c02b4SAlex Smith 907d894fc60SAlex Smith dma_async_device_unregister(&jzdma->dma_device); 908d894fc60SAlex Smith return 0; 909d894fc60SAlex Smith } 910d894fc60SAlex Smith 9116147b032SPaul Cercueil static const struct jz4780_dma_soc_data jz4780_dma_soc_data = { 9126147b032SPaul Cercueil .nb_channels = 32, 9136147b032SPaul Cercueil }; 9146147b032SPaul Cercueil 915d894fc60SAlex Smith static const struct of_device_id jz4780_dma_dt_match[] = { 9166147b032SPaul Cercueil { .compatible = "ingenic,jz4780-dma", .data = &jz4780_dma_soc_data }, 917d894fc60SAlex Smith {}, 918d894fc60SAlex Smith }; 919d894fc60SAlex Smith MODULE_DEVICE_TABLE(of, jz4780_dma_dt_match); 920d894fc60SAlex Smith 921d894fc60SAlex Smith static struct platform_driver jz4780_dma_driver = { 922d894fc60SAlex Smith .probe = jz4780_dma_probe, 923d894fc60SAlex Smith .remove = jz4780_dma_remove, 924d894fc60SAlex Smith .driver = { 925d894fc60SAlex Smith .name = "jz4780-dma", 926d894fc60SAlex Smith .of_match_table = of_match_ptr(jz4780_dma_dt_match), 927d894fc60SAlex Smith }, 928d894fc60SAlex Smith }; 929d894fc60SAlex Smith 930d894fc60SAlex Smith static int __init jz4780_dma_init(void) 931d894fc60SAlex Smith { 932d894fc60SAlex Smith return platform_driver_register(&jz4780_dma_driver); 933d894fc60SAlex Smith } 934d894fc60SAlex Smith subsys_initcall(jz4780_dma_init); 935d894fc60SAlex Smith 936d894fc60SAlex Smith static void __exit jz4780_dma_exit(void) 937d894fc60SAlex Smith { 938d894fc60SAlex Smith platform_driver_unregister(&jz4780_dma_driver); 939d894fc60SAlex Smith } 940d894fc60SAlex Smith module_exit(jz4780_dma_exit); 941d894fc60SAlex Smith 942d894fc60SAlex Smith MODULE_AUTHOR("Alex Smith <alex@alex-smith.me.uk>"); 943d894fc60SAlex Smith MODULE_DESCRIPTION("Ingenic JZ4780 DMA controller driver"); 944d894fc60SAlex Smith MODULE_LICENSE("GPL"); 945