1d894fc60SAlex Smith /* 2d894fc60SAlex Smith * Ingenic JZ4780 DMA controller 3d894fc60SAlex Smith * 4d894fc60SAlex Smith * Copyright (c) 2015 Imagination Technologies 5d894fc60SAlex Smith * Author: Alex Smith <alex@alex-smith.me.uk> 6d894fc60SAlex Smith * 7d894fc60SAlex Smith * This program is free software; you can redistribute it and/or modify it 8d894fc60SAlex Smith * under the terms of the GNU General Public License as published by the 9d894fc60SAlex Smith * Free Software Foundation; either version 2 of the License, or (at your 10d894fc60SAlex Smith * option) any later version. 11d894fc60SAlex Smith */ 12d894fc60SAlex Smith 13d894fc60SAlex Smith #include <linux/clk.h> 14d894fc60SAlex Smith #include <linux/dmapool.h> 15d894fc60SAlex Smith #include <linux/init.h> 16d894fc60SAlex Smith #include <linux/interrupt.h> 17d894fc60SAlex Smith #include <linux/module.h> 18d894fc60SAlex Smith #include <linux/of.h> 19d894fc60SAlex Smith #include <linux/of_dma.h> 20d894fc60SAlex Smith #include <linux/platform_device.h> 21d894fc60SAlex Smith #include <linux/slab.h> 22d894fc60SAlex Smith 23d894fc60SAlex Smith #include "dmaengine.h" 24d894fc60SAlex Smith #include "virt-dma.h" 25d894fc60SAlex Smith 26d894fc60SAlex Smith #define JZ_DMA_NR_CHANNELS 32 27d894fc60SAlex Smith 28d894fc60SAlex Smith /* Global registers. */ 29d894fc60SAlex Smith #define JZ_DMA_REG_DMAC 0x1000 30d894fc60SAlex Smith #define JZ_DMA_REG_DIRQP 0x1004 31d894fc60SAlex Smith #define JZ_DMA_REG_DDR 0x1008 32d894fc60SAlex Smith #define JZ_DMA_REG_DDRS 0x100c 33d894fc60SAlex Smith #define JZ_DMA_REG_DMACP 0x101c 34d894fc60SAlex Smith #define JZ_DMA_REG_DSIRQP 0x1020 35d894fc60SAlex Smith #define JZ_DMA_REG_DSIRQM 0x1024 36d894fc60SAlex Smith #define JZ_DMA_REG_DCIRQP 0x1028 37d894fc60SAlex Smith #define JZ_DMA_REG_DCIRQM 0x102c 38d894fc60SAlex Smith 39d894fc60SAlex Smith /* Per-channel registers. */ 40d894fc60SAlex Smith #define JZ_DMA_REG_CHAN(n) (n * 0x20) 41d894fc60SAlex Smith #define JZ_DMA_REG_DSA(n) (0x00 + JZ_DMA_REG_CHAN(n)) 42d894fc60SAlex Smith #define JZ_DMA_REG_DTA(n) (0x04 + JZ_DMA_REG_CHAN(n)) 43d894fc60SAlex Smith #define JZ_DMA_REG_DTC(n) (0x08 + JZ_DMA_REG_CHAN(n)) 44d894fc60SAlex Smith #define JZ_DMA_REG_DRT(n) (0x0c + JZ_DMA_REG_CHAN(n)) 45d894fc60SAlex Smith #define JZ_DMA_REG_DCS(n) (0x10 + JZ_DMA_REG_CHAN(n)) 46d894fc60SAlex Smith #define JZ_DMA_REG_DCM(n) (0x14 + JZ_DMA_REG_CHAN(n)) 47d894fc60SAlex Smith #define JZ_DMA_REG_DDA(n) (0x18 + JZ_DMA_REG_CHAN(n)) 48d894fc60SAlex Smith #define JZ_DMA_REG_DSD(n) (0x1c + JZ_DMA_REG_CHAN(n)) 49d894fc60SAlex Smith 50d894fc60SAlex Smith #define JZ_DMA_DMAC_DMAE BIT(0) 51d894fc60SAlex Smith #define JZ_DMA_DMAC_AR BIT(2) 52d894fc60SAlex Smith #define JZ_DMA_DMAC_HLT BIT(3) 53d894fc60SAlex Smith #define JZ_DMA_DMAC_FMSC BIT(31) 54d894fc60SAlex Smith 55d894fc60SAlex Smith #define JZ_DMA_DRT_AUTO 0x8 56d894fc60SAlex Smith 57d894fc60SAlex Smith #define JZ_DMA_DCS_CTE BIT(0) 58d894fc60SAlex Smith #define JZ_DMA_DCS_HLT BIT(2) 59d894fc60SAlex Smith #define JZ_DMA_DCS_TT BIT(3) 60d894fc60SAlex Smith #define JZ_DMA_DCS_AR BIT(4) 61d894fc60SAlex Smith #define JZ_DMA_DCS_DES8 BIT(30) 62d894fc60SAlex Smith 63d894fc60SAlex Smith #define JZ_DMA_DCM_LINK BIT(0) 64d894fc60SAlex Smith #define JZ_DMA_DCM_TIE BIT(1) 65d894fc60SAlex Smith #define JZ_DMA_DCM_STDE BIT(2) 66d894fc60SAlex Smith #define JZ_DMA_DCM_TSZ_SHIFT 8 67d894fc60SAlex Smith #define JZ_DMA_DCM_TSZ_MASK (0x7 << JZ_DMA_DCM_TSZ_SHIFT) 68d894fc60SAlex Smith #define JZ_DMA_DCM_DP_SHIFT 12 69d894fc60SAlex Smith #define JZ_DMA_DCM_SP_SHIFT 14 70d894fc60SAlex Smith #define JZ_DMA_DCM_DAI BIT(22) 71d894fc60SAlex Smith #define JZ_DMA_DCM_SAI BIT(23) 72d894fc60SAlex Smith 73d894fc60SAlex Smith #define JZ_DMA_SIZE_4_BYTE 0x0 74d894fc60SAlex Smith #define JZ_DMA_SIZE_1_BYTE 0x1 75d894fc60SAlex Smith #define JZ_DMA_SIZE_2_BYTE 0x2 76d894fc60SAlex Smith #define JZ_DMA_SIZE_16_BYTE 0x3 77d894fc60SAlex Smith #define JZ_DMA_SIZE_32_BYTE 0x4 78d894fc60SAlex Smith #define JZ_DMA_SIZE_64_BYTE 0x5 79d894fc60SAlex Smith #define JZ_DMA_SIZE_128_BYTE 0x6 80d894fc60SAlex Smith 81d894fc60SAlex Smith #define JZ_DMA_WIDTH_32_BIT 0x0 82d894fc60SAlex Smith #define JZ_DMA_WIDTH_8_BIT 0x1 83d894fc60SAlex Smith #define JZ_DMA_WIDTH_16_BIT 0x2 84d894fc60SAlex Smith 85d894fc60SAlex Smith #define JZ_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \ 86d894fc60SAlex Smith BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \ 87d894fc60SAlex Smith BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)) 88d894fc60SAlex Smith 89d894fc60SAlex Smith /** 90d894fc60SAlex Smith * struct jz4780_dma_hwdesc - descriptor structure read by the DMA controller. 91d894fc60SAlex Smith * @dcm: value for the DCM (channel command) register 92d894fc60SAlex Smith * @dsa: source address 93d894fc60SAlex Smith * @dta: target address 94d894fc60SAlex Smith * @dtc: transfer count (number of blocks of the transfer size specified in DCM 95d894fc60SAlex Smith * to transfer) in the low 24 bits, offset of the next descriptor from the 96d894fc60SAlex Smith * descriptor base address in the upper 8 bits. 97d894fc60SAlex Smith * @sd: target/source stride difference (in stride transfer mode). 98d894fc60SAlex Smith * @drt: request type 99d894fc60SAlex Smith */ 100d894fc60SAlex Smith struct jz4780_dma_hwdesc { 101d894fc60SAlex Smith uint32_t dcm; 102d894fc60SAlex Smith uint32_t dsa; 103d894fc60SAlex Smith uint32_t dta; 104d894fc60SAlex Smith uint32_t dtc; 105d894fc60SAlex Smith uint32_t sd; 106d894fc60SAlex Smith uint32_t drt; 107d894fc60SAlex Smith uint32_t reserved[2]; 108d894fc60SAlex Smith }; 109d894fc60SAlex Smith 110d894fc60SAlex Smith /* Size of allocations for hardware descriptor blocks. */ 111d894fc60SAlex Smith #define JZ_DMA_DESC_BLOCK_SIZE PAGE_SIZE 112d894fc60SAlex Smith #define JZ_DMA_MAX_DESC \ 113d894fc60SAlex Smith (JZ_DMA_DESC_BLOCK_SIZE / sizeof(struct jz4780_dma_hwdesc)) 114d894fc60SAlex Smith 115d894fc60SAlex Smith struct jz4780_dma_desc { 116d894fc60SAlex Smith struct virt_dma_desc vdesc; 117d894fc60SAlex Smith 118d894fc60SAlex Smith struct jz4780_dma_hwdesc *desc; 119d894fc60SAlex Smith dma_addr_t desc_phys; 120d894fc60SAlex Smith unsigned int count; 121d894fc60SAlex Smith enum dma_transaction_type type; 122d894fc60SAlex Smith uint32_t status; 123d894fc60SAlex Smith }; 124d894fc60SAlex Smith 125d894fc60SAlex Smith struct jz4780_dma_chan { 126d894fc60SAlex Smith struct virt_dma_chan vchan; 127d894fc60SAlex Smith unsigned int id; 128d894fc60SAlex Smith struct dma_pool *desc_pool; 129d894fc60SAlex Smith 130d894fc60SAlex Smith uint32_t transfer_type; 131d894fc60SAlex Smith uint32_t transfer_shift; 132d894fc60SAlex Smith struct dma_slave_config config; 133d894fc60SAlex Smith 134d894fc60SAlex Smith struct jz4780_dma_desc *desc; 135d894fc60SAlex Smith unsigned int curr_hwdesc; 136d894fc60SAlex Smith }; 137d894fc60SAlex Smith 138d894fc60SAlex Smith struct jz4780_dma_dev { 139d894fc60SAlex Smith struct dma_device dma_device; 140d894fc60SAlex Smith void __iomem *base; 141d894fc60SAlex Smith struct clk *clk; 142d894fc60SAlex Smith unsigned int irq; 143d894fc60SAlex Smith 144d894fc60SAlex Smith uint32_t chan_reserved; 145d894fc60SAlex Smith struct jz4780_dma_chan chan[JZ_DMA_NR_CHANNELS]; 146d894fc60SAlex Smith }; 147d894fc60SAlex Smith 148026fd406SAlex Smith struct jz4780_dma_filter_data { 149026fd406SAlex Smith struct device_node *of_node; 150d894fc60SAlex Smith uint32_t transfer_type; 151d894fc60SAlex Smith int channel; 152d894fc60SAlex Smith }; 153d894fc60SAlex Smith 154d894fc60SAlex Smith static inline struct jz4780_dma_chan *to_jz4780_dma_chan(struct dma_chan *chan) 155d894fc60SAlex Smith { 156d894fc60SAlex Smith return container_of(chan, struct jz4780_dma_chan, vchan.chan); 157d894fc60SAlex Smith } 158d894fc60SAlex Smith 159d894fc60SAlex Smith static inline struct jz4780_dma_desc *to_jz4780_dma_desc( 160d894fc60SAlex Smith struct virt_dma_desc *vdesc) 161d894fc60SAlex Smith { 162d894fc60SAlex Smith return container_of(vdesc, struct jz4780_dma_desc, vdesc); 163d894fc60SAlex Smith } 164d894fc60SAlex Smith 165d894fc60SAlex Smith static inline struct jz4780_dma_dev *jz4780_dma_chan_parent( 166d894fc60SAlex Smith struct jz4780_dma_chan *jzchan) 167d894fc60SAlex Smith { 168d894fc60SAlex Smith return container_of(jzchan->vchan.chan.device, struct jz4780_dma_dev, 169d894fc60SAlex Smith dma_device); 170d894fc60SAlex Smith } 171d894fc60SAlex Smith 172d894fc60SAlex Smith static inline uint32_t jz4780_dma_readl(struct jz4780_dma_dev *jzdma, 173d894fc60SAlex Smith unsigned int reg) 174d894fc60SAlex Smith { 175d894fc60SAlex Smith return readl(jzdma->base + reg); 176d894fc60SAlex Smith } 177d894fc60SAlex Smith 178d894fc60SAlex Smith static inline void jz4780_dma_writel(struct jz4780_dma_dev *jzdma, 179d894fc60SAlex Smith unsigned int reg, uint32_t val) 180d894fc60SAlex Smith { 181d894fc60SAlex Smith writel(val, jzdma->base + reg); 182d894fc60SAlex Smith } 183d894fc60SAlex Smith 184d894fc60SAlex Smith static struct jz4780_dma_desc *jz4780_dma_desc_alloc( 185d894fc60SAlex Smith struct jz4780_dma_chan *jzchan, unsigned int count, 186d894fc60SAlex Smith enum dma_transaction_type type) 187d894fc60SAlex Smith { 188d894fc60SAlex Smith struct jz4780_dma_desc *desc; 189d894fc60SAlex Smith 190d894fc60SAlex Smith if (count > JZ_DMA_MAX_DESC) 191d894fc60SAlex Smith return NULL; 192d894fc60SAlex Smith 193d894fc60SAlex Smith desc = kzalloc(sizeof(*desc), GFP_NOWAIT); 194d894fc60SAlex Smith if (!desc) 195d894fc60SAlex Smith return NULL; 196d894fc60SAlex Smith 197d894fc60SAlex Smith desc->desc = dma_pool_alloc(jzchan->desc_pool, GFP_NOWAIT, 198d894fc60SAlex Smith &desc->desc_phys); 199d894fc60SAlex Smith if (!desc->desc) { 200d894fc60SAlex Smith kfree(desc); 201d894fc60SAlex Smith return NULL; 202d894fc60SAlex Smith } 203d894fc60SAlex Smith 204d894fc60SAlex Smith desc->count = count; 205d894fc60SAlex Smith desc->type = type; 206d894fc60SAlex Smith return desc; 207d894fc60SAlex Smith } 208d894fc60SAlex Smith 209d894fc60SAlex Smith static void jz4780_dma_desc_free(struct virt_dma_desc *vdesc) 210d894fc60SAlex Smith { 211d894fc60SAlex Smith struct jz4780_dma_desc *desc = to_jz4780_dma_desc(vdesc); 212d894fc60SAlex Smith struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(vdesc->tx.chan); 213d894fc60SAlex Smith 214d894fc60SAlex Smith dma_pool_free(jzchan->desc_pool, desc->desc, desc->desc_phys); 215d894fc60SAlex Smith kfree(desc); 216d894fc60SAlex Smith } 217d894fc60SAlex Smith 218dc578f31SAlex Smith static uint32_t jz4780_dma_transfer_size(unsigned long val, uint32_t *shift) 219d894fc60SAlex Smith { 220dc578f31SAlex Smith int ord = ffs(val) - 1; 221d894fc60SAlex Smith 222dc578f31SAlex Smith /* 223dc578f31SAlex Smith * 8 byte transfer sizes unsupported so fall back on 4. If it's larger 224dc578f31SAlex Smith * than the maximum, just limit it. It is perfectly safe to fall back 225dc578f31SAlex Smith * in this way since we won't exceed the maximum burst size supported 226dc578f31SAlex Smith * by the device, the only effect is reduced efficiency. This is better 227dc578f31SAlex Smith * than refusing to perform the request at all. 228dc578f31SAlex Smith */ 229dc578f31SAlex Smith if (ord == 3) 230dc578f31SAlex Smith ord = 2; 231dc578f31SAlex Smith else if (ord > 7) 232dc578f31SAlex Smith ord = 7; 233dc578f31SAlex Smith 234dc578f31SAlex Smith *shift = ord; 235dc578f31SAlex Smith 236dc578f31SAlex Smith switch (ord) { 237d894fc60SAlex Smith case 0: 238d894fc60SAlex Smith return JZ_DMA_SIZE_1_BYTE; 239d894fc60SAlex Smith case 1: 240d894fc60SAlex Smith return JZ_DMA_SIZE_2_BYTE; 241d894fc60SAlex Smith case 2: 242d894fc60SAlex Smith return JZ_DMA_SIZE_4_BYTE; 243d894fc60SAlex Smith case 4: 244d894fc60SAlex Smith return JZ_DMA_SIZE_16_BYTE; 245d894fc60SAlex Smith case 5: 246d894fc60SAlex Smith return JZ_DMA_SIZE_32_BYTE; 247d894fc60SAlex Smith case 6: 248d894fc60SAlex Smith return JZ_DMA_SIZE_64_BYTE; 249d894fc60SAlex Smith default: 250dc578f31SAlex Smith return JZ_DMA_SIZE_128_BYTE; 251d894fc60SAlex Smith } 252d894fc60SAlex Smith } 253d894fc60SAlex Smith 254839896efSAlex Smith static int jz4780_dma_setup_hwdesc(struct jz4780_dma_chan *jzchan, 255d894fc60SAlex Smith struct jz4780_dma_hwdesc *desc, dma_addr_t addr, size_t len, 256d894fc60SAlex Smith enum dma_transfer_direction direction) 257d894fc60SAlex Smith { 258d894fc60SAlex Smith struct dma_slave_config *config = &jzchan->config; 259d894fc60SAlex Smith uint32_t width, maxburst, tsz; 260d894fc60SAlex Smith 261d894fc60SAlex Smith if (direction == DMA_MEM_TO_DEV) { 262d894fc60SAlex Smith desc->dcm = JZ_DMA_DCM_SAI; 263d894fc60SAlex Smith desc->dsa = addr; 264d894fc60SAlex Smith desc->dta = config->dst_addr; 265d894fc60SAlex Smith desc->drt = jzchan->transfer_type; 266d894fc60SAlex Smith 267d894fc60SAlex Smith width = config->dst_addr_width; 268d894fc60SAlex Smith maxburst = config->dst_maxburst; 269d894fc60SAlex Smith } else { 270d894fc60SAlex Smith desc->dcm = JZ_DMA_DCM_DAI; 271d894fc60SAlex Smith desc->dsa = config->src_addr; 272d894fc60SAlex Smith desc->dta = addr; 273d894fc60SAlex Smith desc->drt = jzchan->transfer_type; 274d894fc60SAlex Smith 275d894fc60SAlex Smith width = config->src_addr_width; 276d894fc60SAlex Smith maxburst = config->src_maxburst; 277d894fc60SAlex Smith } 278d894fc60SAlex Smith 279d894fc60SAlex Smith /* 280d894fc60SAlex Smith * This calculates the maximum transfer size that can be used with the 281d894fc60SAlex Smith * given address, length, width and maximum burst size. The address 282d894fc60SAlex Smith * must be aligned to the transfer size, the total length must be 283d894fc60SAlex Smith * divisible by the transfer size, and we must not use more than the 284d894fc60SAlex Smith * maximum burst specified by the user. 285d894fc60SAlex Smith */ 286dc578f31SAlex Smith tsz = jz4780_dma_transfer_size(addr | len | (width * maxburst), 287dc578f31SAlex Smith &jzchan->transfer_shift); 288d894fc60SAlex Smith 289d894fc60SAlex Smith switch (width) { 290d894fc60SAlex Smith case DMA_SLAVE_BUSWIDTH_1_BYTE: 291d894fc60SAlex Smith case DMA_SLAVE_BUSWIDTH_2_BYTES: 292d894fc60SAlex Smith break; 293d894fc60SAlex Smith case DMA_SLAVE_BUSWIDTH_4_BYTES: 294d894fc60SAlex Smith width = JZ_DMA_WIDTH_32_BIT; 295d894fc60SAlex Smith break; 296d894fc60SAlex Smith default: 297d894fc60SAlex Smith return -EINVAL; 298d894fc60SAlex Smith } 299d894fc60SAlex Smith 300d894fc60SAlex Smith desc->dcm |= tsz << JZ_DMA_DCM_TSZ_SHIFT; 301d894fc60SAlex Smith desc->dcm |= width << JZ_DMA_DCM_SP_SHIFT; 302d894fc60SAlex Smith desc->dcm |= width << JZ_DMA_DCM_DP_SHIFT; 303d894fc60SAlex Smith 304dc578f31SAlex Smith desc->dtc = len >> jzchan->transfer_shift; 305839896efSAlex Smith return 0; 306d894fc60SAlex Smith } 307d894fc60SAlex Smith 308d894fc60SAlex Smith static struct dma_async_tx_descriptor *jz4780_dma_prep_slave_sg( 309d894fc60SAlex Smith struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len, 31046fa5168SAlex Smith enum dma_transfer_direction direction, unsigned long flags, 31146fa5168SAlex Smith void *context) 312d894fc60SAlex Smith { 313d894fc60SAlex Smith struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan); 314d894fc60SAlex Smith struct jz4780_dma_desc *desc; 315d894fc60SAlex Smith unsigned int i; 316d894fc60SAlex Smith int err; 317d894fc60SAlex Smith 318d894fc60SAlex Smith desc = jz4780_dma_desc_alloc(jzchan, sg_len, DMA_SLAVE); 319d894fc60SAlex Smith if (!desc) 320d894fc60SAlex Smith return NULL; 321d894fc60SAlex Smith 322d894fc60SAlex Smith for (i = 0; i < sg_len; i++) { 323d894fc60SAlex Smith err = jz4780_dma_setup_hwdesc(jzchan, &desc->desc[i], 324d894fc60SAlex Smith sg_dma_address(&sgl[i]), 325d894fc60SAlex Smith sg_dma_len(&sgl[i]), 326d894fc60SAlex Smith direction); 327fc878efeSColin Ian King if (err < 0) { 328fc878efeSColin Ian King jz4780_dma_desc_free(&jzchan->desc->vdesc); 329839896efSAlex Smith return NULL; 330fc878efeSColin Ian King } 331d894fc60SAlex Smith 332d894fc60SAlex Smith desc->desc[i].dcm |= JZ_DMA_DCM_TIE; 333d894fc60SAlex Smith 334d894fc60SAlex Smith if (i != (sg_len - 1)) { 335d894fc60SAlex Smith /* Automatically proceeed to the next descriptor. */ 336d894fc60SAlex Smith desc->desc[i].dcm |= JZ_DMA_DCM_LINK; 337d894fc60SAlex Smith 338d894fc60SAlex Smith /* 339d894fc60SAlex Smith * The upper 8 bits of the DTC field in the descriptor 340d894fc60SAlex Smith * must be set to (offset from descriptor base of next 341d894fc60SAlex Smith * descriptor >> 4). 342d894fc60SAlex Smith */ 343d894fc60SAlex Smith desc->desc[i].dtc |= 344d894fc60SAlex Smith (((i + 1) * sizeof(*desc->desc)) >> 4) << 24; 345d894fc60SAlex Smith } 346d894fc60SAlex Smith } 347d894fc60SAlex Smith 348d894fc60SAlex Smith return vchan_tx_prep(&jzchan->vchan, &desc->vdesc, flags); 349d894fc60SAlex Smith } 350d894fc60SAlex Smith 351d894fc60SAlex Smith static struct dma_async_tx_descriptor *jz4780_dma_prep_dma_cyclic( 352d894fc60SAlex Smith struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, 353d894fc60SAlex Smith size_t period_len, enum dma_transfer_direction direction, 354d894fc60SAlex Smith unsigned long flags) 355d894fc60SAlex Smith { 356d894fc60SAlex Smith struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan); 357d894fc60SAlex Smith struct jz4780_dma_desc *desc; 358d894fc60SAlex Smith unsigned int periods, i; 359d894fc60SAlex Smith int err; 360d894fc60SAlex Smith 361d894fc60SAlex Smith if (buf_len % period_len) 362d894fc60SAlex Smith return NULL; 363d894fc60SAlex Smith 364d894fc60SAlex Smith periods = buf_len / period_len; 365d894fc60SAlex Smith 366d894fc60SAlex Smith desc = jz4780_dma_desc_alloc(jzchan, periods, DMA_CYCLIC); 367d894fc60SAlex Smith if (!desc) 368d894fc60SAlex Smith return NULL; 369d894fc60SAlex Smith 370d894fc60SAlex Smith for (i = 0; i < periods; i++) { 371d894fc60SAlex Smith err = jz4780_dma_setup_hwdesc(jzchan, &desc->desc[i], buf_addr, 372d894fc60SAlex Smith period_len, direction); 373fc878efeSColin Ian King if (err < 0) { 374fc878efeSColin Ian King jz4780_dma_desc_free(&jzchan->desc->vdesc); 375839896efSAlex Smith return NULL; 376fc878efeSColin Ian King } 377d894fc60SAlex Smith 378d894fc60SAlex Smith buf_addr += period_len; 379d894fc60SAlex Smith 380d894fc60SAlex Smith /* 381d894fc60SAlex Smith * Set the link bit to indicate that the controller should 382d894fc60SAlex Smith * automatically proceed to the next descriptor. In 383d894fc60SAlex Smith * jz4780_dma_begin(), this will be cleared if we need to issue 384d894fc60SAlex Smith * an interrupt after each period. 385d894fc60SAlex Smith */ 386d894fc60SAlex Smith desc->desc[i].dcm |= JZ_DMA_DCM_TIE | JZ_DMA_DCM_LINK; 387d894fc60SAlex Smith 388d894fc60SAlex Smith /* 389d894fc60SAlex Smith * The upper 8 bits of the DTC field in the descriptor must be 390d894fc60SAlex Smith * set to (offset from descriptor base of next descriptor >> 4). 391d894fc60SAlex Smith * If this is the last descriptor, link it back to the first, 392d894fc60SAlex Smith * i.e. leave offset set to 0, otherwise point to the next one. 393d894fc60SAlex Smith */ 394d894fc60SAlex Smith if (i != (periods - 1)) { 395d894fc60SAlex Smith desc->desc[i].dtc |= 396d894fc60SAlex Smith (((i + 1) * sizeof(*desc->desc)) >> 4) << 24; 397d894fc60SAlex Smith } 398d894fc60SAlex Smith } 399d894fc60SAlex Smith 400d894fc60SAlex Smith return vchan_tx_prep(&jzchan->vchan, &desc->vdesc, flags); 401d894fc60SAlex Smith } 402d894fc60SAlex Smith 4034f5db8c8SVinod Koul static struct dma_async_tx_descriptor *jz4780_dma_prep_dma_memcpy( 404d894fc60SAlex Smith struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, 405d894fc60SAlex Smith size_t len, unsigned long flags) 406d894fc60SAlex Smith { 407d894fc60SAlex Smith struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan); 408d894fc60SAlex Smith struct jz4780_dma_desc *desc; 409d894fc60SAlex Smith uint32_t tsz; 410d894fc60SAlex Smith 411d894fc60SAlex Smith desc = jz4780_dma_desc_alloc(jzchan, 1, DMA_MEMCPY); 412d894fc60SAlex Smith if (!desc) 413d894fc60SAlex Smith return NULL; 414d894fc60SAlex Smith 415dc578f31SAlex Smith tsz = jz4780_dma_transfer_size(dest | src | len, 416dc578f31SAlex Smith &jzchan->transfer_shift); 417d894fc60SAlex Smith 418d894fc60SAlex Smith desc->desc[0].dsa = src; 419d894fc60SAlex Smith desc->desc[0].dta = dest; 420d894fc60SAlex Smith desc->desc[0].drt = JZ_DMA_DRT_AUTO; 421d894fc60SAlex Smith desc->desc[0].dcm = JZ_DMA_DCM_TIE | JZ_DMA_DCM_SAI | JZ_DMA_DCM_DAI | 422d894fc60SAlex Smith tsz << JZ_DMA_DCM_TSZ_SHIFT | 423d894fc60SAlex Smith JZ_DMA_WIDTH_32_BIT << JZ_DMA_DCM_SP_SHIFT | 424d894fc60SAlex Smith JZ_DMA_WIDTH_32_BIT << JZ_DMA_DCM_DP_SHIFT; 425839896efSAlex Smith desc->desc[0].dtc = len >> jzchan->transfer_shift; 426d894fc60SAlex Smith 427d894fc60SAlex Smith return vchan_tx_prep(&jzchan->vchan, &desc->vdesc, flags); 428d894fc60SAlex Smith } 429d894fc60SAlex Smith 430d894fc60SAlex Smith static void jz4780_dma_begin(struct jz4780_dma_chan *jzchan) 431d894fc60SAlex Smith { 432d894fc60SAlex Smith struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan); 433d894fc60SAlex Smith struct virt_dma_desc *vdesc; 434d894fc60SAlex Smith unsigned int i; 435d894fc60SAlex Smith dma_addr_t desc_phys; 436d894fc60SAlex Smith 437d894fc60SAlex Smith if (!jzchan->desc) { 438d894fc60SAlex Smith vdesc = vchan_next_desc(&jzchan->vchan); 439d894fc60SAlex Smith if (!vdesc) 440d894fc60SAlex Smith return; 441d894fc60SAlex Smith 442d894fc60SAlex Smith list_del(&vdesc->node); 443d894fc60SAlex Smith 444d894fc60SAlex Smith jzchan->desc = to_jz4780_dma_desc(vdesc); 445d894fc60SAlex Smith jzchan->curr_hwdesc = 0; 446d894fc60SAlex Smith 447d894fc60SAlex Smith if (jzchan->desc->type == DMA_CYCLIC && vdesc->tx.callback) { 448d894fc60SAlex Smith /* 449d894fc60SAlex Smith * The DMA controller doesn't support triggering an 450d894fc60SAlex Smith * interrupt after processing each descriptor, only 451d894fc60SAlex Smith * after processing an entire terminated list of 452d894fc60SAlex Smith * descriptors. For a cyclic DMA setup the list of 453d894fc60SAlex Smith * descriptors is not terminated so we can never get an 454d894fc60SAlex Smith * interrupt. 455d894fc60SAlex Smith * 456d894fc60SAlex Smith * If the user requested a callback for a cyclic DMA 457d894fc60SAlex Smith * setup then we workaround this hardware limitation 458d894fc60SAlex Smith * here by degrading to a set of unlinked descriptors 459d894fc60SAlex Smith * which we will submit in sequence in response to the 460d894fc60SAlex Smith * completion of processing the previous descriptor. 461d894fc60SAlex Smith */ 462d894fc60SAlex Smith for (i = 0; i < jzchan->desc->count; i++) 463d894fc60SAlex Smith jzchan->desc->desc[i].dcm &= ~JZ_DMA_DCM_LINK; 464d894fc60SAlex Smith } 465d894fc60SAlex Smith } else { 466d894fc60SAlex Smith /* 467d894fc60SAlex Smith * There is an existing transfer, therefore this must be one 468d894fc60SAlex Smith * for which we unlinked the descriptors above. Advance to the 469d894fc60SAlex Smith * next one in the list. 470d894fc60SAlex Smith */ 471d894fc60SAlex Smith jzchan->curr_hwdesc = 472d894fc60SAlex Smith (jzchan->curr_hwdesc + 1) % jzchan->desc->count; 473d894fc60SAlex Smith } 474d894fc60SAlex Smith 475d894fc60SAlex Smith /* Use 8-word descriptors. */ 476d894fc60SAlex Smith jz4780_dma_writel(jzdma, JZ_DMA_REG_DCS(jzchan->id), JZ_DMA_DCS_DES8); 477d894fc60SAlex Smith 478d894fc60SAlex Smith /* Write descriptor address and initiate descriptor fetch. */ 479d894fc60SAlex Smith desc_phys = jzchan->desc->desc_phys + 480d894fc60SAlex Smith (jzchan->curr_hwdesc * sizeof(*jzchan->desc->desc)); 481d894fc60SAlex Smith jz4780_dma_writel(jzdma, JZ_DMA_REG_DDA(jzchan->id), desc_phys); 482d894fc60SAlex Smith jz4780_dma_writel(jzdma, JZ_DMA_REG_DDRS, BIT(jzchan->id)); 483d894fc60SAlex Smith 484d894fc60SAlex Smith /* Enable the channel. */ 485d894fc60SAlex Smith jz4780_dma_writel(jzdma, JZ_DMA_REG_DCS(jzchan->id), 486d894fc60SAlex Smith JZ_DMA_DCS_DES8 | JZ_DMA_DCS_CTE); 487d894fc60SAlex Smith } 488d894fc60SAlex Smith 489d894fc60SAlex Smith static void jz4780_dma_issue_pending(struct dma_chan *chan) 490d894fc60SAlex Smith { 491d894fc60SAlex Smith struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan); 492d894fc60SAlex Smith unsigned long flags; 493d894fc60SAlex Smith 494d894fc60SAlex Smith spin_lock_irqsave(&jzchan->vchan.lock, flags); 495d894fc60SAlex Smith 496d894fc60SAlex Smith if (vchan_issue_pending(&jzchan->vchan) && !jzchan->desc) 497d894fc60SAlex Smith jz4780_dma_begin(jzchan); 498d894fc60SAlex Smith 499d894fc60SAlex Smith spin_unlock_irqrestore(&jzchan->vchan.lock, flags); 500d894fc60SAlex Smith } 501d894fc60SAlex Smith 50246fa5168SAlex Smith static int jz4780_dma_terminate_all(struct dma_chan *chan) 503d894fc60SAlex Smith { 50446fa5168SAlex Smith struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan); 505d894fc60SAlex Smith struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan); 506d894fc60SAlex Smith unsigned long flags; 507d894fc60SAlex Smith LIST_HEAD(head); 508d894fc60SAlex Smith 509d894fc60SAlex Smith spin_lock_irqsave(&jzchan->vchan.lock, flags); 510d894fc60SAlex Smith 511d894fc60SAlex Smith /* Clear the DMA status and stop the transfer. */ 512d894fc60SAlex Smith jz4780_dma_writel(jzdma, JZ_DMA_REG_DCS(jzchan->id), 0); 513d894fc60SAlex Smith if (jzchan->desc) { 514f0dd52c8SPeter Ujfalusi vchan_terminate_vdesc(&jzchan->desc->vdesc); 515d894fc60SAlex Smith jzchan->desc = NULL; 516d894fc60SAlex Smith } 517d894fc60SAlex Smith 518d894fc60SAlex Smith vchan_get_all_descriptors(&jzchan->vchan, &head); 519d894fc60SAlex Smith 520d894fc60SAlex Smith spin_unlock_irqrestore(&jzchan->vchan.lock, flags); 521d894fc60SAlex Smith 522d894fc60SAlex Smith vchan_dma_desc_free_list(&jzchan->vchan, &head); 523d894fc60SAlex Smith return 0; 524d894fc60SAlex Smith } 525d894fc60SAlex Smith 526f0dd52c8SPeter Ujfalusi static void jz4780_dma_synchronize(struct dma_chan *chan) 527f0dd52c8SPeter Ujfalusi { 528f0dd52c8SPeter Ujfalusi struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan); 529f0dd52c8SPeter Ujfalusi 530f0dd52c8SPeter Ujfalusi vchan_synchronize(&jzchan->vchan); 531f0dd52c8SPeter Ujfalusi } 532f0dd52c8SPeter Ujfalusi 53346fa5168SAlex Smith static int jz4780_dma_config(struct dma_chan *chan, 53446fa5168SAlex Smith struct dma_slave_config *config) 535d894fc60SAlex Smith { 53646fa5168SAlex Smith struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan); 53746fa5168SAlex Smith 538d894fc60SAlex Smith if ((config->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES) 539d894fc60SAlex Smith || (config->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)) 540d894fc60SAlex Smith return -EINVAL; 541d894fc60SAlex Smith 542d894fc60SAlex Smith /* Copy the reset of the slave configuration, it is used later. */ 543d894fc60SAlex Smith memcpy(&jzchan->config, config, sizeof(jzchan->config)); 544d894fc60SAlex Smith 545d894fc60SAlex Smith return 0; 546d894fc60SAlex Smith } 547d894fc60SAlex Smith 548d894fc60SAlex Smith static size_t jz4780_dma_desc_residue(struct jz4780_dma_chan *jzchan, 549d894fc60SAlex Smith struct jz4780_dma_desc *desc, unsigned int next_sg) 550d894fc60SAlex Smith { 551d894fc60SAlex Smith struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan); 552d894fc60SAlex Smith unsigned int residue, count; 553d894fc60SAlex Smith unsigned int i; 554d894fc60SAlex Smith 555d894fc60SAlex Smith residue = 0; 556d894fc60SAlex Smith 557d894fc60SAlex Smith for (i = next_sg; i < desc->count; i++) 558d894fc60SAlex Smith residue += desc->desc[i].dtc << jzchan->transfer_shift; 559d894fc60SAlex Smith 560d894fc60SAlex Smith if (next_sg != 0) { 561d894fc60SAlex Smith count = jz4780_dma_readl(jzdma, 562d894fc60SAlex Smith JZ_DMA_REG_DTC(jzchan->id)); 563d894fc60SAlex Smith residue += count << jzchan->transfer_shift; 564d894fc60SAlex Smith } 565d894fc60SAlex Smith 566d894fc60SAlex Smith return residue; 567d894fc60SAlex Smith } 568d894fc60SAlex Smith 569d894fc60SAlex Smith static enum dma_status jz4780_dma_tx_status(struct dma_chan *chan, 570d894fc60SAlex Smith dma_cookie_t cookie, struct dma_tx_state *txstate) 571d894fc60SAlex Smith { 572d894fc60SAlex Smith struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan); 573d894fc60SAlex Smith struct virt_dma_desc *vdesc; 574d894fc60SAlex Smith enum dma_status status; 575d894fc60SAlex Smith unsigned long flags; 576d894fc60SAlex Smith 577d894fc60SAlex Smith status = dma_cookie_status(chan, cookie, txstate); 578d894fc60SAlex Smith if ((status == DMA_COMPLETE) || (txstate == NULL)) 579d894fc60SAlex Smith return status; 580d894fc60SAlex Smith 581d894fc60SAlex Smith spin_lock_irqsave(&jzchan->vchan.lock, flags); 582d894fc60SAlex Smith 583d894fc60SAlex Smith vdesc = vchan_find_desc(&jzchan->vchan, cookie); 584d894fc60SAlex Smith if (vdesc) { 585d894fc60SAlex Smith /* On the issued list, so hasn't been processed yet */ 586d894fc60SAlex Smith txstate->residue = jz4780_dma_desc_residue(jzchan, 587d894fc60SAlex Smith to_jz4780_dma_desc(vdesc), 0); 588d894fc60SAlex Smith } else if (cookie == jzchan->desc->vdesc.tx.cookie) { 589d894fc60SAlex Smith txstate->residue = jz4780_dma_desc_residue(jzchan, jzchan->desc, 590d894fc60SAlex Smith (jzchan->curr_hwdesc + 1) % jzchan->desc->count); 591d894fc60SAlex Smith } else 592d894fc60SAlex Smith txstate->residue = 0; 593d894fc60SAlex Smith 594d894fc60SAlex Smith if (vdesc && jzchan->desc && vdesc == &jzchan->desc->vdesc 595d894fc60SAlex Smith && jzchan->desc->status & (JZ_DMA_DCS_AR | JZ_DMA_DCS_HLT)) 596d894fc60SAlex Smith status = DMA_ERROR; 597d894fc60SAlex Smith 598d894fc60SAlex Smith spin_unlock_irqrestore(&jzchan->vchan.lock, flags); 599d894fc60SAlex Smith return status; 600d894fc60SAlex Smith } 601d894fc60SAlex Smith 602d894fc60SAlex Smith static void jz4780_dma_chan_irq(struct jz4780_dma_dev *jzdma, 603d894fc60SAlex Smith struct jz4780_dma_chan *jzchan) 604d894fc60SAlex Smith { 605d894fc60SAlex Smith uint32_t dcs; 606d894fc60SAlex Smith 607d894fc60SAlex Smith spin_lock(&jzchan->vchan.lock); 608d894fc60SAlex Smith 609d894fc60SAlex Smith dcs = jz4780_dma_readl(jzdma, JZ_DMA_REG_DCS(jzchan->id)); 610d894fc60SAlex Smith jz4780_dma_writel(jzdma, JZ_DMA_REG_DCS(jzchan->id), 0); 611d894fc60SAlex Smith 612d894fc60SAlex Smith if (dcs & JZ_DMA_DCS_AR) { 613d894fc60SAlex Smith dev_warn(&jzchan->vchan.chan.dev->device, 614d894fc60SAlex Smith "address error (DCS=0x%x)\n", dcs); 615d894fc60SAlex Smith } 616d894fc60SAlex Smith 617d894fc60SAlex Smith if (dcs & JZ_DMA_DCS_HLT) { 618d894fc60SAlex Smith dev_warn(&jzchan->vchan.chan.dev->device, 619d894fc60SAlex Smith "channel halt (DCS=0x%x)\n", dcs); 620d894fc60SAlex Smith } 621d894fc60SAlex Smith 622d894fc60SAlex Smith if (jzchan->desc) { 623d894fc60SAlex Smith jzchan->desc->status = dcs; 624d894fc60SAlex Smith 625d894fc60SAlex Smith if ((dcs & (JZ_DMA_DCS_AR | JZ_DMA_DCS_HLT)) == 0) { 626d894fc60SAlex Smith if (jzchan->desc->type == DMA_CYCLIC) { 627d894fc60SAlex Smith vchan_cyclic_callback(&jzchan->desc->vdesc); 628d894fc60SAlex Smith } else { 629d894fc60SAlex Smith vchan_cookie_complete(&jzchan->desc->vdesc); 630d894fc60SAlex Smith jzchan->desc = NULL; 631d894fc60SAlex Smith } 632d894fc60SAlex Smith 633d894fc60SAlex Smith jz4780_dma_begin(jzchan); 634d894fc60SAlex Smith } 635d894fc60SAlex Smith } else { 636d894fc60SAlex Smith dev_err(&jzchan->vchan.chan.dev->device, 637d894fc60SAlex Smith "channel IRQ with no active transfer\n"); 638d894fc60SAlex Smith } 639d894fc60SAlex Smith 640d894fc60SAlex Smith spin_unlock(&jzchan->vchan.lock); 641d894fc60SAlex Smith } 642d894fc60SAlex Smith 643d894fc60SAlex Smith static irqreturn_t jz4780_dma_irq_handler(int irq, void *data) 644d894fc60SAlex Smith { 645d894fc60SAlex Smith struct jz4780_dma_dev *jzdma = data; 646d894fc60SAlex Smith uint32_t pending, dmac; 647d894fc60SAlex Smith int i; 648d894fc60SAlex Smith 649d894fc60SAlex Smith pending = jz4780_dma_readl(jzdma, JZ_DMA_REG_DIRQP); 650d894fc60SAlex Smith 651d894fc60SAlex Smith for (i = 0; i < JZ_DMA_NR_CHANNELS; i++) { 652d894fc60SAlex Smith if (!(pending & (1<<i))) 653d894fc60SAlex Smith continue; 654d894fc60SAlex Smith 655d894fc60SAlex Smith jz4780_dma_chan_irq(jzdma, &jzdma->chan[i]); 656d894fc60SAlex Smith } 657d894fc60SAlex Smith 658d894fc60SAlex Smith /* Clear halt and address error status of all channels. */ 659d894fc60SAlex Smith dmac = jz4780_dma_readl(jzdma, JZ_DMA_REG_DMAC); 660d894fc60SAlex Smith dmac &= ~(JZ_DMA_DMAC_HLT | JZ_DMA_DMAC_AR); 661d894fc60SAlex Smith jz4780_dma_writel(jzdma, JZ_DMA_REG_DMAC, dmac); 662d894fc60SAlex Smith 663d894fc60SAlex Smith /* Clear interrupt pending status. */ 664d894fc60SAlex Smith jz4780_dma_writel(jzdma, JZ_DMA_REG_DIRQP, 0); 665d894fc60SAlex Smith 666d894fc60SAlex Smith return IRQ_HANDLED; 667d894fc60SAlex Smith } 668d894fc60SAlex Smith 669d894fc60SAlex Smith static int jz4780_dma_alloc_chan_resources(struct dma_chan *chan) 670d894fc60SAlex Smith { 671d894fc60SAlex Smith struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan); 672d894fc60SAlex Smith 673d894fc60SAlex Smith jzchan->desc_pool = dma_pool_create(dev_name(&chan->dev->device), 674d894fc60SAlex Smith chan->device->dev, 675d894fc60SAlex Smith JZ_DMA_DESC_BLOCK_SIZE, 676d894fc60SAlex Smith PAGE_SIZE, 0); 677d894fc60SAlex Smith if (!jzchan->desc_pool) { 678d894fc60SAlex Smith dev_err(&chan->dev->device, 679d894fc60SAlex Smith "failed to allocate descriptor pool\n"); 680d894fc60SAlex Smith return -ENOMEM; 681d894fc60SAlex Smith } 682d894fc60SAlex Smith 683d894fc60SAlex Smith return 0; 684d894fc60SAlex Smith } 685d894fc60SAlex Smith 686d894fc60SAlex Smith static void jz4780_dma_free_chan_resources(struct dma_chan *chan) 687d894fc60SAlex Smith { 688d894fc60SAlex Smith struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan); 689d894fc60SAlex Smith 690d894fc60SAlex Smith vchan_free_chan_resources(&jzchan->vchan); 691d894fc60SAlex Smith dma_pool_destroy(jzchan->desc_pool); 692d894fc60SAlex Smith jzchan->desc_pool = NULL; 693d894fc60SAlex Smith } 694d894fc60SAlex Smith 695d894fc60SAlex Smith static bool jz4780_dma_filter_fn(struct dma_chan *chan, void *param) 696d894fc60SAlex Smith { 697d894fc60SAlex Smith struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan); 698d894fc60SAlex Smith struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan); 699026fd406SAlex Smith struct jz4780_dma_filter_data *data = param; 700026fd406SAlex Smith 701026fd406SAlex Smith if (jzdma->dma_device.dev->of_node != data->of_node) 702026fd406SAlex Smith return false; 703d894fc60SAlex Smith 704d894fc60SAlex Smith if (data->channel > -1) { 705d894fc60SAlex Smith if (data->channel != jzchan->id) 706d894fc60SAlex Smith return false; 707d894fc60SAlex Smith } else if (jzdma->chan_reserved & BIT(jzchan->id)) { 708d894fc60SAlex Smith return false; 709d894fc60SAlex Smith } 710d894fc60SAlex Smith 711d894fc60SAlex Smith jzchan->transfer_type = data->transfer_type; 712d894fc60SAlex Smith 713d894fc60SAlex Smith return true; 714d894fc60SAlex Smith } 715d894fc60SAlex Smith 716d894fc60SAlex Smith static struct dma_chan *jz4780_of_dma_xlate(struct of_phandle_args *dma_spec, 717d894fc60SAlex Smith struct of_dma *ofdma) 718d894fc60SAlex Smith { 719d894fc60SAlex Smith struct jz4780_dma_dev *jzdma = ofdma->of_dma_data; 720d894fc60SAlex Smith dma_cap_mask_t mask = jzdma->dma_device.cap_mask; 721026fd406SAlex Smith struct jz4780_dma_filter_data data; 722d894fc60SAlex Smith 723d894fc60SAlex Smith if (dma_spec->args_count != 2) 724d894fc60SAlex Smith return NULL; 725d894fc60SAlex Smith 726026fd406SAlex Smith data.of_node = ofdma->of_node; 727d894fc60SAlex Smith data.transfer_type = dma_spec->args[0]; 728d894fc60SAlex Smith data.channel = dma_spec->args[1]; 729d894fc60SAlex Smith 730d894fc60SAlex Smith if (data.channel > -1) { 731d894fc60SAlex Smith if (data.channel >= JZ_DMA_NR_CHANNELS) { 732d894fc60SAlex Smith dev_err(jzdma->dma_device.dev, 733d894fc60SAlex Smith "device requested non-existent channel %u\n", 734d894fc60SAlex Smith data.channel); 735d894fc60SAlex Smith return NULL; 736d894fc60SAlex Smith } 737d894fc60SAlex Smith 738d894fc60SAlex Smith /* Can only select a channel marked as reserved. */ 739d894fc60SAlex Smith if (!(jzdma->chan_reserved & BIT(data.channel))) { 740d894fc60SAlex Smith dev_err(jzdma->dma_device.dev, 741d894fc60SAlex Smith "device requested unreserved channel %u\n", 742d894fc60SAlex Smith data.channel); 743d894fc60SAlex Smith return NULL; 744d894fc60SAlex Smith } 745d894fc60SAlex Smith 746d3273e10SAlex Smith jzdma->chan[data.channel].transfer_type = data.transfer_type; 747d3273e10SAlex Smith 748d3273e10SAlex Smith return dma_get_slave_channel( 749d3273e10SAlex Smith &jzdma->chan[data.channel].vchan.chan); 750d3273e10SAlex Smith } else { 751d894fc60SAlex Smith return dma_request_channel(mask, jz4780_dma_filter_fn, &data); 752d894fc60SAlex Smith } 753d3273e10SAlex Smith } 754d894fc60SAlex Smith 755d894fc60SAlex Smith static int jz4780_dma_probe(struct platform_device *pdev) 756d894fc60SAlex Smith { 757d894fc60SAlex Smith struct device *dev = &pdev->dev; 758d894fc60SAlex Smith struct jz4780_dma_dev *jzdma; 759d894fc60SAlex Smith struct jz4780_dma_chan *jzchan; 760d894fc60SAlex Smith struct dma_device *dd; 761d894fc60SAlex Smith struct resource *res; 762d894fc60SAlex Smith int i, ret; 763d894fc60SAlex Smith 764d894fc60SAlex Smith jzdma = devm_kzalloc(dev, sizeof(*jzdma), GFP_KERNEL); 765d894fc60SAlex Smith if (!jzdma) 766d894fc60SAlex Smith return -ENOMEM; 767d894fc60SAlex Smith 768d894fc60SAlex Smith platform_set_drvdata(pdev, jzdma); 769d894fc60SAlex Smith 770d894fc60SAlex Smith res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 771d894fc60SAlex Smith if (!res) { 772d894fc60SAlex Smith dev_err(dev, "failed to get I/O memory\n"); 773d894fc60SAlex Smith return -EINVAL; 774d894fc60SAlex Smith } 775d894fc60SAlex Smith 776d894fc60SAlex Smith jzdma->base = devm_ioremap_resource(dev, res); 777d894fc60SAlex Smith if (IS_ERR(jzdma->base)) 778d894fc60SAlex Smith return PTR_ERR(jzdma->base); 779d894fc60SAlex Smith 780839896efSAlex Smith ret = platform_get_irq(pdev, 0); 781839896efSAlex Smith if (ret < 0) { 782d894fc60SAlex Smith dev_err(dev, "failed to get IRQ: %d\n", ret); 783839896efSAlex Smith return ret; 784d894fc60SAlex Smith } 785d894fc60SAlex Smith 786839896efSAlex Smith jzdma->irq = ret; 787839896efSAlex Smith 788d509a83cSAlex Smith ret = request_irq(jzdma->irq, jz4780_dma_irq_handler, 0, dev_name(dev), 789d509a83cSAlex Smith jzdma); 790d894fc60SAlex Smith if (ret) { 791d894fc60SAlex Smith dev_err(dev, "failed to request IRQ %u!\n", jzdma->irq); 792839896efSAlex Smith return ret; 793d894fc60SAlex Smith } 794d894fc60SAlex Smith 795d894fc60SAlex Smith jzdma->clk = devm_clk_get(dev, NULL); 796d894fc60SAlex Smith if (IS_ERR(jzdma->clk)) { 797d894fc60SAlex Smith dev_err(dev, "failed to get clock\n"); 798d509a83cSAlex Smith ret = PTR_ERR(jzdma->clk); 799d509a83cSAlex Smith goto err_free_irq; 800d894fc60SAlex Smith } 801d894fc60SAlex Smith 802d894fc60SAlex Smith clk_prepare_enable(jzdma->clk); 803d894fc60SAlex Smith 804d894fc60SAlex Smith /* Property is optional, if it doesn't exist the value will remain 0. */ 805d894fc60SAlex Smith of_property_read_u32_index(dev->of_node, "ingenic,reserved-channels", 806d894fc60SAlex Smith 0, &jzdma->chan_reserved); 807d894fc60SAlex Smith 808d894fc60SAlex Smith dd = &jzdma->dma_device; 809d894fc60SAlex Smith 810d894fc60SAlex Smith dma_cap_set(DMA_MEMCPY, dd->cap_mask); 811d894fc60SAlex Smith dma_cap_set(DMA_SLAVE, dd->cap_mask); 812d894fc60SAlex Smith dma_cap_set(DMA_CYCLIC, dd->cap_mask); 813d894fc60SAlex Smith 814d894fc60SAlex Smith dd->dev = dev; 81577a68e56SMaxime Ripard dd->copy_align = DMAENGINE_ALIGN_4_BYTES; 816d894fc60SAlex Smith dd->device_alloc_chan_resources = jz4780_dma_alloc_chan_resources; 817d894fc60SAlex Smith dd->device_free_chan_resources = jz4780_dma_free_chan_resources; 818d894fc60SAlex Smith dd->device_prep_slave_sg = jz4780_dma_prep_slave_sg; 819d894fc60SAlex Smith dd->device_prep_dma_cyclic = jz4780_dma_prep_dma_cyclic; 820d894fc60SAlex Smith dd->device_prep_dma_memcpy = jz4780_dma_prep_dma_memcpy; 82146fa5168SAlex Smith dd->device_config = jz4780_dma_config; 822d894fc60SAlex Smith dd->device_terminate_all = jz4780_dma_terminate_all; 823f0dd52c8SPeter Ujfalusi dd->device_synchronize = jz4780_dma_synchronize; 824d894fc60SAlex Smith dd->device_tx_status = jz4780_dma_tx_status; 825d894fc60SAlex Smith dd->device_issue_pending = jz4780_dma_issue_pending; 826d894fc60SAlex Smith dd->src_addr_widths = JZ_DMA_BUSWIDTHS; 827d894fc60SAlex Smith dd->dst_addr_widths = JZ_DMA_BUSWIDTHS; 828d894fc60SAlex Smith dd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV); 829d894fc60SAlex Smith dd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; 830d894fc60SAlex Smith 831d894fc60SAlex Smith /* 832d894fc60SAlex Smith * Enable DMA controller, mark all channels as not programmable. 833d894fc60SAlex Smith * Also set the FMSC bit - it increases MSC performance, so it makes 834d894fc60SAlex Smith * little sense not to enable it. 835d894fc60SAlex Smith */ 836d894fc60SAlex Smith jz4780_dma_writel(jzdma, JZ_DMA_REG_DMAC, 837d894fc60SAlex Smith JZ_DMA_DMAC_DMAE | JZ_DMA_DMAC_FMSC); 838d894fc60SAlex Smith jz4780_dma_writel(jzdma, JZ_DMA_REG_DMACP, 0); 839d894fc60SAlex Smith 840d894fc60SAlex Smith INIT_LIST_HEAD(&dd->channels); 841d894fc60SAlex Smith 842d894fc60SAlex Smith for (i = 0; i < JZ_DMA_NR_CHANNELS; i++) { 843d894fc60SAlex Smith jzchan = &jzdma->chan[i]; 844d894fc60SAlex Smith jzchan->id = i; 845d894fc60SAlex Smith 846d894fc60SAlex Smith vchan_init(&jzchan->vchan, dd); 847d894fc60SAlex Smith jzchan->vchan.desc_free = jz4780_dma_desc_free; 848d894fc60SAlex Smith } 849d894fc60SAlex Smith 8500f5a5e57SHuang Shijie ret = dmaenginem_async_device_register(dd); 851d894fc60SAlex Smith if (ret) { 852d894fc60SAlex Smith dev_err(dev, "failed to register device\n"); 853d894fc60SAlex Smith goto err_disable_clk; 854d894fc60SAlex Smith } 855d894fc60SAlex Smith 856d894fc60SAlex Smith /* Register with OF DMA helpers. */ 857d894fc60SAlex Smith ret = of_dma_controller_register(dev->of_node, jz4780_of_dma_xlate, 858d894fc60SAlex Smith jzdma); 859d894fc60SAlex Smith if (ret) { 860d894fc60SAlex Smith dev_err(dev, "failed to register OF DMA controller\n"); 8610f5a5e57SHuang Shijie goto err_disable_clk; 862d894fc60SAlex Smith } 863d894fc60SAlex Smith 864d894fc60SAlex Smith dev_info(dev, "JZ4780 DMA controller initialised\n"); 865d894fc60SAlex Smith return 0; 866d894fc60SAlex Smith 867d894fc60SAlex Smith err_disable_clk: 868d894fc60SAlex Smith clk_disable_unprepare(jzdma->clk); 869d509a83cSAlex Smith 870d509a83cSAlex Smith err_free_irq: 871d509a83cSAlex Smith free_irq(jzdma->irq, jzdma); 872d894fc60SAlex Smith return ret; 873d894fc60SAlex Smith } 874d894fc60SAlex Smith 875d894fc60SAlex Smith static int jz4780_dma_remove(struct platform_device *pdev) 876d894fc60SAlex Smith { 877d894fc60SAlex Smith struct jz4780_dma_dev *jzdma = platform_get_drvdata(pdev); 878ae9c02b4SAlex Smith int i; 879d894fc60SAlex Smith 880d894fc60SAlex Smith of_dma_controller_free(pdev->dev.of_node); 881ae9c02b4SAlex Smith 882d509a83cSAlex Smith free_irq(jzdma->irq, jzdma); 883ae9c02b4SAlex Smith 884ae9c02b4SAlex Smith for (i = 0; i < JZ_DMA_NR_CHANNELS; i++) 885ae9c02b4SAlex Smith tasklet_kill(&jzdma->chan[i].vchan.task); 886ae9c02b4SAlex Smith 887d894fc60SAlex Smith return 0; 888d894fc60SAlex Smith } 889d894fc60SAlex Smith 890d894fc60SAlex Smith static const struct of_device_id jz4780_dma_dt_match[] = { 891d894fc60SAlex Smith { .compatible = "ingenic,jz4780-dma", .data = NULL }, 892d894fc60SAlex Smith {}, 893d894fc60SAlex Smith }; 894d894fc60SAlex Smith MODULE_DEVICE_TABLE(of, jz4780_dma_dt_match); 895d894fc60SAlex Smith 896d894fc60SAlex Smith static struct platform_driver jz4780_dma_driver = { 897d894fc60SAlex Smith .probe = jz4780_dma_probe, 898d894fc60SAlex Smith .remove = jz4780_dma_remove, 899d894fc60SAlex Smith .driver = { 900d894fc60SAlex Smith .name = "jz4780-dma", 901d894fc60SAlex Smith .of_match_table = of_match_ptr(jz4780_dma_dt_match), 902d894fc60SAlex Smith }, 903d894fc60SAlex Smith }; 904d894fc60SAlex Smith 905d894fc60SAlex Smith static int __init jz4780_dma_init(void) 906d894fc60SAlex Smith { 907d894fc60SAlex Smith return platform_driver_register(&jz4780_dma_driver); 908d894fc60SAlex Smith } 909d894fc60SAlex Smith subsys_initcall(jz4780_dma_init); 910d894fc60SAlex Smith 911d894fc60SAlex Smith static void __exit jz4780_dma_exit(void) 912d894fc60SAlex Smith { 913d894fc60SAlex Smith platform_driver_unregister(&jz4780_dma_driver); 914d894fc60SAlex Smith } 915d894fc60SAlex Smith module_exit(jz4780_dma_exit); 916d894fc60SAlex Smith 917d894fc60SAlex Smith MODULE_AUTHOR("Alex Smith <alex@alex-smith.me.uk>"); 918d894fc60SAlex Smith MODULE_DESCRIPTION("Ingenic JZ4780 DMA controller driver"); 919d894fc60SAlex Smith MODULE_LICENSE("GPL"); 920