12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
2d894fc60SAlex Smith /*
3d894fc60SAlex Smith * Ingenic JZ4780 DMA controller
4d894fc60SAlex Smith *
5d894fc60SAlex Smith * Copyright (c) 2015 Imagination Technologies
6d894fc60SAlex Smith * Author: Alex Smith <alex@alex-smith.me.uk>
7d894fc60SAlex Smith */
8d894fc60SAlex Smith
9d894fc60SAlex Smith #include <linux/clk.h>
10d894fc60SAlex Smith #include <linux/dmapool.h>
112128565aSAidan MacDonald #include <linux/dma-mapping.h>
12d894fc60SAlex Smith #include <linux/init.h>
13d894fc60SAlex Smith #include <linux/interrupt.h>
14d894fc60SAlex Smith #include <linux/module.h>
15d894fc60SAlex Smith #include <linux/of.h>
16d894fc60SAlex Smith #include <linux/of_dma.h>
17d894fc60SAlex Smith #include <linux/platform_device.h>
18d894fc60SAlex Smith #include <linux/slab.h>
19d894fc60SAlex Smith
20d894fc60SAlex Smith #include "dmaengine.h"
21d894fc60SAlex Smith #include "virt-dma.h"
22d894fc60SAlex Smith
23d894fc60SAlex Smith /* Global registers. */
2433633583SPaul Cercueil #define JZ_DMA_REG_DMAC 0x00
2533633583SPaul Cercueil #define JZ_DMA_REG_DIRQP 0x04
2633633583SPaul Cercueil #define JZ_DMA_REG_DDR 0x08
2733633583SPaul Cercueil #define JZ_DMA_REG_DDRS 0x0c
2829870eb7SPaul Cercueil #define JZ_DMA_REG_DCKE 0x10
2929870eb7SPaul Cercueil #define JZ_DMA_REG_DCKES 0x14
3029870eb7SPaul Cercueil #define JZ_DMA_REG_DCKEC 0x18
3133633583SPaul Cercueil #define JZ_DMA_REG_DMACP 0x1c
3233633583SPaul Cercueil #define JZ_DMA_REG_DSIRQP 0x20
3333633583SPaul Cercueil #define JZ_DMA_REG_DSIRQM 0x24
3433633583SPaul Cercueil #define JZ_DMA_REG_DCIRQP 0x28
3533633583SPaul Cercueil #define JZ_DMA_REG_DCIRQM 0x2c
36d894fc60SAlex Smith
37d894fc60SAlex Smith /* Per-channel registers. */
38d894fc60SAlex Smith #define JZ_DMA_REG_CHAN(n) (n * 0x20)
3933633583SPaul Cercueil #define JZ_DMA_REG_DSA 0x00
4033633583SPaul Cercueil #define JZ_DMA_REG_DTA 0x04
4133633583SPaul Cercueil #define JZ_DMA_REG_DTC 0x08
4233633583SPaul Cercueil #define JZ_DMA_REG_DRT 0x0c
4333633583SPaul Cercueil #define JZ_DMA_REG_DCS 0x10
4433633583SPaul Cercueil #define JZ_DMA_REG_DCM 0x14
4533633583SPaul Cercueil #define JZ_DMA_REG_DDA 0x18
4633633583SPaul Cercueil #define JZ_DMA_REG_DSD 0x1c
47d894fc60SAlex Smith
48d894fc60SAlex Smith #define JZ_DMA_DMAC_DMAE BIT(0)
49d894fc60SAlex Smith #define JZ_DMA_DMAC_AR BIT(2)
50d894fc60SAlex Smith #define JZ_DMA_DMAC_HLT BIT(3)
5117a8e30eSPaul Cercueil #define JZ_DMA_DMAC_FAIC BIT(27)
52d894fc60SAlex Smith #define JZ_DMA_DMAC_FMSC BIT(31)
53d894fc60SAlex Smith
54d894fc60SAlex Smith #define JZ_DMA_DRT_AUTO 0x8
55d894fc60SAlex Smith
56d894fc60SAlex Smith #define JZ_DMA_DCS_CTE BIT(0)
57d894fc60SAlex Smith #define JZ_DMA_DCS_HLT BIT(2)
58d894fc60SAlex Smith #define JZ_DMA_DCS_TT BIT(3)
59d894fc60SAlex Smith #define JZ_DMA_DCS_AR BIT(4)
60d894fc60SAlex Smith #define JZ_DMA_DCS_DES8 BIT(30)
61d894fc60SAlex Smith
62d894fc60SAlex Smith #define JZ_DMA_DCM_LINK BIT(0)
63d894fc60SAlex Smith #define JZ_DMA_DCM_TIE BIT(1)
64d894fc60SAlex Smith #define JZ_DMA_DCM_STDE BIT(2)
65d894fc60SAlex Smith #define JZ_DMA_DCM_TSZ_SHIFT 8
66d894fc60SAlex Smith #define JZ_DMA_DCM_TSZ_MASK (0x7 << JZ_DMA_DCM_TSZ_SHIFT)
67d894fc60SAlex Smith #define JZ_DMA_DCM_DP_SHIFT 12
68d894fc60SAlex Smith #define JZ_DMA_DCM_SP_SHIFT 14
69d894fc60SAlex Smith #define JZ_DMA_DCM_DAI BIT(22)
70d894fc60SAlex Smith #define JZ_DMA_DCM_SAI BIT(23)
71d894fc60SAlex Smith
72d894fc60SAlex Smith #define JZ_DMA_SIZE_4_BYTE 0x0
73d894fc60SAlex Smith #define JZ_DMA_SIZE_1_BYTE 0x1
74d894fc60SAlex Smith #define JZ_DMA_SIZE_2_BYTE 0x2
75d894fc60SAlex Smith #define JZ_DMA_SIZE_16_BYTE 0x3
76d894fc60SAlex Smith #define JZ_DMA_SIZE_32_BYTE 0x4
77d894fc60SAlex Smith #define JZ_DMA_SIZE_64_BYTE 0x5
78d894fc60SAlex Smith #define JZ_DMA_SIZE_128_BYTE 0x6
79d894fc60SAlex Smith
80d894fc60SAlex Smith #define JZ_DMA_WIDTH_32_BIT 0x0
81d894fc60SAlex Smith #define JZ_DMA_WIDTH_8_BIT 0x1
82d894fc60SAlex Smith #define JZ_DMA_WIDTH_16_BIT 0x2
83d894fc60SAlex Smith
84d894fc60SAlex Smith #define JZ_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
85d894fc60SAlex Smith BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
86d894fc60SAlex Smith BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
87d894fc60SAlex Smith
8833633583SPaul Cercueil #define JZ4780_DMA_CTRL_OFFSET 0x1000
8933633583SPaul Cercueil
9029870eb7SPaul Cercueil /* macros for use with jz4780_dma_soc_data.flags */
9129870eb7SPaul Cercueil #define JZ_SOC_DATA_ALLOW_LEGACY_DT BIT(0)
9229870eb7SPaul Cercueil #define JZ_SOC_DATA_PROGRAMMABLE_DMA BIT(1)
9329870eb7SPaul Cercueil #define JZ_SOC_DATA_PER_CHAN_PM BIT(2)
94ae9156b6SPaul Cercueil #define JZ_SOC_DATA_NO_DCKES_DCKEC BIT(3)
95f4c255f1SPaul Cercueil #define JZ_SOC_DATA_BREAK_LINKS BIT(4)
9629870eb7SPaul Cercueil
97d894fc60SAlex Smith /**
98d894fc60SAlex Smith * struct jz4780_dma_hwdesc - descriptor structure read by the DMA controller.
99d894fc60SAlex Smith * @dcm: value for the DCM (channel command) register
100d894fc60SAlex Smith * @dsa: source address
101d894fc60SAlex Smith * @dta: target address
102d894fc60SAlex Smith * @dtc: transfer count (number of blocks of the transfer size specified in DCM
103d894fc60SAlex Smith * to transfer) in the low 24 bits, offset of the next descriptor from the
104d894fc60SAlex Smith * descriptor base address in the upper 8 bits.
105d894fc60SAlex Smith */
106d894fc60SAlex Smith struct jz4780_dma_hwdesc {
107c8c0cda8SPaul Cercueil u32 dcm;
108c8c0cda8SPaul Cercueil u32 dsa;
109c8c0cda8SPaul Cercueil u32 dta;
110c8c0cda8SPaul Cercueil u32 dtc;
111d894fc60SAlex Smith };
112d894fc60SAlex Smith
113d894fc60SAlex Smith /* Size of allocations for hardware descriptor blocks. */
114d894fc60SAlex Smith #define JZ_DMA_DESC_BLOCK_SIZE PAGE_SIZE
115d894fc60SAlex Smith #define JZ_DMA_MAX_DESC \
116d894fc60SAlex Smith (JZ_DMA_DESC_BLOCK_SIZE / sizeof(struct jz4780_dma_hwdesc))
117d894fc60SAlex Smith
118d894fc60SAlex Smith struct jz4780_dma_desc {
119d894fc60SAlex Smith struct virt_dma_desc vdesc;
120d894fc60SAlex Smith
121d894fc60SAlex Smith struct jz4780_dma_hwdesc *desc;
122d894fc60SAlex Smith dma_addr_t desc_phys;
123d894fc60SAlex Smith unsigned int count;
124d894fc60SAlex Smith enum dma_transaction_type type;
12576a09663SPaul Cercueil u32 transfer_type;
126c8c0cda8SPaul Cercueil u32 status;
127d894fc60SAlex Smith };
128d894fc60SAlex Smith
129d894fc60SAlex Smith struct jz4780_dma_chan {
130d894fc60SAlex Smith struct virt_dma_chan vchan;
131d894fc60SAlex Smith unsigned int id;
132d894fc60SAlex Smith struct dma_pool *desc_pool;
133d894fc60SAlex Smith
13476a09663SPaul Cercueil u32 transfer_type_tx, transfer_type_rx;
135c8c0cda8SPaul Cercueil u32 transfer_shift;
136d894fc60SAlex Smith struct dma_slave_config config;
137d894fc60SAlex Smith
138d894fc60SAlex Smith struct jz4780_dma_desc *desc;
139d894fc60SAlex Smith unsigned int curr_hwdesc;
140d894fc60SAlex Smith };
141d894fc60SAlex Smith
1426147b032SPaul Cercueil struct jz4780_dma_soc_data {
1436147b032SPaul Cercueil unsigned int nb_channels;
14429870eb7SPaul Cercueil unsigned int transfer_ord_max;
14529870eb7SPaul Cercueil unsigned long flags;
1466147b032SPaul Cercueil };
1476147b032SPaul Cercueil
148d894fc60SAlex Smith struct jz4780_dma_dev {
149d894fc60SAlex Smith struct dma_device dma_device;
15033633583SPaul Cercueil void __iomem *chn_base;
15133633583SPaul Cercueil void __iomem *ctrl_base;
152d894fc60SAlex Smith struct clk *clk;
153d894fc60SAlex Smith unsigned int irq;
1546147b032SPaul Cercueil const struct jz4780_dma_soc_data *soc_data;
155d894fc60SAlex Smith
156c8c0cda8SPaul Cercueil u32 chan_reserved;
1576147b032SPaul Cercueil struct jz4780_dma_chan chan[];
158d894fc60SAlex Smith };
159d894fc60SAlex Smith
160026fd406SAlex Smith struct jz4780_dma_filter_data {
16176a09663SPaul Cercueil u32 transfer_type_tx, transfer_type_rx;
162d894fc60SAlex Smith int channel;
163d894fc60SAlex Smith };
164d894fc60SAlex Smith
to_jz4780_dma_chan(struct dma_chan * chan)165d894fc60SAlex Smith static inline struct jz4780_dma_chan *to_jz4780_dma_chan(struct dma_chan *chan)
166d894fc60SAlex Smith {
167d894fc60SAlex Smith return container_of(chan, struct jz4780_dma_chan, vchan.chan);
168d894fc60SAlex Smith }
169d894fc60SAlex Smith
to_jz4780_dma_desc(struct virt_dma_desc * vdesc)170d894fc60SAlex Smith static inline struct jz4780_dma_desc *to_jz4780_dma_desc(
171d894fc60SAlex Smith struct virt_dma_desc *vdesc)
172d894fc60SAlex Smith {
173d894fc60SAlex Smith return container_of(vdesc, struct jz4780_dma_desc, vdesc);
174d894fc60SAlex Smith }
175d894fc60SAlex Smith
jz4780_dma_chan_parent(struct jz4780_dma_chan * jzchan)176d894fc60SAlex Smith static inline struct jz4780_dma_dev *jz4780_dma_chan_parent(
177d894fc60SAlex Smith struct jz4780_dma_chan *jzchan)
178d894fc60SAlex Smith {
179d894fc60SAlex Smith return container_of(jzchan->vchan.chan.device, struct jz4780_dma_dev,
180d894fc60SAlex Smith dma_device);
181d894fc60SAlex Smith }
182d894fc60SAlex Smith
jz4780_dma_chn_readl(struct jz4780_dma_dev * jzdma,unsigned int chn,unsigned int reg)183c8c0cda8SPaul Cercueil static inline u32 jz4780_dma_chn_readl(struct jz4780_dma_dev *jzdma,
18433633583SPaul Cercueil unsigned int chn, unsigned int reg)
185d894fc60SAlex Smith {
18633633583SPaul Cercueil return readl(jzdma->chn_base + reg + JZ_DMA_REG_CHAN(chn));
187d894fc60SAlex Smith }
188d894fc60SAlex Smith
jz4780_dma_chn_writel(struct jz4780_dma_dev * jzdma,unsigned int chn,unsigned int reg,u32 val)18933633583SPaul Cercueil static inline void jz4780_dma_chn_writel(struct jz4780_dma_dev *jzdma,
190c8c0cda8SPaul Cercueil unsigned int chn, unsigned int reg, u32 val)
19133633583SPaul Cercueil {
19233633583SPaul Cercueil writel(val, jzdma->chn_base + reg + JZ_DMA_REG_CHAN(chn));
19333633583SPaul Cercueil }
19433633583SPaul Cercueil
jz4780_dma_ctrl_readl(struct jz4780_dma_dev * jzdma,unsigned int reg)195c8c0cda8SPaul Cercueil static inline u32 jz4780_dma_ctrl_readl(struct jz4780_dma_dev *jzdma,
19633633583SPaul Cercueil unsigned int reg)
19733633583SPaul Cercueil {
19833633583SPaul Cercueil return readl(jzdma->ctrl_base + reg);
19933633583SPaul Cercueil }
20033633583SPaul Cercueil
jz4780_dma_ctrl_writel(struct jz4780_dma_dev * jzdma,unsigned int reg,u32 val)20133633583SPaul Cercueil static inline void jz4780_dma_ctrl_writel(struct jz4780_dma_dev *jzdma,
202c8c0cda8SPaul Cercueil unsigned int reg, u32 val)
203d894fc60SAlex Smith {
20433633583SPaul Cercueil writel(val, jzdma->ctrl_base + reg);
205d894fc60SAlex Smith }
206d894fc60SAlex Smith
jz4780_dma_chan_enable(struct jz4780_dma_dev * jzdma,unsigned int chn)20729870eb7SPaul Cercueil static inline void jz4780_dma_chan_enable(struct jz4780_dma_dev *jzdma,
20829870eb7SPaul Cercueil unsigned int chn)
20929870eb7SPaul Cercueil {
210ae9156b6SPaul Cercueil if (jzdma->soc_data->flags & JZ_SOC_DATA_PER_CHAN_PM) {
211ae9156b6SPaul Cercueil unsigned int reg;
212ae9156b6SPaul Cercueil
213ae9156b6SPaul Cercueil if (jzdma->soc_data->flags & JZ_SOC_DATA_NO_DCKES_DCKEC)
214ae9156b6SPaul Cercueil reg = JZ_DMA_REG_DCKE;
215ae9156b6SPaul Cercueil else
216ae9156b6SPaul Cercueil reg = JZ_DMA_REG_DCKES;
217ae9156b6SPaul Cercueil
218ae9156b6SPaul Cercueil jz4780_dma_ctrl_writel(jzdma, reg, BIT(chn));
219ae9156b6SPaul Cercueil }
22029870eb7SPaul Cercueil }
22129870eb7SPaul Cercueil
jz4780_dma_chan_disable(struct jz4780_dma_dev * jzdma,unsigned int chn)22229870eb7SPaul Cercueil static inline void jz4780_dma_chan_disable(struct jz4780_dma_dev *jzdma,
22329870eb7SPaul Cercueil unsigned int chn)
22429870eb7SPaul Cercueil {
225ae9156b6SPaul Cercueil if ((jzdma->soc_data->flags & JZ_SOC_DATA_PER_CHAN_PM) &&
226ae9156b6SPaul Cercueil !(jzdma->soc_data->flags & JZ_SOC_DATA_NO_DCKES_DCKEC))
22729870eb7SPaul Cercueil jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DCKEC, BIT(chn));
228d894fc60SAlex Smith }
229d894fc60SAlex Smith
23076a09663SPaul Cercueil static struct jz4780_dma_desc *
jz4780_dma_desc_alloc(struct jz4780_dma_chan * jzchan,unsigned int count,enum dma_transaction_type type,enum dma_transfer_direction direction)23176a09663SPaul Cercueil jz4780_dma_desc_alloc(struct jz4780_dma_chan *jzchan, unsigned int count,
23276a09663SPaul Cercueil enum dma_transaction_type type,
23376a09663SPaul Cercueil enum dma_transfer_direction direction)
234d894fc60SAlex Smith {
235d894fc60SAlex Smith struct jz4780_dma_desc *desc;
236d894fc60SAlex Smith
237d894fc60SAlex Smith if (count > JZ_DMA_MAX_DESC)
238d894fc60SAlex Smith return NULL;
239d894fc60SAlex Smith
240d894fc60SAlex Smith desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
241d894fc60SAlex Smith if (!desc)
242d894fc60SAlex Smith return NULL;
243d894fc60SAlex Smith
244d894fc60SAlex Smith desc->desc = dma_pool_alloc(jzchan->desc_pool, GFP_NOWAIT,
245d894fc60SAlex Smith &desc->desc_phys);
246d894fc60SAlex Smith if (!desc->desc) {
247d894fc60SAlex Smith kfree(desc);
248d894fc60SAlex Smith return NULL;
249d894fc60SAlex Smith }
250d894fc60SAlex Smith
251d894fc60SAlex Smith desc->count = count;
252d894fc60SAlex Smith desc->type = type;
25376a09663SPaul Cercueil
25476a09663SPaul Cercueil if (direction == DMA_DEV_TO_MEM)
25576a09663SPaul Cercueil desc->transfer_type = jzchan->transfer_type_rx;
25676a09663SPaul Cercueil else
25776a09663SPaul Cercueil desc->transfer_type = jzchan->transfer_type_tx;
25876a09663SPaul Cercueil
259d894fc60SAlex Smith return desc;
260d894fc60SAlex Smith }
261d894fc60SAlex Smith
jz4780_dma_desc_free(struct virt_dma_desc * vdesc)262d894fc60SAlex Smith static void jz4780_dma_desc_free(struct virt_dma_desc *vdesc)
263d894fc60SAlex Smith {
264d894fc60SAlex Smith struct jz4780_dma_desc *desc = to_jz4780_dma_desc(vdesc);
265d894fc60SAlex Smith struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(vdesc->tx.chan);
266d894fc60SAlex Smith
267d894fc60SAlex Smith dma_pool_free(jzchan->desc_pool, desc->desc, desc->desc_phys);
268d894fc60SAlex Smith kfree(desc);
269d894fc60SAlex Smith }
270d894fc60SAlex Smith
jz4780_dma_transfer_size(struct jz4780_dma_chan * jzchan,unsigned long val,u32 * shift)271c8c0cda8SPaul Cercueil static u32 jz4780_dma_transfer_size(struct jz4780_dma_chan *jzchan,
272c8c0cda8SPaul Cercueil unsigned long val, u32 *shift)
273d894fc60SAlex Smith {
27429870eb7SPaul Cercueil struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan);
275dc578f31SAlex Smith int ord = ffs(val) - 1;
276d894fc60SAlex Smith
277dc578f31SAlex Smith /*
278dc578f31SAlex Smith * 8 byte transfer sizes unsupported so fall back on 4. If it's larger
279dc578f31SAlex Smith * than the maximum, just limit it. It is perfectly safe to fall back
280dc578f31SAlex Smith * in this way since we won't exceed the maximum burst size supported
281dc578f31SAlex Smith * by the device, the only effect is reduced efficiency. This is better
282dc578f31SAlex Smith * than refusing to perform the request at all.
283dc578f31SAlex Smith */
284dc578f31SAlex Smith if (ord == 3)
285dc578f31SAlex Smith ord = 2;
28629870eb7SPaul Cercueil else if (ord > jzdma->soc_data->transfer_ord_max)
28729870eb7SPaul Cercueil ord = jzdma->soc_data->transfer_ord_max;
288dc578f31SAlex Smith
289dc578f31SAlex Smith *shift = ord;
290dc578f31SAlex Smith
291dc578f31SAlex Smith switch (ord) {
292d894fc60SAlex Smith case 0:
293d894fc60SAlex Smith return JZ_DMA_SIZE_1_BYTE;
294d894fc60SAlex Smith case 1:
295d894fc60SAlex Smith return JZ_DMA_SIZE_2_BYTE;
296d894fc60SAlex Smith case 2:
297d894fc60SAlex Smith return JZ_DMA_SIZE_4_BYTE;
298d894fc60SAlex Smith case 4:
299d894fc60SAlex Smith return JZ_DMA_SIZE_16_BYTE;
300d894fc60SAlex Smith case 5:
301d894fc60SAlex Smith return JZ_DMA_SIZE_32_BYTE;
302d894fc60SAlex Smith case 6:
303d894fc60SAlex Smith return JZ_DMA_SIZE_64_BYTE;
304d894fc60SAlex Smith default:
305dc578f31SAlex Smith return JZ_DMA_SIZE_128_BYTE;
306d894fc60SAlex Smith }
307d894fc60SAlex Smith }
308d894fc60SAlex Smith
jz4780_dma_setup_hwdesc(struct jz4780_dma_chan * jzchan,struct jz4780_dma_hwdesc * desc,dma_addr_t addr,size_t len,enum dma_transfer_direction direction)309839896efSAlex Smith static int jz4780_dma_setup_hwdesc(struct jz4780_dma_chan *jzchan,
310d894fc60SAlex Smith struct jz4780_dma_hwdesc *desc, dma_addr_t addr, size_t len,
311d894fc60SAlex Smith enum dma_transfer_direction direction)
312d894fc60SAlex Smith {
313d894fc60SAlex Smith struct dma_slave_config *config = &jzchan->config;
314c8c0cda8SPaul Cercueil u32 width, maxburst, tsz;
315d894fc60SAlex Smith
316d894fc60SAlex Smith if (direction == DMA_MEM_TO_DEV) {
317d894fc60SAlex Smith desc->dcm = JZ_DMA_DCM_SAI;
318d894fc60SAlex Smith desc->dsa = addr;
319d894fc60SAlex Smith desc->dta = config->dst_addr;
320d894fc60SAlex Smith
321d894fc60SAlex Smith width = config->dst_addr_width;
322d894fc60SAlex Smith maxburst = config->dst_maxburst;
323d894fc60SAlex Smith } else {
324d894fc60SAlex Smith desc->dcm = JZ_DMA_DCM_DAI;
325d894fc60SAlex Smith desc->dsa = config->src_addr;
326d894fc60SAlex Smith desc->dta = addr;
327d894fc60SAlex Smith
328d894fc60SAlex Smith width = config->src_addr_width;
329d894fc60SAlex Smith maxburst = config->src_maxburst;
330d894fc60SAlex Smith }
331d894fc60SAlex Smith
332d894fc60SAlex Smith /*
333d894fc60SAlex Smith * This calculates the maximum transfer size that can be used with the
334d894fc60SAlex Smith * given address, length, width and maximum burst size. The address
335d894fc60SAlex Smith * must be aligned to the transfer size, the total length must be
336d894fc60SAlex Smith * divisible by the transfer size, and we must not use more than the
337d894fc60SAlex Smith * maximum burst specified by the user.
338d894fc60SAlex Smith */
33929870eb7SPaul Cercueil tsz = jz4780_dma_transfer_size(jzchan, addr | len | (width * maxburst),
340dc578f31SAlex Smith &jzchan->transfer_shift);
341d894fc60SAlex Smith
342d894fc60SAlex Smith switch (width) {
343d894fc60SAlex Smith case DMA_SLAVE_BUSWIDTH_1_BYTE:
344d894fc60SAlex Smith case DMA_SLAVE_BUSWIDTH_2_BYTES:
345d894fc60SAlex Smith break;
346d894fc60SAlex Smith case DMA_SLAVE_BUSWIDTH_4_BYTES:
347d894fc60SAlex Smith width = JZ_DMA_WIDTH_32_BIT;
348d894fc60SAlex Smith break;
349d894fc60SAlex Smith default:
350d894fc60SAlex Smith return -EINVAL;
351d894fc60SAlex Smith }
352d894fc60SAlex Smith
353d894fc60SAlex Smith desc->dcm |= tsz << JZ_DMA_DCM_TSZ_SHIFT;
354d894fc60SAlex Smith desc->dcm |= width << JZ_DMA_DCM_SP_SHIFT;
355d894fc60SAlex Smith desc->dcm |= width << JZ_DMA_DCM_DP_SHIFT;
356d894fc60SAlex Smith
357dc578f31SAlex Smith desc->dtc = len >> jzchan->transfer_shift;
358839896efSAlex Smith return 0;
359d894fc60SAlex Smith }
360d894fc60SAlex Smith
jz4780_dma_prep_slave_sg(struct dma_chan * chan,struct scatterlist * sgl,unsigned int sg_len,enum dma_transfer_direction direction,unsigned long flags,void * context)361d894fc60SAlex Smith static struct dma_async_tx_descriptor *jz4780_dma_prep_slave_sg(
362d894fc60SAlex Smith struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
36346fa5168SAlex Smith enum dma_transfer_direction direction, unsigned long flags,
36446fa5168SAlex Smith void *context)
365d894fc60SAlex Smith {
366d894fc60SAlex Smith struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
367f4c255f1SPaul Cercueil struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan);
368d894fc60SAlex Smith struct jz4780_dma_desc *desc;
369d894fc60SAlex Smith unsigned int i;
370d894fc60SAlex Smith int err;
371d894fc60SAlex Smith
37276a09663SPaul Cercueil desc = jz4780_dma_desc_alloc(jzchan, sg_len, DMA_SLAVE, direction);
373d894fc60SAlex Smith if (!desc)
374d894fc60SAlex Smith return NULL;
375d894fc60SAlex Smith
376d894fc60SAlex Smith for (i = 0; i < sg_len; i++) {
377d894fc60SAlex Smith err = jz4780_dma_setup_hwdesc(jzchan, &desc->desc[i],
378d894fc60SAlex Smith sg_dma_address(&sgl[i]),
379d894fc60SAlex Smith sg_dma_len(&sgl[i]),
380d894fc60SAlex Smith direction);
381fc878efeSColin Ian King if (err < 0) {
382fc878efeSColin Ian King jz4780_dma_desc_free(&jzchan->desc->vdesc);
383839896efSAlex Smith return NULL;
384fc878efeSColin Ian King }
385d894fc60SAlex Smith
386d894fc60SAlex Smith desc->desc[i].dcm |= JZ_DMA_DCM_TIE;
387d894fc60SAlex Smith
388f4c255f1SPaul Cercueil if (i != (sg_len - 1) &&
389f4c255f1SPaul Cercueil !(jzdma->soc_data->flags & JZ_SOC_DATA_BREAK_LINKS)) {
3900d7c11afSJulia Lawall /* Automatically proceed to the next descriptor. */
391d894fc60SAlex Smith desc->desc[i].dcm |= JZ_DMA_DCM_LINK;
392d894fc60SAlex Smith
393d894fc60SAlex Smith /*
394d894fc60SAlex Smith * The upper 8 bits of the DTC field in the descriptor
395d894fc60SAlex Smith * must be set to (offset from descriptor base of next
396d894fc60SAlex Smith * descriptor >> 4).
397d894fc60SAlex Smith */
398d894fc60SAlex Smith desc->desc[i].dtc |=
399d894fc60SAlex Smith (((i + 1) * sizeof(*desc->desc)) >> 4) << 24;
400d894fc60SAlex Smith }
401d894fc60SAlex Smith }
402d894fc60SAlex Smith
403d894fc60SAlex Smith return vchan_tx_prep(&jzchan->vchan, &desc->vdesc, flags);
404d894fc60SAlex Smith }
405d894fc60SAlex Smith
jz4780_dma_prep_dma_cyclic(struct dma_chan * chan,dma_addr_t buf_addr,size_t buf_len,size_t period_len,enum dma_transfer_direction direction,unsigned long flags)406d894fc60SAlex Smith static struct dma_async_tx_descriptor *jz4780_dma_prep_dma_cyclic(
407d894fc60SAlex Smith struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
408d894fc60SAlex Smith size_t period_len, enum dma_transfer_direction direction,
409d894fc60SAlex Smith unsigned long flags)
410d894fc60SAlex Smith {
411d894fc60SAlex Smith struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
412d894fc60SAlex Smith struct jz4780_dma_desc *desc;
413d894fc60SAlex Smith unsigned int periods, i;
414d894fc60SAlex Smith int err;
415d894fc60SAlex Smith
416d894fc60SAlex Smith if (buf_len % period_len)
417d894fc60SAlex Smith return NULL;
418d894fc60SAlex Smith
419d894fc60SAlex Smith periods = buf_len / period_len;
420d894fc60SAlex Smith
42176a09663SPaul Cercueil desc = jz4780_dma_desc_alloc(jzchan, periods, DMA_CYCLIC, direction);
422d894fc60SAlex Smith if (!desc)
423d894fc60SAlex Smith return NULL;
424d894fc60SAlex Smith
425d894fc60SAlex Smith for (i = 0; i < periods; i++) {
426d894fc60SAlex Smith err = jz4780_dma_setup_hwdesc(jzchan, &desc->desc[i], buf_addr,
427d894fc60SAlex Smith period_len, direction);
428fc878efeSColin Ian King if (err < 0) {
429fc878efeSColin Ian King jz4780_dma_desc_free(&jzchan->desc->vdesc);
430839896efSAlex Smith return NULL;
431fc878efeSColin Ian King }
432d894fc60SAlex Smith
433d894fc60SAlex Smith buf_addr += period_len;
434d894fc60SAlex Smith
435d894fc60SAlex Smith /*
436d894fc60SAlex Smith * Set the link bit to indicate that the controller should
437d894fc60SAlex Smith * automatically proceed to the next descriptor. In
438d894fc60SAlex Smith * jz4780_dma_begin(), this will be cleared if we need to issue
439d894fc60SAlex Smith * an interrupt after each period.
440d894fc60SAlex Smith */
441d894fc60SAlex Smith desc->desc[i].dcm |= JZ_DMA_DCM_TIE | JZ_DMA_DCM_LINK;
442d894fc60SAlex Smith
443d894fc60SAlex Smith /*
444d894fc60SAlex Smith * The upper 8 bits of the DTC field in the descriptor must be
445d894fc60SAlex Smith * set to (offset from descriptor base of next descriptor >> 4).
446d894fc60SAlex Smith * If this is the last descriptor, link it back to the first,
447d894fc60SAlex Smith * i.e. leave offset set to 0, otherwise point to the next one.
448d894fc60SAlex Smith */
449d894fc60SAlex Smith if (i != (periods - 1)) {
450d894fc60SAlex Smith desc->desc[i].dtc |=
451d894fc60SAlex Smith (((i + 1) * sizeof(*desc->desc)) >> 4) << 24;
452d894fc60SAlex Smith }
453d894fc60SAlex Smith }
454d894fc60SAlex Smith
455d894fc60SAlex Smith return vchan_tx_prep(&jzchan->vchan, &desc->vdesc, flags);
456d894fc60SAlex Smith }
457d894fc60SAlex Smith
jz4780_dma_prep_dma_memcpy(struct dma_chan * chan,dma_addr_t dest,dma_addr_t src,size_t len,unsigned long flags)4584f5db8c8SVinod Koul static struct dma_async_tx_descriptor *jz4780_dma_prep_dma_memcpy(
459d894fc60SAlex Smith struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
460d894fc60SAlex Smith size_t len, unsigned long flags)
461d894fc60SAlex Smith {
462d894fc60SAlex Smith struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
463d894fc60SAlex Smith struct jz4780_dma_desc *desc;
464c8c0cda8SPaul Cercueil u32 tsz;
465d894fc60SAlex Smith
46676a09663SPaul Cercueil desc = jz4780_dma_desc_alloc(jzchan, 1, DMA_MEMCPY, 0);
467d894fc60SAlex Smith if (!desc)
468d894fc60SAlex Smith return NULL;
469d894fc60SAlex Smith
47029870eb7SPaul Cercueil tsz = jz4780_dma_transfer_size(jzchan, dest | src | len,
471dc578f31SAlex Smith &jzchan->transfer_shift);
472d894fc60SAlex Smith
47376a09663SPaul Cercueil desc->transfer_type = JZ_DMA_DRT_AUTO;
4745eed7d84SPaul Cercueil
475d894fc60SAlex Smith desc->desc[0].dsa = src;
476d894fc60SAlex Smith desc->desc[0].dta = dest;
477d894fc60SAlex Smith desc->desc[0].dcm = JZ_DMA_DCM_TIE | JZ_DMA_DCM_SAI | JZ_DMA_DCM_DAI |
478d894fc60SAlex Smith tsz << JZ_DMA_DCM_TSZ_SHIFT |
479d894fc60SAlex Smith JZ_DMA_WIDTH_32_BIT << JZ_DMA_DCM_SP_SHIFT |
480d894fc60SAlex Smith JZ_DMA_WIDTH_32_BIT << JZ_DMA_DCM_DP_SHIFT;
481839896efSAlex Smith desc->desc[0].dtc = len >> jzchan->transfer_shift;
482d894fc60SAlex Smith
483d894fc60SAlex Smith return vchan_tx_prep(&jzchan->vchan, &desc->vdesc, flags);
484d894fc60SAlex Smith }
485d894fc60SAlex Smith
jz4780_dma_begin(struct jz4780_dma_chan * jzchan)486d894fc60SAlex Smith static void jz4780_dma_begin(struct jz4780_dma_chan *jzchan)
487d894fc60SAlex Smith {
488d894fc60SAlex Smith struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan);
489d894fc60SAlex Smith struct virt_dma_desc *vdesc;
490d894fc60SAlex Smith unsigned int i;
491d894fc60SAlex Smith dma_addr_t desc_phys;
492d894fc60SAlex Smith
493d894fc60SAlex Smith if (!jzchan->desc) {
494d894fc60SAlex Smith vdesc = vchan_next_desc(&jzchan->vchan);
495d894fc60SAlex Smith if (!vdesc)
496d894fc60SAlex Smith return;
497d894fc60SAlex Smith
498d894fc60SAlex Smith list_del(&vdesc->node);
499d894fc60SAlex Smith
500d894fc60SAlex Smith jzchan->desc = to_jz4780_dma_desc(vdesc);
501d894fc60SAlex Smith jzchan->curr_hwdesc = 0;
502d894fc60SAlex Smith
503d894fc60SAlex Smith if (jzchan->desc->type == DMA_CYCLIC && vdesc->tx.callback) {
504d894fc60SAlex Smith /*
505d894fc60SAlex Smith * The DMA controller doesn't support triggering an
506d894fc60SAlex Smith * interrupt after processing each descriptor, only
507d894fc60SAlex Smith * after processing an entire terminated list of
508d894fc60SAlex Smith * descriptors. For a cyclic DMA setup the list of
509d894fc60SAlex Smith * descriptors is not terminated so we can never get an
510d894fc60SAlex Smith * interrupt.
511d894fc60SAlex Smith *
512d894fc60SAlex Smith * If the user requested a callback for a cyclic DMA
513d894fc60SAlex Smith * setup then we workaround this hardware limitation
514d894fc60SAlex Smith * here by degrading to a set of unlinked descriptors
515d894fc60SAlex Smith * which we will submit in sequence in response to the
516d894fc60SAlex Smith * completion of processing the previous descriptor.
517d894fc60SAlex Smith */
518d894fc60SAlex Smith for (i = 0; i < jzchan->desc->count; i++)
519d894fc60SAlex Smith jzchan->desc->desc[i].dcm &= ~JZ_DMA_DCM_LINK;
520d894fc60SAlex Smith }
521d894fc60SAlex Smith } else {
522d894fc60SAlex Smith /*
523d894fc60SAlex Smith * There is an existing transfer, therefore this must be one
524d894fc60SAlex Smith * for which we unlinked the descriptors above. Advance to the
525d894fc60SAlex Smith * next one in the list.
526d894fc60SAlex Smith */
527d894fc60SAlex Smith jzchan->curr_hwdesc =
528d894fc60SAlex Smith (jzchan->curr_hwdesc + 1) % jzchan->desc->count;
529d894fc60SAlex Smith }
530d894fc60SAlex Smith
53129870eb7SPaul Cercueil /* Enable the channel's clock. */
53229870eb7SPaul Cercueil jz4780_dma_chan_enable(jzdma, jzchan->id);
53329870eb7SPaul Cercueil
5345eed7d84SPaul Cercueil /* Use 4-word descriptors. */
5355eed7d84SPaul Cercueil jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DCS, 0);
5365eed7d84SPaul Cercueil
5375eed7d84SPaul Cercueil /* Set transfer type. */
5385eed7d84SPaul Cercueil jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DRT,
53976a09663SPaul Cercueil jzchan->desc->transfer_type);
540d894fc60SAlex Smith
5419e4e3a4cSDaniel Silsby /*
5429e4e3a4cSDaniel Silsby * Set the transfer count. This is redundant for a descriptor-driven
5439e4e3a4cSDaniel Silsby * transfer. However, there can be a delay between the transfer start
5449e4e3a4cSDaniel Silsby * time and when DTCn reg contains the new transfer count. Setting
5459e4e3a4cSDaniel Silsby * it explicitly ensures residue is computed correctly at all times.
5469e4e3a4cSDaniel Silsby */
5479e4e3a4cSDaniel Silsby jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DTC,
5489e4e3a4cSDaniel Silsby jzchan->desc->desc[jzchan->curr_hwdesc].dtc);
549d894fc60SAlex Smith
550d894fc60SAlex Smith /* Write descriptor address and initiate descriptor fetch. */
551d894fc60SAlex Smith desc_phys = jzchan->desc->desc_phys +
552d894fc60SAlex Smith (jzchan->curr_hwdesc * sizeof(*jzchan->desc->desc));
55333633583SPaul Cercueil jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DDA, desc_phys);
55433633583SPaul Cercueil jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DDRS, BIT(jzchan->id));
555d894fc60SAlex Smith
556d894fc60SAlex Smith /* Enable the channel. */
55733633583SPaul Cercueil jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DCS,
5585eed7d84SPaul Cercueil JZ_DMA_DCS_CTE);
559d894fc60SAlex Smith }
560d894fc60SAlex Smith
jz4780_dma_issue_pending(struct dma_chan * chan)561d894fc60SAlex Smith static void jz4780_dma_issue_pending(struct dma_chan *chan)
562d894fc60SAlex Smith {
563d894fc60SAlex Smith struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
564d894fc60SAlex Smith unsigned long flags;
565d894fc60SAlex Smith
566d894fc60SAlex Smith spin_lock_irqsave(&jzchan->vchan.lock, flags);
567d894fc60SAlex Smith
568d894fc60SAlex Smith if (vchan_issue_pending(&jzchan->vchan) && !jzchan->desc)
569d894fc60SAlex Smith jz4780_dma_begin(jzchan);
570d894fc60SAlex Smith
571d894fc60SAlex Smith spin_unlock_irqrestore(&jzchan->vchan.lock, flags);
572d894fc60SAlex Smith }
573d894fc60SAlex Smith
jz4780_dma_terminate_all(struct dma_chan * chan)57446fa5168SAlex Smith static int jz4780_dma_terminate_all(struct dma_chan *chan)
575d894fc60SAlex Smith {
57646fa5168SAlex Smith struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
577d894fc60SAlex Smith struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan);
578d894fc60SAlex Smith unsigned long flags;
579d894fc60SAlex Smith LIST_HEAD(head);
580d894fc60SAlex Smith
581d894fc60SAlex Smith spin_lock_irqsave(&jzchan->vchan.lock, flags);
582d894fc60SAlex Smith
583d894fc60SAlex Smith /* Clear the DMA status and stop the transfer. */
58433633583SPaul Cercueil jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DCS, 0);
585d894fc60SAlex Smith if (jzchan->desc) {
586f0dd52c8SPeter Ujfalusi vchan_terminate_vdesc(&jzchan->desc->vdesc);
587d894fc60SAlex Smith jzchan->desc = NULL;
588d894fc60SAlex Smith }
589d894fc60SAlex Smith
59029870eb7SPaul Cercueil jz4780_dma_chan_disable(jzdma, jzchan->id);
59129870eb7SPaul Cercueil
592d894fc60SAlex Smith vchan_get_all_descriptors(&jzchan->vchan, &head);
593d894fc60SAlex Smith
594d894fc60SAlex Smith spin_unlock_irqrestore(&jzchan->vchan.lock, flags);
595d894fc60SAlex Smith
596d894fc60SAlex Smith vchan_dma_desc_free_list(&jzchan->vchan, &head);
597d894fc60SAlex Smith return 0;
598d894fc60SAlex Smith }
599d894fc60SAlex Smith
jz4780_dma_synchronize(struct dma_chan * chan)600f0dd52c8SPeter Ujfalusi static void jz4780_dma_synchronize(struct dma_chan *chan)
601f0dd52c8SPeter Ujfalusi {
602f0dd52c8SPeter Ujfalusi struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
60329870eb7SPaul Cercueil struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan);
604f0dd52c8SPeter Ujfalusi
605f0dd52c8SPeter Ujfalusi vchan_synchronize(&jzchan->vchan);
60629870eb7SPaul Cercueil jz4780_dma_chan_disable(jzdma, jzchan->id);
607f0dd52c8SPeter Ujfalusi }
608f0dd52c8SPeter Ujfalusi
jz4780_dma_config(struct dma_chan * chan,struct dma_slave_config * config)60946fa5168SAlex Smith static int jz4780_dma_config(struct dma_chan *chan,
61046fa5168SAlex Smith struct dma_slave_config *config)
611d894fc60SAlex Smith {
61246fa5168SAlex Smith struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
61346fa5168SAlex Smith
614d894fc60SAlex Smith if ((config->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
615d894fc60SAlex Smith || (config->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES))
616d894fc60SAlex Smith return -EINVAL;
617d894fc60SAlex Smith
618d894fc60SAlex Smith /* Copy the reset of the slave configuration, it is used later. */
619d894fc60SAlex Smith memcpy(&jzchan->config, config, sizeof(jzchan->config));
620d894fc60SAlex Smith
621d894fc60SAlex Smith return 0;
622d894fc60SAlex Smith }
623d894fc60SAlex Smith
jz4780_dma_desc_residue(struct jz4780_dma_chan * jzchan,struct jz4780_dma_desc * desc,unsigned int next_sg)624d894fc60SAlex Smith static size_t jz4780_dma_desc_residue(struct jz4780_dma_chan *jzchan,
625d894fc60SAlex Smith struct jz4780_dma_desc *desc, unsigned int next_sg)
626d894fc60SAlex Smith {
627d894fc60SAlex Smith struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan);
628f3c045dfSDaniel Silsby unsigned int count = 0;
629d894fc60SAlex Smith unsigned int i;
630d894fc60SAlex Smith
631d894fc60SAlex Smith for (i = next_sg; i < desc->count; i++)
632f3c045dfSDaniel Silsby count += desc->desc[i].dtc & GENMASK(23, 0);
633d894fc60SAlex Smith
634f3c045dfSDaniel Silsby if (next_sg != 0)
635f3c045dfSDaniel Silsby count += jz4780_dma_chn_readl(jzdma, jzchan->id,
63633633583SPaul Cercueil JZ_DMA_REG_DTC);
637d894fc60SAlex Smith
638f3c045dfSDaniel Silsby return count << jzchan->transfer_shift;
639d894fc60SAlex Smith }
640d894fc60SAlex Smith
jz4780_dma_tx_status(struct dma_chan * chan,dma_cookie_t cookie,struct dma_tx_state * txstate)641d894fc60SAlex Smith static enum dma_status jz4780_dma_tx_status(struct dma_chan *chan,
642d894fc60SAlex Smith dma_cookie_t cookie, struct dma_tx_state *txstate)
643d894fc60SAlex Smith {
644d894fc60SAlex Smith struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
645d894fc60SAlex Smith struct virt_dma_desc *vdesc;
646d894fc60SAlex Smith enum dma_status status;
647d894fc60SAlex Smith unsigned long flags;
6481f0b0f23SDaniel Silsby unsigned long residue = 0;
649d894fc60SAlex Smith
650baf6fd97SPaul Cercueil spin_lock_irqsave(&jzchan->vchan.lock, flags);
651baf6fd97SPaul Cercueil
652d894fc60SAlex Smith status = dma_cookie_status(chan, cookie, txstate);
653d894fc60SAlex Smith if ((status == DMA_COMPLETE) || (txstate == NULL))
654baf6fd97SPaul Cercueil goto out_unlock_irqrestore;
655d894fc60SAlex Smith
656d894fc60SAlex Smith vdesc = vchan_find_desc(&jzchan->vchan, cookie);
657d894fc60SAlex Smith if (vdesc) {
658d894fc60SAlex Smith /* On the issued list, so hasn't been processed yet */
6591f0b0f23SDaniel Silsby residue = jz4780_dma_desc_residue(jzchan,
660d894fc60SAlex Smith to_jz4780_dma_desc(vdesc), 0);
661d894fc60SAlex Smith } else if (cookie == jzchan->desc->vdesc.tx.cookie) {
6621f0b0f23SDaniel Silsby residue = jz4780_dma_desc_residue(jzchan, jzchan->desc,
66383ef4fb7SDaniel Silsby jzchan->curr_hwdesc + 1);
6641f0b0f23SDaniel Silsby }
6651f0b0f23SDaniel Silsby dma_set_residue(txstate, residue);
666d894fc60SAlex Smith
667d894fc60SAlex Smith if (vdesc && jzchan->desc && vdesc == &jzchan->desc->vdesc
668d894fc60SAlex Smith && jzchan->desc->status & (JZ_DMA_DCS_AR | JZ_DMA_DCS_HLT))
669d894fc60SAlex Smith status = DMA_ERROR;
670d894fc60SAlex Smith
671baf6fd97SPaul Cercueil out_unlock_irqrestore:
672d894fc60SAlex Smith spin_unlock_irqrestore(&jzchan->vchan.lock, flags);
673d894fc60SAlex Smith return status;
674d894fc60SAlex Smith }
675d894fc60SAlex Smith
jz4780_dma_chan_irq(struct jz4780_dma_dev * jzdma,struct jz4780_dma_chan * jzchan)6764e4106f5SPaul Cercueil static bool jz4780_dma_chan_irq(struct jz4780_dma_dev *jzdma,
677d894fc60SAlex Smith struct jz4780_dma_chan *jzchan)
678d894fc60SAlex Smith {
679f4c255f1SPaul Cercueil const unsigned int soc_flags = jzdma->soc_data->flags;
680f4c255f1SPaul Cercueil struct jz4780_dma_desc *desc = jzchan->desc;
681c8c0cda8SPaul Cercueil u32 dcs;
6824e4106f5SPaul Cercueil bool ack = true;
683d894fc60SAlex Smith
684d894fc60SAlex Smith spin_lock(&jzchan->vchan.lock);
685d894fc60SAlex Smith
68633633583SPaul Cercueil dcs = jz4780_dma_chn_readl(jzdma, jzchan->id, JZ_DMA_REG_DCS);
68733633583SPaul Cercueil jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DCS, 0);
688d894fc60SAlex Smith
689d894fc60SAlex Smith if (dcs & JZ_DMA_DCS_AR) {
690d894fc60SAlex Smith dev_warn(&jzchan->vchan.chan.dev->device,
691d894fc60SAlex Smith "address error (DCS=0x%x)\n", dcs);
692d894fc60SAlex Smith }
693d894fc60SAlex Smith
694d894fc60SAlex Smith if (dcs & JZ_DMA_DCS_HLT) {
695d894fc60SAlex Smith dev_warn(&jzchan->vchan.chan.dev->device,
696d894fc60SAlex Smith "channel halt (DCS=0x%x)\n", dcs);
697d894fc60SAlex Smith }
698d894fc60SAlex Smith
699d894fc60SAlex Smith if (jzchan->desc) {
700d894fc60SAlex Smith jzchan->desc->status = dcs;
701d894fc60SAlex Smith
702d894fc60SAlex Smith if ((dcs & (JZ_DMA_DCS_AR | JZ_DMA_DCS_HLT)) == 0) {
703d894fc60SAlex Smith if (jzchan->desc->type == DMA_CYCLIC) {
704d894fc60SAlex Smith vchan_cyclic_callback(&jzchan->desc->vdesc);
705d894fc60SAlex Smith
706d894fc60SAlex Smith jz4780_dma_begin(jzchan);
7074e4106f5SPaul Cercueil } else if (dcs & JZ_DMA_DCS_TT) {
708f4c255f1SPaul Cercueil if (!(soc_flags & JZ_SOC_DATA_BREAK_LINKS) ||
709f4c255f1SPaul Cercueil (jzchan->curr_hwdesc + 1 == desc->count)) {
710f4c255f1SPaul Cercueil vchan_cookie_complete(&desc->vdesc);
7114e4106f5SPaul Cercueil jzchan->desc = NULL;
712f4c255f1SPaul Cercueil }
7134e4106f5SPaul Cercueil
7144e4106f5SPaul Cercueil jz4780_dma_begin(jzchan);
7154e4106f5SPaul Cercueil } else {
7164e4106f5SPaul Cercueil /* False positive - continue the transfer */
7174e4106f5SPaul Cercueil ack = false;
7184e4106f5SPaul Cercueil jz4780_dma_chn_writel(jzdma, jzchan->id,
7194e4106f5SPaul Cercueil JZ_DMA_REG_DCS,
7204e4106f5SPaul Cercueil JZ_DMA_DCS_CTE);
7214e4106f5SPaul Cercueil }
722d894fc60SAlex Smith }
723d894fc60SAlex Smith } else {
724d894fc60SAlex Smith dev_err(&jzchan->vchan.chan.dev->device,
725d894fc60SAlex Smith "channel IRQ with no active transfer\n");
726d894fc60SAlex Smith }
727d894fc60SAlex Smith
728d894fc60SAlex Smith spin_unlock(&jzchan->vchan.lock);
7294e4106f5SPaul Cercueil
7304e4106f5SPaul Cercueil return ack;
731d894fc60SAlex Smith }
732d894fc60SAlex Smith
jz4780_dma_irq_handler(int irq,void * data)733d894fc60SAlex Smith static irqreturn_t jz4780_dma_irq_handler(int irq, void *data)
734d894fc60SAlex Smith {
735d894fc60SAlex Smith struct jz4780_dma_dev *jzdma = data;
7364e4106f5SPaul Cercueil unsigned int nb_channels = jzdma->soc_data->nb_channels;
7374c89cc73SDan Carpenter unsigned long pending;
738c8c0cda8SPaul Cercueil u32 dmac;
739d894fc60SAlex Smith int i;
740d894fc60SAlex Smith
74133633583SPaul Cercueil pending = jz4780_dma_ctrl_readl(jzdma, JZ_DMA_REG_DIRQP);
742d894fc60SAlex Smith
7434c89cc73SDan Carpenter for_each_set_bit(i, &pending, nb_channels) {
7444e4106f5SPaul Cercueil if (jz4780_dma_chan_irq(jzdma, &jzdma->chan[i]))
7454e4106f5SPaul Cercueil pending &= ~BIT(i);
746d894fc60SAlex Smith }
747d894fc60SAlex Smith
748d894fc60SAlex Smith /* Clear halt and address error status of all channels. */
74933633583SPaul Cercueil dmac = jz4780_dma_ctrl_readl(jzdma, JZ_DMA_REG_DMAC);
750d894fc60SAlex Smith dmac &= ~(JZ_DMA_DMAC_HLT | JZ_DMA_DMAC_AR);
75133633583SPaul Cercueil jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DMAC, dmac);
752d894fc60SAlex Smith
753d894fc60SAlex Smith /* Clear interrupt pending status. */
7544e4106f5SPaul Cercueil jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DIRQP, pending);
755d894fc60SAlex Smith
756d894fc60SAlex Smith return IRQ_HANDLED;
757d894fc60SAlex Smith }
758d894fc60SAlex Smith
jz4780_dma_alloc_chan_resources(struct dma_chan * chan)759d894fc60SAlex Smith static int jz4780_dma_alloc_chan_resources(struct dma_chan *chan)
760d894fc60SAlex Smith {
761d894fc60SAlex Smith struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
762d894fc60SAlex Smith
763d894fc60SAlex Smith jzchan->desc_pool = dma_pool_create(dev_name(&chan->dev->device),
764d894fc60SAlex Smith chan->device->dev,
765d894fc60SAlex Smith JZ_DMA_DESC_BLOCK_SIZE,
766d894fc60SAlex Smith PAGE_SIZE, 0);
767d894fc60SAlex Smith if (!jzchan->desc_pool) {
768d894fc60SAlex Smith dev_err(&chan->dev->device,
769d894fc60SAlex Smith "failed to allocate descriptor pool\n");
770d894fc60SAlex Smith return -ENOMEM;
771d894fc60SAlex Smith }
772d894fc60SAlex Smith
773d894fc60SAlex Smith return 0;
774d894fc60SAlex Smith }
775d894fc60SAlex Smith
jz4780_dma_free_chan_resources(struct dma_chan * chan)776d894fc60SAlex Smith static void jz4780_dma_free_chan_resources(struct dma_chan *chan)
777d894fc60SAlex Smith {
778d894fc60SAlex Smith struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
779d894fc60SAlex Smith
780d894fc60SAlex Smith vchan_free_chan_resources(&jzchan->vchan);
781d894fc60SAlex Smith dma_pool_destroy(jzchan->desc_pool);
782d894fc60SAlex Smith jzchan->desc_pool = NULL;
783d894fc60SAlex Smith }
784d894fc60SAlex Smith
jz4780_dma_filter_fn(struct dma_chan * chan,void * param)785d894fc60SAlex Smith static bool jz4780_dma_filter_fn(struct dma_chan *chan, void *param)
786d894fc60SAlex Smith {
787d894fc60SAlex Smith struct jz4780_dma_chan *jzchan = to_jz4780_dma_chan(chan);
788d894fc60SAlex Smith struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan);
789026fd406SAlex Smith struct jz4780_dma_filter_data *data = param;
790026fd406SAlex Smith
791d894fc60SAlex Smith
792d894fc60SAlex Smith if (data->channel > -1) {
793d894fc60SAlex Smith if (data->channel != jzchan->id)
794d894fc60SAlex Smith return false;
795d894fc60SAlex Smith } else if (jzdma->chan_reserved & BIT(jzchan->id)) {
796d894fc60SAlex Smith return false;
797d894fc60SAlex Smith }
798d894fc60SAlex Smith
79976a09663SPaul Cercueil jzchan->transfer_type_tx = data->transfer_type_tx;
80076a09663SPaul Cercueil jzchan->transfer_type_rx = data->transfer_type_rx;
801d894fc60SAlex Smith
802d894fc60SAlex Smith return true;
803d894fc60SAlex Smith }
804d894fc60SAlex Smith
jz4780_of_dma_xlate(struct of_phandle_args * dma_spec,struct of_dma * ofdma)805d894fc60SAlex Smith static struct dma_chan *jz4780_of_dma_xlate(struct of_phandle_args *dma_spec,
806d894fc60SAlex Smith struct of_dma *ofdma)
807d894fc60SAlex Smith {
808d894fc60SAlex Smith struct jz4780_dma_dev *jzdma = ofdma->of_dma_data;
809d894fc60SAlex Smith dma_cap_mask_t mask = jzdma->dma_device.cap_mask;
810026fd406SAlex Smith struct jz4780_dma_filter_data data;
811d894fc60SAlex Smith
81276a09663SPaul Cercueil if (dma_spec->args_count == 2) {
81376a09663SPaul Cercueil data.transfer_type_tx = dma_spec->args[0];
81476a09663SPaul Cercueil data.transfer_type_rx = dma_spec->args[0];
815d894fc60SAlex Smith data.channel = dma_spec->args[1];
81676a09663SPaul Cercueil } else if (dma_spec->args_count == 3) {
81776a09663SPaul Cercueil data.transfer_type_tx = dma_spec->args[0];
81876a09663SPaul Cercueil data.transfer_type_rx = dma_spec->args[1];
81976a09663SPaul Cercueil data.channel = dma_spec->args[2];
82076a09663SPaul Cercueil } else {
82176a09663SPaul Cercueil return NULL;
82276a09663SPaul Cercueil }
823d894fc60SAlex Smith
824d894fc60SAlex Smith if (data.channel > -1) {
8256147b032SPaul Cercueil if (data.channel >= jzdma->soc_data->nb_channels) {
826d894fc60SAlex Smith dev_err(jzdma->dma_device.dev,
827d894fc60SAlex Smith "device requested non-existent channel %u\n",
828d894fc60SAlex Smith data.channel);
829d894fc60SAlex Smith return NULL;
830d894fc60SAlex Smith }
831d894fc60SAlex Smith
832d894fc60SAlex Smith /* Can only select a channel marked as reserved. */
833d894fc60SAlex Smith if (!(jzdma->chan_reserved & BIT(data.channel))) {
834d894fc60SAlex Smith dev_err(jzdma->dma_device.dev,
835d894fc60SAlex Smith "device requested unreserved channel %u\n",
836d894fc60SAlex Smith data.channel);
837d894fc60SAlex Smith return NULL;
838d894fc60SAlex Smith }
839d894fc60SAlex Smith
84076a09663SPaul Cercueil jzdma->chan[data.channel].transfer_type_tx = data.transfer_type_tx;
84176a09663SPaul Cercueil jzdma->chan[data.channel].transfer_type_rx = data.transfer_type_rx;
842d3273e10SAlex Smith
843d3273e10SAlex Smith return dma_get_slave_channel(
844d3273e10SAlex Smith &jzdma->chan[data.channel].vchan.chan);
845d3273e10SAlex Smith } else {
846c88ba7b9SBaolin Wang return __dma_request_channel(&mask, jz4780_dma_filter_fn, &data,
847c88ba7b9SBaolin Wang ofdma->of_node);
848d894fc60SAlex Smith }
849d3273e10SAlex Smith }
850d894fc60SAlex Smith
jz4780_dma_probe(struct platform_device * pdev)851d894fc60SAlex Smith static int jz4780_dma_probe(struct platform_device *pdev)
852d894fc60SAlex Smith {
853d894fc60SAlex Smith struct device *dev = &pdev->dev;
8546147b032SPaul Cercueil const struct jz4780_dma_soc_data *soc_data;
855d894fc60SAlex Smith struct jz4780_dma_dev *jzdma;
856d894fc60SAlex Smith struct jz4780_dma_chan *jzchan;
857d894fc60SAlex Smith struct dma_device *dd;
858d894fc60SAlex Smith struct resource *res;
859d894fc60SAlex Smith int i, ret;
860d894fc60SAlex Smith
86154f919a0SPaul Cercueil if (!dev->of_node) {
86254f919a0SPaul Cercueil dev_err(dev, "This driver must be probed from devicetree\n");
86354f919a0SPaul Cercueil return -EINVAL;
86454f919a0SPaul Cercueil }
86554f919a0SPaul Cercueil
8666147b032SPaul Cercueil soc_data = device_get_match_data(dev);
8676147b032SPaul Cercueil if (!soc_data)
8686147b032SPaul Cercueil return -EINVAL;
8696147b032SPaul Cercueil
870ed414d58SGustavo A. R. Silva jzdma = devm_kzalloc(dev, struct_size(jzdma, chan,
871ed414d58SGustavo A. R. Silva soc_data->nb_channels), GFP_KERNEL);
872d894fc60SAlex Smith if (!jzdma)
873d894fc60SAlex Smith return -ENOMEM;
874d894fc60SAlex Smith
8756147b032SPaul Cercueil jzdma->soc_data = soc_data;
876d894fc60SAlex Smith platform_set_drvdata(pdev, jzdma);
877d894fc60SAlex Smith
8781148ac67SMarkus Elfring jzdma->chn_base = devm_platform_ioremap_resource(pdev, 0);
87933633583SPaul Cercueil if (IS_ERR(jzdma->chn_base))
88033633583SPaul Cercueil return PTR_ERR(jzdma->chn_base);
88133633583SPaul Cercueil
88233633583SPaul Cercueil res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
88333633583SPaul Cercueil if (res) {
88433633583SPaul Cercueil jzdma->ctrl_base = devm_ioremap_resource(dev, res);
88533633583SPaul Cercueil if (IS_ERR(jzdma->ctrl_base))
88633633583SPaul Cercueil return PTR_ERR(jzdma->ctrl_base);
88729870eb7SPaul Cercueil } else if (soc_data->flags & JZ_SOC_DATA_ALLOW_LEGACY_DT) {
88833633583SPaul Cercueil /*
88933633583SPaul Cercueil * On JZ4780, if the second memory resource was not supplied,
89033633583SPaul Cercueil * assume we're using an old devicetree, and calculate the
89133633583SPaul Cercueil * offset to the control registers.
89233633583SPaul Cercueil */
89333633583SPaul Cercueil jzdma->ctrl_base = jzdma->chn_base + JZ4780_DMA_CTRL_OFFSET;
89429870eb7SPaul Cercueil } else {
89529870eb7SPaul Cercueil dev_err(dev, "failed to get I/O memory\n");
89629870eb7SPaul Cercueil return -EINVAL;
89733633583SPaul Cercueil }
898d894fc60SAlex Smith
899d894fc60SAlex Smith jzdma->clk = devm_clk_get(dev, NULL);
900d894fc60SAlex Smith if (IS_ERR(jzdma->clk)) {
901d894fc60SAlex Smith dev_err(dev, "failed to get clock\n");
902d509a83cSAlex Smith ret = PTR_ERR(jzdma->clk);
9036d6018fcSMadhuparna Bhowmik return ret;
904d894fc60SAlex Smith }
905d894fc60SAlex Smith
906d894fc60SAlex Smith clk_prepare_enable(jzdma->clk);
907d894fc60SAlex Smith
908d894fc60SAlex Smith /* Property is optional, if it doesn't exist the value will remain 0. */
909d894fc60SAlex Smith of_property_read_u32_index(dev->of_node, "ingenic,reserved-channels",
910d894fc60SAlex Smith 0, &jzdma->chan_reserved);
911d894fc60SAlex Smith
912d894fc60SAlex Smith dd = &jzdma->dma_device;
913d894fc60SAlex Smith
9142128565aSAidan MacDonald /*
9152128565aSAidan MacDonald * The real segment size limit is dependent on the size unit selected
9162128565aSAidan MacDonald * for the transfer. Because the size unit is selected automatically
9172128565aSAidan MacDonald * and may be as small as 1 byte, use a safe limit of 2^24-1 bytes to
9182128565aSAidan MacDonald * ensure the 24-bit transfer count in the descriptor cannot overflow.
9192128565aSAidan MacDonald */
9202128565aSAidan MacDonald dma_set_max_seg_size(dev, 0xffffff);
9212128565aSAidan MacDonald
922d894fc60SAlex Smith dma_cap_set(DMA_MEMCPY, dd->cap_mask);
923d894fc60SAlex Smith dma_cap_set(DMA_SLAVE, dd->cap_mask);
924d894fc60SAlex Smith dma_cap_set(DMA_CYCLIC, dd->cap_mask);
925d894fc60SAlex Smith
926d894fc60SAlex Smith dd->dev = dev;
92777a68e56SMaxime Ripard dd->copy_align = DMAENGINE_ALIGN_4_BYTES;
928d894fc60SAlex Smith dd->device_alloc_chan_resources = jz4780_dma_alloc_chan_resources;
929d894fc60SAlex Smith dd->device_free_chan_resources = jz4780_dma_free_chan_resources;
930d894fc60SAlex Smith dd->device_prep_slave_sg = jz4780_dma_prep_slave_sg;
931d894fc60SAlex Smith dd->device_prep_dma_cyclic = jz4780_dma_prep_dma_cyclic;
932d894fc60SAlex Smith dd->device_prep_dma_memcpy = jz4780_dma_prep_dma_memcpy;
93346fa5168SAlex Smith dd->device_config = jz4780_dma_config;
934d894fc60SAlex Smith dd->device_terminate_all = jz4780_dma_terminate_all;
935f0dd52c8SPeter Ujfalusi dd->device_synchronize = jz4780_dma_synchronize;
936d894fc60SAlex Smith dd->device_tx_status = jz4780_dma_tx_status;
937d894fc60SAlex Smith dd->device_issue_pending = jz4780_dma_issue_pending;
938d894fc60SAlex Smith dd->src_addr_widths = JZ_DMA_BUSWIDTHS;
939d894fc60SAlex Smith dd->dst_addr_widths = JZ_DMA_BUSWIDTHS;
940d894fc60SAlex Smith dd->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
941d894fc60SAlex Smith dd->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
942d59f7037SArtur Rojek dd->max_sg_burst = JZ_DMA_MAX_DESC;
943d894fc60SAlex Smith
944d894fc60SAlex Smith /*
945d894fc60SAlex Smith * Enable DMA controller, mark all channels as not programmable.
946d894fc60SAlex Smith * Also set the FMSC bit - it increases MSC performance, so it makes
947d894fc60SAlex Smith * little sense not to enable it.
948d894fc60SAlex Smith */
94917a8e30eSPaul Cercueil jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DMAC, JZ_DMA_DMAC_DMAE |
95017a8e30eSPaul Cercueil JZ_DMA_DMAC_FAIC | JZ_DMA_DMAC_FMSC);
95129870eb7SPaul Cercueil
95229870eb7SPaul Cercueil if (soc_data->flags & JZ_SOC_DATA_PROGRAMMABLE_DMA)
95333633583SPaul Cercueil jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DMACP, 0);
954d894fc60SAlex Smith
955d894fc60SAlex Smith INIT_LIST_HEAD(&dd->channels);
956d894fc60SAlex Smith
9576147b032SPaul Cercueil for (i = 0; i < soc_data->nb_channels; i++) {
958d894fc60SAlex Smith jzchan = &jzdma->chan[i];
959d894fc60SAlex Smith jzchan->id = i;
960d894fc60SAlex Smith
961d894fc60SAlex Smith vchan_init(&jzchan->vchan, dd);
962d894fc60SAlex Smith jzchan->vchan.desc_free = jz4780_dma_desc_free;
963d894fc60SAlex Smith }
964d894fc60SAlex Smith
965b72cbb1aSPaul Cercueil /*
966b72cbb1aSPaul Cercueil * On JZ4760, chan0 won't enable properly the first time.
967b72cbb1aSPaul Cercueil * Enabling then disabling chan1 will magically make chan0 work
968b72cbb1aSPaul Cercueil * correctly.
969b72cbb1aSPaul Cercueil */
970b72cbb1aSPaul Cercueil jz4780_dma_chan_enable(jzdma, 1);
971b72cbb1aSPaul Cercueil jz4780_dma_chan_disable(jzdma, 1);
972b72cbb1aSPaul Cercueil
9736d6018fcSMadhuparna Bhowmik ret = platform_get_irq(pdev, 0);
9746d6018fcSMadhuparna Bhowmik if (ret < 0)
9756d6018fcSMadhuparna Bhowmik goto err_disable_clk;
9766d6018fcSMadhuparna Bhowmik
9776d6018fcSMadhuparna Bhowmik jzdma->irq = ret;
9786d6018fcSMadhuparna Bhowmik
9796d6018fcSMadhuparna Bhowmik ret = request_irq(jzdma->irq, jz4780_dma_irq_handler, 0, dev_name(dev),
9806d6018fcSMadhuparna Bhowmik jzdma);
9816d6018fcSMadhuparna Bhowmik if (ret) {
9826d6018fcSMadhuparna Bhowmik dev_err(dev, "failed to request IRQ %u!\n", jzdma->irq);
9836d6018fcSMadhuparna Bhowmik goto err_disable_clk;
9846d6018fcSMadhuparna Bhowmik }
9856d6018fcSMadhuparna Bhowmik
9860f5a5e57SHuang Shijie ret = dmaenginem_async_device_register(dd);
987d894fc60SAlex Smith if (ret) {
988d894fc60SAlex Smith dev_err(dev, "failed to register device\n");
9896d6018fcSMadhuparna Bhowmik goto err_free_irq;
990d894fc60SAlex Smith }
991d894fc60SAlex Smith
992d894fc60SAlex Smith /* Register with OF DMA helpers. */
993d894fc60SAlex Smith ret = of_dma_controller_register(dev->of_node, jz4780_of_dma_xlate,
994d894fc60SAlex Smith jzdma);
995d894fc60SAlex Smith if (ret) {
996d894fc60SAlex Smith dev_err(dev, "failed to register OF DMA controller\n");
9976d6018fcSMadhuparna Bhowmik goto err_free_irq;
998d894fc60SAlex Smith }
999d894fc60SAlex Smith
1000d894fc60SAlex Smith dev_info(dev, "JZ4780 DMA controller initialised\n");
1001d894fc60SAlex Smith return 0;
1002d894fc60SAlex Smith
1003d509a83cSAlex Smith err_free_irq:
1004d509a83cSAlex Smith free_irq(jzdma->irq, jzdma);
10056d6018fcSMadhuparna Bhowmik
10066d6018fcSMadhuparna Bhowmik err_disable_clk:
10076d6018fcSMadhuparna Bhowmik clk_disable_unprepare(jzdma->clk);
1008d894fc60SAlex Smith return ret;
1009d894fc60SAlex Smith }
1010d894fc60SAlex Smith
jz4780_dma_remove(struct platform_device * pdev)1011d894fc60SAlex Smith static int jz4780_dma_remove(struct platform_device *pdev)
1012d894fc60SAlex Smith {
1013d894fc60SAlex Smith struct jz4780_dma_dev *jzdma = platform_get_drvdata(pdev);
1014ae9c02b4SAlex Smith int i;
1015d894fc60SAlex Smith
1016d894fc60SAlex Smith of_dma_controller_free(pdev->dev.of_node);
1017ae9c02b4SAlex Smith
10189568fedaSChuhong Yuan clk_disable_unprepare(jzdma->clk);
1019d509a83cSAlex Smith free_irq(jzdma->irq, jzdma);
1020ae9c02b4SAlex Smith
10216147b032SPaul Cercueil for (i = 0; i < jzdma->soc_data->nb_channels; i++)
1022ae9c02b4SAlex Smith tasklet_kill(&jzdma->chan[i].vchan.task);
1023ae9c02b4SAlex Smith
1024d894fc60SAlex Smith return 0;
1025d894fc60SAlex Smith }
1026d894fc60SAlex Smith
1027ffaaa8ccSPaul Cercueil static const struct jz4780_dma_soc_data jz4740_dma_soc_data = {
1028ffaaa8ccSPaul Cercueil .nb_channels = 6,
1029ffaaa8ccSPaul Cercueil .transfer_ord_max = 5,
1030f4c255f1SPaul Cercueil .flags = JZ_SOC_DATA_BREAK_LINKS,
1031ffaaa8ccSPaul Cercueil };
1032ffaaa8ccSPaul Cercueil
1033ae9156b6SPaul Cercueil static const struct jz4780_dma_soc_data jz4725b_dma_soc_data = {
1034ae9156b6SPaul Cercueil .nb_channels = 6,
1035ae9156b6SPaul Cercueil .transfer_ord_max = 5,
1036a40c94beSPaul Cercueil .flags = JZ_SOC_DATA_PER_CHAN_PM | JZ_SOC_DATA_NO_DCKES_DCKEC |
1037a40c94beSPaul Cercueil JZ_SOC_DATA_BREAK_LINKS,
1038ae9156b6SPaul Cercueil };
1039ae9156b6SPaul Cercueil
1040*042427eaSSiarhei Volkau static const struct jz4780_dma_soc_data jz4755_dma_soc_data = {
1041*042427eaSSiarhei Volkau .nb_channels = 4,
1042*042427eaSSiarhei Volkau .transfer_ord_max = 5,
1043*042427eaSSiarhei Volkau .flags = JZ_SOC_DATA_PER_CHAN_PM | JZ_SOC_DATA_NO_DCKES_DCKEC |
1044*042427eaSSiarhei Volkau JZ_SOC_DATA_BREAK_LINKS,
1045*042427eaSSiarhei Volkau };
1046*042427eaSSiarhei Volkau
1047d2852a3eSPaul Cercueil static const struct jz4780_dma_soc_data jz4760_dma_soc_data = {
1048d2852a3eSPaul Cercueil .nb_channels = 5,
1049d2852a3eSPaul Cercueil .transfer_ord_max = 6,
1050d2852a3eSPaul Cercueil .flags = JZ_SOC_DATA_PER_CHAN_PM | JZ_SOC_DATA_NO_DCKES_DCKEC,
1051d2852a3eSPaul Cercueil };
1052d2852a3eSPaul Cercueil
10533d70fccfSPaul Cercueil static const struct jz4780_dma_soc_data jz4760_mdma_soc_data = {
10543d70fccfSPaul Cercueil .nb_channels = 2,
10553d70fccfSPaul Cercueil .transfer_ord_max = 6,
10563d70fccfSPaul Cercueil .flags = JZ_SOC_DATA_PER_CHAN_PM | JZ_SOC_DATA_NO_DCKES_DCKEC,
10573d70fccfSPaul Cercueil };
10583d70fccfSPaul Cercueil
10593d70fccfSPaul Cercueil static const struct jz4780_dma_soc_data jz4760_bdma_soc_data = {
10603d70fccfSPaul Cercueil .nb_channels = 3,
10613d70fccfSPaul Cercueil .transfer_ord_max = 6,
10623d70fccfSPaul Cercueil .flags = JZ_SOC_DATA_PER_CHAN_PM | JZ_SOC_DATA_NO_DCKES_DCKEC,
10633d70fccfSPaul Cercueil };
10643d70fccfSPaul Cercueil
1065d2852a3eSPaul Cercueil static const struct jz4780_dma_soc_data jz4760b_dma_soc_data = {
1066d2852a3eSPaul Cercueil .nb_channels = 5,
1067d2852a3eSPaul Cercueil .transfer_ord_max = 6,
1068d2852a3eSPaul Cercueil .flags = JZ_SOC_DATA_PER_CHAN_PM,
1069d2852a3eSPaul Cercueil };
1070d2852a3eSPaul Cercueil
10713d70fccfSPaul Cercueil static const struct jz4780_dma_soc_data jz4760b_mdma_soc_data = {
10723d70fccfSPaul Cercueil .nb_channels = 2,
10733d70fccfSPaul Cercueil .transfer_ord_max = 6,
10743d70fccfSPaul Cercueil .flags = JZ_SOC_DATA_PER_CHAN_PM,
10753d70fccfSPaul Cercueil };
10763d70fccfSPaul Cercueil
10773d70fccfSPaul Cercueil static const struct jz4780_dma_soc_data jz4760b_bdma_soc_data = {
10783d70fccfSPaul Cercueil .nb_channels = 3,
10793d70fccfSPaul Cercueil .transfer_ord_max = 6,
10803d70fccfSPaul Cercueil .flags = JZ_SOC_DATA_PER_CHAN_PM,
10813d70fccfSPaul Cercueil };
10823d70fccfSPaul Cercueil
108329870eb7SPaul Cercueil static const struct jz4780_dma_soc_data jz4770_dma_soc_data = {
108429870eb7SPaul Cercueil .nb_channels = 6,
108529870eb7SPaul Cercueil .transfer_ord_max = 6,
108629870eb7SPaul Cercueil .flags = JZ_SOC_DATA_PER_CHAN_PM,
108729870eb7SPaul Cercueil };
108829870eb7SPaul Cercueil
10896147b032SPaul Cercueil static const struct jz4780_dma_soc_data jz4780_dma_soc_data = {
10906147b032SPaul Cercueil .nb_channels = 32,
109129870eb7SPaul Cercueil .transfer_ord_max = 7,
109229870eb7SPaul Cercueil .flags = JZ_SOC_DATA_ALLOW_LEGACY_DT | JZ_SOC_DATA_PROGRAMMABLE_DMA,
10936147b032SPaul Cercueil };
10946147b032SPaul Cercueil
1095fee175e4SZhou Yanjie static const struct jz4780_dma_soc_data x1000_dma_soc_data = {
1096fee175e4SZhou Yanjie .nb_channels = 8,
1097fee175e4SZhou Yanjie .transfer_ord_max = 7,
1098fee175e4SZhou Yanjie .flags = JZ_SOC_DATA_PROGRAMMABLE_DMA,
1099fee175e4SZhou Yanjie };
1100fee175e4SZhou Yanjie
110120f5a659S周琰杰 (Zhou Yanjie) static const struct jz4780_dma_soc_data x1830_dma_soc_data = {
110220f5a659S周琰杰 (Zhou Yanjie) .nb_channels = 32,
110320f5a659S周琰杰 (Zhou Yanjie) .transfer_ord_max = 7,
110420f5a659S周琰杰 (Zhou Yanjie) .flags = JZ_SOC_DATA_PROGRAMMABLE_DMA,
110520f5a659S周琰杰 (Zhou Yanjie) };
110620f5a659S周琰杰 (Zhou Yanjie)
1107d894fc60SAlex Smith static const struct of_device_id jz4780_dma_dt_match[] = {
1108ffaaa8ccSPaul Cercueil { .compatible = "ingenic,jz4740-dma", .data = &jz4740_dma_soc_data },
1109ae9156b6SPaul Cercueil { .compatible = "ingenic,jz4725b-dma", .data = &jz4725b_dma_soc_data },
1110*042427eaSSiarhei Volkau { .compatible = "ingenic,jz4755-dma", .data = &jz4755_dma_soc_data },
1111d2852a3eSPaul Cercueil { .compatible = "ingenic,jz4760-dma", .data = &jz4760_dma_soc_data },
11123d70fccfSPaul Cercueil { .compatible = "ingenic,jz4760-mdma", .data = &jz4760_mdma_soc_data },
11133d70fccfSPaul Cercueil { .compatible = "ingenic,jz4760-bdma", .data = &jz4760_bdma_soc_data },
1114d2852a3eSPaul Cercueil { .compatible = "ingenic,jz4760b-dma", .data = &jz4760b_dma_soc_data },
11153d70fccfSPaul Cercueil { .compatible = "ingenic,jz4760b-mdma", .data = &jz4760b_mdma_soc_data },
11163d70fccfSPaul Cercueil { .compatible = "ingenic,jz4760b-bdma", .data = &jz4760b_bdma_soc_data },
111729870eb7SPaul Cercueil { .compatible = "ingenic,jz4770-dma", .data = &jz4770_dma_soc_data },
11186147b032SPaul Cercueil { .compatible = "ingenic,jz4780-dma", .data = &jz4780_dma_soc_data },
1119fee175e4SZhou Yanjie { .compatible = "ingenic,x1000-dma", .data = &x1000_dma_soc_data },
112020f5a659S周琰杰 (Zhou Yanjie) { .compatible = "ingenic,x1830-dma", .data = &x1830_dma_soc_data },
1121d894fc60SAlex Smith {},
1122d894fc60SAlex Smith };
1123d894fc60SAlex Smith MODULE_DEVICE_TABLE(of, jz4780_dma_dt_match);
1124d894fc60SAlex Smith
1125d894fc60SAlex Smith static struct platform_driver jz4780_dma_driver = {
1126d894fc60SAlex Smith .probe = jz4780_dma_probe,
1127d894fc60SAlex Smith .remove = jz4780_dma_remove,
1128d894fc60SAlex Smith .driver = {
1129d894fc60SAlex Smith .name = "jz4780-dma",
1130255c2cc8SKrzysztof Kozlowski .of_match_table = jz4780_dma_dt_match,
1131d894fc60SAlex Smith },
1132d894fc60SAlex Smith };
1133d894fc60SAlex Smith
jz4780_dma_init(void)1134d894fc60SAlex Smith static int __init jz4780_dma_init(void)
1135d894fc60SAlex Smith {
1136d894fc60SAlex Smith return platform_driver_register(&jz4780_dma_driver);
1137d894fc60SAlex Smith }
1138d894fc60SAlex Smith subsys_initcall(jz4780_dma_init);
1139d894fc60SAlex Smith
jz4780_dma_exit(void)1140d894fc60SAlex Smith static void __exit jz4780_dma_exit(void)
1141d894fc60SAlex Smith {
1142d894fc60SAlex Smith platform_driver_unregister(&jz4780_dma_driver);
1143d894fc60SAlex Smith }
1144d894fc60SAlex Smith module_exit(jz4780_dma_exit);
1145d894fc60SAlex Smith
1146d894fc60SAlex Smith MODULE_AUTHOR("Alex Smith <alex@alex-smith.me.uk>");
1147d894fc60SAlex Smith MODULE_DESCRIPTION("Ingenic JZ4780 DMA controller driver");
1148d894fc60SAlex Smith MODULE_LICENSE("GPL");
1149