1 /* 2 * BCM2835 DMA engine support 3 * 4 * This driver only supports cyclic DMA transfers 5 * as needed for the I2S module. 6 * 7 * Author: Florian Meier <florian.meier@koalo.de> 8 * Copyright 2013 9 * 10 * Based on 11 * OMAP DMAengine support by Russell King 12 * 13 * BCM2708 DMA Driver 14 * Copyright (C) 2010 Broadcom 15 * 16 * Raspberry Pi PCM I2S ALSA Driver 17 * Copyright (c) by Phil Poole 2013 18 * 19 * MARVELL MMP Peripheral DMA Driver 20 * Copyright 2012 Marvell International Ltd. 21 * 22 * This program is free software; you can redistribute it and/or modify 23 * it under the terms of the GNU General Public License as published by 24 * the Free Software Foundation; either version 2 of the License, or 25 * (at your option) any later version. 26 * 27 * This program is distributed in the hope that it will be useful, 28 * but WITHOUT ANY WARRANTY; without even the implied warranty of 29 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 30 * GNU General Public License for more details. 31 */ 32 #include <linux/dmaengine.h> 33 #include <linux/dma-mapping.h> 34 #include <linux/dmapool.h> 35 #include <linux/err.h> 36 #include <linux/init.h> 37 #include <linux/interrupt.h> 38 #include <linux/list.h> 39 #include <linux/module.h> 40 #include <linux/platform_device.h> 41 #include <linux/slab.h> 42 #include <linux/io.h> 43 #include <linux/spinlock.h> 44 #include <linux/of.h> 45 #include <linux/of_dma.h> 46 47 #include "virt-dma.h" 48 49 #define BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED 14 50 #define BCM2835_DMA_CHAN_NAME_SIZE 8 51 52 struct bcm2835_dmadev { 53 struct dma_device ddev; 54 spinlock_t lock; 55 void __iomem *base; 56 struct device_dma_parameters dma_parms; 57 }; 58 59 struct bcm2835_dma_cb { 60 uint32_t info; 61 uint32_t src; 62 uint32_t dst; 63 uint32_t length; 64 uint32_t stride; 65 uint32_t next; 66 uint32_t pad[2]; 67 }; 68 69 struct bcm2835_cb_entry { 70 struct bcm2835_dma_cb *cb; 71 dma_addr_t paddr; 72 }; 73 74 struct bcm2835_chan { 75 struct virt_dma_chan vc; 76 struct list_head node; 77 78 struct dma_slave_config cfg; 79 unsigned int dreq; 80 81 int ch; 82 struct bcm2835_desc *desc; 83 struct dma_pool *cb_pool; 84 85 void __iomem *chan_base; 86 int irq_number; 87 unsigned int irq_flags; 88 89 bool is_lite_channel; 90 }; 91 92 struct bcm2835_desc { 93 struct bcm2835_chan *c; 94 struct virt_dma_desc vd; 95 enum dma_transfer_direction dir; 96 97 unsigned int frames; 98 size_t size; 99 100 bool cyclic; 101 102 struct bcm2835_cb_entry cb_list[]; 103 }; 104 105 #define BCM2835_DMA_CS 0x00 106 #define BCM2835_DMA_ADDR 0x04 107 #define BCM2835_DMA_TI 0x08 108 #define BCM2835_DMA_SOURCE_AD 0x0c 109 #define BCM2835_DMA_DEST_AD 0x10 110 #define BCM2835_DMA_LEN 0x14 111 #define BCM2835_DMA_STRIDE 0x18 112 #define BCM2835_DMA_NEXTCB 0x1c 113 #define BCM2835_DMA_DEBUG 0x20 114 115 /* DMA CS Control and Status bits */ 116 #define BCM2835_DMA_ACTIVE BIT(0) /* activate the DMA */ 117 #define BCM2835_DMA_END BIT(1) /* current CB has ended */ 118 #define BCM2835_DMA_INT BIT(2) /* interrupt status */ 119 #define BCM2835_DMA_DREQ BIT(3) /* DREQ state */ 120 #define BCM2835_DMA_ISPAUSED BIT(4) /* Pause requested or not active */ 121 #define BCM2835_DMA_ISHELD BIT(5) /* Is held by DREQ flow control */ 122 #define BCM2835_DMA_WAITING_FOR_WRITES BIT(6) /* waiting for last 123 * AXI-write to ack 124 */ 125 #define BCM2835_DMA_ERR BIT(8) 126 #define BCM2835_DMA_PRIORITY(x) ((x & 15) << 16) /* AXI priority */ 127 #define BCM2835_DMA_PANIC_PRIORITY(x) ((x & 15) << 20) /* panic priority */ 128 /* current value of TI.BCM2835_DMA_WAIT_RESP */ 129 #define BCM2835_DMA_WAIT_FOR_WRITES BIT(28) 130 #define BCM2835_DMA_DIS_DEBUG BIT(29) /* disable debug pause signal */ 131 #define BCM2835_DMA_ABORT BIT(30) /* Stop current CB, go to next, WO */ 132 #define BCM2835_DMA_RESET BIT(31) /* WO, self clearing */ 133 134 /* Transfer information bits - also bcm2835_cb.info field */ 135 #define BCM2835_DMA_INT_EN BIT(0) 136 #define BCM2835_DMA_TDMODE BIT(1) /* 2D-Mode */ 137 #define BCM2835_DMA_WAIT_RESP BIT(3) /* wait for AXI-write to be acked */ 138 #define BCM2835_DMA_D_INC BIT(4) 139 #define BCM2835_DMA_D_WIDTH BIT(5) /* 128bit writes if set */ 140 #define BCM2835_DMA_D_DREQ BIT(6) /* enable DREQ for destination */ 141 #define BCM2835_DMA_D_IGNORE BIT(7) /* ignore destination writes */ 142 #define BCM2835_DMA_S_INC BIT(8) 143 #define BCM2835_DMA_S_WIDTH BIT(9) /* 128bit writes if set */ 144 #define BCM2835_DMA_S_DREQ BIT(10) /* enable SREQ for source */ 145 #define BCM2835_DMA_S_IGNORE BIT(11) /* ignore source reads - read 0 */ 146 #define BCM2835_DMA_BURST_LENGTH(x) ((x & 15) << 12) 147 #define BCM2835_DMA_PER_MAP(x) ((x & 31) << 16) /* REQ source */ 148 #define BCM2835_DMA_WAIT(x) ((x & 31) << 21) /* add DMA-wait cycles */ 149 #define BCM2835_DMA_NO_WIDE_BURSTS BIT(26) /* no 2 beat write bursts */ 150 151 /* debug register bits */ 152 #define BCM2835_DMA_DEBUG_LAST_NOT_SET_ERR BIT(0) 153 #define BCM2835_DMA_DEBUG_FIFO_ERR BIT(1) 154 #define BCM2835_DMA_DEBUG_READ_ERR BIT(2) 155 #define BCM2835_DMA_DEBUG_OUTSTANDING_WRITES_SHIFT 4 156 #define BCM2835_DMA_DEBUG_OUTSTANDING_WRITES_BITS 4 157 #define BCM2835_DMA_DEBUG_ID_SHIFT 16 158 #define BCM2835_DMA_DEBUG_ID_BITS 9 159 #define BCM2835_DMA_DEBUG_STATE_SHIFT 16 160 #define BCM2835_DMA_DEBUG_STATE_BITS 9 161 #define BCM2835_DMA_DEBUG_VERSION_SHIFT 25 162 #define BCM2835_DMA_DEBUG_VERSION_BITS 3 163 #define BCM2835_DMA_DEBUG_LITE BIT(28) 164 165 /* shared registers for all dma channels */ 166 #define BCM2835_DMA_INT_STATUS 0xfe0 167 #define BCM2835_DMA_ENABLE 0xff0 168 169 #define BCM2835_DMA_DATA_TYPE_S8 1 170 #define BCM2835_DMA_DATA_TYPE_S16 2 171 #define BCM2835_DMA_DATA_TYPE_S32 4 172 #define BCM2835_DMA_DATA_TYPE_S128 16 173 174 /* Valid only for channels 0 - 14, 15 has its own base address */ 175 #define BCM2835_DMA_CHAN(n) ((n) << 8) /* Base address */ 176 #define BCM2835_DMA_CHANIO(base, n) ((base) + BCM2835_DMA_CHAN(n)) 177 178 /* the max dma length for different channels */ 179 #define MAX_DMA_LEN SZ_1G 180 #define MAX_LITE_DMA_LEN (SZ_64K - 4) 181 182 static inline size_t bcm2835_dma_max_frame_length(struct bcm2835_chan *c) 183 { 184 /* lite and normal channels have different max frame length */ 185 return c->is_lite_channel ? MAX_LITE_DMA_LEN : MAX_DMA_LEN; 186 } 187 188 /* how many frames of max_len size do we need to transfer len bytes */ 189 static inline size_t bcm2835_dma_frames_for_length(size_t len, 190 size_t max_len) 191 { 192 return DIV_ROUND_UP(len, max_len); 193 } 194 195 static inline struct bcm2835_dmadev *to_bcm2835_dma_dev(struct dma_device *d) 196 { 197 return container_of(d, struct bcm2835_dmadev, ddev); 198 } 199 200 static inline struct bcm2835_chan *to_bcm2835_dma_chan(struct dma_chan *c) 201 { 202 return container_of(c, struct bcm2835_chan, vc.chan); 203 } 204 205 static inline struct bcm2835_desc *to_bcm2835_dma_desc( 206 struct dma_async_tx_descriptor *t) 207 { 208 return container_of(t, struct bcm2835_desc, vd.tx); 209 } 210 211 static void bcm2835_dma_free_cb_chain(struct bcm2835_desc *desc) 212 { 213 size_t i; 214 215 for (i = 0; i < desc->frames; i++) 216 dma_pool_free(desc->c->cb_pool, desc->cb_list[i].cb, 217 desc->cb_list[i].paddr); 218 219 kfree(desc); 220 } 221 222 static void bcm2835_dma_desc_free(struct virt_dma_desc *vd) 223 { 224 bcm2835_dma_free_cb_chain( 225 container_of(vd, struct bcm2835_desc, vd)); 226 } 227 228 static void bcm2835_dma_create_cb_set_length( 229 struct bcm2835_chan *chan, 230 struct bcm2835_dma_cb *control_block, 231 size_t len, 232 size_t period_len, 233 size_t *total_len, 234 u32 finalextrainfo) 235 { 236 size_t max_len = bcm2835_dma_max_frame_length(chan); 237 238 /* set the length taking lite-channel limitations into account */ 239 control_block->length = min_t(u32, len, max_len); 240 241 /* finished if we have no period_length */ 242 if (!period_len) 243 return; 244 245 /* 246 * period_len means: that we need to generate 247 * transfers that are terminating at every 248 * multiple of period_len - this is typically 249 * used to set the interrupt flag in info 250 * which is required during cyclic transfers 251 */ 252 253 /* have we filled in period_length yet? */ 254 if (*total_len + control_block->length < period_len) { 255 /* update number of bytes in this period so far */ 256 *total_len += control_block->length; 257 return; 258 } 259 260 /* calculate the length that remains to reach period_length */ 261 control_block->length = period_len - *total_len; 262 263 /* reset total_length for next period */ 264 *total_len = 0; 265 266 /* add extrainfo bits in info */ 267 control_block->info |= finalextrainfo; 268 } 269 270 static inline size_t bcm2835_dma_count_frames_for_sg( 271 struct bcm2835_chan *c, 272 struct scatterlist *sgl, 273 unsigned int sg_len) 274 { 275 size_t frames = 0; 276 struct scatterlist *sgent; 277 unsigned int i; 278 size_t plength = bcm2835_dma_max_frame_length(c); 279 280 for_each_sg(sgl, sgent, sg_len, i) 281 frames += bcm2835_dma_frames_for_length( 282 sg_dma_len(sgent), plength); 283 284 return frames; 285 } 286 287 /** 288 * bcm2835_dma_create_cb_chain - create a control block and fills data in 289 * 290 * @chan: the @dma_chan for which we run this 291 * @direction: the direction in which we transfer 292 * @cyclic: it is a cyclic transfer 293 * @info: the default info bits to apply per controlblock 294 * @frames: number of controlblocks to allocate 295 * @src: the src address to assign (if the S_INC bit is set 296 * in @info, then it gets incremented) 297 * @dst: the dst address to assign (if the D_INC bit is set 298 * in @info, then it gets incremented) 299 * @buf_len: the full buffer length (may also be 0) 300 * @period_len: the period length when to apply @finalextrainfo 301 * in addition to the last transfer 302 * this will also break some control-blocks early 303 * @finalextrainfo: additional bits in last controlblock 304 * (or when period_len is reached in case of cyclic) 305 * @gfp: the GFP flag to use for allocation 306 */ 307 static struct bcm2835_desc *bcm2835_dma_create_cb_chain( 308 struct dma_chan *chan, enum dma_transfer_direction direction, 309 bool cyclic, u32 info, u32 finalextrainfo, size_t frames, 310 dma_addr_t src, dma_addr_t dst, size_t buf_len, 311 size_t period_len, gfp_t gfp) 312 { 313 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); 314 size_t len = buf_len, total_len; 315 size_t frame; 316 struct bcm2835_desc *d; 317 struct bcm2835_cb_entry *cb_entry; 318 struct bcm2835_dma_cb *control_block; 319 320 if (!frames) 321 return NULL; 322 323 /* allocate and setup the descriptor. */ 324 d = kzalloc(sizeof(*d) + frames * sizeof(struct bcm2835_cb_entry), 325 gfp); 326 if (!d) 327 return NULL; 328 329 d->c = c; 330 d->dir = direction; 331 d->cyclic = cyclic; 332 333 /* 334 * Iterate over all frames, create a control block 335 * for each frame and link them together. 336 */ 337 for (frame = 0, total_len = 0; frame < frames; d->frames++, frame++) { 338 cb_entry = &d->cb_list[frame]; 339 cb_entry->cb = dma_pool_alloc(c->cb_pool, gfp, 340 &cb_entry->paddr); 341 if (!cb_entry->cb) 342 goto error_cb; 343 344 /* fill in the control block */ 345 control_block = cb_entry->cb; 346 control_block->info = info; 347 control_block->src = src; 348 control_block->dst = dst; 349 control_block->stride = 0; 350 control_block->next = 0; 351 /* set up length in control_block if requested */ 352 if (buf_len) { 353 /* calculate length honoring period_length */ 354 bcm2835_dma_create_cb_set_length( 355 c, control_block, 356 len, period_len, &total_len, 357 cyclic ? finalextrainfo : 0); 358 359 /* calculate new remaining length */ 360 len -= control_block->length; 361 } 362 363 /* link this the last controlblock */ 364 if (frame) 365 d->cb_list[frame - 1].cb->next = cb_entry->paddr; 366 367 /* update src and dst and length */ 368 if (src && (info & BCM2835_DMA_S_INC)) 369 src += control_block->length; 370 if (dst && (info & BCM2835_DMA_D_INC)) 371 dst += control_block->length; 372 373 /* Length of total transfer */ 374 d->size += control_block->length; 375 } 376 377 /* the last frame requires extra flags */ 378 d->cb_list[d->frames - 1].cb->info |= finalextrainfo; 379 380 /* detect a size missmatch */ 381 if (buf_len && (d->size != buf_len)) 382 goto error_cb; 383 384 return d; 385 error_cb: 386 bcm2835_dma_free_cb_chain(d); 387 388 return NULL; 389 } 390 391 static void bcm2835_dma_fill_cb_chain_with_sg( 392 struct dma_chan *chan, 393 enum dma_transfer_direction direction, 394 struct bcm2835_cb_entry *cb, 395 struct scatterlist *sgl, 396 unsigned int sg_len) 397 { 398 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); 399 size_t len, max_len; 400 unsigned int i; 401 dma_addr_t addr; 402 struct scatterlist *sgent; 403 404 max_len = bcm2835_dma_max_frame_length(c); 405 for_each_sg(sgl, sgent, sg_len, i) { 406 for (addr = sg_dma_address(sgent), len = sg_dma_len(sgent); 407 len > 0; 408 addr += cb->cb->length, len -= cb->cb->length, cb++) { 409 if (direction == DMA_DEV_TO_MEM) 410 cb->cb->dst = addr; 411 else 412 cb->cb->src = addr; 413 cb->cb->length = min(len, max_len); 414 } 415 } 416 } 417 418 static int bcm2835_dma_abort(void __iomem *chan_base) 419 { 420 unsigned long cs; 421 long int timeout = 10000; 422 423 cs = readl(chan_base + BCM2835_DMA_CS); 424 if (!(cs & BCM2835_DMA_ACTIVE)) 425 return 0; 426 427 /* Write 0 to the active bit - Pause the DMA */ 428 writel(0, chan_base + BCM2835_DMA_CS); 429 430 /* Wait for any current AXI transfer to complete */ 431 while ((cs & BCM2835_DMA_ISPAUSED) && --timeout) { 432 cpu_relax(); 433 cs = readl(chan_base + BCM2835_DMA_CS); 434 } 435 436 /* We'll un-pause when we set of our next DMA */ 437 if (!timeout) 438 return -ETIMEDOUT; 439 440 if (!(cs & BCM2835_DMA_ACTIVE)) 441 return 0; 442 443 /* Terminate the control block chain */ 444 writel(0, chan_base + BCM2835_DMA_NEXTCB); 445 446 /* Abort the whole DMA */ 447 writel(BCM2835_DMA_ABORT | BCM2835_DMA_ACTIVE, 448 chan_base + BCM2835_DMA_CS); 449 450 return 0; 451 } 452 453 static void bcm2835_dma_start_desc(struct bcm2835_chan *c) 454 { 455 struct virt_dma_desc *vd = vchan_next_desc(&c->vc); 456 struct bcm2835_desc *d; 457 458 if (!vd) { 459 c->desc = NULL; 460 return; 461 } 462 463 list_del(&vd->node); 464 465 c->desc = d = to_bcm2835_dma_desc(&vd->tx); 466 467 writel(d->cb_list[0].paddr, c->chan_base + BCM2835_DMA_ADDR); 468 writel(BCM2835_DMA_ACTIVE, c->chan_base + BCM2835_DMA_CS); 469 } 470 471 static irqreturn_t bcm2835_dma_callback(int irq, void *data) 472 { 473 struct bcm2835_chan *c = data; 474 struct bcm2835_desc *d; 475 unsigned long flags; 476 477 /* check the shared interrupt */ 478 if (c->irq_flags & IRQF_SHARED) { 479 /* check if the interrupt is enabled */ 480 flags = readl(c->chan_base + BCM2835_DMA_CS); 481 /* if not set then we are not the reason for the irq */ 482 if (!(flags & BCM2835_DMA_INT)) 483 return IRQ_NONE; 484 } 485 486 spin_lock_irqsave(&c->vc.lock, flags); 487 488 /* Acknowledge interrupt */ 489 writel(BCM2835_DMA_INT, c->chan_base + BCM2835_DMA_CS); 490 491 d = c->desc; 492 493 if (d) { 494 if (d->cyclic) { 495 /* call the cyclic callback */ 496 vchan_cyclic_callback(&d->vd); 497 498 /* Keep the DMA engine running */ 499 writel(BCM2835_DMA_ACTIVE, 500 c->chan_base + BCM2835_DMA_CS); 501 } else { 502 vchan_cookie_complete(&c->desc->vd); 503 bcm2835_dma_start_desc(c); 504 } 505 } 506 507 spin_unlock_irqrestore(&c->vc.lock, flags); 508 509 return IRQ_HANDLED; 510 } 511 512 static int bcm2835_dma_alloc_chan_resources(struct dma_chan *chan) 513 { 514 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); 515 struct device *dev = c->vc.chan.device->dev; 516 517 dev_dbg(dev, "Allocating DMA channel %d\n", c->ch); 518 519 c->cb_pool = dma_pool_create(dev_name(dev), dev, 520 sizeof(struct bcm2835_dma_cb), 0, 0); 521 if (!c->cb_pool) { 522 dev_err(dev, "unable to allocate descriptor pool\n"); 523 return -ENOMEM; 524 } 525 526 return request_irq(c->irq_number, bcm2835_dma_callback, 527 c->irq_flags, "DMA IRQ", c); 528 } 529 530 static void bcm2835_dma_free_chan_resources(struct dma_chan *chan) 531 { 532 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); 533 534 vchan_free_chan_resources(&c->vc); 535 free_irq(c->irq_number, c); 536 dma_pool_destroy(c->cb_pool); 537 538 dev_dbg(c->vc.chan.device->dev, "Freeing DMA channel %u\n", c->ch); 539 } 540 541 static size_t bcm2835_dma_desc_size(struct bcm2835_desc *d) 542 { 543 return d->size; 544 } 545 546 static size_t bcm2835_dma_desc_size_pos(struct bcm2835_desc *d, dma_addr_t addr) 547 { 548 unsigned int i; 549 size_t size; 550 551 for (size = i = 0; i < d->frames; i++) { 552 struct bcm2835_dma_cb *control_block = d->cb_list[i].cb; 553 size_t this_size = control_block->length; 554 dma_addr_t dma; 555 556 if (d->dir == DMA_DEV_TO_MEM) 557 dma = control_block->dst; 558 else 559 dma = control_block->src; 560 561 if (size) 562 size += this_size; 563 else if (addr >= dma && addr < dma + this_size) 564 size += dma + this_size - addr; 565 } 566 567 return size; 568 } 569 570 static enum dma_status bcm2835_dma_tx_status(struct dma_chan *chan, 571 dma_cookie_t cookie, struct dma_tx_state *txstate) 572 { 573 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); 574 struct virt_dma_desc *vd; 575 enum dma_status ret; 576 unsigned long flags; 577 578 ret = dma_cookie_status(chan, cookie, txstate); 579 if (ret == DMA_COMPLETE || !txstate) 580 return ret; 581 582 spin_lock_irqsave(&c->vc.lock, flags); 583 vd = vchan_find_desc(&c->vc, cookie); 584 if (vd) { 585 txstate->residue = 586 bcm2835_dma_desc_size(to_bcm2835_dma_desc(&vd->tx)); 587 } else if (c->desc && c->desc->vd.tx.cookie == cookie) { 588 struct bcm2835_desc *d = c->desc; 589 dma_addr_t pos; 590 591 if (d->dir == DMA_MEM_TO_DEV) 592 pos = readl(c->chan_base + BCM2835_DMA_SOURCE_AD); 593 else if (d->dir == DMA_DEV_TO_MEM) 594 pos = readl(c->chan_base + BCM2835_DMA_DEST_AD); 595 else 596 pos = 0; 597 598 txstate->residue = bcm2835_dma_desc_size_pos(d, pos); 599 } else { 600 txstate->residue = 0; 601 } 602 603 spin_unlock_irqrestore(&c->vc.lock, flags); 604 605 return ret; 606 } 607 608 static void bcm2835_dma_issue_pending(struct dma_chan *chan) 609 { 610 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); 611 unsigned long flags; 612 613 spin_lock_irqsave(&c->vc.lock, flags); 614 if (vchan_issue_pending(&c->vc) && !c->desc) 615 bcm2835_dma_start_desc(c); 616 617 spin_unlock_irqrestore(&c->vc.lock, flags); 618 } 619 620 static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_memcpy( 621 struct dma_chan *chan, dma_addr_t dst, dma_addr_t src, 622 size_t len, unsigned long flags) 623 { 624 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); 625 struct bcm2835_desc *d; 626 u32 info = BCM2835_DMA_D_INC | BCM2835_DMA_S_INC; 627 u32 extra = BCM2835_DMA_INT_EN | BCM2835_DMA_WAIT_RESP; 628 size_t max_len = bcm2835_dma_max_frame_length(c); 629 size_t frames; 630 631 /* if src, dst or len is not given return with an error */ 632 if (!src || !dst || !len) 633 return NULL; 634 635 /* calculate number of frames */ 636 frames = bcm2835_dma_frames_for_length(len, max_len); 637 638 /* allocate the CB chain - this also fills in the pointers */ 639 d = bcm2835_dma_create_cb_chain(chan, DMA_MEM_TO_MEM, false, 640 info, extra, frames, 641 src, dst, len, 0, GFP_KERNEL); 642 if (!d) 643 return NULL; 644 645 return vchan_tx_prep(&c->vc, &d->vd, flags); 646 } 647 648 static struct dma_async_tx_descriptor *bcm2835_dma_prep_slave_sg( 649 struct dma_chan *chan, 650 struct scatterlist *sgl, unsigned int sg_len, 651 enum dma_transfer_direction direction, 652 unsigned long flags, void *context) 653 { 654 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); 655 struct bcm2835_desc *d; 656 dma_addr_t src = 0, dst = 0; 657 u32 info = BCM2835_DMA_WAIT_RESP; 658 u32 extra = BCM2835_DMA_INT_EN; 659 size_t frames; 660 661 if (!is_slave_direction(direction)) { 662 dev_err(chan->device->dev, 663 "%s: bad direction?\n", __func__); 664 return NULL; 665 } 666 667 if (c->dreq != 0) 668 info |= BCM2835_DMA_PER_MAP(c->dreq); 669 670 if (direction == DMA_DEV_TO_MEM) { 671 if (c->cfg.src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) 672 return NULL; 673 src = c->cfg.src_addr; 674 info |= BCM2835_DMA_S_DREQ | BCM2835_DMA_D_INC; 675 } else { 676 if (c->cfg.dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) 677 return NULL; 678 dst = c->cfg.dst_addr; 679 info |= BCM2835_DMA_D_DREQ | BCM2835_DMA_S_INC; 680 } 681 682 /* count frames in sg list */ 683 frames = bcm2835_dma_count_frames_for_sg(c, sgl, sg_len); 684 685 /* allocate the CB chain */ 686 d = bcm2835_dma_create_cb_chain(chan, direction, false, 687 info, extra, 688 frames, src, dst, 0, 0, 689 GFP_KERNEL); 690 if (!d) 691 return NULL; 692 693 /* fill in frames with scatterlist pointers */ 694 bcm2835_dma_fill_cb_chain_with_sg(chan, direction, d->cb_list, 695 sgl, sg_len); 696 697 return vchan_tx_prep(&c->vc, &d->vd, flags); 698 } 699 700 static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic( 701 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, 702 size_t period_len, enum dma_transfer_direction direction, 703 unsigned long flags) 704 { 705 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); 706 struct bcm2835_desc *d; 707 dma_addr_t src, dst; 708 u32 info = BCM2835_DMA_WAIT_RESP; 709 u32 extra = BCM2835_DMA_INT_EN; 710 size_t max_len = bcm2835_dma_max_frame_length(c); 711 size_t frames; 712 713 /* Grab configuration */ 714 if (!is_slave_direction(direction)) { 715 dev_err(chan->device->dev, "%s: bad direction?\n", __func__); 716 return NULL; 717 } 718 719 if (!buf_len) { 720 dev_err(chan->device->dev, 721 "%s: bad buffer length (= 0)\n", __func__); 722 return NULL; 723 } 724 725 /* 726 * warn if buf_len is not a multiple of period_len - this may leed 727 * to unexpected latencies for interrupts and thus audiable clicks 728 */ 729 if (buf_len % period_len) 730 dev_warn_once(chan->device->dev, 731 "%s: buffer_length (%zd) is not a multiple of period_len (%zd)\n", 732 __func__, buf_len, period_len); 733 734 /* Setup DREQ channel */ 735 if (c->dreq != 0) 736 info |= BCM2835_DMA_PER_MAP(c->dreq); 737 738 if (direction == DMA_DEV_TO_MEM) { 739 if (c->cfg.src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) 740 return NULL; 741 src = c->cfg.src_addr; 742 dst = buf_addr; 743 info |= BCM2835_DMA_S_DREQ | BCM2835_DMA_D_INC; 744 } else { 745 if (c->cfg.dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) 746 return NULL; 747 dst = c->cfg.dst_addr; 748 src = buf_addr; 749 info |= BCM2835_DMA_D_DREQ | BCM2835_DMA_S_INC; 750 } 751 752 /* calculate number of frames */ 753 frames = /* number of periods */ 754 DIV_ROUND_UP(buf_len, period_len) * 755 /* number of frames per period */ 756 bcm2835_dma_frames_for_length(period_len, max_len); 757 758 /* 759 * allocate the CB chain 760 * note that we need to use GFP_NOWAIT, as the ALSA i2s dmaengine 761 * implementation calls prep_dma_cyclic with interrupts disabled. 762 */ 763 d = bcm2835_dma_create_cb_chain(chan, direction, true, 764 info, extra, 765 frames, src, dst, buf_len, 766 period_len, GFP_NOWAIT); 767 if (!d) 768 return NULL; 769 770 /* wrap around into a loop */ 771 d->cb_list[d->frames - 1].cb->next = d->cb_list[0].paddr; 772 773 return vchan_tx_prep(&c->vc, &d->vd, flags); 774 } 775 776 static int bcm2835_dma_slave_config(struct dma_chan *chan, 777 struct dma_slave_config *cfg) 778 { 779 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); 780 781 if ((cfg->direction == DMA_DEV_TO_MEM && 782 cfg->src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) || 783 (cfg->direction == DMA_MEM_TO_DEV && 784 cfg->dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES) || 785 !is_slave_direction(cfg->direction)) { 786 return -EINVAL; 787 } 788 789 c->cfg = *cfg; 790 791 return 0; 792 } 793 794 static int bcm2835_dma_terminate_all(struct dma_chan *chan) 795 { 796 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); 797 struct bcm2835_dmadev *d = to_bcm2835_dma_dev(c->vc.chan.device); 798 unsigned long flags; 799 int timeout = 10000; 800 LIST_HEAD(head); 801 802 spin_lock_irqsave(&c->vc.lock, flags); 803 804 /* Prevent this channel being scheduled */ 805 spin_lock(&d->lock); 806 list_del_init(&c->node); 807 spin_unlock(&d->lock); 808 809 /* 810 * Stop DMA activity: we assume the callback will not be called 811 * after bcm_dma_abort() returns (even if it does, it will see 812 * c->desc is NULL and exit.) 813 */ 814 if (c->desc) { 815 vchan_terminate_vdesc(&c->desc->vd); 816 c->desc = NULL; 817 bcm2835_dma_abort(c->chan_base); 818 819 /* Wait for stopping */ 820 while (--timeout) { 821 if (!(readl(c->chan_base + BCM2835_DMA_CS) & 822 BCM2835_DMA_ACTIVE)) 823 break; 824 825 cpu_relax(); 826 } 827 828 if (!timeout) 829 dev_err(d->ddev.dev, "DMA transfer could not be terminated\n"); 830 } 831 832 vchan_get_all_descriptors(&c->vc, &head); 833 spin_unlock_irqrestore(&c->vc.lock, flags); 834 vchan_dma_desc_free_list(&c->vc, &head); 835 836 return 0; 837 } 838 839 static void bcm2835_dma_synchronize(struct dma_chan *chan) 840 { 841 struct bcm2835_chan *c = to_bcm2835_dma_chan(chan); 842 843 vchan_synchronize(&c->vc); 844 } 845 846 static int bcm2835_dma_chan_init(struct bcm2835_dmadev *d, int chan_id, 847 int irq, unsigned int irq_flags) 848 { 849 struct bcm2835_chan *c; 850 851 c = devm_kzalloc(d->ddev.dev, sizeof(*c), GFP_KERNEL); 852 if (!c) 853 return -ENOMEM; 854 855 c->vc.desc_free = bcm2835_dma_desc_free; 856 vchan_init(&c->vc, &d->ddev); 857 INIT_LIST_HEAD(&c->node); 858 859 c->chan_base = BCM2835_DMA_CHANIO(d->base, chan_id); 860 c->ch = chan_id; 861 c->irq_number = irq; 862 c->irq_flags = irq_flags; 863 864 /* check in DEBUG register if this is a LITE channel */ 865 if (readl(c->chan_base + BCM2835_DMA_DEBUG) & 866 BCM2835_DMA_DEBUG_LITE) 867 c->is_lite_channel = true; 868 869 return 0; 870 } 871 872 static void bcm2835_dma_free(struct bcm2835_dmadev *od) 873 { 874 struct bcm2835_chan *c, *next; 875 876 list_for_each_entry_safe(c, next, &od->ddev.channels, 877 vc.chan.device_node) { 878 list_del(&c->vc.chan.device_node); 879 tasklet_kill(&c->vc.task); 880 } 881 } 882 883 static const struct of_device_id bcm2835_dma_of_match[] = { 884 { .compatible = "brcm,bcm2835-dma", }, 885 {}, 886 }; 887 MODULE_DEVICE_TABLE(of, bcm2835_dma_of_match); 888 889 static struct dma_chan *bcm2835_dma_xlate(struct of_phandle_args *spec, 890 struct of_dma *ofdma) 891 { 892 struct bcm2835_dmadev *d = ofdma->of_dma_data; 893 struct dma_chan *chan; 894 895 chan = dma_get_any_slave_channel(&d->ddev); 896 if (!chan) 897 return NULL; 898 899 /* Set DREQ from param */ 900 to_bcm2835_dma_chan(chan)->dreq = spec->args[0]; 901 902 return chan; 903 } 904 905 static int bcm2835_dma_probe(struct platform_device *pdev) 906 { 907 struct bcm2835_dmadev *od; 908 struct resource *res; 909 void __iomem *base; 910 int rc; 911 int i, j; 912 int irq[BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED + 1]; 913 int irq_flags; 914 uint32_t chans_available; 915 char chan_name[BCM2835_DMA_CHAN_NAME_SIZE]; 916 917 if (!pdev->dev.dma_mask) 918 pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask; 919 920 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 921 if (rc) 922 return rc; 923 924 od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL); 925 if (!od) 926 return -ENOMEM; 927 928 pdev->dev.dma_parms = &od->dma_parms; 929 dma_set_max_seg_size(&pdev->dev, 0x3FFFFFFF); 930 931 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 932 base = devm_ioremap_resource(&pdev->dev, res); 933 if (IS_ERR(base)) 934 return PTR_ERR(base); 935 936 od->base = base; 937 938 dma_cap_set(DMA_SLAVE, od->ddev.cap_mask); 939 dma_cap_set(DMA_PRIVATE, od->ddev.cap_mask); 940 dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask); 941 dma_cap_set(DMA_SLAVE, od->ddev.cap_mask); 942 dma_cap_set(DMA_MEMCPY, od->ddev.cap_mask); 943 od->ddev.device_alloc_chan_resources = bcm2835_dma_alloc_chan_resources; 944 od->ddev.device_free_chan_resources = bcm2835_dma_free_chan_resources; 945 od->ddev.device_tx_status = bcm2835_dma_tx_status; 946 od->ddev.device_issue_pending = bcm2835_dma_issue_pending; 947 od->ddev.device_prep_dma_cyclic = bcm2835_dma_prep_dma_cyclic; 948 od->ddev.device_prep_slave_sg = bcm2835_dma_prep_slave_sg; 949 od->ddev.device_prep_dma_memcpy = bcm2835_dma_prep_dma_memcpy; 950 od->ddev.device_config = bcm2835_dma_slave_config; 951 od->ddev.device_terminate_all = bcm2835_dma_terminate_all; 952 od->ddev.device_synchronize = bcm2835_dma_synchronize; 953 od->ddev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); 954 od->ddev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES); 955 od->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) | 956 BIT(DMA_MEM_TO_MEM); 957 od->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST; 958 od->ddev.dev = &pdev->dev; 959 INIT_LIST_HEAD(&od->ddev.channels); 960 spin_lock_init(&od->lock); 961 962 platform_set_drvdata(pdev, od); 963 964 /* Request DMA channel mask from device tree */ 965 if (of_property_read_u32(pdev->dev.of_node, 966 "brcm,dma-channel-mask", 967 &chans_available)) { 968 dev_err(&pdev->dev, "Failed to get channel mask\n"); 969 rc = -EINVAL; 970 goto err_no_dma; 971 } 972 973 /* get irqs for each channel that we support */ 974 for (i = 0; i <= BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED; i++) { 975 /* skip masked out channels */ 976 if (!(chans_available & (1 << i))) { 977 irq[i] = -1; 978 continue; 979 } 980 981 /* get the named irq */ 982 snprintf(chan_name, sizeof(chan_name), "dma%i", i); 983 irq[i] = platform_get_irq_byname(pdev, chan_name); 984 if (irq[i] >= 0) 985 continue; 986 987 /* legacy device tree case handling */ 988 dev_warn_once(&pdev->dev, 989 "missing interrupt-names property in device tree - legacy interpretation is used\n"); 990 /* 991 * in case of channel >= 11 992 * use the 11th interrupt and that is shared 993 */ 994 irq[i] = platform_get_irq(pdev, i < 11 ? i : 11); 995 } 996 997 /* get irqs for each channel */ 998 for (i = 0; i <= BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED; i++) { 999 /* skip channels without irq */ 1000 if (irq[i] < 0) 1001 continue; 1002 1003 /* check if there are other channels that also use this irq */ 1004 irq_flags = 0; 1005 for (j = 0; j <= BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED; j++) 1006 if ((i != j) && (irq[j] == irq[i])) { 1007 irq_flags = IRQF_SHARED; 1008 break; 1009 } 1010 1011 /* initialize the channel */ 1012 rc = bcm2835_dma_chan_init(od, i, irq[i], irq_flags); 1013 if (rc) 1014 goto err_no_dma; 1015 } 1016 1017 dev_dbg(&pdev->dev, "Initialized %i DMA channels\n", i); 1018 1019 /* Device-tree DMA controller registration */ 1020 rc = of_dma_controller_register(pdev->dev.of_node, 1021 bcm2835_dma_xlate, od); 1022 if (rc) { 1023 dev_err(&pdev->dev, "Failed to register DMA controller\n"); 1024 goto err_no_dma; 1025 } 1026 1027 rc = dma_async_device_register(&od->ddev); 1028 if (rc) { 1029 dev_err(&pdev->dev, 1030 "Failed to register slave DMA engine device: %d\n", rc); 1031 goto err_no_dma; 1032 } 1033 1034 dev_dbg(&pdev->dev, "Load BCM2835 DMA engine driver\n"); 1035 1036 return 0; 1037 1038 err_no_dma: 1039 bcm2835_dma_free(od); 1040 return rc; 1041 } 1042 1043 static int bcm2835_dma_remove(struct platform_device *pdev) 1044 { 1045 struct bcm2835_dmadev *od = platform_get_drvdata(pdev); 1046 1047 dma_async_device_unregister(&od->ddev); 1048 bcm2835_dma_free(od); 1049 1050 return 0; 1051 } 1052 1053 static struct platform_driver bcm2835_dma_driver = { 1054 .probe = bcm2835_dma_probe, 1055 .remove = bcm2835_dma_remove, 1056 .driver = { 1057 .name = "bcm2835-dma", 1058 .of_match_table = of_match_ptr(bcm2835_dma_of_match), 1059 }, 1060 }; 1061 1062 module_platform_driver(bcm2835_dma_driver); 1063 1064 MODULE_ALIAS("platform:bcm2835-dma"); 1065 MODULE_DESCRIPTION("BCM2835 DMA engine driver"); 1066 MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>"); 1067 MODULE_LICENSE("GPL v2"); 1068