1dc78baa2SNicolas Ferre /* 2dc78baa2SNicolas Ferre * Driver for the Atmel AHB DMA Controller (aka HDMA or DMAC on AT91 systems) 3dc78baa2SNicolas Ferre * 4dc78baa2SNicolas Ferre * Copyright (C) 2008 Atmel Corporation 5dc78baa2SNicolas Ferre * 6dc78baa2SNicolas Ferre * This program is free software; you can redistribute it and/or modify 7dc78baa2SNicolas Ferre * it under the terms of the GNU General Public License as published by 8dc78baa2SNicolas Ferre * the Free Software Foundation; either version 2 of the License, or 9dc78baa2SNicolas Ferre * (at your option) any later version. 10dc78baa2SNicolas Ferre * 11dc78baa2SNicolas Ferre * 12dc78baa2SNicolas Ferre * This supports the Atmel AHB DMA Controller, 13dc78baa2SNicolas Ferre * 14dc78baa2SNicolas Ferre * The driver has currently been tested with the Atmel AT91SAM9RL 15dc78baa2SNicolas Ferre * and AT91SAM9G45 series. 16dc78baa2SNicolas Ferre */ 17dc78baa2SNicolas Ferre 18dc78baa2SNicolas Ferre #include <linux/clk.h> 19dc78baa2SNicolas Ferre #include <linux/dmaengine.h> 20dc78baa2SNicolas Ferre #include <linux/dma-mapping.h> 21dc78baa2SNicolas Ferre #include <linux/dmapool.h> 22dc78baa2SNicolas Ferre #include <linux/interrupt.h> 23dc78baa2SNicolas Ferre #include <linux/module.h> 24dc78baa2SNicolas Ferre #include <linux/platform_device.h> 255a0e3ad6STejun Heo #include <linux/slab.h> 26dc78baa2SNicolas Ferre 27dc78baa2SNicolas Ferre #include "at_hdmac_regs.h" 28dc78baa2SNicolas Ferre 29dc78baa2SNicolas Ferre /* 30dc78baa2SNicolas Ferre * Glossary 31dc78baa2SNicolas Ferre * -------- 32dc78baa2SNicolas Ferre * 33dc78baa2SNicolas Ferre * at_hdmac : Name of the ATmel AHB DMA Controller 34dc78baa2SNicolas Ferre * at_dma_ / atdma : ATmel DMA controller entity related 35dc78baa2SNicolas Ferre * atc_ / atchan : ATmel DMA Channel entity related 36dc78baa2SNicolas Ferre */ 37dc78baa2SNicolas Ferre 38dc78baa2SNicolas Ferre #define ATC_DEFAULT_CFG (ATC_FIFOCFG_HALFFIFO) 39dc78baa2SNicolas Ferre #define ATC_DEFAULT_CTRLA (0) 40ae14d4b5SNicolas Ferre #define ATC_DEFAULT_CTRLB (ATC_SIF(AT_DMA_MEM_IF) \ 41ae14d4b5SNicolas Ferre |ATC_DIF(AT_DMA_MEM_IF)) 42dc78baa2SNicolas Ferre 43dc78baa2SNicolas Ferre /* 44dc78baa2SNicolas Ferre * Initial number of descriptors to allocate for each channel. This could 45dc78baa2SNicolas Ferre * be increased during dma usage. 46dc78baa2SNicolas Ferre */ 47dc78baa2SNicolas Ferre static unsigned int init_nr_desc_per_channel = 64; 48dc78baa2SNicolas Ferre module_param(init_nr_desc_per_channel, uint, 0644); 49dc78baa2SNicolas Ferre MODULE_PARM_DESC(init_nr_desc_per_channel, 50dc78baa2SNicolas Ferre "initial descriptors per channel (default: 64)"); 51dc78baa2SNicolas Ferre 52dc78baa2SNicolas Ferre 53dc78baa2SNicolas Ferre /* prototypes */ 54dc78baa2SNicolas Ferre static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx); 55dc78baa2SNicolas Ferre 56dc78baa2SNicolas Ferre 57dc78baa2SNicolas Ferre /*----------------------------------------------------------------------*/ 58dc78baa2SNicolas Ferre 59dc78baa2SNicolas Ferre static struct at_desc *atc_first_active(struct at_dma_chan *atchan) 60dc78baa2SNicolas Ferre { 61dc78baa2SNicolas Ferre return list_first_entry(&atchan->active_list, 62dc78baa2SNicolas Ferre struct at_desc, desc_node); 63dc78baa2SNicolas Ferre } 64dc78baa2SNicolas Ferre 65dc78baa2SNicolas Ferre static struct at_desc *atc_first_queued(struct at_dma_chan *atchan) 66dc78baa2SNicolas Ferre { 67dc78baa2SNicolas Ferre return list_first_entry(&atchan->queue, 68dc78baa2SNicolas Ferre struct at_desc, desc_node); 69dc78baa2SNicolas Ferre } 70dc78baa2SNicolas Ferre 71dc78baa2SNicolas Ferre /** 72421f91d2SUwe Kleine-König * atc_alloc_descriptor - allocate and return an initialized descriptor 73dc78baa2SNicolas Ferre * @chan: the channel to allocate descriptors for 74dc78baa2SNicolas Ferre * @gfp_flags: GFP allocation flags 75dc78baa2SNicolas Ferre * 76dc78baa2SNicolas Ferre * Note: The ack-bit is positioned in the descriptor flag at creation time 77dc78baa2SNicolas Ferre * to make initial allocation more convenient. This bit will be cleared 78dc78baa2SNicolas Ferre * and control will be given to client at usage time (during 79dc78baa2SNicolas Ferre * preparation functions). 80dc78baa2SNicolas Ferre */ 81dc78baa2SNicolas Ferre static struct at_desc *atc_alloc_descriptor(struct dma_chan *chan, 82dc78baa2SNicolas Ferre gfp_t gfp_flags) 83dc78baa2SNicolas Ferre { 84dc78baa2SNicolas Ferre struct at_desc *desc = NULL; 85dc78baa2SNicolas Ferre struct at_dma *atdma = to_at_dma(chan->device); 86dc78baa2SNicolas Ferre dma_addr_t phys; 87dc78baa2SNicolas Ferre 88dc78baa2SNicolas Ferre desc = dma_pool_alloc(atdma->dma_desc_pool, gfp_flags, &phys); 89dc78baa2SNicolas Ferre if (desc) { 90dc78baa2SNicolas Ferre memset(desc, 0, sizeof(struct at_desc)); 91285a3c71SDan Williams INIT_LIST_HEAD(&desc->tx_list); 92dc78baa2SNicolas Ferre dma_async_tx_descriptor_init(&desc->txd, chan); 93dc78baa2SNicolas Ferre /* txd.flags will be overwritten in prep functions */ 94dc78baa2SNicolas Ferre desc->txd.flags = DMA_CTRL_ACK; 95dc78baa2SNicolas Ferre desc->txd.tx_submit = atc_tx_submit; 96dc78baa2SNicolas Ferre desc->txd.phys = phys; 97dc78baa2SNicolas Ferre } 98dc78baa2SNicolas Ferre 99dc78baa2SNicolas Ferre return desc; 100dc78baa2SNicolas Ferre } 101dc78baa2SNicolas Ferre 102dc78baa2SNicolas Ferre /** 103af901ca1SAndré Goddard Rosa * atc_desc_get - get an unused descriptor from free_list 104dc78baa2SNicolas Ferre * @atchan: channel we want a new descriptor for 105dc78baa2SNicolas Ferre */ 106dc78baa2SNicolas Ferre static struct at_desc *atc_desc_get(struct at_dma_chan *atchan) 107dc78baa2SNicolas Ferre { 108dc78baa2SNicolas Ferre struct at_desc *desc, *_desc; 109dc78baa2SNicolas Ferre struct at_desc *ret = NULL; 110dc78baa2SNicolas Ferre unsigned int i = 0; 111dc78baa2SNicolas Ferre LIST_HEAD(tmp_list); 112dc78baa2SNicolas Ferre 113dc78baa2SNicolas Ferre spin_lock_bh(&atchan->lock); 114dc78baa2SNicolas Ferre list_for_each_entry_safe(desc, _desc, &atchan->free_list, desc_node) { 115dc78baa2SNicolas Ferre i++; 116dc78baa2SNicolas Ferre if (async_tx_test_ack(&desc->txd)) { 117dc78baa2SNicolas Ferre list_del(&desc->desc_node); 118dc78baa2SNicolas Ferre ret = desc; 119dc78baa2SNicolas Ferre break; 120dc78baa2SNicolas Ferre } 121dc78baa2SNicolas Ferre dev_dbg(chan2dev(&atchan->chan_common), 122dc78baa2SNicolas Ferre "desc %p not ACKed\n", desc); 123dc78baa2SNicolas Ferre } 124dc78baa2SNicolas Ferre spin_unlock_bh(&atchan->lock); 125dc78baa2SNicolas Ferre dev_vdbg(chan2dev(&atchan->chan_common), 126dc78baa2SNicolas Ferre "scanned %u descriptors on freelist\n", i); 127dc78baa2SNicolas Ferre 128dc78baa2SNicolas Ferre /* no more descriptor available in initial pool: create one more */ 129dc78baa2SNicolas Ferre if (!ret) { 130dc78baa2SNicolas Ferre ret = atc_alloc_descriptor(&atchan->chan_common, GFP_ATOMIC); 131dc78baa2SNicolas Ferre if (ret) { 132dc78baa2SNicolas Ferre spin_lock_bh(&atchan->lock); 133dc78baa2SNicolas Ferre atchan->descs_allocated++; 134dc78baa2SNicolas Ferre spin_unlock_bh(&atchan->lock); 135dc78baa2SNicolas Ferre } else { 136dc78baa2SNicolas Ferre dev_err(chan2dev(&atchan->chan_common), 137dc78baa2SNicolas Ferre "not enough descriptors available\n"); 138dc78baa2SNicolas Ferre } 139dc78baa2SNicolas Ferre } 140dc78baa2SNicolas Ferre 141dc78baa2SNicolas Ferre return ret; 142dc78baa2SNicolas Ferre } 143dc78baa2SNicolas Ferre 144dc78baa2SNicolas Ferre /** 145dc78baa2SNicolas Ferre * atc_desc_put - move a descriptor, including any children, to the free list 146dc78baa2SNicolas Ferre * @atchan: channel we work on 147dc78baa2SNicolas Ferre * @desc: descriptor, at the head of a chain, to move to free list 148dc78baa2SNicolas Ferre */ 149dc78baa2SNicolas Ferre static void atc_desc_put(struct at_dma_chan *atchan, struct at_desc *desc) 150dc78baa2SNicolas Ferre { 151dc78baa2SNicolas Ferre if (desc) { 152dc78baa2SNicolas Ferre struct at_desc *child; 153dc78baa2SNicolas Ferre 154dc78baa2SNicolas Ferre spin_lock_bh(&atchan->lock); 155285a3c71SDan Williams list_for_each_entry(child, &desc->tx_list, desc_node) 156dc78baa2SNicolas Ferre dev_vdbg(chan2dev(&atchan->chan_common), 157dc78baa2SNicolas Ferre "moving child desc %p to freelist\n", 158dc78baa2SNicolas Ferre child); 159285a3c71SDan Williams list_splice_init(&desc->tx_list, &atchan->free_list); 160dc78baa2SNicolas Ferre dev_vdbg(chan2dev(&atchan->chan_common), 161dc78baa2SNicolas Ferre "moving desc %p to freelist\n", desc); 162dc78baa2SNicolas Ferre list_add(&desc->desc_node, &atchan->free_list); 163dc78baa2SNicolas Ferre spin_unlock_bh(&atchan->lock); 164dc78baa2SNicolas Ferre } 165dc78baa2SNicolas Ferre } 166dc78baa2SNicolas Ferre 167dc78baa2SNicolas Ferre /** 16853830cc7SNicolas Ferre * atc_desc_chain - build chain adding a descripor 16953830cc7SNicolas Ferre * @first: address of first descripor of the chain 17053830cc7SNicolas Ferre * @prev: address of previous descripor of the chain 17153830cc7SNicolas Ferre * @desc: descriptor to queue 17253830cc7SNicolas Ferre * 17353830cc7SNicolas Ferre * Called from prep_* functions 17453830cc7SNicolas Ferre */ 17553830cc7SNicolas Ferre static void atc_desc_chain(struct at_desc **first, struct at_desc **prev, 17653830cc7SNicolas Ferre struct at_desc *desc) 17753830cc7SNicolas Ferre { 17853830cc7SNicolas Ferre if (!(*first)) { 17953830cc7SNicolas Ferre *first = desc; 18053830cc7SNicolas Ferre } else { 18153830cc7SNicolas Ferre /* inform the HW lli about chaining */ 18253830cc7SNicolas Ferre (*prev)->lli.dscr = desc->txd.phys; 18353830cc7SNicolas Ferre /* insert the link descriptor to the LD ring */ 18453830cc7SNicolas Ferre list_add_tail(&desc->desc_node, 18553830cc7SNicolas Ferre &(*first)->tx_list); 18653830cc7SNicolas Ferre } 18753830cc7SNicolas Ferre *prev = desc; 18853830cc7SNicolas Ferre } 18953830cc7SNicolas Ferre 19053830cc7SNicolas Ferre /** 191dc78baa2SNicolas Ferre * atc_assign_cookie - compute and assign new cookie 192dc78baa2SNicolas Ferre * @atchan: channel we work on 193dc78baa2SNicolas Ferre * @desc: descriptor to asign cookie for 194dc78baa2SNicolas Ferre * 195dc78baa2SNicolas Ferre * Called with atchan->lock held and bh disabled 196dc78baa2SNicolas Ferre */ 197dc78baa2SNicolas Ferre static dma_cookie_t 198dc78baa2SNicolas Ferre atc_assign_cookie(struct at_dma_chan *atchan, struct at_desc *desc) 199dc78baa2SNicolas Ferre { 200dc78baa2SNicolas Ferre dma_cookie_t cookie = atchan->chan_common.cookie; 201dc78baa2SNicolas Ferre 202dc78baa2SNicolas Ferre if (++cookie < 0) 203dc78baa2SNicolas Ferre cookie = 1; 204dc78baa2SNicolas Ferre 205dc78baa2SNicolas Ferre atchan->chan_common.cookie = cookie; 206dc78baa2SNicolas Ferre desc->txd.cookie = cookie; 207dc78baa2SNicolas Ferre 208dc78baa2SNicolas Ferre return cookie; 209dc78baa2SNicolas Ferre } 210dc78baa2SNicolas Ferre 211dc78baa2SNicolas Ferre /** 212dc78baa2SNicolas Ferre * atc_dostart - starts the DMA engine for real 213dc78baa2SNicolas Ferre * @atchan: the channel we want to start 214dc78baa2SNicolas Ferre * @first: first descriptor in the list we want to begin with 215dc78baa2SNicolas Ferre * 216dc78baa2SNicolas Ferre * Called with atchan->lock held and bh disabled 217dc78baa2SNicolas Ferre */ 218dc78baa2SNicolas Ferre static void atc_dostart(struct at_dma_chan *atchan, struct at_desc *first) 219dc78baa2SNicolas Ferre { 220dc78baa2SNicolas Ferre struct at_dma *atdma = to_at_dma(atchan->chan_common.device); 221dc78baa2SNicolas Ferre 222dc78baa2SNicolas Ferre /* ASSERT: channel is idle */ 223dc78baa2SNicolas Ferre if (atc_chan_is_enabled(atchan)) { 224dc78baa2SNicolas Ferre dev_err(chan2dev(&atchan->chan_common), 225dc78baa2SNicolas Ferre "BUG: Attempted to start non-idle channel\n"); 226dc78baa2SNicolas Ferre dev_err(chan2dev(&atchan->chan_common), 227dc78baa2SNicolas Ferre " channel: s0x%x d0x%x ctrl0x%x:0x%x l0x%x\n", 228dc78baa2SNicolas Ferre channel_readl(atchan, SADDR), 229dc78baa2SNicolas Ferre channel_readl(atchan, DADDR), 230dc78baa2SNicolas Ferre channel_readl(atchan, CTRLA), 231dc78baa2SNicolas Ferre channel_readl(atchan, CTRLB), 232dc78baa2SNicolas Ferre channel_readl(atchan, DSCR)); 233dc78baa2SNicolas Ferre 234dc78baa2SNicolas Ferre /* The tasklet will hopefully advance the queue... */ 235dc78baa2SNicolas Ferre return; 236dc78baa2SNicolas Ferre } 237dc78baa2SNicolas Ferre 238dc78baa2SNicolas Ferre vdbg_dump_regs(atchan); 239dc78baa2SNicolas Ferre 240dc78baa2SNicolas Ferre /* clear any pending interrupt */ 241dc78baa2SNicolas Ferre while (dma_readl(atdma, EBCISR)) 242dc78baa2SNicolas Ferre cpu_relax(); 243dc78baa2SNicolas Ferre 244dc78baa2SNicolas Ferre channel_writel(atchan, SADDR, 0); 245dc78baa2SNicolas Ferre channel_writel(atchan, DADDR, 0); 246dc78baa2SNicolas Ferre channel_writel(atchan, CTRLA, 0); 247dc78baa2SNicolas Ferre channel_writel(atchan, CTRLB, 0); 248dc78baa2SNicolas Ferre channel_writel(atchan, DSCR, first->txd.phys); 249dc78baa2SNicolas Ferre dma_writel(atdma, CHER, atchan->mask); 250dc78baa2SNicolas Ferre 251dc78baa2SNicolas Ferre vdbg_dump_regs(atchan); 252dc78baa2SNicolas Ferre } 253dc78baa2SNicolas Ferre 254dc78baa2SNicolas Ferre /** 255dc78baa2SNicolas Ferre * atc_chain_complete - finish work for one transaction chain 256dc78baa2SNicolas Ferre * @atchan: channel we work on 257dc78baa2SNicolas Ferre * @desc: descriptor at the head of the chain we want do complete 258dc78baa2SNicolas Ferre * 259dc78baa2SNicolas Ferre * Called with atchan->lock held and bh disabled */ 260dc78baa2SNicolas Ferre static void 261dc78baa2SNicolas Ferre atc_chain_complete(struct at_dma_chan *atchan, struct at_desc *desc) 262dc78baa2SNicolas Ferre { 263dc78baa2SNicolas Ferre struct dma_async_tx_descriptor *txd = &desc->txd; 264dc78baa2SNicolas Ferre 265dc78baa2SNicolas Ferre dev_vdbg(chan2dev(&atchan->chan_common), 266dc78baa2SNicolas Ferre "descriptor %u complete\n", txd->cookie); 267dc78baa2SNicolas Ferre 268dc78baa2SNicolas Ferre atchan->completed_cookie = txd->cookie; 269dc78baa2SNicolas Ferre 270dc78baa2SNicolas Ferre /* move children to free_list */ 271285a3c71SDan Williams list_splice_init(&desc->tx_list, &atchan->free_list); 272dc78baa2SNicolas Ferre /* move myself to free_list */ 273dc78baa2SNicolas Ferre list_move(&desc->desc_node, &atchan->free_list); 274dc78baa2SNicolas Ferre 275ebcf9b80SNicolas Ferre /* unmap dma addresses (not on slave channels) */ 276657a77faSAtsushi Nemoto if (!atchan->chan_common.private) { 277657a77faSAtsushi Nemoto struct device *parent = chan2parent(&atchan->chan_common); 278dc78baa2SNicolas Ferre if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) { 279dc78baa2SNicolas Ferre if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE) 280657a77faSAtsushi Nemoto dma_unmap_single(parent, 281dc78baa2SNicolas Ferre desc->lli.daddr, 282dc78baa2SNicolas Ferre desc->len, DMA_FROM_DEVICE); 283dc78baa2SNicolas Ferre else 284657a77faSAtsushi Nemoto dma_unmap_page(parent, 285dc78baa2SNicolas Ferre desc->lli.daddr, 286dc78baa2SNicolas Ferre desc->len, DMA_FROM_DEVICE); 287dc78baa2SNicolas Ferre } 288dc78baa2SNicolas Ferre if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) { 289dc78baa2SNicolas Ferre if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE) 290657a77faSAtsushi Nemoto dma_unmap_single(parent, 291dc78baa2SNicolas Ferre desc->lli.saddr, 292dc78baa2SNicolas Ferre desc->len, DMA_TO_DEVICE); 293dc78baa2SNicolas Ferre else 294657a77faSAtsushi Nemoto dma_unmap_page(parent, 295dc78baa2SNicolas Ferre desc->lli.saddr, 296dc78baa2SNicolas Ferre desc->len, DMA_TO_DEVICE); 297dc78baa2SNicolas Ferre } 298657a77faSAtsushi Nemoto } 299dc78baa2SNicolas Ferre 30053830cc7SNicolas Ferre /* for cyclic transfers, 30153830cc7SNicolas Ferre * no need to replay callback function while stopping */ 30253830cc7SNicolas Ferre if (!test_bit(ATC_IS_CYCLIC, &atchan->status)) { 30353830cc7SNicolas Ferre dma_async_tx_callback callback = txd->callback; 30453830cc7SNicolas Ferre void *param = txd->callback_param; 30553830cc7SNicolas Ferre 306dc78baa2SNicolas Ferre /* 307dc78baa2SNicolas Ferre * The API requires that no submissions are done from a 308dc78baa2SNicolas Ferre * callback, so we don't need to drop the lock here 309dc78baa2SNicolas Ferre */ 310dc78baa2SNicolas Ferre if (callback) 311dc78baa2SNicolas Ferre callback(param); 31253830cc7SNicolas Ferre } 313dc78baa2SNicolas Ferre 314dc78baa2SNicolas Ferre dma_run_dependencies(txd); 315dc78baa2SNicolas Ferre } 316dc78baa2SNicolas Ferre 317dc78baa2SNicolas Ferre /** 318dc78baa2SNicolas Ferre * atc_complete_all - finish work for all transactions 319dc78baa2SNicolas Ferre * @atchan: channel to complete transactions for 320dc78baa2SNicolas Ferre * 321dc78baa2SNicolas Ferre * Eventually submit queued descriptors if any 322dc78baa2SNicolas Ferre * 323dc78baa2SNicolas Ferre * Assume channel is idle while calling this function 324dc78baa2SNicolas Ferre * Called with atchan->lock held and bh disabled 325dc78baa2SNicolas Ferre */ 326dc78baa2SNicolas Ferre static void atc_complete_all(struct at_dma_chan *atchan) 327dc78baa2SNicolas Ferre { 328dc78baa2SNicolas Ferre struct at_desc *desc, *_desc; 329dc78baa2SNicolas Ferre LIST_HEAD(list); 330dc78baa2SNicolas Ferre 331dc78baa2SNicolas Ferre dev_vdbg(chan2dev(&atchan->chan_common), "complete all\n"); 332dc78baa2SNicolas Ferre 333dc78baa2SNicolas Ferre BUG_ON(atc_chan_is_enabled(atchan)); 334dc78baa2SNicolas Ferre 335dc78baa2SNicolas Ferre /* 336dc78baa2SNicolas Ferre * Submit queued descriptors ASAP, i.e. before we go through 337dc78baa2SNicolas Ferre * the completed ones. 338dc78baa2SNicolas Ferre */ 339dc78baa2SNicolas Ferre if (!list_empty(&atchan->queue)) 340dc78baa2SNicolas Ferre atc_dostart(atchan, atc_first_queued(atchan)); 341dc78baa2SNicolas Ferre /* empty active_list now it is completed */ 342dc78baa2SNicolas Ferre list_splice_init(&atchan->active_list, &list); 343dc78baa2SNicolas Ferre /* empty queue list by moving descriptors (if any) to active_list */ 344dc78baa2SNicolas Ferre list_splice_init(&atchan->queue, &atchan->active_list); 345dc78baa2SNicolas Ferre 346dc78baa2SNicolas Ferre list_for_each_entry_safe(desc, _desc, &list, desc_node) 347dc78baa2SNicolas Ferre atc_chain_complete(atchan, desc); 348dc78baa2SNicolas Ferre } 349dc78baa2SNicolas Ferre 350dc78baa2SNicolas Ferre /** 351dc78baa2SNicolas Ferre * atc_cleanup_descriptors - cleanup up finished descriptors in active_list 352dc78baa2SNicolas Ferre * @atchan: channel to be cleaned up 353dc78baa2SNicolas Ferre * 354dc78baa2SNicolas Ferre * Called with atchan->lock held and bh disabled 355dc78baa2SNicolas Ferre */ 356dc78baa2SNicolas Ferre static void atc_cleanup_descriptors(struct at_dma_chan *atchan) 357dc78baa2SNicolas Ferre { 358dc78baa2SNicolas Ferre struct at_desc *desc, *_desc; 359dc78baa2SNicolas Ferre struct at_desc *child; 360dc78baa2SNicolas Ferre 361dc78baa2SNicolas Ferre dev_vdbg(chan2dev(&atchan->chan_common), "cleanup descriptors\n"); 362dc78baa2SNicolas Ferre 363dc78baa2SNicolas Ferre list_for_each_entry_safe(desc, _desc, &atchan->active_list, desc_node) { 364dc78baa2SNicolas Ferre if (!(desc->lli.ctrla & ATC_DONE)) 365dc78baa2SNicolas Ferre /* This one is currently in progress */ 366dc78baa2SNicolas Ferre return; 367dc78baa2SNicolas Ferre 368285a3c71SDan Williams list_for_each_entry(child, &desc->tx_list, desc_node) 369dc78baa2SNicolas Ferre if (!(child->lli.ctrla & ATC_DONE)) 370dc78baa2SNicolas Ferre /* Currently in progress */ 371dc78baa2SNicolas Ferre return; 372dc78baa2SNicolas Ferre 373dc78baa2SNicolas Ferre /* 374dc78baa2SNicolas Ferre * No descriptors so far seem to be in progress, i.e. 375dc78baa2SNicolas Ferre * this chain must be done. 376dc78baa2SNicolas Ferre */ 377dc78baa2SNicolas Ferre atc_chain_complete(atchan, desc); 378dc78baa2SNicolas Ferre } 379dc78baa2SNicolas Ferre } 380dc78baa2SNicolas Ferre 381dc78baa2SNicolas Ferre /** 382dc78baa2SNicolas Ferre * atc_advance_work - at the end of a transaction, move forward 383dc78baa2SNicolas Ferre * @atchan: channel where the transaction ended 384dc78baa2SNicolas Ferre * 385dc78baa2SNicolas Ferre * Called with atchan->lock held and bh disabled 386dc78baa2SNicolas Ferre */ 387dc78baa2SNicolas Ferre static void atc_advance_work(struct at_dma_chan *atchan) 388dc78baa2SNicolas Ferre { 389dc78baa2SNicolas Ferre dev_vdbg(chan2dev(&atchan->chan_common), "advance_work\n"); 390dc78baa2SNicolas Ferre 391dc78baa2SNicolas Ferre if (list_empty(&atchan->active_list) || 392dc78baa2SNicolas Ferre list_is_singular(&atchan->active_list)) { 393dc78baa2SNicolas Ferre atc_complete_all(atchan); 394dc78baa2SNicolas Ferre } else { 395dc78baa2SNicolas Ferre atc_chain_complete(atchan, atc_first_active(atchan)); 396dc78baa2SNicolas Ferre /* advance work */ 397dc78baa2SNicolas Ferre atc_dostart(atchan, atc_first_active(atchan)); 398dc78baa2SNicolas Ferre } 399dc78baa2SNicolas Ferre } 400dc78baa2SNicolas Ferre 401dc78baa2SNicolas Ferre 402dc78baa2SNicolas Ferre /** 403dc78baa2SNicolas Ferre * atc_handle_error - handle errors reported by DMA controller 404dc78baa2SNicolas Ferre * @atchan: channel where error occurs 405dc78baa2SNicolas Ferre * 406dc78baa2SNicolas Ferre * Called with atchan->lock held and bh disabled 407dc78baa2SNicolas Ferre */ 408dc78baa2SNicolas Ferre static void atc_handle_error(struct at_dma_chan *atchan) 409dc78baa2SNicolas Ferre { 410dc78baa2SNicolas Ferre struct at_desc *bad_desc; 411dc78baa2SNicolas Ferre struct at_desc *child; 412dc78baa2SNicolas Ferre 413dc78baa2SNicolas Ferre /* 414dc78baa2SNicolas Ferre * The descriptor currently at the head of the active list is 415dc78baa2SNicolas Ferre * broked. Since we don't have any way to report errors, we'll 416dc78baa2SNicolas Ferre * just have to scream loudly and try to carry on. 417dc78baa2SNicolas Ferre */ 418dc78baa2SNicolas Ferre bad_desc = atc_first_active(atchan); 419dc78baa2SNicolas Ferre list_del_init(&bad_desc->desc_node); 420dc78baa2SNicolas Ferre 421dc78baa2SNicolas Ferre /* As we are stopped, take advantage to push queued descriptors 422dc78baa2SNicolas Ferre * in active_list */ 423dc78baa2SNicolas Ferre list_splice_init(&atchan->queue, atchan->active_list.prev); 424dc78baa2SNicolas Ferre 425dc78baa2SNicolas Ferre /* Try to restart the controller */ 426dc78baa2SNicolas Ferre if (!list_empty(&atchan->active_list)) 427dc78baa2SNicolas Ferre atc_dostart(atchan, atc_first_active(atchan)); 428dc78baa2SNicolas Ferre 429dc78baa2SNicolas Ferre /* 430dc78baa2SNicolas Ferre * KERN_CRITICAL may seem harsh, but since this only happens 431dc78baa2SNicolas Ferre * when someone submits a bad physical address in a 432dc78baa2SNicolas Ferre * descriptor, we should consider ourselves lucky that the 433dc78baa2SNicolas Ferre * controller flagged an error instead of scribbling over 434dc78baa2SNicolas Ferre * random memory locations. 435dc78baa2SNicolas Ferre */ 436dc78baa2SNicolas Ferre dev_crit(chan2dev(&atchan->chan_common), 437dc78baa2SNicolas Ferre "Bad descriptor submitted for DMA!\n"); 438dc78baa2SNicolas Ferre dev_crit(chan2dev(&atchan->chan_common), 439dc78baa2SNicolas Ferre " cookie: %d\n", bad_desc->txd.cookie); 440dc78baa2SNicolas Ferre atc_dump_lli(atchan, &bad_desc->lli); 441285a3c71SDan Williams list_for_each_entry(child, &bad_desc->tx_list, desc_node) 442dc78baa2SNicolas Ferre atc_dump_lli(atchan, &child->lli); 443dc78baa2SNicolas Ferre 444dc78baa2SNicolas Ferre /* Pretend the descriptor completed successfully */ 445dc78baa2SNicolas Ferre atc_chain_complete(atchan, bad_desc); 446dc78baa2SNicolas Ferre } 447dc78baa2SNicolas Ferre 44853830cc7SNicolas Ferre /** 44953830cc7SNicolas Ferre * atc_handle_cyclic - at the end of a period, run callback function 45053830cc7SNicolas Ferre * @atchan: channel used for cyclic operations 45153830cc7SNicolas Ferre * 45253830cc7SNicolas Ferre * Called with atchan->lock held and bh disabled 45353830cc7SNicolas Ferre */ 45453830cc7SNicolas Ferre static void atc_handle_cyclic(struct at_dma_chan *atchan) 45553830cc7SNicolas Ferre { 45653830cc7SNicolas Ferre struct at_desc *first = atc_first_active(atchan); 45753830cc7SNicolas Ferre struct dma_async_tx_descriptor *txd = &first->txd; 45853830cc7SNicolas Ferre dma_async_tx_callback callback = txd->callback; 45953830cc7SNicolas Ferre void *param = txd->callback_param; 46053830cc7SNicolas Ferre 46153830cc7SNicolas Ferre dev_vdbg(chan2dev(&atchan->chan_common), 46253830cc7SNicolas Ferre "new cyclic period llp 0x%08x\n", 46353830cc7SNicolas Ferre channel_readl(atchan, DSCR)); 46453830cc7SNicolas Ferre 46553830cc7SNicolas Ferre if (callback) 46653830cc7SNicolas Ferre callback(param); 46753830cc7SNicolas Ferre } 468dc78baa2SNicolas Ferre 469dc78baa2SNicolas Ferre /*-- IRQ & Tasklet ---------------------------------------------------*/ 470dc78baa2SNicolas Ferre 471dc78baa2SNicolas Ferre static void atc_tasklet(unsigned long data) 472dc78baa2SNicolas Ferre { 473dc78baa2SNicolas Ferre struct at_dma_chan *atchan = (struct at_dma_chan *)data; 474dc78baa2SNicolas Ferre 475dc78baa2SNicolas Ferre spin_lock(&atchan->lock); 47653830cc7SNicolas Ferre if (test_and_clear_bit(ATC_IS_ERROR, &atchan->status)) 477dc78baa2SNicolas Ferre atc_handle_error(atchan); 47853830cc7SNicolas Ferre else if (test_bit(ATC_IS_CYCLIC, &atchan->status)) 47953830cc7SNicolas Ferre atc_handle_cyclic(atchan); 480dc78baa2SNicolas Ferre else 481dc78baa2SNicolas Ferre atc_advance_work(atchan); 482dc78baa2SNicolas Ferre 483dc78baa2SNicolas Ferre spin_unlock(&atchan->lock); 484dc78baa2SNicolas Ferre } 485dc78baa2SNicolas Ferre 486dc78baa2SNicolas Ferre static irqreturn_t at_dma_interrupt(int irq, void *dev_id) 487dc78baa2SNicolas Ferre { 488dc78baa2SNicolas Ferre struct at_dma *atdma = (struct at_dma *)dev_id; 489dc78baa2SNicolas Ferre struct at_dma_chan *atchan; 490dc78baa2SNicolas Ferre int i; 491dc78baa2SNicolas Ferre u32 status, pending, imr; 492dc78baa2SNicolas Ferre int ret = IRQ_NONE; 493dc78baa2SNicolas Ferre 494dc78baa2SNicolas Ferre do { 495dc78baa2SNicolas Ferre imr = dma_readl(atdma, EBCIMR); 496dc78baa2SNicolas Ferre status = dma_readl(atdma, EBCISR); 497dc78baa2SNicolas Ferre pending = status & imr; 498dc78baa2SNicolas Ferre 499dc78baa2SNicolas Ferre if (!pending) 500dc78baa2SNicolas Ferre break; 501dc78baa2SNicolas Ferre 502dc78baa2SNicolas Ferre dev_vdbg(atdma->dma_common.dev, 503dc78baa2SNicolas Ferre "interrupt: status = 0x%08x, 0x%08x, 0x%08x\n", 504dc78baa2SNicolas Ferre status, imr, pending); 505dc78baa2SNicolas Ferre 506dc78baa2SNicolas Ferre for (i = 0; i < atdma->dma_common.chancnt; i++) { 507dc78baa2SNicolas Ferre atchan = &atdma->chan[i]; 5089b3aa589SNicolas Ferre if (pending & (AT_DMA_BTC(i) | AT_DMA_ERR(i))) { 509dc78baa2SNicolas Ferre if (pending & AT_DMA_ERR(i)) { 510dc78baa2SNicolas Ferre /* Disable channel on AHB error */ 51123b5e3adSNicolas Ferre dma_writel(atdma, CHDR, 51223b5e3adSNicolas Ferre AT_DMA_RES(i) | atchan->mask); 513dc78baa2SNicolas Ferre /* Give information to tasklet */ 51453830cc7SNicolas Ferre set_bit(ATC_IS_ERROR, &atchan->status); 515dc78baa2SNicolas Ferre } 516dc78baa2SNicolas Ferre tasklet_schedule(&atchan->tasklet); 517dc78baa2SNicolas Ferre ret = IRQ_HANDLED; 518dc78baa2SNicolas Ferre } 519dc78baa2SNicolas Ferre } 520dc78baa2SNicolas Ferre 521dc78baa2SNicolas Ferre } while (pending); 522dc78baa2SNicolas Ferre 523dc78baa2SNicolas Ferre return ret; 524dc78baa2SNicolas Ferre } 525dc78baa2SNicolas Ferre 526dc78baa2SNicolas Ferre 527dc78baa2SNicolas Ferre /*-- DMA Engine API --------------------------------------------------*/ 528dc78baa2SNicolas Ferre 529dc78baa2SNicolas Ferre /** 530dc78baa2SNicolas Ferre * atc_tx_submit - set the prepared descriptor(s) to be executed by the engine 531dc78baa2SNicolas Ferre * @desc: descriptor at the head of the transaction chain 532dc78baa2SNicolas Ferre * 533dc78baa2SNicolas Ferre * Queue chain if DMA engine is working already 534dc78baa2SNicolas Ferre * 535dc78baa2SNicolas Ferre * Cookie increment and adding to active_list or queue must be atomic 536dc78baa2SNicolas Ferre */ 537dc78baa2SNicolas Ferre static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx) 538dc78baa2SNicolas Ferre { 539dc78baa2SNicolas Ferre struct at_desc *desc = txd_to_at_desc(tx); 540dc78baa2SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(tx->chan); 541dc78baa2SNicolas Ferre dma_cookie_t cookie; 542dc78baa2SNicolas Ferre 543dc78baa2SNicolas Ferre spin_lock_bh(&atchan->lock); 544dc78baa2SNicolas Ferre cookie = atc_assign_cookie(atchan, desc); 545dc78baa2SNicolas Ferre 546dc78baa2SNicolas Ferre if (list_empty(&atchan->active_list)) { 547dc78baa2SNicolas Ferre dev_vdbg(chan2dev(tx->chan), "tx_submit: started %u\n", 548dc78baa2SNicolas Ferre desc->txd.cookie); 549dc78baa2SNicolas Ferre atc_dostart(atchan, desc); 550dc78baa2SNicolas Ferre list_add_tail(&desc->desc_node, &atchan->active_list); 551dc78baa2SNicolas Ferre } else { 552dc78baa2SNicolas Ferre dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u\n", 553dc78baa2SNicolas Ferre desc->txd.cookie); 554dc78baa2SNicolas Ferre list_add_tail(&desc->desc_node, &atchan->queue); 555dc78baa2SNicolas Ferre } 556dc78baa2SNicolas Ferre 557dc78baa2SNicolas Ferre spin_unlock_bh(&atchan->lock); 558dc78baa2SNicolas Ferre 559dc78baa2SNicolas Ferre return cookie; 560dc78baa2SNicolas Ferre } 561dc78baa2SNicolas Ferre 562dc78baa2SNicolas Ferre /** 563dc78baa2SNicolas Ferre * atc_prep_dma_memcpy - prepare a memcpy operation 564dc78baa2SNicolas Ferre * @chan: the channel to prepare operation on 565dc78baa2SNicolas Ferre * @dest: operation virtual destination address 566dc78baa2SNicolas Ferre * @src: operation virtual source address 567dc78baa2SNicolas Ferre * @len: operation length 568dc78baa2SNicolas Ferre * @flags: tx descriptor status flags 569dc78baa2SNicolas Ferre */ 570dc78baa2SNicolas Ferre static struct dma_async_tx_descriptor * 571dc78baa2SNicolas Ferre atc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, 572dc78baa2SNicolas Ferre size_t len, unsigned long flags) 573dc78baa2SNicolas Ferre { 574dc78baa2SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 575dc78baa2SNicolas Ferre struct at_desc *desc = NULL; 576dc78baa2SNicolas Ferre struct at_desc *first = NULL; 577dc78baa2SNicolas Ferre struct at_desc *prev = NULL; 578dc78baa2SNicolas Ferre size_t xfer_count; 579dc78baa2SNicolas Ferre size_t offset; 580dc78baa2SNicolas Ferre unsigned int src_width; 581dc78baa2SNicolas Ferre unsigned int dst_width; 582dc78baa2SNicolas Ferre u32 ctrla; 583dc78baa2SNicolas Ferre u32 ctrlb; 584dc78baa2SNicolas Ferre 585dc78baa2SNicolas Ferre dev_vdbg(chan2dev(chan), "prep_dma_memcpy: d0x%x s0x%x l0x%zx f0x%lx\n", 586dc78baa2SNicolas Ferre dest, src, len, flags); 587dc78baa2SNicolas Ferre 588dc78baa2SNicolas Ferre if (unlikely(!len)) { 589dc78baa2SNicolas Ferre dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n"); 590dc78baa2SNicolas Ferre return NULL; 591dc78baa2SNicolas Ferre } 592dc78baa2SNicolas Ferre 593dc78baa2SNicolas Ferre ctrla = ATC_DEFAULT_CTRLA; 5949b3aa589SNicolas Ferre ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN 595dc78baa2SNicolas Ferre | ATC_SRC_ADDR_MODE_INCR 596dc78baa2SNicolas Ferre | ATC_DST_ADDR_MODE_INCR 597dc78baa2SNicolas Ferre | ATC_FC_MEM2MEM; 598dc78baa2SNicolas Ferre 599dc78baa2SNicolas Ferre /* 600dc78baa2SNicolas Ferre * We can be a lot more clever here, but this should take care 601dc78baa2SNicolas Ferre * of the most common optimization. 602dc78baa2SNicolas Ferre */ 603dc78baa2SNicolas Ferre if (!((src | dest | len) & 3)) { 604dc78baa2SNicolas Ferre ctrla |= ATC_SRC_WIDTH_WORD | ATC_DST_WIDTH_WORD; 605dc78baa2SNicolas Ferre src_width = dst_width = 2; 606dc78baa2SNicolas Ferre } else if (!((src | dest | len) & 1)) { 607dc78baa2SNicolas Ferre ctrla |= ATC_SRC_WIDTH_HALFWORD | ATC_DST_WIDTH_HALFWORD; 608dc78baa2SNicolas Ferre src_width = dst_width = 1; 609dc78baa2SNicolas Ferre } else { 610dc78baa2SNicolas Ferre ctrla |= ATC_SRC_WIDTH_BYTE | ATC_DST_WIDTH_BYTE; 611dc78baa2SNicolas Ferre src_width = dst_width = 0; 612dc78baa2SNicolas Ferre } 613dc78baa2SNicolas Ferre 614dc78baa2SNicolas Ferre for (offset = 0; offset < len; offset += xfer_count << src_width) { 615dc78baa2SNicolas Ferre xfer_count = min_t(size_t, (len - offset) >> src_width, 616dc78baa2SNicolas Ferre ATC_BTSIZE_MAX); 617dc78baa2SNicolas Ferre 618dc78baa2SNicolas Ferre desc = atc_desc_get(atchan); 619dc78baa2SNicolas Ferre if (!desc) 620dc78baa2SNicolas Ferre goto err_desc_get; 621dc78baa2SNicolas Ferre 622dc78baa2SNicolas Ferre desc->lli.saddr = src + offset; 623dc78baa2SNicolas Ferre desc->lli.daddr = dest + offset; 624dc78baa2SNicolas Ferre desc->lli.ctrla = ctrla | xfer_count; 625dc78baa2SNicolas Ferre desc->lli.ctrlb = ctrlb; 626dc78baa2SNicolas Ferre 627dc78baa2SNicolas Ferre desc->txd.cookie = 0; 628dc78baa2SNicolas Ferre 629e257e156SNicolas Ferre atc_desc_chain(&first, &prev, desc); 630dc78baa2SNicolas Ferre } 631dc78baa2SNicolas Ferre 632dc78baa2SNicolas Ferre /* First descriptor of the chain embedds additional information */ 633dc78baa2SNicolas Ferre first->txd.cookie = -EBUSY; 634dc78baa2SNicolas Ferre first->len = len; 635dc78baa2SNicolas Ferre 636dc78baa2SNicolas Ferre /* set end-of-link to the last link descriptor of list*/ 637dc78baa2SNicolas Ferre set_desc_eol(desc); 638dc78baa2SNicolas Ferre 639568f7f0cSNicolas Ferre first->txd.flags = flags; /* client is in control of this ack */ 640dc78baa2SNicolas Ferre 641dc78baa2SNicolas Ferre return &first->txd; 642dc78baa2SNicolas Ferre 643dc78baa2SNicolas Ferre err_desc_get: 644dc78baa2SNicolas Ferre atc_desc_put(atchan, first); 645dc78baa2SNicolas Ferre return NULL; 646dc78baa2SNicolas Ferre } 647dc78baa2SNicolas Ferre 648808347f6SNicolas Ferre 649808347f6SNicolas Ferre /** 650808347f6SNicolas Ferre * atc_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction 651808347f6SNicolas Ferre * @chan: DMA channel 652808347f6SNicolas Ferre * @sgl: scatterlist to transfer to/from 653808347f6SNicolas Ferre * @sg_len: number of entries in @scatterlist 654808347f6SNicolas Ferre * @direction: DMA direction 655808347f6SNicolas Ferre * @flags: tx descriptor status flags 656808347f6SNicolas Ferre */ 657808347f6SNicolas Ferre static struct dma_async_tx_descriptor * 658808347f6SNicolas Ferre atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, 659808347f6SNicolas Ferre unsigned int sg_len, enum dma_data_direction direction, 660808347f6SNicolas Ferre unsigned long flags) 661808347f6SNicolas Ferre { 662808347f6SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 663808347f6SNicolas Ferre struct at_dma_slave *atslave = chan->private; 664808347f6SNicolas Ferre struct at_desc *first = NULL; 665808347f6SNicolas Ferre struct at_desc *prev = NULL; 666808347f6SNicolas Ferre u32 ctrla; 667808347f6SNicolas Ferre u32 ctrlb; 668808347f6SNicolas Ferre dma_addr_t reg; 669808347f6SNicolas Ferre unsigned int reg_width; 670808347f6SNicolas Ferre unsigned int mem_width; 671808347f6SNicolas Ferre unsigned int i; 672808347f6SNicolas Ferre struct scatterlist *sg; 673808347f6SNicolas Ferre size_t total_len = 0; 674808347f6SNicolas Ferre 675cc52a10aSNicolas Ferre dev_vdbg(chan2dev(chan), "prep_slave_sg (%d): %s f0x%lx\n", 676cc52a10aSNicolas Ferre sg_len, 677808347f6SNicolas Ferre direction == DMA_TO_DEVICE ? "TO DEVICE" : "FROM DEVICE", 678808347f6SNicolas Ferre flags); 679808347f6SNicolas Ferre 680808347f6SNicolas Ferre if (unlikely(!atslave || !sg_len)) { 681808347f6SNicolas Ferre dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n"); 682808347f6SNicolas Ferre return NULL; 683808347f6SNicolas Ferre } 684808347f6SNicolas Ferre 685808347f6SNicolas Ferre reg_width = atslave->reg_width; 686808347f6SNicolas Ferre 687808347f6SNicolas Ferre ctrla = ATC_DEFAULT_CTRLA | atslave->ctrla; 688ae14d4b5SNicolas Ferre ctrlb = ATC_IEN; 689808347f6SNicolas Ferre 690808347f6SNicolas Ferre switch (direction) { 691808347f6SNicolas Ferre case DMA_TO_DEVICE: 692808347f6SNicolas Ferre ctrla |= ATC_DST_WIDTH(reg_width); 693808347f6SNicolas Ferre ctrlb |= ATC_DST_ADDR_MODE_FIXED 694808347f6SNicolas Ferre | ATC_SRC_ADDR_MODE_INCR 695ae14d4b5SNicolas Ferre | ATC_FC_MEM2PER 696ae14d4b5SNicolas Ferre | ATC_SIF(AT_DMA_MEM_IF) | ATC_DIF(AT_DMA_PER_IF); 697808347f6SNicolas Ferre reg = atslave->tx_reg; 698808347f6SNicolas Ferre for_each_sg(sgl, sg, sg_len, i) { 699808347f6SNicolas Ferre struct at_desc *desc; 700808347f6SNicolas Ferre u32 len; 701808347f6SNicolas Ferre u32 mem; 702808347f6SNicolas Ferre 703808347f6SNicolas Ferre desc = atc_desc_get(atchan); 704808347f6SNicolas Ferre if (!desc) 705808347f6SNicolas Ferre goto err_desc_get; 706808347f6SNicolas Ferre 7070f70e8ceSNicolas Ferre mem = sg_dma_address(sg); 708808347f6SNicolas Ferre len = sg_dma_len(sg); 709808347f6SNicolas Ferre mem_width = 2; 710808347f6SNicolas Ferre if (unlikely(mem & 3 || len & 3)) 711808347f6SNicolas Ferre mem_width = 0; 712808347f6SNicolas Ferre 713808347f6SNicolas Ferre desc->lli.saddr = mem; 714808347f6SNicolas Ferre desc->lli.daddr = reg; 715808347f6SNicolas Ferre desc->lli.ctrla = ctrla 716808347f6SNicolas Ferre | ATC_SRC_WIDTH(mem_width) 717808347f6SNicolas Ferre | len >> mem_width; 718808347f6SNicolas Ferre desc->lli.ctrlb = ctrlb; 719808347f6SNicolas Ferre 720e257e156SNicolas Ferre atc_desc_chain(&first, &prev, desc); 721808347f6SNicolas Ferre total_len += len; 722808347f6SNicolas Ferre } 723808347f6SNicolas Ferre break; 724808347f6SNicolas Ferre case DMA_FROM_DEVICE: 725808347f6SNicolas Ferre ctrla |= ATC_SRC_WIDTH(reg_width); 726808347f6SNicolas Ferre ctrlb |= ATC_DST_ADDR_MODE_INCR 727808347f6SNicolas Ferre | ATC_SRC_ADDR_MODE_FIXED 728ae14d4b5SNicolas Ferre | ATC_FC_PER2MEM 729ae14d4b5SNicolas Ferre | ATC_SIF(AT_DMA_PER_IF) | ATC_DIF(AT_DMA_MEM_IF); 730808347f6SNicolas Ferre 731808347f6SNicolas Ferre reg = atslave->rx_reg; 732808347f6SNicolas Ferre for_each_sg(sgl, sg, sg_len, i) { 733808347f6SNicolas Ferre struct at_desc *desc; 734808347f6SNicolas Ferre u32 len; 735808347f6SNicolas Ferre u32 mem; 736808347f6SNicolas Ferre 737808347f6SNicolas Ferre desc = atc_desc_get(atchan); 738808347f6SNicolas Ferre if (!desc) 739808347f6SNicolas Ferre goto err_desc_get; 740808347f6SNicolas Ferre 7410f70e8ceSNicolas Ferre mem = sg_dma_address(sg); 742808347f6SNicolas Ferre len = sg_dma_len(sg); 743808347f6SNicolas Ferre mem_width = 2; 744808347f6SNicolas Ferre if (unlikely(mem & 3 || len & 3)) 745808347f6SNicolas Ferre mem_width = 0; 746808347f6SNicolas Ferre 747808347f6SNicolas Ferre desc->lli.saddr = reg; 748808347f6SNicolas Ferre desc->lli.daddr = mem; 749808347f6SNicolas Ferre desc->lli.ctrla = ctrla 750808347f6SNicolas Ferre | ATC_DST_WIDTH(mem_width) 75159a609d9SNicolas Ferre | len >> reg_width; 752808347f6SNicolas Ferre desc->lli.ctrlb = ctrlb; 753808347f6SNicolas Ferre 754e257e156SNicolas Ferre atc_desc_chain(&first, &prev, desc); 755808347f6SNicolas Ferre total_len += len; 756808347f6SNicolas Ferre } 757808347f6SNicolas Ferre break; 758808347f6SNicolas Ferre default: 759808347f6SNicolas Ferre return NULL; 760808347f6SNicolas Ferre } 761808347f6SNicolas Ferre 762808347f6SNicolas Ferre /* set end-of-link to the last link descriptor of list*/ 763808347f6SNicolas Ferre set_desc_eol(prev); 764808347f6SNicolas Ferre 765808347f6SNicolas Ferre /* First descriptor of the chain embedds additional information */ 766808347f6SNicolas Ferre first->txd.cookie = -EBUSY; 767808347f6SNicolas Ferre first->len = total_len; 768808347f6SNicolas Ferre 769568f7f0cSNicolas Ferre /* first link descriptor of list is responsible of flags */ 770568f7f0cSNicolas Ferre first->txd.flags = flags; /* client is in control of this ack */ 771808347f6SNicolas Ferre 772808347f6SNicolas Ferre return &first->txd; 773808347f6SNicolas Ferre 774808347f6SNicolas Ferre err_desc_get: 775808347f6SNicolas Ferre dev_err(chan2dev(chan), "not enough descriptors available\n"); 776808347f6SNicolas Ferre atc_desc_put(atchan, first); 777808347f6SNicolas Ferre return NULL; 778808347f6SNicolas Ferre } 779808347f6SNicolas Ferre 78053830cc7SNicolas Ferre /** 78153830cc7SNicolas Ferre * atc_dma_cyclic_check_values 78253830cc7SNicolas Ferre * Check for too big/unaligned periods and unaligned DMA buffer 78353830cc7SNicolas Ferre */ 78453830cc7SNicolas Ferre static int 78553830cc7SNicolas Ferre atc_dma_cyclic_check_values(unsigned int reg_width, dma_addr_t buf_addr, 78653830cc7SNicolas Ferre size_t period_len, enum dma_data_direction direction) 78753830cc7SNicolas Ferre { 78853830cc7SNicolas Ferre if (period_len > (ATC_BTSIZE_MAX << reg_width)) 78953830cc7SNicolas Ferre goto err_out; 79053830cc7SNicolas Ferre if (unlikely(period_len & ((1 << reg_width) - 1))) 79153830cc7SNicolas Ferre goto err_out; 79253830cc7SNicolas Ferre if (unlikely(buf_addr & ((1 << reg_width) - 1))) 79353830cc7SNicolas Ferre goto err_out; 79453830cc7SNicolas Ferre if (unlikely(!(direction & (DMA_TO_DEVICE | DMA_FROM_DEVICE)))) 79553830cc7SNicolas Ferre goto err_out; 79653830cc7SNicolas Ferre 79753830cc7SNicolas Ferre return 0; 79853830cc7SNicolas Ferre 79953830cc7SNicolas Ferre err_out: 80053830cc7SNicolas Ferre return -EINVAL; 80153830cc7SNicolas Ferre } 80253830cc7SNicolas Ferre 80353830cc7SNicolas Ferre /** 80453830cc7SNicolas Ferre * atc_dma_cyclic_fill_desc - Fill one period decriptor 80553830cc7SNicolas Ferre */ 80653830cc7SNicolas Ferre static int 80753830cc7SNicolas Ferre atc_dma_cyclic_fill_desc(struct at_dma_slave *atslave, struct at_desc *desc, 80853830cc7SNicolas Ferre unsigned int period_index, dma_addr_t buf_addr, 80953830cc7SNicolas Ferre size_t period_len, enum dma_data_direction direction) 81053830cc7SNicolas Ferre { 81153830cc7SNicolas Ferre u32 ctrla; 81253830cc7SNicolas Ferre unsigned int reg_width = atslave->reg_width; 81353830cc7SNicolas Ferre 81453830cc7SNicolas Ferre /* prepare common CRTLA value */ 81553830cc7SNicolas Ferre ctrla = ATC_DEFAULT_CTRLA | atslave->ctrla 81653830cc7SNicolas Ferre | ATC_DST_WIDTH(reg_width) 81753830cc7SNicolas Ferre | ATC_SRC_WIDTH(reg_width) 81853830cc7SNicolas Ferre | period_len >> reg_width; 81953830cc7SNicolas Ferre 82053830cc7SNicolas Ferre switch (direction) { 82153830cc7SNicolas Ferre case DMA_TO_DEVICE: 82253830cc7SNicolas Ferre desc->lli.saddr = buf_addr + (period_len * period_index); 82353830cc7SNicolas Ferre desc->lli.daddr = atslave->tx_reg; 82453830cc7SNicolas Ferre desc->lli.ctrla = ctrla; 825ae14d4b5SNicolas Ferre desc->lli.ctrlb = ATC_DST_ADDR_MODE_FIXED 82653830cc7SNicolas Ferre | ATC_SRC_ADDR_MODE_INCR 827ae14d4b5SNicolas Ferre | ATC_FC_MEM2PER 828ae14d4b5SNicolas Ferre | ATC_SIF(AT_DMA_MEM_IF) 829ae14d4b5SNicolas Ferre | ATC_DIF(AT_DMA_PER_IF); 83053830cc7SNicolas Ferre break; 83153830cc7SNicolas Ferre 83253830cc7SNicolas Ferre case DMA_FROM_DEVICE: 83353830cc7SNicolas Ferre desc->lli.saddr = atslave->rx_reg; 83453830cc7SNicolas Ferre desc->lli.daddr = buf_addr + (period_len * period_index); 83553830cc7SNicolas Ferre desc->lli.ctrla = ctrla; 836ae14d4b5SNicolas Ferre desc->lli.ctrlb = ATC_DST_ADDR_MODE_INCR 83753830cc7SNicolas Ferre | ATC_SRC_ADDR_MODE_FIXED 838ae14d4b5SNicolas Ferre | ATC_FC_PER2MEM 839ae14d4b5SNicolas Ferre | ATC_SIF(AT_DMA_PER_IF) 840ae14d4b5SNicolas Ferre | ATC_DIF(AT_DMA_MEM_IF); 84153830cc7SNicolas Ferre break; 84253830cc7SNicolas Ferre 84353830cc7SNicolas Ferre default: 84453830cc7SNicolas Ferre return -EINVAL; 84553830cc7SNicolas Ferre } 84653830cc7SNicolas Ferre 84753830cc7SNicolas Ferre return 0; 84853830cc7SNicolas Ferre } 84953830cc7SNicolas Ferre 85053830cc7SNicolas Ferre /** 85153830cc7SNicolas Ferre * atc_prep_dma_cyclic - prepare the cyclic DMA transfer 85253830cc7SNicolas Ferre * @chan: the DMA channel to prepare 85353830cc7SNicolas Ferre * @buf_addr: physical DMA address where the buffer starts 85453830cc7SNicolas Ferre * @buf_len: total number of bytes for the entire buffer 85553830cc7SNicolas Ferre * @period_len: number of bytes for each period 85653830cc7SNicolas Ferre * @direction: transfer direction, to or from device 85753830cc7SNicolas Ferre */ 85853830cc7SNicolas Ferre static struct dma_async_tx_descriptor * 85953830cc7SNicolas Ferre atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, 86053830cc7SNicolas Ferre size_t period_len, enum dma_data_direction direction) 86153830cc7SNicolas Ferre { 86253830cc7SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 86353830cc7SNicolas Ferre struct at_dma_slave *atslave = chan->private; 86453830cc7SNicolas Ferre struct at_desc *first = NULL; 86553830cc7SNicolas Ferre struct at_desc *prev = NULL; 86653830cc7SNicolas Ferre unsigned long was_cyclic; 86753830cc7SNicolas Ferre unsigned int periods = buf_len / period_len; 86853830cc7SNicolas Ferre unsigned int i; 86953830cc7SNicolas Ferre 87053830cc7SNicolas Ferre dev_vdbg(chan2dev(chan), "prep_dma_cyclic: %s buf@0x%08x - %d (%d/%d)\n", 87153830cc7SNicolas Ferre direction == DMA_TO_DEVICE ? "TO DEVICE" : "FROM DEVICE", 87253830cc7SNicolas Ferre buf_addr, 87353830cc7SNicolas Ferre periods, buf_len, period_len); 87453830cc7SNicolas Ferre 87553830cc7SNicolas Ferre if (unlikely(!atslave || !buf_len || !period_len)) { 87653830cc7SNicolas Ferre dev_dbg(chan2dev(chan), "prep_dma_cyclic: length is zero!\n"); 87753830cc7SNicolas Ferre return NULL; 87853830cc7SNicolas Ferre } 87953830cc7SNicolas Ferre 88053830cc7SNicolas Ferre was_cyclic = test_and_set_bit(ATC_IS_CYCLIC, &atchan->status); 88153830cc7SNicolas Ferre if (was_cyclic) { 88253830cc7SNicolas Ferre dev_dbg(chan2dev(chan), "prep_dma_cyclic: channel in use!\n"); 88353830cc7SNicolas Ferre return NULL; 88453830cc7SNicolas Ferre } 88553830cc7SNicolas Ferre 88653830cc7SNicolas Ferre /* Check for too big/unaligned periods and unaligned DMA buffer */ 88753830cc7SNicolas Ferre if (atc_dma_cyclic_check_values(atslave->reg_width, buf_addr, 88853830cc7SNicolas Ferre period_len, direction)) 88953830cc7SNicolas Ferre goto err_out; 89053830cc7SNicolas Ferre 89153830cc7SNicolas Ferre /* build cyclic linked list */ 89253830cc7SNicolas Ferre for (i = 0; i < periods; i++) { 89353830cc7SNicolas Ferre struct at_desc *desc; 89453830cc7SNicolas Ferre 89553830cc7SNicolas Ferre desc = atc_desc_get(atchan); 89653830cc7SNicolas Ferre if (!desc) 89753830cc7SNicolas Ferre goto err_desc_get; 89853830cc7SNicolas Ferre 89953830cc7SNicolas Ferre if (atc_dma_cyclic_fill_desc(atslave, desc, i, buf_addr, 90053830cc7SNicolas Ferre period_len, direction)) 90153830cc7SNicolas Ferre goto err_desc_get; 90253830cc7SNicolas Ferre 90353830cc7SNicolas Ferre atc_desc_chain(&first, &prev, desc); 90453830cc7SNicolas Ferre } 90553830cc7SNicolas Ferre 90653830cc7SNicolas Ferre /* lets make a cyclic list */ 90753830cc7SNicolas Ferre prev->lli.dscr = first->txd.phys; 90853830cc7SNicolas Ferre 90953830cc7SNicolas Ferre /* First descriptor of the chain embedds additional information */ 91053830cc7SNicolas Ferre first->txd.cookie = -EBUSY; 91153830cc7SNicolas Ferre first->len = buf_len; 91253830cc7SNicolas Ferre 91353830cc7SNicolas Ferre return &first->txd; 91453830cc7SNicolas Ferre 91553830cc7SNicolas Ferre err_desc_get: 91653830cc7SNicolas Ferre dev_err(chan2dev(chan), "not enough descriptors available\n"); 91753830cc7SNicolas Ferre atc_desc_put(atchan, first); 91853830cc7SNicolas Ferre err_out: 91953830cc7SNicolas Ferre clear_bit(ATC_IS_CYCLIC, &atchan->status); 92053830cc7SNicolas Ferre return NULL; 92153830cc7SNicolas Ferre } 92253830cc7SNicolas Ferre 92353830cc7SNicolas Ferre 92405827630SLinus Walleij static int atc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, 92505827630SLinus Walleij unsigned long arg) 926808347f6SNicolas Ferre { 927808347f6SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 928808347f6SNicolas Ferre struct at_dma *atdma = to_at_dma(chan->device); 92923b5e3adSNicolas Ferre int chan_id = atchan->chan_common.chan_id; 93023b5e3adSNicolas Ferre 931808347f6SNicolas Ferre LIST_HEAD(list); 932808347f6SNicolas Ferre 93323b5e3adSNicolas Ferre dev_vdbg(chan2dev(chan), "atc_control (%d)\n", cmd); 934c3635c78SLinus Walleij 93523b5e3adSNicolas Ferre if (cmd == DMA_PAUSE) { 93623b5e3adSNicolas Ferre int pause_timeout = 1000; 93723b5e3adSNicolas Ferre 93823b5e3adSNicolas Ferre spin_lock_bh(&atchan->lock); 93923b5e3adSNicolas Ferre 94023b5e3adSNicolas Ferre dma_writel(atdma, CHER, AT_DMA_SUSP(chan_id)); 94123b5e3adSNicolas Ferre 94223b5e3adSNicolas Ferre /* wait for FIFO to be empty */ 94323b5e3adSNicolas Ferre while (!(dma_readl(atdma, CHSR) & AT_DMA_EMPT(chan_id))) { 94423b5e3adSNicolas Ferre if (pause_timeout-- > 0) { 94523b5e3adSNicolas Ferre /* the FIFO can only drain if the peripheral 94623b5e3adSNicolas Ferre * is still requesting data: 94723b5e3adSNicolas Ferre * -> timeout if it is not the case. */ 94823b5e3adSNicolas Ferre dma_writel(atdma, CHDR, AT_DMA_RES(chan_id)); 94923b5e3adSNicolas Ferre spin_unlock_bh(&atchan->lock); 95023b5e3adSNicolas Ferre return -ETIMEDOUT; 95123b5e3adSNicolas Ferre } 95223b5e3adSNicolas Ferre cpu_relax(); 95323b5e3adSNicolas Ferre } 95423b5e3adSNicolas Ferre 95523b5e3adSNicolas Ferre set_bit(ATC_IS_PAUSED, &atchan->status); 95623b5e3adSNicolas Ferre 95723b5e3adSNicolas Ferre spin_unlock_bh(&atchan->lock); 95823b5e3adSNicolas Ferre } else if (cmd == DMA_RESUME) { 95923b5e3adSNicolas Ferre if (!test_bit(ATC_IS_PAUSED, &atchan->status)) 96023b5e3adSNicolas Ferre return 0; 96123b5e3adSNicolas Ferre 96223b5e3adSNicolas Ferre spin_lock_bh(&atchan->lock); 96323b5e3adSNicolas Ferre 96423b5e3adSNicolas Ferre dma_writel(atdma, CHDR, AT_DMA_RES(chan_id)); 96523b5e3adSNicolas Ferre clear_bit(ATC_IS_PAUSED, &atchan->status); 96623b5e3adSNicolas Ferre 96723b5e3adSNicolas Ferre spin_unlock_bh(&atchan->lock); 96823b5e3adSNicolas Ferre } else if (cmd == DMA_TERMINATE_ALL) { 96923b5e3adSNicolas Ferre struct at_desc *desc, *_desc; 970808347f6SNicolas Ferre /* 971808347f6SNicolas Ferre * This is only called when something went wrong elsewhere, so 972808347f6SNicolas Ferre * we don't really care about the data. Just disable the 973808347f6SNicolas Ferre * channel. We still have to poll the channel enable bit due 974808347f6SNicolas Ferre * to AHB/HSB limitations. 975808347f6SNicolas Ferre */ 976808347f6SNicolas Ferre spin_lock_bh(&atchan->lock); 977808347f6SNicolas Ferre 97823b5e3adSNicolas Ferre /* disabling channel: must also remove suspend state */ 97923b5e3adSNicolas Ferre dma_writel(atdma, CHDR, AT_DMA_RES(chan_id) | atchan->mask); 980808347f6SNicolas Ferre 981808347f6SNicolas Ferre /* confirm that this channel is disabled */ 982808347f6SNicolas Ferre while (dma_readl(atdma, CHSR) & atchan->mask) 983808347f6SNicolas Ferre cpu_relax(); 984808347f6SNicolas Ferre 985808347f6SNicolas Ferre /* active_list entries will end up before queued entries */ 986808347f6SNicolas Ferre list_splice_init(&atchan->queue, &list); 987808347f6SNicolas Ferre list_splice_init(&atchan->active_list, &list); 988808347f6SNicolas Ferre 989808347f6SNicolas Ferre /* Flush all pending and queued descriptors */ 990808347f6SNicolas Ferre list_for_each_entry_safe(desc, _desc, &list, desc_node) 991808347f6SNicolas Ferre atc_chain_complete(atchan, desc); 992c3635c78SLinus Walleij 99323b5e3adSNicolas Ferre clear_bit(ATC_IS_PAUSED, &atchan->status); 99453830cc7SNicolas Ferre /* if channel dedicated to cyclic operations, free it */ 99553830cc7SNicolas Ferre clear_bit(ATC_IS_CYCLIC, &atchan->status); 99653830cc7SNicolas Ferre 997b0ebeb9cSYong Wang spin_unlock_bh(&atchan->lock); 99823b5e3adSNicolas Ferre } else { 99923b5e3adSNicolas Ferre return -ENXIO; 100023b5e3adSNicolas Ferre } 1001b0ebeb9cSYong Wang 1002c3635c78SLinus Walleij return 0; 1003808347f6SNicolas Ferre } 1004808347f6SNicolas Ferre 1005dc78baa2SNicolas Ferre /** 100607934481SLinus Walleij * atc_tx_status - poll for transaction completion 1007dc78baa2SNicolas Ferre * @chan: DMA channel 1008dc78baa2SNicolas Ferre * @cookie: transaction identifier to check status of 100907934481SLinus Walleij * @txstate: if not %NULL updated with transaction state 1010dc78baa2SNicolas Ferre * 101107934481SLinus Walleij * If @txstate is passed in, upon return it reflect the driver 1012dc78baa2SNicolas Ferre * internal state and can be used with dma_async_is_complete() to check 1013dc78baa2SNicolas Ferre * the status of multiple cookies without re-checking hardware state. 1014dc78baa2SNicolas Ferre */ 1015dc78baa2SNicolas Ferre static enum dma_status 101607934481SLinus Walleij atc_tx_status(struct dma_chan *chan, 1017dc78baa2SNicolas Ferre dma_cookie_t cookie, 101807934481SLinus Walleij struct dma_tx_state *txstate) 1019dc78baa2SNicolas Ferre { 1020dc78baa2SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 1021dc78baa2SNicolas Ferre dma_cookie_t last_used; 1022dc78baa2SNicolas Ferre dma_cookie_t last_complete; 1023dc78baa2SNicolas Ferre enum dma_status ret; 1024dc78baa2SNicolas Ferre 10254297a462SNicolas Ferre spin_lock_bh(&atchan->lock); 1026dc78baa2SNicolas Ferre 1027dc78baa2SNicolas Ferre last_complete = atchan->completed_cookie; 1028dc78baa2SNicolas Ferre last_used = chan->cookie; 1029dc78baa2SNicolas Ferre 1030dc78baa2SNicolas Ferre ret = dma_async_is_complete(cookie, last_complete, last_used); 1031dc78baa2SNicolas Ferre if (ret != DMA_SUCCESS) { 1032dc78baa2SNicolas Ferre atc_cleanup_descriptors(atchan); 1033dc78baa2SNicolas Ferre 1034dc78baa2SNicolas Ferre last_complete = atchan->completed_cookie; 1035dc78baa2SNicolas Ferre last_used = chan->cookie; 1036dc78baa2SNicolas Ferre 1037dc78baa2SNicolas Ferre ret = dma_async_is_complete(cookie, last_complete, last_used); 1038dc78baa2SNicolas Ferre } 1039dc78baa2SNicolas Ferre 10404297a462SNicolas Ferre spin_unlock_bh(&atchan->lock); 1041dc78baa2SNicolas Ferre 1042543aabc7SNicolas Ferre if (ret != DMA_SUCCESS) 1043543aabc7SNicolas Ferre dma_set_tx_state(txstate, last_complete, last_used, 1044543aabc7SNicolas Ferre atc_first_active(atchan)->len); 1045543aabc7SNicolas Ferre else 1046bca34692SDan Williams dma_set_tx_state(txstate, last_complete, last_used, 0); 1047543aabc7SNicolas Ferre 104823b5e3adSNicolas Ferre if (test_bit(ATC_IS_PAUSED, &atchan->status)) 104923b5e3adSNicolas Ferre ret = DMA_PAUSED; 105023b5e3adSNicolas Ferre 105123b5e3adSNicolas Ferre dev_vdbg(chan2dev(chan), "tx_status %d: cookie = %d (d%d, u%d)\n", 105223b5e3adSNicolas Ferre ret, cookie, last_complete ? last_complete : 0, 105307934481SLinus Walleij last_used ? last_used : 0); 1054dc78baa2SNicolas Ferre 1055dc78baa2SNicolas Ferre return ret; 1056dc78baa2SNicolas Ferre } 1057dc78baa2SNicolas Ferre 1058dc78baa2SNicolas Ferre /** 1059dc78baa2SNicolas Ferre * atc_issue_pending - try to finish work 1060dc78baa2SNicolas Ferre * @chan: target DMA channel 1061dc78baa2SNicolas Ferre */ 1062dc78baa2SNicolas Ferre static void atc_issue_pending(struct dma_chan *chan) 1063dc78baa2SNicolas Ferre { 1064dc78baa2SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 1065dc78baa2SNicolas Ferre 1066dc78baa2SNicolas Ferre dev_vdbg(chan2dev(chan), "issue_pending\n"); 1067dc78baa2SNicolas Ferre 106853830cc7SNicolas Ferre /* Not needed for cyclic transfers */ 106953830cc7SNicolas Ferre if (test_bit(ATC_IS_CYCLIC, &atchan->status)) 107053830cc7SNicolas Ferre return; 107153830cc7SNicolas Ferre 1072dc78baa2SNicolas Ferre spin_lock_bh(&atchan->lock); 1073dda36f98SNicolas Ferre if (!atc_chan_is_enabled(atchan)) { 1074dc78baa2SNicolas Ferre atc_advance_work(atchan); 1075dc78baa2SNicolas Ferre } 1076dda36f98SNicolas Ferre spin_unlock_bh(&atchan->lock); 1077dc78baa2SNicolas Ferre } 1078dc78baa2SNicolas Ferre 1079dc78baa2SNicolas Ferre /** 1080dc78baa2SNicolas Ferre * atc_alloc_chan_resources - allocate resources for DMA channel 1081dc78baa2SNicolas Ferre * @chan: allocate descriptor resources for this channel 1082dc78baa2SNicolas Ferre * @client: current client requesting the channel be ready for requests 1083dc78baa2SNicolas Ferre * 1084dc78baa2SNicolas Ferre * return - the number of allocated descriptors 1085dc78baa2SNicolas Ferre */ 1086dc78baa2SNicolas Ferre static int atc_alloc_chan_resources(struct dma_chan *chan) 1087dc78baa2SNicolas Ferre { 1088dc78baa2SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 1089dc78baa2SNicolas Ferre struct at_dma *atdma = to_at_dma(chan->device); 1090dc78baa2SNicolas Ferre struct at_desc *desc; 1091808347f6SNicolas Ferre struct at_dma_slave *atslave; 1092dc78baa2SNicolas Ferre int i; 1093808347f6SNicolas Ferre u32 cfg; 1094dc78baa2SNicolas Ferre LIST_HEAD(tmp_list); 1095dc78baa2SNicolas Ferre 1096dc78baa2SNicolas Ferre dev_vdbg(chan2dev(chan), "alloc_chan_resources\n"); 1097dc78baa2SNicolas Ferre 1098dc78baa2SNicolas Ferre /* ASSERT: channel is idle */ 1099dc78baa2SNicolas Ferre if (atc_chan_is_enabled(atchan)) { 1100dc78baa2SNicolas Ferre dev_dbg(chan2dev(chan), "DMA channel not idle ?\n"); 1101dc78baa2SNicolas Ferre return -EIO; 1102dc78baa2SNicolas Ferre } 1103dc78baa2SNicolas Ferre 1104808347f6SNicolas Ferre cfg = ATC_DEFAULT_CFG; 1105808347f6SNicolas Ferre 1106808347f6SNicolas Ferre atslave = chan->private; 1107808347f6SNicolas Ferre if (atslave) { 1108808347f6SNicolas Ferre /* 1109808347f6SNicolas Ferre * We need controller-specific data to set up slave 1110808347f6SNicolas Ferre * transfers. 1111808347f6SNicolas Ferre */ 1112808347f6SNicolas Ferre BUG_ON(!atslave->dma_dev || atslave->dma_dev != atdma->dma_common.dev); 1113808347f6SNicolas Ferre 1114808347f6SNicolas Ferre /* if cfg configuration specified take it instad of default */ 1115808347f6SNicolas Ferre if (atslave->cfg) 1116808347f6SNicolas Ferre cfg = atslave->cfg; 1117808347f6SNicolas Ferre } 1118808347f6SNicolas Ferre 1119808347f6SNicolas Ferre /* have we already been set up? 1120808347f6SNicolas Ferre * reconfigure channel but no need to reallocate descriptors */ 1121dc78baa2SNicolas Ferre if (!list_empty(&atchan->free_list)) 1122dc78baa2SNicolas Ferre return atchan->descs_allocated; 1123dc78baa2SNicolas Ferre 1124dc78baa2SNicolas Ferre /* Allocate initial pool of descriptors */ 1125dc78baa2SNicolas Ferre for (i = 0; i < init_nr_desc_per_channel; i++) { 1126dc78baa2SNicolas Ferre desc = atc_alloc_descriptor(chan, GFP_KERNEL); 1127dc78baa2SNicolas Ferre if (!desc) { 1128dc78baa2SNicolas Ferre dev_err(atdma->dma_common.dev, 1129dc78baa2SNicolas Ferre "Only %d initial descriptors\n", i); 1130dc78baa2SNicolas Ferre break; 1131dc78baa2SNicolas Ferre } 1132dc78baa2SNicolas Ferre list_add_tail(&desc->desc_node, &tmp_list); 1133dc78baa2SNicolas Ferre } 1134dc78baa2SNicolas Ferre 1135dc78baa2SNicolas Ferre spin_lock_bh(&atchan->lock); 1136dc78baa2SNicolas Ferre atchan->descs_allocated = i; 1137dc78baa2SNicolas Ferre list_splice(&tmp_list, &atchan->free_list); 1138dc78baa2SNicolas Ferre atchan->completed_cookie = chan->cookie = 1; 1139dc78baa2SNicolas Ferre spin_unlock_bh(&atchan->lock); 1140dc78baa2SNicolas Ferre 1141dc78baa2SNicolas Ferre /* channel parameters */ 1142808347f6SNicolas Ferre channel_writel(atchan, CFG, cfg); 1143dc78baa2SNicolas Ferre 1144dc78baa2SNicolas Ferre dev_dbg(chan2dev(chan), 1145dc78baa2SNicolas Ferre "alloc_chan_resources: allocated %d descriptors\n", 1146dc78baa2SNicolas Ferre atchan->descs_allocated); 1147dc78baa2SNicolas Ferre 1148dc78baa2SNicolas Ferre return atchan->descs_allocated; 1149dc78baa2SNicolas Ferre } 1150dc78baa2SNicolas Ferre 1151dc78baa2SNicolas Ferre /** 1152dc78baa2SNicolas Ferre * atc_free_chan_resources - free all channel resources 1153dc78baa2SNicolas Ferre * @chan: DMA channel 1154dc78baa2SNicolas Ferre */ 1155dc78baa2SNicolas Ferre static void atc_free_chan_resources(struct dma_chan *chan) 1156dc78baa2SNicolas Ferre { 1157dc78baa2SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 1158dc78baa2SNicolas Ferre struct at_dma *atdma = to_at_dma(chan->device); 1159dc78baa2SNicolas Ferre struct at_desc *desc, *_desc; 1160dc78baa2SNicolas Ferre LIST_HEAD(list); 1161dc78baa2SNicolas Ferre 1162dc78baa2SNicolas Ferre dev_dbg(chan2dev(chan), "free_chan_resources: (descs allocated=%u)\n", 1163dc78baa2SNicolas Ferre atchan->descs_allocated); 1164dc78baa2SNicolas Ferre 1165dc78baa2SNicolas Ferre /* ASSERT: channel is idle */ 1166dc78baa2SNicolas Ferre BUG_ON(!list_empty(&atchan->active_list)); 1167dc78baa2SNicolas Ferre BUG_ON(!list_empty(&atchan->queue)); 1168dc78baa2SNicolas Ferre BUG_ON(atc_chan_is_enabled(atchan)); 1169dc78baa2SNicolas Ferre 1170dc78baa2SNicolas Ferre list_for_each_entry_safe(desc, _desc, &atchan->free_list, desc_node) { 1171dc78baa2SNicolas Ferre dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc); 1172dc78baa2SNicolas Ferre list_del(&desc->desc_node); 1173dc78baa2SNicolas Ferre /* free link descriptor */ 1174dc78baa2SNicolas Ferre dma_pool_free(atdma->dma_desc_pool, desc, desc->txd.phys); 1175dc78baa2SNicolas Ferre } 1176dc78baa2SNicolas Ferre list_splice_init(&atchan->free_list, &list); 1177dc78baa2SNicolas Ferre atchan->descs_allocated = 0; 117853830cc7SNicolas Ferre atchan->status = 0; 1179dc78baa2SNicolas Ferre 1180dc78baa2SNicolas Ferre dev_vdbg(chan2dev(chan), "free_chan_resources: done\n"); 1181dc78baa2SNicolas Ferre } 1182dc78baa2SNicolas Ferre 1183dc78baa2SNicolas Ferre 1184dc78baa2SNicolas Ferre /*-- Module Management -----------------------------------------------*/ 1185dc78baa2SNicolas Ferre 1186dc78baa2SNicolas Ferre /** 1187dc78baa2SNicolas Ferre * at_dma_off - disable DMA controller 1188dc78baa2SNicolas Ferre * @atdma: the Atmel HDAMC device 1189dc78baa2SNicolas Ferre */ 1190dc78baa2SNicolas Ferre static void at_dma_off(struct at_dma *atdma) 1191dc78baa2SNicolas Ferre { 1192dc78baa2SNicolas Ferre dma_writel(atdma, EN, 0); 1193dc78baa2SNicolas Ferre 1194dc78baa2SNicolas Ferre /* disable all interrupts */ 1195dc78baa2SNicolas Ferre dma_writel(atdma, EBCIDR, -1L); 1196dc78baa2SNicolas Ferre 1197dc78baa2SNicolas Ferre /* confirm that all channels are disabled */ 1198dc78baa2SNicolas Ferre while (dma_readl(atdma, CHSR) & atdma->all_chan_mask) 1199dc78baa2SNicolas Ferre cpu_relax(); 1200dc78baa2SNicolas Ferre } 1201dc78baa2SNicolas Ferre 1202dc78baa2SNicolas Ferre static int __init at_dma_probe(struct platform_device *pdev) 1203dc78baa2SNicolas Ferre { 1204dc78baa2SNicolas Ferre struct at_dma_platform_data *pdata; 1205dc78baa2SNicolas Ferre struct resource *io; 1206dc78baa2SNicolas Ferre struct at_dma *atdma; 1207dc78baa2SNicolas Ferre size_t size; 1208dc78baa2SNicolas Ferre int irq; 1209dc78baa2SNicolas Ferre int err; 1210dc78baa2SNicolas Ferre int i; 1211dc78baa2SNicolas Ferre 1212dc78baa2SNicolas Ferre /* get DMA Controller parameters from platform */ 1213dc78baa2SNicolas Ferre pdata = pdev->dev.platform_data; 1214dc78baa2SNicolas Ferre if (!pdata || pdata->nr_channels > AT_DMA_MAX_NR_CHANNELS) 1215dc78baa2SNicolas Ferre return -EINVAL; 1216dc78baa2SNicolas Ferre 1217dc78baa2SNicolas Ferre io = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1218dc78baa2SNicolas Ferre if (!io) 1219dc78baa2SNicolas Ferre return -EINVAL; 1220dc78baa2SNicolas Ferre 1221dc78baa2SNicolas Ferre irq = platform_get_irq(pdev, 0); 1222dc78baa2SNicolas Ferre if (irq < 0) 1223dc78baa2SNicolas Ferre return irq; 1224dc78baa2SNicolas Ferre 1225dc78baa2SNicolas Ferre size = sizeof(struct at_dma); 1226dc78baa2SNicolas Ferre size += pdata->nr_channels * sizeof(struct at_dma_chan); 1227dc78baa2SNicolas Ferre atdma = kzalloc(size, GFP_KERNEL); 1228dc78baa2SNicolas Ferre if (!atdma) 1229dc78baa2SNicolas Ferre return -ENOMEM; 1230dc78baa2SNicolas Ferre 1231dc78baa2SNicolas Ferre /* discover transaction capabilites from the platform data */ 1232dc78baa2SNicolas Ferre atdma->dma_common.cap_mask = pdata->cap_mask; 1233dc78baa2SNicolas Ferre atdma->all_chan_mask = (1 << pdata->nr_channels) - 1; 1234dc78baa2SNicolas Ferre 1235dc78baa2SNicolas Ferre size = io->end - io->start + 1; 1236dc78baa2SNicolas Ferre if (!request_mem_region(io->start, size, pdev->dev.driver->name)) { 1237dc78baa2SNicolas Ferre err = -EBUSY; 1238dc78baa2SNicolas Ferre goto err_kfree; 1239dc78baa2SNicolas Ferre } 1240dc78baa2SNicolas Ferre 1241dc78baa2SNicolas Ferre atdma->regs = ioremap(io->start, size); 1242dc78baa2SNicolas Ferre if (!atdma->regs) { 1243dc78baa2SNicolas Ferre err = -ENOMEM; 1244dc78baa2SNicolas Ferre goto err_release_r; 1245dc78baa2SNicolas Ferre } 1246dc78baa2SNicolas Ferre 1247dc78baa2SNicolas Ferre atdma->clk = clk_get(&pdev->dev, "dma_clk"); 1248dc78baa2SNicolas Ferre if (IS_ERR(atdma->clk)) { 1249dc78baa2SNicolas Ferre err = PTR_ERR(atdma->clk); 1250dc78baa2SNicolas Ferre goto err_clk; 1251dc78baa2SNicolas Ferre } 1252dc78baa2SNicolas Ferre clk_enable(atdma->clk); 1253dc78baa2SNicolas Ferre 1254dc78baa2SNicolas Ferre /* force dma off, just in case */ 1255dc78baa2SNicolas Ferre at_dma_off(atdma); 1256dc78baa2SNicolas Ferre 1257dc78baa2SNicolas Ferre err = request_irq(irq, at_dma_interrupt, 0, "at_hdmac", atdma); 1258dc78baa2SNicolas Ferre if (err) 1259dc78baa2SNicolas Ferre goto err_irq; 1260dc78baa2SNicolas Ferre 1261dc78baa2SNicolas Ferre platform_set_drvdata(pdev, atdma); 1262dc78baa2SNicolas Ferre 1263dc78baa2SNicolas Ferre /* create a pool of consistent memory blocks for hardware descriptors */ 1264dc78baa2SNicolas Ferre atdma->dma_desc_pool = dma_pool_create("at_hdmac_desc_pool", 1265dc78baa2SNicolas Ferre &pdev->dev, sizeof(struct at_desc), 1266dc78baa2SNicolas Ferre 4 /* word alignment */, 0); 1267dc78baa2SNicolas Ferre if (!atdma->dma_desc_pool) { 1268dc78baa2SNicolas Ferre dev_err(&pdev->dev, "No memory for descriptors dma pool\n"); 1269dc78baa2SNicolas Ferre err = -ENOMEM; 1270dc78baa2SNicolas Ferre goto err_pool_create; 1271dc78baa2SNicolas Ferre } 1272dc78baa2SNicolas Ferre 1273dc78baa2SNicolas Ferre /* clear any pending interrupt */ 1274dc78baa2SNicolas Ferre while (dma_readl(atdma, EBCISR)) 1275dc78baa2SNicolas Ferre cpu_relax(); 1276dc78baa2SNicolas Ferre 1277dc78baa2SNicolas Ferre /* initialize channels related values */ 1278dc78baa2SNicolas Ferre INIT_LIST_HEAD(&atdma->dma_common.channels); 1279dc78baa2SNicolas Ferre for (i = 0; i < pdata->nr_channels; i++, atdma->dma_common.chancnt++) { 1280dc78baa2SNicolas Ferre struct at_dma_chan *atchan = &atdma->chan[i]; 1281dc78baa2SNicolas Ferre 1282dc78baa2SNicolas Ferre atchan->chan_common.device = &atdma->dma_common; 1283dc78baa2SNicolas Ferre atchan->chan_common.cookie = atchan->completed_cookie = 1; 1284dc78baa2SNicolas Ferre atchan->chan_common.chan_id = i; 1285dc78baa2SNicolas Ferre list_add_tail(&atchan->chan_common.device_node, 1286dc78baa2SNicolas Ferre &atdma->dma_common.channels); 1287dc78baa2SNicolas Ferre 1288dc78baa2SNicolas Ferre atchan->ch_regs = atdma->regs + ch_regs(i); 1289dc78baa2SNicolas Ferre spin_lock_init(&atchan->lock); 1290dc78baa2SNicolas Ferre atchan->mask = 1 << i; 1291dc78baa2SNicolas Ferre 1292dc78baa2SNicolas Ferre INIT_LIST_HEAD(&atchan->active_list); 1293dc78baa2SNicolas Ferre INIT_LIST_HEAD(&atchan->queue); 1294dc78baa2SNicolas Ferre INIT_LIST_HEAD(&atchan->free_list); 1295dc78baa2SNicolas Ferre 1296dc78baa2SNicolas Ferre tasklet_init(&atchan->tasklet, atc_tasklet, 1297dc78baa2SNicolas Ferre (unsigned long)atchan); 1298dc78baa2SNicolas Ferre atc_enable_irq(atchan); 1299dc78baa2SNicolas Ferre } 1300dc78baa2SNicolas Ferre 1301dc78baa2SNicolas Ferre /* set base routines */ 1302dc78baa2SNicolas Ferre atdma->dma_common.device_alloc_chan_resources = atc_alloc_chan_resources; 1303dc78baa2SNicolas Ferre atdma->dma_common.device_free_chan_resources = atc_free_chan_resources; 130407934481SLinus Walleij atdma->dma_common.device_tx_status = atc_tx_status; 1305dc78baa2SNicolas Ferre atdma->dma_common.device_issue_pending = atc_issue_pending; 1306dc78baa2SNicolas Ferre atdma->dma_common.dev = &pdev->dev; 1307dc78baa2SNicolas Ferre 1308dc78baa2SNicolas Ferre /* set prep routines based on capability */ 1309dc78baa2SNicolas Ferre if (dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask)) 1310dc78baa2SNicolas Ferre atdma->dma_common.device_prep_dma_memcpy = atc_prep_dma_memcpy; 1311dc78baa2SNicolas Ferre 131253830cc7SNicolas Ferre if (dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask)) 1313808347f6SNicolas Ferre atdma->dma_common.device_prep_slave_sg = atc_prep_slave_sg; 131453830cc7SNicolas Ferre 131553830cc7SNicolas Ferre if (dma_has_cap(DMA_CYCLIC, atdma->dma_common.cap_mask)) 131653830cc7SNicolas Ferre atdma->dma_common.device_prep_dma_cyclic = atc_prep_dma_cyclic; 131753830cc7SNicolas Ferre 131853830cc7SNicolas Ferre if (dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask) || 131953830cc7SNicolas Ferre dma_has_cap(DMA_CYCLIC, atdma->dma_common.cap_mask)) 1320c3635c78SLinus Walleij atdma->dma_common.device_control = atc_control; 1321808347f6SNicolas Ferre 1322dc78baa2SNicolas Ferre dma_writel(atdma, EN, AT_DMA_ENABLE); 1323dc78baa2SNicolas Ferre 1324dc78baa2SNicolas Ferre dev_info(&pdev->dev, "Atmel AHB DMA Controller ( %s%s), %d channels\n", 1325dc78baa2SNicolas Ferre dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask) ? "cpy " : "", 1326dc78baa2SNicolas Ferre dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask) ? "slave " : "", 1327dc78baa2SNicolas Ferre atdma->dma_common.chancnt); 1328dc78baa2SNicolas Ferre 1329dc78baa2SNicolas Ferre dma_async_device_register(&atdma->dma_common); 1330dc78baa2SNicolas Ferre 1331dc78baa2SNicolas Ferre return 0; 1332dc78baa2SNicolas Ferre 1333dc78baa2SNicolas Ferre err_pool_create: 1334dc78baa2SNicolas Ferre platform_set_drvdata(pdev, NULL); 1335dc78baa2SNicolas Ferre free_irq(platform_get_irq(pdev, 0), atdma); 1336dc78baa2SNicolas Ferre err_irq: 1337dc78baa2SNicolas Ferre clk_disable(atdma->clk); 1338dc78baa2SNicolas Ferre clk_put(atdma->clk); 1339dc78baa2SNicolas Ferre err_clk: 1340dc78baa2SNicolas Ferre iounmap(atdma->regs); 1341dc78baa2SNicolas Ferre atdma->regs = NULL; 1342dc78baa2SNicolas Ferre err_release_r: 1343dc78baa2SNicolas Ferre release_mem_region(io->start, size); 1344dc78baa2SNicolas Ferre err_kfree: 1345dc78baa2SNicolas Ferre kfree(atdma); 1346dc78baa2SNicolas Ferre return err; 1347dc78baa2SNicolas Ferre } 1348dc78baa2SNicolas Ferre 1349dc78baa2SNicolas Ferre static int __exit at_dma_remove(struct platform_device *pdev) 1350dc78baa2SNicolas Ferre { 1351dc78baa2SNicolas Ferre struct at_dma *atdma = platform_get_drvdata(pdev); 1352dc78baa2SNicolas Ferre struct dma_chan *chan, *_chan; 1353dc78baa2SNicolas Ferre struct resource *io; 1354dc78baa2SNicolas Ferre 1355dc78baa2SNicolas Ferre at_dma_off(atdma); 1356dc78baa2SNicolas Ferre dma_async_device_unregister(&atdma->dma_common); 1357dc78baa2SNicolas Ferre 1358dc78baa2SNicolas Ferre dma_pool_destroy(atdma->dma_desc_pool); 1359dc78baa2SNicolas Ferre platform_set_drvdata(pdev, NULL); 1360dc78baa2SNicolas Ferre free_irq(platform_get_irq(pdev, 0), atdma); 1361dc78baa2SNicolas Ferre 1362dc78baa2SNicolas Ferre list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels, 1363dc78baa2SNicolas Ferre device_node) { 1364dc78baa2SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 1365dc78baa2SNicolas Ferre 1366dc78baa2SNicolas Ferre /* Disable interrupts */ 1367dc78baa2SNicolas Ferre atc_disable_irq(atchan); 1368dc78baa2SNicolas Ferre tasklet_disable(&atchan->tasklet); 1369dc78baa2SNicolas Ferre 1370dc78baa2SNicolas Ferre tasklet_kill(&atchan->tasklet); 1371dc78baa2SNicolas Ferre list_del(&chan->device_node); 1372dc78baa2SNicolas Ferre } 1373dc78baa2SNicolas Ferre 1374dc78baa2SNicolas Ferre clk_disable(atdma->clk); 1375dc78baa2SNicolas Ferre clk_put(atdma->clk); 1376dc78baa2SNicolas Ferre 1377dc78baa2SNicolas Ferre iounmap(atdma->regs); 1378dc78baa2SNicolas Ferre atdma->regs = NULL; 1379dc78baa2SNicolas Ferre 1380dc78baa2SNicolas Ferre io = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1381dc78baa2SNicolas Ferre release_mem_region(io->start, io->end - io->start + 1); 1382dc78baa2SNicolas Ferre 1383dc78baa2SNicolas Ferre kfree(atdma); 1384dc78baa2SNicolas Ferre 1385dc78baa2SNicolas Ferre return 0; 1386dc78baa2SNicolas Ferre } 1387dc78baa2SNicolas Ferre 1388dc78baa2SNicolas Ferre static void at_dma_shutdown(struct platform_device *pdev) 1389dc78baa2SNicolas Ferre { 1390dc78baa2SNicolas Ferre struct at_dma *atdma = platform_get_drvdata(pdev); 1391dc78baa2SNicolas Ferre 1392dc78baa2SNicolas Ferre at_dma_off(platform_get_drvdata(pdev)); 1393dc78baa2SNicolas Ferre clk_disable(atdma->clk); 1394dc78baa2SNicolas Ferre } 1395dc78baa2SNicolas Ferre 139633f82d14SDan Williams static int at_dma_suspend_noirq(struct device *dev) 1397dc78baa2SNicolas Ferre { 139833f82d14SDan Williams struct platform_device *pdev = to_platform_device(dev); 1399dc78baa2SNicolas Ferre struct at_dma *atdma = platform_get_drvdata(pdev); 1400dc78baa2SNicolas Ferre 1401dc78baa2SNicolas Ferre at_dma_off(platform_get_drvdata(pdev)); 1402dc78baa2SNicolas Ferre clk_disable(atdma->clk); 1403dc78baa2SNicolas Ferre return 0; 1404dc78baa2SNicolas Ferre } 1405dc78baa2SNicolas Ferre 140633f82d14SDan Williams static int at_dma_resume_noirq(struct device *dev) 1407dc78baa2SNicolas Ferre { 140833f82d14SDan Williams struct platform_device *pdev = to_platform_device(dev); 1409dc78baa2SNicolas Ferre struct at_dma *atdma = platform_get_drvdata(pdev); 1410dc78baa2SNicolas Ferre 1411dc78baa2SNicolas Ferre clk_enable(atdma->clk); 1412dc78baa2SNicolas Ferre dma_writel(atdma, EN, AT_DMA_ENABLE); 1413dc78baa2SNicolas Ferre return 0; 1414dc78baa2SNicolas Ferre } 1415dc78baa2SNicolas Ferre 141647145210SAlexey Dobriyan static const struct dev_pm_ops at_dma_dev_pm_ops = { 141733f82d14SDan Williams .suspend_noirq = at_dma_suspend_noirq, 141833f82d14SDan Williams .resume_noirq = at_dma_resume_noirq, 141933f82d14SDan Williams }; 142033f82d14SDan Williams 1421dc78baa2SNicolas Ferre static struct platform_driver at_dma_driver = { 1422dc78baa2SNicolas Ferre .remove = __exit_p(at_dma_remove), 1423dc78baa2SNicolas Ferre .shutdown = at_dma_shutdown, 1424dc78baa2SNicolas Ferre .driver = { 1425dc78baa2SNicolas Ferre .name = "at_hdmac", 142633f82d14SDan Williams .pm = &at_dma_dev_pm_ops, 1427dc78baa2SNicolas Ferre }, 1428dc78baa2SNicolas Ferre }; 1429dc78baa2SNicolas Ferre 1430dc78baa2SNicolas Ferre static int __init at_dma_init(void) 1431dc78baa2SNicolas Ferre { 1432dc78baa2SNicolas Ferre return platform_driver_probe(&at_dma_driver, at_dma_probe); 1433dc78baa2SNicolas Ferre } 143493d0bec2SEric Xu subsys_initcall(at_dma_init); 1435dc78baa2SNicolas Ferre 1436dc78baa2SNicolas Ferre static void __exit at_dma_exit(void) 1437dc78baa2SNicolas Ferre { 1438dc78baa2SNicolas Ferre platform_driver_unregister(&at_dma_driver); 1439dc78baa2SNicolas Ferre } 1440dc78baa2SNicolas Ferre module_exit(at_dma_exit); 1441dc78baa2SNicolas Ferre 1442dc78baa2SNicolas Ferre MODULE_DESCRIPTION("Atmel AHB DMA Controller driver"); 1443dc78baa2SNicolas Ferre MODULE_AUTHOR("Nicolas Ferre <nicolas.ferre@atmel.com>"); 1444dc78baa2SNicolas Ferre MODULE_LICENSE("GPL"); 1445dc78baa2SNicolas Ferre MODULE_ALIAS("platform:at_hdmac"); 1446