1dc78baa2SNicolas Ferre /* 2dc78baa2SNicolas Ferre * Driver for the Atmel AHB DMA Controller (aka HDMA or DMAC on AT91 systems) 3dc78baa2SNicolas Ferre * 4dc78baa2SNicolas Ferre * Copyright (C) 2008 Atmel Corporation 5dc78baa2SNicolas Ferre * 6dc78baa2SNicolas Ferre * This program is free software; you can redistribute it and/or modify 7dc78baa2SNicolas Ferre * it under the terms of the GNU General Public License as published by 8dc78baa2SNicolas Ferre * the Free Software Foundation; either version 2 of the License, or 9dc78baa2SNicolas Ferre * (at your option) any later version. 10dc78baa2SNicolas Ferre * 11dc78baa2SNicolas Ferre * 12dc78baa2SNicolas Ferre * This supports the Atmel AHB DMA Controller, 13dc78baa2SNicolas Ferre * 14dc78baa2SNicolas Ferre * The driver has currently been tested with the Atmel AT91SAM9RL 15dc78baa2SNicolas Ferre * and AT91SAM9G45 series. 16dc78baa2SNicolas Ferre */ 17dc78baa2SNicolas Ferre 18dc78baa2SNicolas Ferre #include <linux/clk.h> 19dc78baa2SNicolas Ferre #include <linux/dmaengine.h> 20dc78baa2SNicolas Ferre #include <linux/dma-mapping.h> 21dc78baa2SNicolas Ferre #include <linux/dmapool.h> 22dc78baa2SNicolas Ferre #include <linux/interrupt.h> 23dc78baa2SNicolas Ferre #include <linux/module.h> 24dc78baa2SNicolas Ferre #include <linux/platform_device.h> 255a0e3ad6STejun Heo #include <linux/slab.h> 26c5115953SNicolas Ferre #include <linux/of.h> 27c5115953SNicolas Ferre #include <linux/of_device.h> 28dc78baa2SNicolas Ferre 29dc78baa2SNicolas Ferre #include "at_hdmac_regs.h" 30d2ebfb33SRussell King - ARM Linux #include "dmaengine.h" 31dc78baa2SNicolas Ferre 32dc78baa2SNicolas Ferre /* 33dc78baa2SNicolas Ferre * Glossary 34dc78baa2SNicolas Ferre * -------- 35dc78baa2SNicolas Ferre * 36dc78baa2SNicolas Ferre * at_hdmac : Name of the ATmel AHB DMA Controller 37dc78baa2SNicolas Ferre * at_dma_ / atdma : ATmel DMA controller entity related 38dc78baa2SNicolas Ferre * atc_ / atchan : ATmel DMA Channel entity related 39dc78baa2SNicolas Ferre */ 40dc78baa2SNicolas Ferre 41dc78baa2SNicolas Ferre #define ATC_DEFAULT_CFG (ATC_FIFOCFG_HALFFIFO) 42ae14d4b5SNicolas Ferre #define ATC_DEFAULT_CTRLB (ATC_SIF(AT_DMA_MEM_IF) \ 43ae14d4b5SNicolas Ferre |ATC_DIF(AT_DMA_MEM_IF)) 44dc78baa2SNicolas Ferre 45dc78baa2SNicolas Ferre /* 46dc78baa2SNicolas Ferre * Initial number of descriptors to allocate for each channel. This could 47dc78baa2SNicolas Ferre * be increased during dma usage. 48dc78baa2SNicolas Ferre */ 49dc78baa2SNicolas Ferre static unsigned int init_nr_desc_per_channel = 64; 50dc78baa2SNicolas Ferre module_param(init_nr_desc_per_channel, uint, 0644); 51dc78baa2SNicolas Ferre MODULE_PARM_DESC(init_nr_desc_per_channel, 52dc78baa2SNicolas Ferre "initial descriptors per channel (default: 64)"); 53dc78baa2SNicolas Ferre 54dc78baa2SNicolas Ferre 55dc78baa2SNicolas Ferre /* prototypes */ 56dc78baa2SNicolas Ferre static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx); 57dc78baa2SNicolas Ferre 58dc78baa2SNicolas Ferre 59dc78baa2SNicolas Ferre /*----------------------------------------------------------------------*/ 60dc78baa2SNicolas Ferre 61dc78baa2SNicolas Ferre static struct at_desc *atc_first_active(struct at_dma_chan *atchan) 62dc78baa2SNicolas Ferre { 63dc78baa2SNicolas Ferre return list_first_entry(&atchan->active_list, 64dc78baa2SNicolas Ferre struct at_desc, desc_node); 65dc78baa2SNicolas Ferre } 66dc78baa2SNicolas Ferre 67dc78baa2SNicolas Ferre static struct at_desc *atc_first_queued(struct at_dma_chan *atchan) 68dc78baa2SNicolas Ferre { 69dc78baa2SNicolas Ferre return list_first_entry(&atchan->queue, 70dc78baa2SNicolas Ferre struct at_desc, desc_node); 71dc78baa2SNicolas Ferre } 72dc78baa2SNicolas Ferre 73dc78baa2SNicolas Ferre /** 74421f91d2SUwe Kleine-König * atc_alloc_descriptor - allocate and return an initialized descriptor 75dc78baa2SNicolas Ferre * @chan: the channel to allocate descriptors for 76dc78baa2SNicolas Ferre * @gfp_flags: GFP allocation flags 77dc78baa2SNicolas Ferre * 78dc78baa2SNicolas Ferre * Note: The ack-bit is positioned in the descriptor flag at creation time 79dc78baa2SNicolas Ferre * to make initial allocation more convenient. This bit will be cleared 80dc78baa2SNicolas Ferre * and control will be given to client at usage time (during 81dc78baa2SNicolas Ferre * preparation functions). 82dc78baa2SNicolas Ferre */ 83dc78baa2SNicolas Ferre static struct at_desc *atc_alloc_descriptor(struct dma_chan *chan, 84dc78baa2SNicolas Ferre gfp_t gfp_flags) 85dc78baa2SNicolas Ferre { 86dc78baa2SNicolas Ferre struct at_desc *desc = NULL; 87dc78baa2SNicolas Ferre struct at_dma *atdma = to_at_dma(chan->device); 88dc78baa2SNicolas Ferre dma_addr_t phys; 89dc78baa2SNicolas Ferre 90dc78baa2SNicolas Ferre desc = dma_pool_alloc(atdma->dma_desc_pool, gfp_flags, &phys); 91dc78baa2SNicolas Ferre if (desc) { 92dc78baa2SNicolas Ferre memset(desc, 0, sizeof(struct at_desc)); 93285a3c71SDan Williams INIT_LIST_HEAD(&desc->tx_list); 94dc78baa2SNicolas Ferre dma_async_tx_descriptor_init(&desc->txd, chan); 95dc78baa2SNicolas Ferre /* txd.flags will be overwritten in prep functions */ 96dc78baa2SNicolas Ferre desc->txd.flags = DMA_CTRL_ACK; 97dc78baa2SNicolas Ferre desc->txd.tx_submit = atc_tx_submit; 98dc78baa2SNicolas Ferre desc->txd.phys = phys; 99dc78baa2SNicolas Ferre } 100dc78baa2SNicolas Ferre 101dc78baa2SNicolas Ferre return desc; 102dc78baa2SNicolas Ferre } 103dc78baa2SNicolas Ferre 104dc78baa2SNicolas Ferre /** 105af901ca1SAndré Goddard Rosa * atc_desc_get - get an unused descriptor from free_list 106dc78baa2SNicolas Ferre * @atchan: channel we want a new descriptor for 107dc78baa2SNicolas Ferre */ 108dc78baa2SNicolas Ferre static struct at_desc *atc_desc_get(struct at_dma_chan *atchan) 109dc78baa2SNicolas Ferre { 110dc78baa2SNicolas Ferre struct at_desc *desc, *_desc; 111dc78baa2SNicolas Ferre struct at_desc *ret = NULL; 112d8cb04b0SNicolas Ferre unsigned long flags; 113dc78baa2SNicolas Ferre unsigned int i = 0; 114dc78baa2SNicolas Ferre LIST_HEAD(tmp_list); 115dc78baa2SNicolas Ferre 116d8cb04b0SNicolas Ferre spin_lock_irqsave(&atchan->lock, flags); 117dc78baa2SNicolas Ferre list_for_each_entry_safe(desc, _desc, &atchan->free_list, desc_node) { 118dc78baa2SNicolas Ferre i++; 119dc78baa2SNicolas Ferre if (async_tx_test_ack(&desc->txd)) { 120dc78baa2SNicolas Ferre list_del(&desc->desc_node); 121dc78baa2SNicolas Ferre ret = desc; 122dc78baa2SNicolas Ferre break; 123dc78baa2SNicolas Ferre } 124dc78baa2SNicolas Ferre dev_dbg(chan2dev(&atchan->chan_common), 125dc78baa2SNicolas Ferre "desc %p not ACKed\n", desc); 126dc78baa2SNicolas Ferre } 127d8cb04b0SNicolas Ferre spin_unlock_irqrestore(&atchan->lock, flags); 128dc78baa2SNicolas Ferre dev_vdbg(chan2dev(&atchan->chan_common), 129dc78baa2SNicolas Ferre "scanned %u descriptors on freelist\n", i); 130dc78baa2SNicolas Ferre 131dc78baa2SNicolas Ferre /* no more descriptor available in initial pool: create one more */ 132dc78baa2SNicolas Ferre if (!ret) { 133dc78baa2SNicolas Ferre ret = atc_alloc_descriptor(&atchan->chan_common, GFP_ATOMIC); 134dc78baa2SNicolas Ferre if (ret) { 135d8cb04b0SNicolas Ferre spin_lock_irqsave(&atchan->lock, flags); 136dc78baa2SNicolas Ferre atchan->descs_allocated++; 137d8cb04b0SNicolas Ferre spin_unlock_irqrestore(&atchan->lock, flags); 138dc78baa2SNicolas Ferre } else { 139dc78baa2SNicolas Ferre dev_err(chan2dev(&atchan->chan_common), 140dc78baa2SNicolas Ferre "not enough descriptors available\n"); 141dc78baa2SNicolas Ferre } 142dc78baa2SNicolas Ferre } 143dc78baa2SNicolas Ferre 144dc78baa2SNicolas Ferre return ret; 145dc78baa2SNicolas Ferre } 146dc78baa2SNicolas Ferre 147dc78baa2SNicolas Ferre /** 148dc78baa2SNicolas Ferre * atc_desc_put - move a descriptor, including any children, to the free list 149dc78baa2SNicolas Ferre * @atchan: channel we work on 150dc78baa2SNicolas Ferre * @desc: descriptor, at the head of a chain, to move to free list 151dc78baa2SNicolas Ferre */ 152dc78baa2SNicolas Ferre static void atc_desc_put(struct at_dma_chan *atchan, struct at_desc *desc) 153dc78baa2SNicolas Ferre { 154dc78baa2SNicolas Ferre if (desc) { 155dc78baa2SNicolas Ferre struct at_desc *child; 156d8cb04b0SNicolas Ferre unsigned long flags; 157dc78baa2SNicolas Ferre 158d8cb04b0SNicolas Ferre spin_lock_irqsave(&atchan->lock, flags); 159285a3c71SDan Williams list_for_each_entry(child, &desc->tx_list, desc_node) 160dc78baa2SNicolas Ferre dev_vdbg(chan2dev(&atchan->chan_common), 161dc78baa2SNicolas Ferre "moving child desc %p to freelist\n", 162dc78baa2SNicolas Ferre child); 163285a3c71SDan Williams list_splice_init(&desc->tx_list, &atchan->free_list); 164dc78baa2SNicolas Ferre dev_vdbg(chan2dev(&atchan->chan_common), 165dc78baa2SNicolas Ferre "moving desc %p to freelist\n", desc); 166dc78baa2SNicolas Ferre list_add(&desc->desc_node, &atchan->free_list); 167d8cb04b0SNicolas Ferre spin_unlock_irqrestore(&atchan->lock, flags); 168dc78baa2SNicolas Ferre } 169dc78baa2SNicolas Ferre } 170dc78baa2SNicolas Ferre 171dc78baa2SNicolas Ferre /** 172d73111c6SMasanari Iida * atc_desc_chain - build chain adding a descriptor 173d73111c6SMasanari Iida * @first: address of first descriptor of the chain 174d73111c6SMasanari Iida * @prev: address of previous descriptor of the chain 17553830cc7SNicolas Ferre * @desc: descriptor to queue 17653830cc7SNicolas Ferre * 17753830cc7SNicolas Ferre * Called from prep_* functions 17853830cc7SNicolas Ferre */ 17953830cc7SNicolas Ferre static void atc_desc_chain(struct at_desc **first, struct at_desc **prev, 18053830cc7SNicolas Ferre struct at_desc *desc) 18153830cc7SNicolas Ferre { 18253830cc7SNicolas Ferre if (!(*first)) { 18353830cc7SNicolas Ferre *first = desc; 18453830cc7SNicolas Ferre } else { 18553830cc7SNicolas Ferre /* inform the HW lli about chaining */ 18653830cc7SNicolas Ferre (*prev)->lli.dscr = desc->txd.phys; 18753830cc7SNicolas Ferre /* insert the link descriptor to the LD ring */ 18853830cc7SNicolas Ferre list_add_tail(&desc->desc_node, 18953830cc7SNicolas Ferre &(*first)->tx_list); 19053830cc7SNicolas Ferre } 19153830cc7SNicolas Ferre *prev = desc; 19253830cc7SNicolas Ferre } 19353830cc7SNicolas Ferre 19453830cc7SNicolas Ferre /** 195dc78baa2SNicolas Ferre * atc_dostart - starts the DMA engine for real 196dc78baa2SNicolas Ferre * @atchan: the channel we want to start 197dc78baa2SNicolas Ferre * @first: first descriptor in the list we want to begin with 198dc78baa2SNicolas Ferre * 199dc78baa2SNicolas Ferre * Called with atchan->lock held and bh disabled 200dc78baa2SNicolas Ferre */ 201dc78baa2SNicolas Ferre static void atc_dostart(struct at_dma_chan *atchan, struct at_desc *first) 202dc78baa2SNicolas Ferre { 203dc78baa2SNicolas Ferre struct at_dma *atdma = to_at_dma(atchan->chan_common.device); 204dc78baa2SNicolas Ferre 205dc78baa2SNicolas Ferre /* ASSERT: channel is idle */ 206dc78baa2SNicolas Ferre if (atc_chan_is_enabled(atchan)) { 207dc78baa2SNicolas Ferre dev_err(chan2dev(&atchan->chan_common), 208dc78baa2SNicolas Ferre "BUG: Attempted to start non-idle channel\n"); 209dc78baa2SNicolas Ferre dev_err(chan2dev(&atchan->chan_common), 210dc78baa2SNicolas Ferre " channel: s0x%x d0x%x ctrl0x%x:0x%x l0x%x\n", 211dc78baa2SNicolas Ferre channel_readl(atchan, SADDR), 212dc78baa2SNicolas Ferre channel_readl(atchan, DADDR), 213dc78baa2SNicolas Ferre channel_readl(atchan, CTRLA), 214dc78baa2SNicolas Ferre channel_readl(atchan, CTRLB), 215dc78baa2SNicolas Ferre channel_readl(atchan, DSCR)); 216dc78baa2SNicolas Ferre 217dc78baa2SNicolas Ferre /* The tasklet will hopefully advance the queue... */ 218dc78baa2SNicolas Ferre return; 219dc78baa2SNicolas Ferre } 220dc78baa2SNicolas Ferre 221dc78baa2SNicolas Ferre vdbg_dump_regs(atchan); 222dc78baa2SNicolas Ferre 223dc78baa2SNicolas Ferre channel_writel(atchan, SADDR, 0); 224dc78baa2SNicolas Ferre channel_writel(atchan, DADDR, 0); 225dc78baa2SNicolas Ferre channel_writel(atchan, CTRLA, 0); 226dc78baa2SNicolas Ferre channel_writel(atchan, CTRLB, 0); 227dc78baa2SNicolas Ferre channel_writel(atchan, DSCR, first->txd.phys); 228dc78baa2SNicolas Ferre dma_writel(atdma, CHER, atchan->mask); 229dc78baa2SNicolas Ferre 230dc78baa2SNicolas Ferre vdbg_dump_regs(atchan); 231dc78baa2SNicolas Ferre } 232dc78baa2SNicolas Ferre 233dc78baa2SNicolas Ferre /** 234dc78baa2SNicolas Ferre * atc_chain_complete - finish work for one transaction chain 235dc78baa2SNicolas Ferre * @atchan: channel we work on 236dc78baa2SNicolas Ferre * @desc: descriptor at the head of the chain we want do complete 237dc78baa2SNicolas Ferre * 238dc78baa2SNicolas Ferre * Called with atchan->lock held and bh disabled */ 239dc78baa2SNicolas Ferre static void 240dc78baa2SNicolas Ferre atc_chain_complete(struct at_dma_chan *atchan, struct at_desc *desc) 241dc78baa2SNicolas Ferre { 242dc78baa2SNicolas Ferre struct dma_async_tx_descriptor *txd = &desc->txd; 243dc78baa2SNicolas Ferre 244dc78baa2SNicolas Ferre dev_vdbg(chan2dev(&atchan->chan_common), 245dc78baa2SNicolas Ferre "descriptor %u complete\n", txd->cookie); 246dc78baa2SNicolas Ferre 247d4116052SVinod Koul /* mark the descriptor as complete for non cyclic cases only */ 248d4116052SVinod Koul if (!atc_chan_is_cyclic(atchan)) 249f7fbce07SRussell King - ARM Linux dma_cookie_complete(txd); 250dc78baa2SNicolas Ferre 251dc78baa2SNicolas Ferre /* move children to free_list */ 252285a3c71SDan Williams list_splice_init(&desc->tx_list, &atchan->free_list); 253dc78baa2SNicolas Ferre /* move myself to free_list */ 254dc78baa2SNicolas Ferre list_move(&desc->desc_node, &atchan->free_list); 255dc78baa2SNicolas Ferre 256ebcf9b80SNicolas Ferre /* unmap dma addresses (not on slave channels) */ 257657a77faSAtsushi Nemoto if (!atchan->chan_common.private) { 258657a77faSAtsushi Nemoto struct device *parent = chan2parent(&atchan->chan_common); 259dc78baa2SNicolas Ferre if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) { 260dc78baa2SNicolas Ferre if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE) 261657a77faSAtsushi Nemoto dma_unmap_single(parent, 262dc78baa2SNicolas Ferre desc->lli.daddr, 263dc78baa2SNicolas Ferre desc->len, DMA_FROM_DEVICE); 264dc78baa2SNicolas Ferre else 265657a77faSAtsushi Nemoto dma_unmap_page(parent, 266dc78baa2SNicolas Ferre desc->lli.daddr, 267dc78baa2SNicolas Ferre desc->len, DMA_FROM_DEVICE); 268dc78baa2SNicolas Ferre } 269dc78baa2SNicolas Ferre if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) { 270dc78baa2SNicolas Ferre if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE) 271657a77faSAtsushi Nemoto dma_unmap_single(parent, 272dc78baa2SNicolas Ferre desc->lli.saddr, 273dc78baa2SNicolas Ferre desc->len, DMA_TO_DEVICE); 274dc78baa2SNicolas Ferre else 275657a77faSAtsushi Nemoto dma_unmap_page(parent, 276dc78baa2SNicolas Ferre desc->lli.saddr, 277dc78baa2SNicolas Ferre desc->len, DMA_TO_DEVICE); 278dc78baa2SNicolas Ferre } 279657a77faSAtsushi Nemoto } 280dc78baa2SNicolas Ferre 28153830cc7SNicolas Ferre /* for cyclic transfers, 28253830cc7SNicolas Ferre * no need to replay callback function while stopping */ 2833c477482SNicolas Ferre if (!atc_chan_is_cyclic(atchan)) { 28453830cc7SNicolas Ferre dma_async_tx_callback callback = txd->callback; 28553830cc7SNicolas Ferre void *param = txd->callback_param; 28653830cc7SNicolas Ferre 287dc78baa2SNicolas Ferre /* 288dc78baa2SNicolas Ferre * The API requires that no submissions are done from a 289dc78baa2SNicolas Ferre * callback, so we don't need to drop the lock here 290dc78baa2SNicolas Ferre */ 291dc78baa2SNicolas Ferre if (callback) 292dc78baa2SNicolas Ferre callback(param); 29353830cc7SNicolas Ferre } 294dc78baa2SNicolas Ferre 295dc78baa2SNicolas Ferre dma_run_dependencies(txd); 296dc78baa2SNicolas Ferre } 297dc78baa2SNicolas Ferre 298dc78baa2SNicolas Ferre /** 299dc78baa2SNicolas Ferre * atc_complete_all - finish work for all transactions 300dc78baa2SNicolas Ferre * @atchan: channel to complete transactions for 301dc78baa2SNicolas Ferre * 302dc78baa2SNicolas Ferre * Eventually submit queued descriptors if any 303dc78baa2SNicolas Ferre * 304dc78baa2SNicolas Ferre * Assume channel is idle while calling this function 305dc78baa2SNicolas Ferre * Called with atchan->lock held and bh disabled 306dc78baa2SNicolas Ferre */ 307dc78baa2SNicolas Ferre static void atc_complete_all(struct at_dma_chan *atchan) 308dc78baa2SNicolas Ferre { 309dc78baa2SNicolas Ferre struct at_desc *desc, *_desc; 310dc78baa2SNicolas Ferre LIST_HEAD(list); 311dc78baa2SNicolas Ferre 312dc78baa2SNicolas Ferre dev_vdbg(chan2dev(&atchan->chan_common), "complete all\n"); 313dc78baa2SNicolas Ferre 314dc78baa2SNicolas Ferre BUG_ON(atc_chan_is_enabled(atchan)); 315dc78baa2SNicolas Ferre 316dc78baa2SNicolas Ferre /* 317dc78baa2SNicolas Ferre * Submit queued descriptors ASAP, i.e. before we go through 318dc78baa2SNicolas Ferre * the completed ones. 319dc78baa2SNicolas Ferre */ 320dc78baa2SNicolas Ferre if (!list_empty(&atchan->queue)) 321dc78baa2SNicolas Ferre atc_dostart(atchan, atc_first_queued(atchan)); 322dc78baa2SNicolas Ferre /* empty active_list now it is completed */ 323dc78baa2SNicolas Ferre list_splice_init(&atchan->active_list, &list); 324dc78baa2SNicolas Ferre /* empty queue list by moving descriptors (if any) to active_list */ 325dc78baa2SNicolas Ferre list_splice_init(&atchan->queue, &atchan->active_list); 326dc78baa2SNicolas Ferre 327dc78baa2SNicolas Ferre list_for_each_entry_safe(desc, _desc, &list, desc_node) 328dc78baa2SNicolas Ferre atc_chain_complete(atchan, desc); 329dc78baa2SNicolas Ferre } 330dc78baa2SNicolas Ferre 331dc78baa2SNicolas Ferre /** 332dc78baa2SNicolas Ferre * atc_cleanup_descriptors - cleanup up finished descriptors in active_list 333dc78baa2SNicolas Ferre * @atchan: channel to be cleaned up 334dc78baa2SNicolas Ferre * 335dc78baa2SNicolas Ferre * Called with atchan->lock held and bh disabled 336dc78baa2SNicolas Ferre */ 337dc78baa2SNicolas Ferre static void atc_cleanup_descriptors(struct at_dma_chan *atchan) 338dc78baa2SNicolas Ferre { 339dc78baa2SNicolas Ferre struct at_desc *desc, *_desc; 340dc78baa2SNicolas Ferre struct at_desc *child; 341dc78baa2SNicolas Ferre 342dc78baa2SNicolas Ferre dev_vdbg(chan2dev(&atchan->chan_common), "cleanup descriptors\n"); 343dc78baa2SNicolas Ferre 344dc78baa2SNicolas Ferre list_for_each_entry_safe(desc, _desc, &atchan->active_list, desc_node) { 345dc78baa2SNicolas Ferre if (!(desc->lli.ctrla & ATC_DONE)) 346dc78baa2SNicolas Ferre /* This one is currently in progress */ 347dc78baa2SNicolas Ferre return; 348dc78baa2SNicolas Ferre 349285a3c71SDan Williams list_for_each_entry(child, &desc->tx_list, desc_node) 350dc78baa2SNicolas Ferre if (!(child->lli.ctrla & ATC_DONE)) 351dc78baa2SNicolas Ferre /* Currently in progress */ 352dc78baa2SNicolas Ferre return; 353dc78baa2SNicolas Ferre 354dc78baa2SNicolas Ferre /* 355dc78baa2SNicolas Ferre * No descriptors so far seem to be in progress, i.e. 356dc78baa2SNicolas Ferre * this chain must be done. 357dc78baa2SNicolas Ferre */ 358dc78baa2SNicolas Ferre atc_chain_complete(atchan, desc); 359dc78baa2SNicolas Ferre } 360dc78baa2SNicolas Ferre } 361dc78baa2SNicolas Ferre 362dc78baa2SNicolas Ferre /** 363dc78baa2SNicolas Ferre * atc_advance_work - at the end of a transaction, move forward 364dc78baa2SNicolas Ferre * @atchan: channel where the transaction ended 365dc78baa2SNicolas Ferre * 366dc78baa2SNicolas Ferre * Called with atchan->lock held and bh disabled 367dc78baa2SNicolas Ferre */ 368dc78baa2SNicolas Ferre static void atc_advance_work(struct at_dma_chan *atchan) 369dc78baa2SNicolas Ferre { 370dc78baa2SNicolas Ferre dev_vdbg(chan2dev(&atchan->chan_common), "advance_work\n"); 371dc78baa2SNicolas Ferre 372dc78baa2SNicolas Ferre if (list_empty(&atchan->active_list) || 373dc78baa2SNicolas Ferre list_is_singular(&atchan->active_list)) { 374dc78baa2SNicolas Ferre atc_complete_all(atchan); 375dc78baa2SNicolas Ferre } else { 376dc78baa2SNicolas Ferre atc_chain_complete(atchan, atc_first_active(atchan)); 377dc78baa2SNicolas Ferre /* advance work */ 378dc78baa2SNicolas Ferre atc_dostart(atchan, atc_first_active(atchan)); 379dc78baa2SNicolas Ferre } 380dc78baa2SNicolas Ferre } 381dc78baa2SNicolas Ferre 382dc78baa2SNicolas Ferre 383dc78baa2SNicolas Ferre /** 384dc78baa2SNicolas Ferre * atc_handle_error - handle errors reported by DMA controller 385dc78baa2SNicolas Ferre * @atchan: channel where error occurs 386dc78baa2SNicolas Ferre * 387dc78baa2SNicolas Ferre * Called with atchan->lock held and bh disabled 388dc78baa2SNicolas Ferre */ 389dc78baa2SNicolas Ferre static void atc_handle_error(struct at_dma_chan *atchan) 390dc78baa2SNicolas Ferre { 391dc78baa2SNicolas Ferre struct at_desc *bad_desc; 392dc78baa2SNicolas Ferre struct at_desc *child; 393dc78baa2SNicolas Ferre 394dc78baa2SNicolas Ferre /* 395dc78baa2SNicolas Ferre * The descriptor currently at the head of the active list is 396dc78baa2SNicolas Ferre * broked. Since we don't have any way to report errors, we'll 397dc78baa2SNicolas Ferre * just have to scream loudly and try to carry on. 398dc78baa2SNicolas Ferre */ 399dc78baa2SNicolas Ferre bad_desc = atc_first_active(atchan); 400dc78baa2SNicolas Ferre list_del_init(&bad_desc->desc_node); 401dc78baa2SNicolas Ferre 402dc78baa2SNicolas Ferre /* As we are stopped, take advantage to push queued descriptors 403dc78baa2SNicolas Ferre * in active_list */ 404dc78baa2SNicolas Ferre list_splice_init(&atchan->queue, atchan->active_list.prev); 405dc78baa2SNicolas Ferre 406dc78baa2SNicolas Ferre /* Try to restart the controller */ 407dc78baa2SNicolas Ferre if (!list_empty(&atchan->active_list)) 408dc78baa2SNicolas Ferre atc_dostart(atchan, atc_first_active(atchan)); 409dc78baa2SNicolas Ferre 410dc78baa2SNicolas Ferre /* 411dc78baa2SNicolas Ferre * KERN_CRITICAL may seem harsh, but since this only happens 412dc78baa2SNicolas Ferre * when someone submits a bad physical address in a 413dc78baa2SNicolas Ferre * descriptor, we should consider ourselves lucky that the 414dc78baa2SNicolas Ferre * controller flagged an error instead of scribbling over 415dc78baa2SNicolas Ferre * random memory locations. 416dc78baa2SNicolas Ferre */ 417dc78baa2SNicolas Ferre dev_crit(chan2dev(&atchan->chan_common), 418dc78baa2SNicolas Ferre "Bad descriptor submitted for DMA!\n"); 419dc78baa2SNicolas Ferre dev_crit(chan2dev(&atchan->chan_common), 420dc78baa2SNicolas Ferre " cookie: %d\n", bad_desc->txd.cookie); 421dc78baa2SNicolas Ferre atc_dump_lli(atchan, &bad_desc->lli); 422285a3c71SDan Williams list_for_each_entry(child, &bad_desc->tx_list, desc_node) 423dc78baa2SNicolas Ferre atc_dump_lli(atchan, &child->lli); 424dc78baa2SNicolas Ferre 425dc78baa2SNicolas Ferre /* Pretend the descriptor completed successfully */ 426dc78baa2SNicolas Ferre atc_chain_complete(atchan, bad_desc); 427dc78baa2SNicolas Ferre } 428dc78baa2SNicolas Ferre 42953830cc7SNicolas Ferre /** 43053830cc7SNicolas Ferre * atc_handle_cyclic - at the end of a period, run callback function 43153830cc7SNicolas Ferre * @atchan: channel used for cyclic operations 43253830cc7SNicolas Ferre * 43353830cc7SNicolas Ferre * Called with atchan->lock held and bh disabled 43453830cc7SNicolas Ferre */ 43553830cc7SNicolas Ferre static void atc_handle_cyclic(struct at_dma_chan *atchan) 43653830cc7SNicolas Ferre { 43753830cc7SNicolas Ferre struct at_desc *first = atc_first_active(atchan); 43853830cc7SNicolas Ferre struct dma_async_tx_descriptor *txd = &first->txd; 43953830cc7SNicolas Ferre dma_async_tx_callback callback = txd->callback; 44053830cc7SNicolas Ferre void *param = txd->callback_param; 44153830cc7SNicolas Ferre 44253830cc7SNicolas Ferre dev_vdbg(chan2dev(&atchan->chan_common), 44353830cc7SNicolas Ferre "new cyclic period llp 0x%08x\n", 44453830cc7SNicolas Ferre channel_readl(atchan, DSCR)); 44553830cc7SNicolas Ferre 44653830cc7SNicolas Ferre if (callback) 44753830cc7SNicolas Ferre callback(param); 44853830cc7SNicolas Ferre } 449dc78baa2SNicolas Ferre 450dc78baa2SNicolas Ferre /*-- IRQ & Tasklet ---------------------------------------------------*/ 451dc78baa2SNicolas Ferre 452dc78baa2SNicolas Ferre static void atc_tasklet(unsigned long data) 453dc78baa2SNicolas Ferre { 454dc78baa2SNicolas Ferre struct at_dma_chan *atchan = (struct at_dma_chan *)data; 455d8cb04b0SNicolas Ferre unsigned long flags; 456dc78baa2SNicolas Ferre 457d8cb04b0SNicolas Ferre spin_lock_irqsave(&atchan->lock, flags); 45853830cc7SNicolas Ferre if (test_and_clear_bit(ATC_IS_ERROR, &atchan->status)) 459dc78baa2SNicolas Ferre atc_handle_error(atchan); 4603c477482SNicolas Ferre else if (atc_chan_is_cyclic(atchan)) 46153830cc7SNicolas Ferre atc_handle_cyclic(atchan); 462dc78baa2SNicolas Ferre else 463dc78baa2SNicolas Ferre atc_advance_work(atchan); 464dc78baa2SNicolas Ferre 465d8cb04b0SNicolas Ferre spin_unlock_irqrestore(&atchan->lock, flags); 466dc78baa2SNicolas Ferre } 467dc78baa2SNicolas Ferre 468dc78baa2SNicolas Ferre static irqreturn_t at_dma_interrupt(int irq, void *dev_id) 469dc78baa2SNicolas Ferre { 470dc78baa2SNicolas Ferre struct at_dma *atdma = (struct at_dma *)dev_id; 471dc78baa2SNicolas Ferre struct at_dma_chan *atchan; 472dc78baa2SNicolas Ferre int i; 473dc78baa2SNicolas Ferre u32 status, pending, imr; 474dc78baa2SNicolas Ferre int ret = IRQ_NONE; 475dc78baa2SNicolas Ferre 476dc78baa2SNicolas Ferre do { 477dc78baa2SNicolas Ferre imr = dma_readl(atdma, EBCIMR); 478dc78baa2SNicolas Ferre status = dma_readl(atdma, EBCISR); 479dc78baa2SNicolas Ferre pending = status & imr; 480dc78baa2SNicolas Ferre 481dc78baa2SNicolas Ferre if (!pending) 482dc78baa2SNicolas Ferre break; 483dc78baa2SNicolas Ferre 484dc78baa2SNicolas Ferre dev_vdbg(atdma->dma_common.dev, 485dc78baa2SNicolas Ferre "interrupt: status = 0x%08x, 0x%08x, 0x%08x\n", 486dc78baa2SNicolas Ferre status, imr, pending); 487dc78baa2SNicolas Ferre 488dc78baa2SNicolas Ferre for (i = 0; i < atdma->dma_common.chancnt; i++) { 489dc78baa2SNicolas Ferre atchan = &atdma->chan[i]; 4909b3aa589SNicolas Ferre if (pending & (AT_DMA_BTC(i) | AT_DMA_ERR(i))) { 491dc78baa2SNicolas Ferre if (pending & AT_DMA_ERR(i)) { 492dc78baa2SNicolas Ferre /* Disable channel on AHB error */ 49323b5e3adSNicolas Ferre dma_writel(atdma, CHDR, 49423b5e3adSNicolas Ferre AT_DMA_RES(i) | atchan->mask); 495dc78baa2SNicolas Ferre /* Give information to tasklet */ 49653830cc7SNicolas Ferre set_bit(ATC_IS_ERROR, &atchan->status); 497dc78baa2SNicolas Ferre } 498dc78baa2SNicolas Ferre tasklet_schedule(&atchan->tasklet); 499dc78baa2SNicolas Ferre ret = IRQ_HANDLED; 500dc78baa2SNicolas Ferre } 501dc78baa2SNicolas Ferre } 502dc78baa2SNicolas Ferre 503dc78baa2SNicolas Ferre } while (pending); 504dc78baa2SNicolas Ferre 505dc78baa2SNicolas Ferre return ret; 506dc78baa2SNicolas Ferre } 507dc78baa2SNicolas Ferre 508dc78baa2SNicolas Ferre 509dc78baa2SNicolas Ferre /*-- DMA Engine API --------------------------------------------------*/ 510dc78baa2SNicolas Ferre 511dc78baa2SNicolas Ferre /** 512dc78baa2SNicolas Ferre * atc_tx_submit - set the prepared descriptor(s) to be executed by the engine 513dc78baa2SNicolas Ferre * @desc: descriptor at the head of the transaction chain 514dc78baa2SNicolas Ferre * 515dc78baa2SNicolas Ferre * Queue chain if DMA engine is working already 516dc78baa2SNicolas Ferre * 517dc78baa2SNicolas Ferre * Cookie increment and adding to active_list or queue must be atomic 518dc78baa2SNicolas Ferre */ 519dc78baa2SNicolas Ferre static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx) 520dc78baa2SNicolas Ferre { 521dc78baa2SNicolas Ferre struct at_desc *desc = txd_to_at_desc(tx); 522dc78baa2SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(tx->chan); 523dc78baa2SNicolas Ferre dma_cookie_t cookie; 524d8cb04b0SNicolas Ferre unsigned long flags; 525dc78baa2SNicolas Ferre 526d8cb04b0SNicolas Ferre spin_lock_irqsave(&atchan->lock, flags); 527884485e1SRussell King - ARM Linux cookie = dma_cookie_assign(tx); 528dc78baa2SNicolas Ferre 529dc78baa2SNicolas Ferre if (list_empty(&atchan->active_list)) { 530dc78baa2SNicolas Ferre dev_vdbg(chan2dev(tx->chan), "tx_submit: started %u\n", 531dc78baa2SNicolas Ferre desc->txd.cookie); 532dc78baa2SNicolas Ferre atc_dostart(atchan, desc); 533dc78baa2SNicolas Ferre list_add_tail(&desc->desc_node, &atchan->active_list); 534dc78baa2SNicolas Ferre } else { 535dc78baa2SNicolas Ferre dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u\n", 536dc78baa2SNicolas Ferre desc->txd.cookie); 537dc78baa2SNicolas Ferre list_add_tail(&desc->desc_node, &atchan->queue); 538dc78baa2SNicolas Ferre } 539dc78baa2SNicolas Ferre 540d8cb04b0SNicolas Ferre spin_unlock_irqrestore(&atchan->lock, flags); 541dc78baa2SNicolas Ferre 542dc78baa2SNicolas Ferre return cookie; 543dc78baa2SNicolas Ferre } 544dc78baa2SNicolas Ferre 545dc78baa2SNicolas Ferre /** 546dc78baa2SNicolas Ferre * atc_prep_dma_memcpy - prepare a memcpy operation 547dc78baa2SNicolas Ferre * @chan: the channel to prepare operation on 548dc78baa2SNicolas Ferre * @dest: operation virtual destination address 549dc78baa2SNicolas Ferre * @src: operation virtual source address 550dc78baa2SNicolas Ferre * @len: operation length 551dc78baa2SNicolas Ferre * @flags: tx descriptor status flags 552dc78baa2SNicolas Ferre */ 553dc78baa2SNicolas Ferre static struct dma_async_tx_descriptor * 554dc78baa2SNicolas Ferre atc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, 555dc78baa2SNicolas Ferre size_t len, unsigned long flags) 556dc78baa2SNicolas Ferre { 557dc78baa2SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 558dc78baa2SNicolas Ferre struct at_desc *desc = NULL; 559dc78baa2SNicolas Ferre struct at_desc *first = NULL; 560dc78baa2SNicolas Ferre struct at_desc *prev = NULL; 561dc78baa2SNicolas Ferre size_t xfer_count; 562dc78baa2SNicolas Ferre size_t offset; 563dc78baa2SNicolas Ferre unsigned int src_width; 564dc78baa2SNicolas Ferre unsigned int dst_width; 565dc78baa2SNicolas Ferre u32 ctrla; 566dc78baa2SNicolas Ferre u32 ctrlb; 567dc78baa2SNicolas Ferre 568dc78baa2SNicolas Ferre dev_vdbg(chan2dev(chan), "prep_dma_memcpy: d0x%x s0x%x l0x%zx f0x%lx\n", 569dc78baa2SNicolas Ferre dest, src, len, flags); 570dc78baa2SNicolas Ferre 571dc78baa2SNicolas Ferre if (unlikely(!len)) { 572dc78baa2SNicolas Ferre dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n"); 573dc78baa2SNicolas Ferre return NULL; 574dc78baa2SNicolas Ferre } 575dc78baa2SNicolas Ferre 5769b3aa589SNicolas Ferre ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN 577dc78baa2SNicolas Ferre | ATC_SRC_ADDR_MODE_INCR 578dc78baa2SNicolas Ferre | ATC_DST_ADDR_MODE_INCR 579dc78baa2SNicolas Ferre | ATC_FC_MEM2MEM; 580dc78baa2SNicolas Ferre 581dc78baa2SNicolas Ferre /* 582dc78baa2SNicolas Ferre * We can be a lot more clever here, but this should take care 583dc78baa2SNicolas Ferre * of the most common optimization. 584dc78baa2SNicolas Ferre */ 585dc78baa2SNicolas Ferre if (!((src | dest | len) & 3)) { 586b409ebfbSNicolas Ferre ctrla = ATC_SRC_WIDTH_WORD | ATC_DST_WIDTH_WORD; 587dc78baa2SNicolas Ferre src_width = dst_width = 2; 588dc78baa2SNicolas Ferre } else if (!((src | dest | len) & 1)) { 589b409ebfbSNicolas Ferre ctrla = ATC_SRC_WIDTH_HALFWORD | ATC_DST_WIDTH_HALFWORD; 590dc78baa2SNicolas Ferre src_width = dst_width = 1; 591dc78baa2SNicolas Ferre } else { 592b409ebfbSNicolas Ferre ctrla = ATC_SRC_WIDTH_BYTE | ATC_DST_WIDTH_BYTE; 593dc78baa2SNicolas Ferre src_width = dst_width = 0; 594dc78baa2SNicolas Ferre } 595dc78baa2SNicolas Ferre 596dc78baa2SNicolas Ferre for (offset = 0; offset < len; offset += xfer_count << src_width) { 597dc78baa2SNicolas Ferre xfer_count = min_t(size_t, (len - offset) >> src_width, 598dc78baa2SNicolas Ferre ATC_BTSIZE_MAX); 599dc78baa2SNicolas Ferre 600dc78baa2SNicolas Ferre desc = atc_desc_get(atchan); 601dc78baa2SNicolas Ferre if (!desc) 602dc78baa2SNicolas Ferre goto err_desc_get; 603dc78baa2SNicolas Ferre 604dc78baa2SNicolas Ferre desc->lli.saddr = src + offset; 605dc78baa2SNicolas Ferre desc->lli.daddr = dest + offset; 606dc78baa2SNicolas Ferre desc->lli.ctrla = ctrla | xfer_count; 607dc78baa2SNicolas Ferre desc->lli.ctrlb = ctrlb; 608dc78baa2SNicolas Ferre 609dc78baa2SNicolas Ferre desc->txd.cookie = 0; 610dc78baa2SNicolas Ferre 611e257e156SNicolas Ferre atc_desc_chain(&first, &prev, desc); 612dc78baa2SNicolas Ferre } 613dc78baa2SNicolas Ferre 614dc78baa2SNicolas Ferre /* First descriptor of the chain embedds additional information */ 615dc78baa2SNicolas Ferre first->txd.cookie = -EBUSY; 616dc78baa2SNicolas Ferre first->len = len; 617dc78baa2SNicolas Ferre 618dc78baa2SNicolas Ferre /* set end-of-link to the last link descriptor of list*/ 619dc78baa2SNicolas Ferre set_desc_eol(desc); 620dc78baa2SNicolas Ferre 621568f7f0cSNicolas Ferre first->txd.flags = flags; /* client is in control of this ack */ 622dc78baa2SNicolas Ferre 623dc78baa2SNicolas Ferre return &first->txd; 624dc78baa2SNicolas Ferre 625dc78baa2SNicolas Ferre err_desc_get: 626dc78baa2SNicolas Ferre atc_desc_put(atchan, first); 627dc78baa2SNicolas Ferre return NULL; 628dc78baa2SNicolas Ferre } 629dc78baa2SNicolas Ferre 630808347f6SNicolas Ferre 631808347f6SNicolas Ferre /** 632808347f6SNicolas Ferre * atc_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction 633808347f6SNicolas Ferre * @chan: DMA channel 634808347f6SNicolas Ferre * @sgl: scatterlist to transfer to/from 635808347f6SNicolas Ferre * @sg_len: number of entries in @scatterlist 636808347f6SNicolas Ferre * @direction: DMA direction 637808347f6SNicolas Ferre * @flags: tx descriptor status flags 638185ecb5fSAlexandre Bounine * @context: transaction context (ignored) 639808347f6SNicolas Ferre */ 640808347f6SNicolas Ferre static struct dma_async_tx_descriptor * 641808347f6SNicolas Ferre atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, 642db8196dfSVinod Koul unsigned int sg_len, enum dma_transfer_direction direction, 643185ecb5fSAlexandre Bounine unsigned long flags, void *context) 644808347f6SNicolas Ferre { 645808347f6SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 646808347f6SNicolas Ferre struct at_dma_slave *atslave = chan->private; 647beeaa103SNicolas Ferre struct dma_slave_config *sconfig = &atchan->dma_sconfig; 648808347f6SNicolas Ferre struct at_desc *first = NULL; 649808347f6SNicolas Ferre struct at_desc *prev = NULL; 650808347f6SNicolas Ferre u32 ctrla; 651808347f6SNicolas Ferre u32 ctrlb; 652808347f6SNicolas Ferre dma_addr_t reg; 653808347f6SNicolas Ferre unsigned int reg_width; 654808347f6SNicolas Ferre unsigned int mem_width; 655808347f6SNicolas Ferre unsigned int i; 656808347f6SNicolas Ferre struct scatterlist *sg; 657808347f6SNicolas Ferre size_t total_len = 0; 658808347f6SNicolas Ferre 659cc52a10aSNicolas Ferre dev_vdbg(chan2dev(chan), "prep_slave_sg (%d): %s f0x%lx\n", 660cc52a10aSNicolas Ferre sg_len, 661db8196dfSVinod Koul direction == DMA_MEM_TO_DEV ? "TO DEVICE" : "FROM DEVICE", 662808347f6SNicolas Ferre flags); 663808347f6SNicolas Ferre 664808347f6SNicolas Ferre if (unlikely(!atslave || !sg_len)) { 665808347f6SNicolas Ferre dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n"); 666808347f6SNicolas Ferre return NULL; 667808347f6SNicolas Ferre } 668808347f6SNicolas Ferre 6691dd1ea8eSNicolas Ferre ctrla = ATC_SCSIZE(sconfig->src_maxburst) 6701dd1ea8eSNicolas Ferre | ATC_DCSIZE(sconfig->dst_maxburst); 671ae14d4b5SNicolas Ferre ctrlb = ATC_IEN; 672808347f6SNicolas Ferre 673808347f6SNicolas Ferre switch (direction) { 674db8196dfSVinod Koul case DMA_MEM_TO_DEV: 675beeaa103SNicolas Ferre reg_width = convert_buswidth(sconfig->dst_addr_width); 676808347f6SNicolas Ferre ctrla |= ATC_DST_WIDTH(reg_width); 677808347f6SNicolas Ferre ctrlb |= ATC_DST_ADDR_MODE_FIXED 678808347f6SNicolas Ferre | ATC_SRC_ADDR_MODE_INCR 679ae14d4b5SNicolas Ferre | ATC_FC_MEM2PER 680ae14d4b5SNicolas Ferre | ATC_SIF(AT_DMA_MEM_IF) | ATC_DIF(AT_DMA_PER_IF); 681beeaa103SNicolas Ferre reg = sconfig->dst_addr; 682808347f6SNicolas Ferre for_each_sg(sgl, sg, sg_len, i) { 683808347f6SNicolas Ferre struct at_desc *desc; 684808347f6SNicolas Ferre u32 len; 685808347f6SNicolas Ferre u32 mem; 686808347f6SNicolas Ferre 687808347f6SNicolas Ferre desc = atc_desc_get(atchan); 688808347f6SNicolas Ferre if (!desc) 689808347f6SNicolas Ferre goto err_desc_get; 690808347f6SNicolas Ferre 6910f70e8ceSNicolas Ferre mem = sg_dma_address(sg); 692808347f6SNicolas Ferre len = sg_dma_len(sg); 693808347f6SNicolas Ferre mem_width = 2; 694808347f6SNicolas Ferre if (unlikely(mem & 3 || len & 3)) 695808347f6SNicolas Ferre mem_width = 0; 696808347f6SNicolas Ferre 697808347f6SNicolas Ferre desc->lli.saddr = mem; 698808347f6SNicolas Ferre desc->lli.daddr = reg; 699808347f6SNicolas Ferre desc->lli.ctrla = ctrla 700808347f6SNicolas Ferre | ATC_SRC_WIDTH(mem_width) 701808347f6SNicolas Ferre | len >> mem_width; 702808347f6SNicolas Ferre desc->lli.ctrlb = ctrlb; 703808347f6SNicolas Ferre 704e257e156SNicolas Ferre atc_desc_chain(&first, &prev, desc); 705808347f6SNicolas Ferre total_len += len; 706808347f6SNicolas Ferre } 707808347f6SNicolas Ferre break; 708db8196dfSVinod Koul case DMA_DEV_TO_MEM: 709beeaa103SNicolas Ferre reg_width = convert_buswidth(sconfig->src_addr_width); 710808347f6SNicolas Ferre ctrla |= ATC_SRC_WIDTH(reg_width); 711808347f6SNicolas Ferre ctrlb |= ATC_DST_ADDR_MODE_INCR 712808347f6SNicolas Ferre | ATC_SRC_ADDR_MODE_FIXED 713ae14d4b5SNicolas Ferre | ATC_FC_PER2MEM 714ae14d4b5SNicolas Ferre | ATC_SIF(AT_DMA_PER_IF) | ATC_DIF(AT_DMA_MEM_IF); 715808347f6SNicolas Ferre 716beeaa103SNicolas Ferre reg = sconfig->src_addr; 717808347f6SNicolas Ferre for_each_sg(sgl, sg, sg_len, i) { 718808347f6SNicolas Ferre struct at_desc *desc; 719808347f6SNicolas Ferre u32 len; 720808347f6SNicolas Ferre u32 mem; 721808347f6SNicolas Ferre 722808347f6SNicolas Ferre desc = atc_desc_get(atchan); 723808347f6SNicolas Ferre if (!desc) 724808347f6SNicolas Ferre goto err_desc_get; 725808347f6SNicolas Ferre 7260f70e8ceSNicolas Ferre mem = sg_dma_address(sg); 727808347f6SNicolas Ferre len = sg_dma_len(sg); 728808347f6SNicolas Ferre mem_width = 2; 729808347f6SNicolas Ferre if (unlikely(mem & 3 || len & 3)) 730808347f6SNicolas Ferre mem_width = 0; 731808347f6SNicolas Ferre 732808347f6SNicolas Ferre desc->lli.saddr = reg; 733808347f6SNicolas Ferre desc->lli.daddr = mem; 734808347f6SNicolas Ferre desc->lli.ctrla = ctrla 735808347f6SNicolas Ferre | ATC_DST_WIDTH(mem_width) 73659a609d9SNicolas Ferre | len >> reg_width; 737808347f6SNicolas Ferre desc->lli.ctrlb = ctrlb; 738808347f6SNicolas Ferre 739e257e156SNicolas Ferre atc_desc_chain(&first, &prev, desc); 740808347f6SNicolas Ferre total_len += len; 741808347f6SNicolas Ferre } 742808347f6SNicolas Ferre break; 743808347f6SNicolas Ferre default: 744808347f6SNicolas Ferre return NULL; 745808347f6SNicolas Ferre } 746808347f6SNicolas Ferre 747808347f6SNicolas Ferre /* set end-of-link to the last link descriptor of list*/ 748808347f6SNicolas Ferre set_desc_eol(prev); 749808347f6SNicolas Ferre 750808347f6SNicolas Ferre /* First descriptor of the chain embedds additional information */ 751808347f6SNicolas Ferre first->txd.cookie = -EBUSY; 752808347f6SNicolas Ferre first->len = total_len; 753808347f6SNicolas Ferre 754568f7f0cSNicolas Ferre /* first link descriptor of list is responsible of flags */ 755568f7f0cSNicolas Ferre first->txd.flags = flags; /* client is in control of this ack */ 756808347f6SNicolas Ferre 757808347f6SNicolas Ferre return &first->txd; 758808347f6SNicolas Ferre 759808347f6SNicolas Ferre err_desc_get: 760808347f6SNicolas Ferre dev_err(chan2dev(chan), "not enough descriptors available\n"); 761808347f6SNicolas Ferre atc_desc_put(atchan, first); 762808347f6SNicolas Ferre return NULL; 763808347f6SNicolas Ferre } 764808347f6SNicolas Ferre 76553830cc7SNicolas Ferre /** 76653830cc7SNicolas Ferre * atc_dma_cyclic_check_values 76753830cc7SNicolas Ferre * Check for too big/unaligned periods and unaligned DMA buffer 76853830cc7SNicolas Ferre */ 76953830cc7SNicolas Ferre static int 77053830cc7SNicolas Ferre atc_dma_cyclic_check_values(unsigned int reg_width, dma_addr_t buf_addr, 771db8196dfSVinod Koul size_t period_len, enum dma_transfer_direction direction) 77253830cc7SNicolas Ferre { 77353830cc7SNicolas Ferre if (period_len > (ATC_BTSIZE_MAX << reg_width)) 77453830cc7SNicolas Ferre goto err_out; 77553830cc7SNicolas Ferre if (unlikely(period_len & ((1 << reg_width) - 1))) 77653830cc7SNicolas Ferre goto err_out; 77753830cc7SNicolas Ferre if (unlikely(buf_addr & ((1 << reg_width) - 1))) 77853830cc7SNicolas Ferre goto err_out; 779db8196dfSVinod Koul if (unlikely(!(direction & (DMA_DEV_TO_MEM | DMA_MEM_TO_DEV)))) 78053830cc7SNicolas Ferre goto err_out; 78153830cc7SNicolas Ferre 78253830cc7SNicolas Ferre return 0; 78353830cc7SNicolas Ferre 78453830cc7SNicolas Ferre err_out: 78553830cc7SNicolas Ferre return -EINVAL; 78653830cc7SNicolas Ferre } 78753830cc7SNicolas Ferre 78853830cc7SNicolas Ferre /** 789d73111c6SMasanari Iida * atc_dma_cyclic_fill_desc - Fill one period descriptor 79053830cc7SNicolas Ferre */ 79153830cc7SNicolas Ferre static int 792beeaa103SNicolas Ferre atc_dma_cyclic_fill_desc(struct dma_chan *chan, struct at_desc *desc, 79353830cc7SNicolas Ferre unsigned int period_index, dma_addr_t buf_addr, 794beeaa103SNicolas Ferre unsigned int reg_width, size_t period_len, 795beeaa103SNicolas Ferre enum dma_transfer_direction direction) 79653830cc7SNicolas Ferre { 797beeaa103SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 798beeaa103SNicolas Ferre struct dma_slave_config *sconfig = &atchan->dma_sconfig; 79953830cc7SNicolas Ferre u32 ctrla; 80053830cc7SNicolas Ferre 80153830cc7SNicolas Ferre /* prepare common CRTLA value */ 8021dd1ea8eSNicolas Ferre ctrla = ATC_SCSIZE(sconfig->src_maxburst) 8031dd1ea8eSNicolas Ferre | ATC_DCSIZE(sconfig->dst_maxburst) 80453830cc7SNicolas Ferre | ATC_DST_WIDTH(reg_width) 80553830cc7SNicolas Ferre | ATC_SRC_WIDTH(reg_width) 80653830cc7SNicolas Ferre | period_len >> reg_width; 80753830cc7SNicolas Ferre 80853830cc7SNicolas Ferre switch (direction) { 809db8196dfSVinod Koul case DMA_MEM_TO_DEV: 81053830cc7SNicolas Ferre desc->lli.saddr = buf_addr + (period_len * period_index); 811beeaa103SNicolas Ferre desc->lli.daddr = sconfig->dst_addr; 81253830cc7SNicolas Ferre desc->lli.ctrla = ctrla; 813ae14d4b5SNicolas Ferre desc->lli.ctrlb = ATC_DST_ADDR_MODE_FIXED 81453830cc7SNicolas Ferre | ATC_SRC_ADDR_MODE_INCR 815ae14d4b5SNicolas Ferre | ATC_FC_MEM2PER 816ae14d4b5SNicolas Ferre | ATC_SIF(AT_DMA_MEM_IF) 817ae14d4b5SNicolas Ferre | ATC_DIF(AT_DMA_PER_IF); 81853830cc7SNicolas Ferre break; 81953830cc7SNicolas Ferre 820db8196dfSVinod Koul case DMA_DEV_TO_MEM: 821beeaa103SNicolas Ferre desc->lli.saddr = sconfig->src_addr; 82253830cc7SNicolas Ferre desc->lli.daddr = buf_addr + (period_len * period_index); 82353830cc7SNicolas Ferre desc->lli.ctrla = ctrla; 824ae14d4b5SNicolas Ferre desc->lli.ctrlb = ATC_DST_ADDR_MODE_INCR 82553830cc7SNicolas Ferre | ATC_SRC_ADDR_MODE_FIXED 826ae14d4b5SNicolas Ferre | ATC_FC_PER2MEM 827ae14d4b5SNicolas Ferre | ATC_SIF(AT_DMA_PER_IF) 828ae14d4b5SNicolas Ferre | ATC_DIF(AT_DMA_MEM_IF); 82953830cc7SNicolas Ferre break; 83053830cc7SNicolas Ferre 83153830cc7SNicolas Ferre default: 83253830cc7SNicolas Ferre return -EINVAL; 83353830cc7SNicolas Ferre } 83453830cc7SNicolas Ferre 83553830cc7SNicolas Ferre return 0; 83653830cc7SNicolas Ferre } 83753830cc7SNicolas Ferre 83853830cc7SNicolas Ferre /** 83953830cc7SNicolas Ferre * atc_prep_dma_cyclic - prepare the cyclic DMA transfer 84053830cc7SNicolas Ferre * @chan: the DMA channel to prepare 84153830cc7SNicolas Ferre * @buf_addr: physical DMA address where the buffer starts 84253830cc7SNicolas Ferre * @buf_len: total number of bytes for the entire buffer 84353830cc7SNicolas Ferre * @period_len: number of bytes for each period 84453830cc7SNicolas Ferre * @direction: transfer direction, to or from device 845185ecb5fSAlexandre Bounine * @context: transfer context (ignored) 84653830cc7SNicolas Ferre */ 84753830cc7SNicolas Ferre static struct dma_async_tx_descriptor * 84853830cc7SNicolas Ferre atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, 849185ecb5fSAlexandre Bounine size_t period_len, enum dma_transfer_direction direction, 850185ecb5fSAlexandre Bounine void *context) 85153830cc7SNicolas Ferre { 85253830cc7SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 85353830cc7SNicolas Ferre struct at_dma_slave *atslave = chan->private; 854beeaa103SNicolas Ferre struct dma_slave_config *sconfig = &atchan->dma_sconfig; 85553830cc7SNicolas Ferre struct at_desc *first = NULL; 85653830cc7SNicolas Ferre struct at_desc *prev = NULL; 85753830cc7SNicolas Ferre unsigned long was_cyclic; 858beeaa103SNicolas Ferre unsigned int reg_width; 85953830cc7SNicolas Ferre unsigned int periods = buf_len / period_len; 86053830cc7SNicolas Ferre unsigned int i; 86153830cc7SNicolas Ferre 86253830cc7SNicolas Ferre dev_vdbg(chan2dev(chan), "prep_dma_cyclic: %s buf@0x%08x - %d (%d/%d)\n", 863db8196dfSVinod Koul direction == DMA_MEM_TO_DEV ? "TO DEVICE" : "FROM DEVICE", 86453830cc7SNicolas Ferre buf_addr, 86553830cc7SNicolas Ferre periods, buf_len, period_len); 86653830cc7SNicolas Ferre 86753830cc7SNicolas Ferre if (unlikely(!atslave || !buf_len || !period_len)) { 86853830cc7SNicolas Ferre dev_dbg(chan2dev(chan), "prep_dma_cyclic: length is zero!\n"); 86953830cc7SNicolas Ferre return NULL; 87053830cc7SNicolas Ferre } 87153830cc7SNicolas Ferre 87253830cc7SNicolas Ferre was_cyclic = test_and_set_bit(ATC_IS_CYCLIC, &atchan->status); 87353830cc7SNicolas Ferre if (was_cyclic) { 87453830cc7SNicolas Ferre dev_dbg(chan2dev(chan), "prep_dma_cyclic: channel in use!\n"); 87553830cc7SNicolas Ferre return NULL; 87653830cc7SNicolas Ferre } 87753830cc7SNicolas Ferre 878beeaa103SNicolas Ferre if (sconfig->direction == DMA_MEM_TO_DEV) 879beeaa103SNicolas Ferre reg_width = convert_buswidth(sconfig->dst_addr_width); 880beeaa103SNicolas Ferre else 881beeaa103SNicolas Ferre reg_width = convert_buswidth(sconfig->src_addr_width); 882beeaa103SNicolas Ferre 88353830cc7SNicolas Ferre /* Check for too big/unaligned periods and unaligned DMA buffer */ 884beeaa103SNicolas Ferre if (atc_dma_cyclic_check_values(reg_width, buf_addr, 88553830cc7SNicolas Ferre period_len, direction)) 88653830cc7SNicolas Ferre goto err_out; 88753830cc7SNicolas Ferre 88853830cc7SNicolas Ferre /* build cyclic linked list */ 88953830cc7SNicolas Ferre for (i = 0; i < periods; i++) { 89053830cc7SNicolas Ferre struct at_desc *desc; 89153830cc7SNicolas Ferre 89253830cc7SNicolas Ferre desc = atc_desc_get(atchan); 89353830cc7SNicolas Ferre if (!desc) 89453830cc7SNicolas Ferre goto err_desc_get; 89553830cc7SNicolas Ferre 896beeaa103SNicolas Ferre if (atc_dma_cyclic_fill_desc(chan, desc, i, buf_addr, 897beeaa103SNicolas Ferre reg_width, period_len, direction)) 89853830cc7SNicolas Ferre goto err_desc_get; 89953830cc7SNicolas Ferre 90053830cc7SNicolas Ferre atc_desc_chain(&first, &prev, desc); 90153830cc7SNicolas Ferre } 90253830cc7SNicolas Ferre 90353830cc7SNicolas Ferre /* lets make a cyclic list */ 90453830cc7SNicolas Ferre prev->lli.dscr = first->txd.phys; 90553830cc7SNicolas Ferre 90653830cc7SNicolas Ferre /* First descriptor of the chain embedds additional information */ 90753830cc7SNicolas Ferre first->txd.cookie = -EBUSY; 90853830cc7SNicolas Ferre first->len = buf_len; 90953830cc7SNicolas Ferre 91053830cc7SNicolas Ferre return &first->txd; 91153830cc7SNicolas Ferre 91253830cc7SNicolas Ferre err_desc_get: 91353830cc7SNicolas Ferre dev_err(chan2dev(chan), "not enough descriptors available\n"); 91453830cc7SNicolas Ferre atc_desc_put(atchan, first); 91553830cc7SNicolas Ferre err_out: 91653830cc7SNicolas Ferre clear_bit(ATC_IS_CYCLIC, &atchan->status); 91753830cc7SNicolas Ferre return NULL; 91853830cc7SNicolas Ferre } 91953830cc7SNicolas Ferre 920beeaa103SNicolas Ferre static int set_runtime_config(struct dma_chan *chan, 921beeaa103SNicolas Ferre struct dma_slave_config *sconfig) 922beeaa103SNicolas Ferre { 923beeaa103SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 924beeaa103SNicolas Ferre 925beeaa103SNicolas Ferre /* Check if it is chan is configured for slave transfers */ 926beeaa103SNicolas Ferre if (!chan->private) 927beeaa103SNicolas Ferre return -EINVAL; 928beeaa103SNicolas Ferre 929beeaa103SNicolas Ferre memcpy(&atchan->dma_sconfig, sconfig, sizeof(*sconfig)); 930beeaa103SNicolas Ferre 931beeaa103SNicolas Ferre convert_burst(&atchan->dma_sconfig.src_maxburst); 932beeaa103SNicolas Ferre convert_burst(&atchan->dma_sconfig.dst_maxburst); 933beeaa103SNicolas Ferre 934beeaa103SNicolas Ferre return 0; 935beeaa103SNicolas Ferre } 936beeaa103SNicolas Ferre 93753830cc7SNicolas Ferre 93805827630SLinus Walleij static int atc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, 93905827630SLinus Walleij unsigned long arg) 940808347f6SNicolas Ferre { 941808347f6SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 942808347f6SNicolas Ferre struct at_dma *atdma = to_at_dma(chan->device); 94323b5e3adSNicolas Ferre int chan_id = atchan->chan_common.chan_id; 944d8cb04b0SNicolas Ferre unsigned long flags; 94523b5e3adSNicolas Ferre 946808347f6SNicolas Ferre LIST_HEAD(list); 947808347f6SNicolas Ferre 94823b5e3adSNicolas Ferre dev_vdbg(chan2dev(chan), "atc_control (%d)\n", cmd); 949c3635c78SLinus Walleij 95023b5e3adSNicolas Ferre if (cmd == DMA_PAUSE) { 951d8cb04b0SNicolas Ferre spin_lock_irqsave(&atchan->lock, flags); 95223b5e3adSNicolas Ferre 95323b5e3adSNicolas Ferre dma_writel(atdma, CHER, AT_DMA_SUSP(chan_id)); 95423b5e3adSNicolas Ferre set_bit(ATC_IS_PAUSED, &atchan->status); 95523b5e3adSNicolas Ferre 956d8cb04b0SNicolas Ferre spin_unlock_irqrestore(&atchan->lock, flags); 95723b5e3adSNicolas Ferre } else if (cmd == DMA_RESUME) { 9583c477482SNicolas Ferre if (!atc_chan_is_paused(atchan)) 95923b5e3adSNicolas Ferre return 0; 96023b5e3adSNicolas Ferre 961d8cb04b0SNicolas Ferre spin_lock_irqsave(&atchan->lock, flags); 96223b5e3adSNicolas Ferre 96323b5e3adSNicolas Ferre dma_writel(atdma, CHDR, AT_DMA_RES(chan_id)); 96423b5e3adSNicolas Ferre clear_bit(ATC_IS_PAUSED, &atchan->status); 96523b5e3adSNicolas Ferre 966d8cb04b0SNicolas Ferre spin_unlock_irqrestore(&atchan->lock, flags); 96723b5e3adSNicolas Ferre } else if (cmd == DMA_TERMINATE_ALL) { 96823b5e3adSNicolas Ferre struct at_desc *desc, *_desc; 969808347f6SNicolas Ferre /* 970808347f6SNicolas Ferre * This is only called when something went wrong elsewhere, so 971808347f6SNicolas Ferre * we don't really care about the data. Just disable the 972808347f6SNicolas Ferre * channel. We still have to poll the channel enable bit due 973808347f6SNicolas Ferre * to AHB/HSB limitations. 974808347f6SNicolas Ferre */ 975d8cb04b0SNicolas Ferre spin_lock_irqsave(&atchan->lock, flags); 976808347f6SNicolas Ferre 97723b5e3adSNicolas Ferre /* disabling channel: must also remove suspend state */ 97823b5e3adSNicolas Ferre dma_writel(atdma, CHDR, AT_DMA_RES(chan_id) | atchan->mask); 979808347f6SNicolas Ferre 980808347f6SNicolas Ferre /* confirm that this channel is disabled */ 981808347f6SNicolas Ferre while (dma_readl(atdma, CHSR) & atchan->mask) 982808347f6SNicolas Ferre cpu_relax(); 983808347f6SNicolas Ferre 984808347f6SNicolas Ferre /* active_list entries will end up before queued entries */ 985808347f6SNicolas Ferre list_splice_init(&atchan->queue, &list); 986808347f6SNicolas Ferre list_splice_init(&atchan->active_list, &list); 987808347f6SNicolas Ferre 988808347f6SNicolas Ferre /* Flush all pending and queued descriptors */ 989808347f6SNicolas Ferre list_for_each_entry_safe(desc, _desc, &list, desc_node) 990808347f6SNicolas Ferre atc_chain_complete(atchan, desc); 991c3635c78SLinus Walleij 99223b5e3adSNicolas Ferre clear_bit(ATC_IS_PAUSED, &atchan->status); 99353830cc7SNicolas Ferre /* if channel dedicated to cyclic operations, free it */ 99453830cc7SNicolas Ferre clear_bit(ATC_IS_CYCLIC, &atchan->status); 99553830cc7SNicolas Ferre 996d8cb04b0SNicolas Ferre spin_unlock_irqrestore(&atchan->lock, flags); 997beeaa103SNicolas Ferre } else if (cmd == DMA_SLAVE_CONFIG) { 998beeaa103SNicolas Ferre return set_runtime_config(chan, (struct dma_slave_config *)arg); 99923b5e3adSNicolas Ferre } else { 100023b5e3adSNicolas Ferre return -ENXIO; 100123b5e3adSNicolas Ferre } 1002b0ebeb9cSYong Wang 1003c3635c78SLinus Walleij return 0; 1004808347f6SNicolas Ferre } 1005808347f6SNicolas Ferre 1006dc78baa2SNicolas Ferre /** 100707934481SLinus Walleij * atc_tx_status - poll for transaction completion 1008dc78baa2SNicolas Ferre * @chan: DMA channel 1009dc78baa2SNicolas Ferre * @cookie: transaction identifier to check status of 101007934481SLinus Walleij * @txstate: if not %NULL updated with transaction state 1011dc78baa2SNicolas Ferre * 101207934481SLinus Walleij * If @txstate is passed in, upon return it reflect the driver 1013dc78baa2SNicolas Ferre * internal state and can be used with dma_async_is_complete() to check 1014dc78baa2SNicolas Ferre * the status of multiple cookies without re-checking hardware state. 1015dc78baa2SNicolas Ferre */ 1016dc78baa2SNicolas Ferre static enum dma_status 101707934481SLinus Walleij atc_tx_status(struct dma_chan *chan, 1018dc78baa2SNicolas Ferre dma_cookie_t cookie, 101907934481SLinus Walleij struct dma_tx_state *txstate) 1020dc78baa2SNicolas Ferre { 1021dc78baa2SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 1022dc78baa2SNicolas Ferre dma_cookie_t last_used; 1023dc78baa2SNicolas Ferre dma_cookie_t last_complete; 1024d8cb04b0SNicolas Ferre unsigned long flags; 1025dc78baa2SNicolas Ferre enum dma_status ret; 1026dc78baa2SNicolas Ferre 1027d8cb04b0SNicolas Ferre spin_lock_irqsave(&atchan->lock, flags); 1028dc78baa2SNicolas Ferre 102996a2af41SRussell King - ARM Linux ret = dma_cookie_status(chan, cookie, txstate); 1030dc78baa2SNicolas Ferre if (ret != DMA_SUCCESS) { 1031dc78baa2SNicolas Ferre atc_cleanup_descriptors(atchan); 1032dc78baa2SNicolas Ferre 103396a2af41SRussell King - ARM Linux ret = dma_cookie_status(chan, cookie, txstate); 103496a2af41SRussell King - ARM Linux } 103596a2af41SRussell King - ARM Linux 10364d4e58deSRussell King - ARM Linux last_complete = chan->completed_cookie; 1037dc78baa2SNicolas Ferre last_used = chan->cookie; 1038dc78baa2SNicolas Ferre 1039d8cb04b0SNicolas Ferre spin_unlock_irqrestore(&atchan->lock, flags); 1040dc78baa2SNicolas Ferre 1041543aabc7SNicolas Ferre if (ret != DMA_SUCCESS) 104296a2af41SRussell King - ARM Linux dma_set_residue(txstate, atc_first_active(atchan)->len); 1043543aabc7SNicolas Ferre 10443c477482SNicolas Ferre if (atc_chan_is_paused(atchan)) 104523b5e3adSNicolas Ferre ret = DMA_PAUSED; 104623b5e3adSNicolas Ferre 104723b5e3adSNicolas Ferre dev_vdbg(chan2dev(chan), "tx_status %d: cookie = %d (d%d, u%d)\n", 104823b5e3adSNicolas Ferre ret, cookie, last_complete ? last_complete : 0, 104907934481SLinus Walleij last_used ? last_used : 0); 1050dc78baa2SNicolas Ferre 1051dc78baa2SNicolas Ferre return ret; 1052dc78baa2SNicolas Ferre } 1053dc78baa2SNicolas Ferre 1054dc78baa2SNicolas Ferre /** 1055dc78baa2SNicolas Ferre * atc_issue_pending - try to finish work 1056dc78baa2SNicolas Ferre * @chan: target DMA channel 1057dc78baa2SNicolas Ferre */ 1058dc78baa2SNicolas Ferre static void atc_issue_pending(struct dma_chan *chan) 1059dc78baa2SNicolas Ferre { 1060dc78baa2SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 1061d8cb04b0SNicolas Ferre unsigned long flags; 1062dc78baa2SNicolas Ferre 1063dc78baa2SNicolas Ferre dev_vdbg(chan2dev(chan), "issue_pending\n"); 1064dc78baa2SNicolas Ferre 106553830cc7SNicolas Ferre /* Not needed for cyclic transfers */ 10663c477482SNicolas Ferre if (atc_chan_is_cyclic(atchan)) 106753830cc7SNicolas Ferre return; 106853830cc7SNicolas Ferre 1069d8cb04b0SNicolas Ferre spin_lock_irqsave(&atchan->lock, flags); 1070dda36f98SNicolas Ferre if (!atc_chan_is_enabled(atchan)) { 1071dc78baa2SNicolas Ferre atc_advance_work(atchan); 1072dc78baa2SNicolas Ferre } 1073d8cb04b0SNicolas Ferre spin_unlock_irqrestore(&atchan->lock, flags); 1074dc78baa2SNicolas Ferre } 1075dc78baa2SNicolas Ferre 1076dc78baa2SNicolas Ferre /** 1077dc78baa2SNicolas Ferre * atc_alloc_chan_resources - allocate resources for DMA channel 1078dc78baa2SNicolas Ferre * @chan: allocate descriptor resources for this channel 1079dc78baa2SNicolas Ferre * @client: current client requesting the channel be ready for requests 1080dc78baa2SNicolas Ferre * 1081dc78baa2SNicolas Ferre * return - the number of allocated descriptors 1082dc78baa2SNicolas Ferre */ 1083dc78baa2SNicolas Ferre static int atc_alloc_chan_resources(struct dma_chan *chan) 1084dc78baa2SNicolas Ferre { 1085dc78baa2SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 1086dc78baa2SNicolas Ferre struct at_dma *atdma = to_at_dma(chan->device); 1087dc78baa2SNicolas Ferre struct at_desc *desc; 1088808347f6SNicolas Ferre struct at_dma_slave *atslave; 1089d8cb04b0SNicolas Ferre unsigned long flags; 1090dc78baa2SNicolas Ferre int i; 1091808347f6SNicolas Ferre u32 cfg; 1092dc78baa2SNicolas Ferre LIST_HEAD(tmp_list); 1093dc78baa2SNicolas Ferre 1094dc78baa2SNicolas Ferre dev_vdbg(chan2dev(chan), "alloc_chan_resources\n"); 1095dc78baa2SNicolas Ferre 1096dc78baa2SNicolas Ferre /* ASSERT: channel is idle */ 1097dc78baa2SNicolas Ferre if (atc_chan_is_enabled(atchan)) { 1098dc78baa2SNicolas Ferre dev_dbg(chan2dev(chan), "DMA channel not idle ?\n"); 1099dc78baa2SNicolas Ferre return -EIO; 1100dc78baa2SNicolas Ferre } 1101dc78baa2SNicolas Ferre 1102808347f6SNicolas Ferre cfg = ATC_DEFAULT_CFG; 1103808347f6SNicolas Ferre 1104808347f6SNicolas Ferre atslave = chan->private; 1105808347f6SNicolas Ferre if (atslave) { 1106808347f6SNicolas Ferre /* 1107808347f6SNicolas Ferre * We need controller-specific data to set up slave 1108808347f6SNicolas Ferre * transfers. 1109808347f6SNicolas Ferre */ 1110808347f6SNicolas Ferre BUG_ON(!atslave->dma_dev || atslave->dma_dev != atdma->dma_common.dev); 1111808347f6SNicolas Ferre 1112808347f6SNicolas Ferre /* if cfg configuration specified take it instad of default */ 1113808347f6SNicolas Ferre if (atslave->cfg) 1114808347f6SNicolas Ferre cfg = atslave->cfg; 1115808347f6SNicolas Ferre } 1116808347f6SNicolas Ferre 1117808347f6SNicolas Ferre /* have we already been set up? 1118808347f6SNicolas Ferre * reconfigure channel but no need to reallocate descriptors */ 1119dc78baa2SNicolas Ferre if (!list_empty(&atchan->free_list)) 1120dc78baa2SNicolas Ferre return atchan->descs_allocated; 1121dc78baa2SNicolas Ferre 1122dc78baa2SNicolas Ferre /* Allocate initial pool of descriptors */ 1123dc78baa2SNicolas Ferre for (i = 0; i < init_nr_desc_per_channel; i++) { 1124dc78baa2SNicolas Ferre desc = atc_alloc_descriptor(chan, GFP_KERNEL); 1125dc78baa2SNicolas Ferre if (!desc) { 1126dc78baa2SNicolas Ferre dev_err(atdma->dma_common.dev, 1127dc78baa2SNicolas Ferre "Only %d initial descriptors\n", i); 1128dc78baa2SNicolas Ferre break; 1129dc78baa2SNicolas Ferre } 1130dc78baa2SNicolas Ferre list_add_tail(&desc->desc_node, &tmp_list); 1131dc78baa2SNicolas Ferre } 1132dc78baa2SNicolas Ferre 1133d8cb04b0SNicolas Ferre spin_lock_irqsave(&atchan->lock, flags); 1134dc78baa2SNicolas Ferre atchan->descs_allocated = i; 1135dc78baa2SNicolas Ferre list_splice(&tmp_list, &atchan->free_list); 1136d3ee98cdSRussell King - ARM Linux dma_cookie_init(chan); 1137d8cb04b0SNicolas Ferre spin_unlock_irqrestore(&atchan->lock, flags); 1138dc78baa2SNicolas Ferre 1139dc78baa2SNicolas Ferre /* channel parameters */ 1140808347f6SNicolas Ferre channel_writel(atchan, CFG, cfg); 1141dc78baa2SNicolas Ferre 1142dc78baa2SNicolas Ferre dev_dbg(chan2dev(chan), 1143dc78baa2SNicolas Ferre "alloc_chan_resources: allocated %d descriptors\n", 1144dc78baa2SNicolas Ferre atchan->descs_allocated); 1145dc78baa2SNicolas Ferre 1146dc78baa2SNicolas Ferre return atchan->descs_allocated; 1147dc78baa2SNicolas Ferre } 1148dc78baa2SNicolas Ferre 1149dc78baa2SNicolas Ferre /** 1150dc78baa2SNicolas Ferre * atc_free_chan_resources - free all channel resources 1151dc78baa2SNicolas Ferre * @chan: DMA channel 1152dc78baa2SNicolas Ferre */ 1153dc78baa2SNicolas Ferre static void atc_free_chan_resources(struct dma_chan *chan) 1154dc78baa2SNicolas Ferre { 1155dc78baa2SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 1156dc78baa2SNicolas Ferre struct at_dma *atdma = to_at_dma(chan->device); 1157dc78baa2SNicolas Ferre struct at_desc *desc, *_desc; 1158dc78baa2SNicolas Ferre LIST_HEAD(list); 1159dc78baa2SNicolas Ferre 1160dc78baa2SNicolas Ferre dev_dbg(chan2dev(chan), "free_chan_resources: (descs allocated=%u)\n", 1161dc78baa2SNicolas Ferre atchan->descs_allocated); 1162dc78baa2SNicolas Ferre 1163dc78baa2SNicolas Ferre /* ASSERT: channel is idle */ 1164dc78baa2SNicolas Ferre BUG_ON(!list_empty(&atchan->active_list)); 1165dc78baa2SNicolas Ferre BUG_ON(!list_empty(&atchan->queue)); 1166dc78baa2SNicolas Ferre BUG_ON(atc_chan_is_enabled(atchan)); 1167dc78baa2SNicolas Ferre 1168dc78baa2SNicolas Ferre list_for_each_entry_safe(desc, _desc, &atchan->free_list, desc_node) { 1169dc78baa2SNicolas Ferre dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc); 1170dc78baa2SNicolas Ferre list_del(&desc->desc_node); 1171dc78baa2SNicolas Ferre /* free link descriptor */ 1172dc78baa2SNicolas Ferre dma_pool_free(atdma->dma_desc_pool, desc, desc->txd.phys); 1173dc78baa2SNicolas Ferre } 1174dc78baa2SNicolas Ferre list_splice_init(&atchan->free_list, &list); 1175dc78baa2SNicolas Ferre atchan->descs_allocated = 0; 117653830cc7SNicolas Ferre atchan->status = 0; 1177dc78baa2SNicolas Ferre 1178dc78baa2SNicolas Ferre dev_vdbg(chan2dev(chan), "free_chan_resources: done\n"); 1179dc78baa2SNicolas Ferre } 1180dc78baa2SNicolas Ferre 1181dc78baa2SNicolas Ferre 1182dc78baa2SNicolas Ferre /*-- Module Management -----------------------------------------------*/ 1183dc78baa2SNicolas Ferre 118402f88be9SNicolas Ferre /* cap_mask is a multi-u32 bitfield, fill it with proper C code. */ 118502f88be9SNicolas Ferre static struct at_dma_platform_data at91sam9rl_config = { 118602f88be9SNicolas Ferre .nr_channels = 2, 118702f88be9SNicolas Ferre }; 118802f88be9SNicolas Ferre static struct at_dma_platform_data at91sam9g45_config = { 118902f88be9SNicolas Ferre .nr_channels = 8, 119002f88be9SNicolas Ferre }; 119102f88be9SNicolas Ferre 1192c5115953SNicolas Ferre #if defined(CONFIG_OF) 1193c5115953SNicolas Ferre static const struct of_device_id atmel_dma_dt_ids[] = { 1194c5115953SNicolas Ferre { 1195c5115953SNicolas Ferre .compatible = "atmel,at91sam9rl-dma", 119602f88be9SNicolas Ferre .data = &at91sam9rl_config, 1197c5115953SNicolas Ferre }, { 1198c5115953SNicolas Ferre .compatible = "atmel,at91sam9g45-dma", 119902f88be9SNicolas Ferre .data = &at91sam9g45_config, 1200dcc81734SNicolas Ferre }, { 1201dcc81734SNicolas Ferre /* sentinel */ 1202dcc81734SNicolas Ferre } 1203c5115953SNicolas Ferre }; 1204c5115953SNicolas Ferre 1205c5115953SNicolas Ferre MODULE_DEVICE_TABLE(of, atmel_dma_dt_ids); 1206c5115953SNicolas Ferre #endif 1207c5115953SNicolas Ferre 12080ab88a01SNicolas Ferre static const struct platform_device_id atdma_devtypes[] = { 120967348450SNicolas Ferre { 121067348450SNicolas Ferre .name = "at91sam9rl_dma", 121102f88be9SNicolas Ferre .driver_data = (unsigned long) &at91sam9rl_config, 121267348450SNicolas Ferre }, { 121367348450SNicolas Ferre .name = "at91sam9g45_dma", 121402f88be9SNicolas Ferre .driver_data = (unsigned long) &at91sam9g45_config, 121567348450SNicolas Ferre }, { 121667348450SNicolas Ferre /* sentinel */ 121767348450SNicolas Ferre } 121867348450SNicolas Ferre }; 121967348450SNicolas Ferre 122002f88be9SNicolas Ferre static inline struct at_dma_platform_data * __init at_dma_get_driver_data( 1221c5115953SNicolas Ferre struct platform_device *pdev) 1222c5115953SNicolas Ferre { 1223c5115953SNicolas Ferre if (pdev->dev.of_node) { 1224c5115953SNicolas Ferre const struct of_device_id *match; 1225c5115953SNicolas Ferre match = of_match_node(atmel_dma_dt_ids, pdev->dev.of_node); 1226c5115953SNicolas Ferre if (match == NULL) 122702f88be9SNicolas Ferre return NULL; 122802f88be9SNicolas Ferre return match->data; 1229c5115953SNicolas Ferre } 123002f88be9SNicolas Ferre return (struct at_dma_platform_data *) 123102f88be9SNicolas Ferre platform_get_device_id(pdev)->driver_data; 1232c5115953SNicolas Ferre } 1233c5115953SNicolas Ferre 1234dc78baa2SNicolas Ferre /** 1235dc78baa2SNicolas Ferre * at_dma_off - disable DMA controller 1236dc78baa2SNicolas Ferre * @atdma: the Atmel HDAMC device 1237dc78baa2SNicolas Ferre */ 1238dc78baa2SNicolas Ferre static void at_dma_off(struct at_dma *atdma) 1239dc78baa2SNicolas Ferre { 1240dc78baa2SNicolas Ferre dma_writel(atdma, EN, 0); 1241dc78baa2SNicolas Ferre 1242dc78baa2SNicolas Ferre /* disable all interrupts */ 1243dc78baa2SNicolas Ferre dma_writel(atdma, EBCIDR, -1L); 1244dc78baa2SNicolas Ferre 1245dc78baa2SNicolas Ferre /* confirm that all channels are disabled */ 1246dc78baa2SNicolas Ferre while (dma_readl(atdma, CHSR) & atdma->all_chan_mask) 1247dc78baa2SNicolas Ferre cpu_relax(); 1248dc78baa2SNicolas Ferre } 1249dc78baa2SNicolas Ferre 1250dc78baa2SNicolas Ferre static int __init at_dma_probe(struct platform_device *pdev) 1251dc78baa2SNicolas Ferre { 1252dc78baa2SNicolas Ferre struct resource *io; 1253dc78baa2SNicolas Ferre struct at_dma *atdma; 1254dc78baa2SNicolas Ferre size_t size; 1255dc78baa2SNicolas Ferre int irq; 1256dc78baa2SNicolas Ferre int err; 1257dc78baa2SNicolas Ferre int i; 125802f88be9SNicolas Ferre struct at_dma_platform_data *plat_dat; 1259dc78baa2SNicolas Ferre 126002f88be9SNicolas Ferre /* setup platform data for each SoC */ 126102f88be9SNicolas Ferre dma_cap_set(DMA_MEMCPY, at91sam9rl_config.cap_mask); 126202f88be9SNicolas Ferre dma_cap_set(DMA_MEMCPY, at91sam9g45_config.cap_mask); 126302f88be9SNicolas Ferre dma_cap_set(DMA_SLAVE, at91sam9g45_config.cap_mask); 126467348450SNicolas Ferre 126567348450SNicolas Ferre /* get DMA parameters from controller type */ 126602f88be9SNicolas Ferre plat_dat = at_dma_get_driver_data(pdev); 126702f88be9SNicolas Ferre if (!plat_dat) 126802f88be9SNicolas Ferre return -ENODEV; 1269dc78baa2SNicolas Ferre 1270dc78baa2SNicolas Ferre io = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1271dc78baa2SNicolas Ferre if (!io) 1272dc78baa2SNicolas Ferre return -EINVAL; 1273dc78baa2SNicolas Ferre 1274dc78baa2SNicolas Ferre irq = platform_get_irq(pdev, 0); 1275dc78baa2SNicolas Ferre if (irq < 0) 1276dc78baa2SNicolas Ferre return irq; 1277dc78baa2SNicolas Ferre 1278dc78baa2SNicolas Ferre size = sizeof(struct at_dma); 127902f88be9SNicolas Ferre size += plat_dat->nr_channels * sizeof(struct at_dma_chan); 1280dc78baa2SNicolas Ferre atdma = kzalloc(size, GFP_KERNEL); 1281dc78baa2SNicolas Ferre if (!atdma) 1282dc78baa2SNicolas Ferre return -ENOMEM; 1283dc78baa2SNicolas Ferre 128467348450SNicolas Ferre /* discover transaction capabilities */ 128502f88be9SNicolas Ferre atdma->dma_common.cap_mask = plat_dat->cap_mask; 128602f88be9SNicolas Ferre atdma->all_chan_mask = (1 << plat_dat->nr_channels) - 1; 1287dc78baa2SNicolas Ferre 1288114df7d6SH Hartley Sweeten size = resource_size(io); 1289dc78baa2SNicolas Ferre if (!request_mem_region(io->start, size, pdev->dev.driver->name)) { 1290dc78baa2SNicolas Ferre err = -EBUSY; 1291dc78baa2SNicolas Ferre goto err_kfree; 1292dc78baa2SNicolas Ferre } 1293dc78baa2SNicolas Ferre 1294dc78baa2SNicolas Ferre atdma->regs = ioremap(io->start, size); 1295dc78baa2SNicolas Ferre if (!atdma->regs) { 1296dc78baa2SNicolas Ferre err = -ENOMEM; 1297dc78baa2SNicolas Ferre goto err_release_r; 1298dc78baa2SNicolas Ferre } 1299dc78baa2SNicolas Ferre 1300dc78baa2SNicolas Ferre atdma->clk = clk_get(&pdev->dev, "dma_clk"); 1301dc78baa2SNicolas Ferre if (IS_ERR(atdma->clk)) { 1302dc78baa2SNicolas Ferre err = PTR_ERR(atdma->clk); 1303dc78baa2SNicolas Ferre goto err_clk; 1304dc78baa2SNicolas Ferre } 1305dc78baa2SNicolas Ferre clk_enable(atdma->clk); 1306dc78baa2SNicolas Ferre 1307dc78baa2SNicolas Ferre /* force dma off, just in case */ 1308dc78baa2SNicolas Ferre at_dma_off(atdma); 1309dc78baa2SNicolas Ferre 1310dc78baa2SNicolas Ferre err = request_irq(irq, at_dma_interrupt, 0, "at_hdmac", atdma); 1311dc78baa2SNicolas Ferre if (err) 1312dc78baa2SNicolas Ferre goto err_irq; 1313dc78baa2SNicolas Ferre 1314dc78baa2SNicolas Ferre platform_set_drvdata(pdev, atdma); 1315dc78baa2SNicolas Ferre 1316dc78baa2SNicolas Ferre /* create a pool of consistent memory blocks for hardware descriptors */ 1317dc78baa2SNicolas Ferre atdma->dma_desc_pool = dma_pool_create("at_hdmac_desc_pool", 1318dc78baa2SNicolas Ferre &pdev->dev, sizeof(struct at_desc), 1319dc78baa2SNicolas Ferre 4 /* word alignment */, 0); 1320dc78baa2SNicolas Ferre if (!atdma->dma_desc_pool) { 1321dc78baa2SNicolas Ferre dev_err(&pdev->dev, "No memory for descriptors dma pool\n"); 1322dc78baa2SNicolas Ferre err = -ENOMEM; 1323dc78baa2SNicolas Ferre goto err_pool_create; 1324dc78baa2SNicolas Ferre } 1325dc78baa2SNicolas Ferre 1326dc78baa2SNicolas Ferre /* clear any pending interrupt */ 1327dc78baa2SNicolas Ferre while (dma_readl(atdma, EBCISR)) 1328dc78baa2SNicolas Ferre cpu_relax(); 1329dc78baa2SNicolas Ferre 1330dc78baa2SNicolas Ferre /* initialize channels related values */ 1331dc78baa2SNicolas Ferre INIT_LIST_HEAD(&atdma->dma_common.channels); 133202f88be9SNicolas Ferre for (i = 0; i < plat_dat->nr_channels; i++) { 1333dc78baa2SNicolas Ferre struct at_dma_chan *atchan = &atdma->chan[i]; 1334dc78baa2SNicolas Ferre 1335dc78baa2SNicolas Ferre atchan->chan_common.device = &atdma->dma_common; 1336d3ee98cdSRussell King - ARM Linux dma_cookie_init(&atchan->chan_common); 1337dc78baa2SNicolas Ferre list_add_tail(&atchan->chan_common.device_node, 1338dc78baa2SNicolas Ferre &atdma->dma_common.channels); 1339dc78baa2SNicolas Ferre 1340dc78baa2SNicolas Ferre atchan->ch_regs = atdma->regs + ch_regs(i); 1341dc78baa2SNicolas Ferre spin_lock_init(&atchan->lock); 1342dc78baa2SNicolas Ferre atchan->mask = 1 << i; 1343dc78baa2SNicolas Ferre 1344dc78baa2SNicolas Ferre INIT_LIST_HEAD(&atchan->active_list); 1345dc78baa2SNicolas Ferre INIT_LIST_HEAD(&atchan->queue); 1346dc78baa2SNicolas Ferre INIT_LIST_HEAD(&atchan->free_list); 1347dc78baa2SNicolas Ferre 1348dc78baa2SNicolas Ferre tasklet_init(&atchan->tasklet, atc_tasklet, 1349dc78baa2SNicolas Ferre (unsigned long)atchan); 1350bda3a47cSNikolaus Voss atc_enable_chan_irq(atdma, i); 1351dc78baa2SNicolas Ferre } 1352dc78baa2SNicolas Ferre 1353dc78baa2SNicolas Ferre /* set base routines */ 1354dc78baa2SNicolas Ferre atdma->dma_common.device_alloc_chan_resources = atc_alloc_chan_resources; 1355dc78baa2SNicolas Ferre atdma->dma_common.device_free_chan_resources = atc_free_chan_resources; 135607934481SLinus Walleij atdma->dma_common.device_tx_status = atc_tx_status; 1357dc78baa2SNicolas Ferre atdma->dma_common.device_issue_pending = atc_issue_pending; 1358dc78baa2SNicolas Ferre atdma->dma_common.dev = &pdev->dev; 1359dc78baa2SNicolas Ferre 1360dc78baa2SNicolas Ferre /* set prep routines based on capability */ 1361dc78baa2SNicolas Ferre if (dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask)) 1362dc78baa2SNicolas Ferre atdma->dma_common.device_prep_dma_memcpy = atc_prep_dma_memcpy; 1363dc78baa2SNicolas Ferre 1364d7db8080SNicolas Ferre if (dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask)) { 1365808347f6SNicolas Ferre atdma->dma_common.device_prep_slave_sg = atc_prep_slave_sg; 1366d7db8080SNicolas Ferre /* controller can do slave DMA: can trigger cyclic transfers */ 1367d7db8080SNicolas Ferre dma_cap_set(DMA_CYCLIC, atdma->dma_common.cap_mask); 136853830cc7SNicolas Ferre atdma->dma_common.device_prep_dma_cyclic = atc_prep_dma_cyclic; 1369c3635c78SLinus Walleij atdma->dma_common.device_control = atc_control; 1370d7db8080SNicolas Ferre } 1371808347f6SNicolas Ferre 1372dc78baa2SNicolas Ferre dma_writel(atdma, EN, AT_DMA_ENABLE); 1373dc78baa2SNicolas Ferre 1374dc78baa2SNicolas Ferre dev_info(&pdev->dev, "Atmel AHB DMA Controller ( %s%s), %d channels\n", 1375dc78baa2SNicolas Ferre dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask) ? "cpy " : "", 1376dc78baa2SNicolas Ferre dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask) ? "slave " : "", 137702f88be9SNicolas Ferre plat_dat->nr_channels); 1378dc78baa2SNicolas Ferre 1379dc78baa2SNicolas Ferre dma_async_device_register(&atdma->dma_common); 1380dc78baa2SNicolas Ferre 1381dc78baa2SNicolas Ferre return 0; 1382dc78baa2SNicolas Ferre 1383dc78baa2SNicolas Ferre err_pool_create: 1384dc78baa2SNicolas Ferre platform_set_drvdata(pdev, NULL); 1385dc78baa2SNicolas Ferre free_irq(platform_get_irq(pdev, 0), atdma); 1386dc78baa2SNicolas Ferre err_irq: 1387dc78baa2SNicolas Ferre clk_disable(atdma->clk); 1388dc78baa2SNicolas Ferre clk_put(atdma->clk); 1389dc78baa2SNicolas Ferre err_clk: 1390dc78baa2SNicolas Ferre iounmap(atdma->regs); 1391dc78baa2SNicolas Ferre atdma->regs = NULL; 1392dc78baa2SNicolas Ferre err_release_r: 1393dc78baa2SNicolas Ferre release_mem_region(io->start, size); 1394dc78baa2SNicolas Ferre err_kfree: 1395dc78baa2SNicolas Ferre kfree(atdma); 1396dc78baa2SNicolas Ferre return err; 1397dc78baa2SNicolas Ferre } 1398dc78baa2SNicolas Ferre 1399dc78baa2SNicolas Ferre static int __exit at_dma_remove(struct platform_device *pdev) 1400dc78baa2SNicolas Ferre { 1401dc78baa2SNicolas Ferre struct at_dma *atdma = platform_get_drvdata(pdev); 1402dc78baa2SNicolas Ferre struct dma_chan *chan, *_chan; 1403dc78baa2SNicolas Ferre struct resource *io; 1404dc78baa2SNicolas Ferre 1405dc78baa2SNicolas Ferre at_dma_off(atdma); 1406dc78baa2SNicolas Ferre dma_async_device_unregister(&atdma->dma_common); 1407dc78baa2SNicolas Ferre 1408dc78baa2SNicolas Ferre dma_pool_destroy(atdma->dma_desc_pool); 1409dc78baa2SNicolas Ferre platform_set_drvdata(pdev, NULL); 1410dc78baa2SNicolas Ferre free_irq(platform_get_irq(pdev, 0), atdma); 1411dc78baa2SNicolas Ferre 1412dc78baa2SNicolas Ferre list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels, 1413dc78baa2SNicolas Ferre device_node) { 1414dc78baa2SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 1415dc78baa2SNicolas Ferre 1416dc78baa2SNicolas Ferre /* Disable interrupts */ 1417bda3a47cSNikolaus Voss atc_disable_chan_irq(atdma, chan->chan_id); 1418dc78baa2SNicolas Ferre tasklet_disable(&atchan->tasklet); 1419dc78baa2SNicolas Ferre 1420dc78baa2SNicolas Ferre tasklet_kill(&atchan->tasklet); 1421dc78baa2SNicolas Ferre list_del(&chan->device_node); 1422dc78baa2SNicolas Ferre } 1423dc78baa2SNicolas Ferre 1424dc78baa2SNicolas Ferre clk_disable(atdma->clk); 1425dc78baa2SNicolas Ferre clk_put(atdma->clk); 1426dc78baa2SNicolas Ferre 1427dc78baa2SNicolas Ferre iounmap(atdma->regs); 1428dc78baa2SNicolas Ferre atdma->regs = NULL; 1429dc78baa2SNicolas Ferre 1430dc78baa2SNicolas Ferre io = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1431114df7d6SH Hartley Sweeten release_mem_region(io->start, resource_size(io)); 1432dc78baa2SNicolas Ferre 1433dc78baa2SNicolas Ferre kfree(atdma); 1434dc78baa2SNicolas Ferre 1435dc78baa2SNicolas Ferre return 0; 1436dc78baa2SNicolas Ferre } 1437dc78baa2SNicolas Ferre 1438dc78baa2SNicolas Ferre static void at_dma_shutdown(struct platform_device *pdev) 1439dc78baa2SNicolas Ferre { 1440dc78baa2SNicolas Ferre struct at_dma *atdma = platform_get_drvdata(pdev); 1441dc78baa2SNicolas Ferre 1442dc78baa2SNicolas Ferre at_dma_off(platform_get_drvdata(pdev)); 1443dc78baa2SNicolas Ferre clk_disable(atdma->clk); 1444dc78baa2SNicolas Ferre } 1445dc78baa2SNicolas Ferre 1446c0ba5947SNicolas Ferre static int at_dma_prepare(struct device *dev) 1447c0ba5947SNicolas Ferre { 1448c0ba5947SNicolas Ferre struct platform_device *pdev = to_platform_device(dev); 1449c0ba5947SNicolas Ferre struct at_dma *atdma = platform_get_drvdata(pdev); 1450c0ba5947SNicolas Ferre struct dma_chan *chan, *_chan; 1451c0ba5947SNicolas Ferre 1452c0ba5947SNicolas Ferre list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels, 1453c0ba5947SNicolas Ferre device_node) { 1454c0ba5947SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 1455c0ba5947SNicolas Ferre /* wait for transaction completion (except in cyclic case) */ 14563c477482SNicolas Ferre if (atc_chan_is_enabled(atchan) && !atc_chan_is_cyclic(atchan)) 1457c0ba5947SNicolas Ferre return -EAGAIN; 1458c0ba5947SNicolas Ferre } 1459c0ba5947SNicolas Ferre return 0; 1460c0ba5947SNicolas Ferre } 1461c0ba5947SNicolas Ferre 1462c0ba5947SNicolas Ferre static void atc_suspend_cyclic(struct at_dma_chan *atchan) 1463c0ba5947SNicolas Ferre { 1464c0ba5947SNicolas Ferre struct dma_chan *chan = &atchan->chan_common; 1465c0ba5947SNicolas Ferre 1466c0ba5947SNicolas Ferre /* Channel should be paused by user 1467c0ba5947SNicolas Ferre * do it anyway even if it is not done already */ 14683c477482SNicolas Ferre if (!atc_chan_is_paused(atchan)) { 1469c0ba5947SNicolas Ferre dev_warn(chan2dev(chan), 1470c0ba5947SNicolas Ferre "cyclic channel not paused, should be done by channel user\n"); 1471c0ba5947SNicolas Ferre atc_control(chan, DMA_PAUSE, 0); 1472c0ba5947SNicolas Ferre } 1473c0ba5947SNicolas Ferre 1474c0ba5947SNicolas Ferre /* now preserve additional data for cyclic operations */ 1475c0ba5947SNicolas Ferre /* next descriptor address in the cyclic list */ 1476c0ba5947SNicolas Ferre atchan->save_dscr = channel_readl(atchan, DSCR); 1477c0ba5947SNicolas Ferre 1478c0ba5947SNicolas Ferre vdbg_dump_regs(atchan); 1479c0ba5947SNicolas Ferre } 1480c0ba5947SNicolas Ferre 148133f82d14SDan Williams static int at_dma_suspend_noirq(struct device *dev) 1482dc78baa2SNicolas Ferre { 148333f82d14SDan Williams struct platform_device *pdev = to_platform_device(dev); 1484dc78baa2SNicolas Ferre struct at_dma *atdma = platform_get_drvdata(pdev); 1485c0ba5947SNicolas Ferre struct dma_chan *chan, *_chan; 1486dc78baa2SNicolas Ferre 1487c0ba5947SNicolas Ferre /* preserve data */ 1488c0ba5947SNicolas Ferre list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels, 1489c0ba5947SNicolas Ferre device_node) { 1490c0ba5947SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 1491c0ba5947SNicolas Ferre 14923c477482SNicolas Ferre if (atc_chan_is_cyclic(atchan)) 1493c0ba5947SNicolas Ferre atc_suspend_cyclic(atchan); 1494c0ba5947SNicolas Ferre atchan->save_cfg = channel_readl(atchan, CFG); 1495c0ba5947SNicolas Ferre } 1496c0ba5947SNicolas Ferre atdma->save_imr = dma_readl(atdma, EBCIMR); 1497c0ba5947SNicolas Ferre 1498c0ba5947SNicolas Ferre /* disable DMA controller */ 1499c0ba5947SNicolas Ferre at_dma_off(atdma); 1500dc78baa2SNicolas Ferre clk_disable(atdma->clk); 1501dc78baa2SNicolas Ferre return 0; 1502dc78baa2SNicolas Ferre } 1503dc78baa2SNicolas Ferre 1504c0ba5947SNicolas Ferre static void atc_resume_cyclic(struct at_dma_chan *atchan) 1505c0ba5947SNicolas Ferre { 1506c0ba5947SNicolas Ferre struct at_dma *atdma = to_at_dma(atchan->chan_common.device); 1507c0ba5947SNicolas Ferre 1508c0ba5947SNicolas Ferre /* restore channel status for cyclic descriptors list: 1509c0ba5947SNicolas Ferre * next descriptor in the cyclic list at the time of suspend */ 1510c0ba5947SNicolas Ferre channel_writel(atchan, SADDR, 0); 1511c0ba5947SNicolas Ferre channel_writel(atchan, DADDR, 0); 1512c0ba5947SNicolas Ferre channel_writel(atchan, CTRLA, 0); 1513c0ba5947SNicolas Ferre channel_writel(atchan, CTRLB, 0); 1514c0ba5947SNicolas Ferre channel_writel(atchan, DSCR, atchan->save_dscr); 1515c0ba5947SNicolas Ferre dma_writel(atdma, CHER, atchan->mask); 1516c0ba5947SNicolas Ferre 1517c0ba5947SNicolas Ferre /* channel pause status should be removed by channel user 1518c0ba5947SNicolas Ferre * We cannot take the initiative to do it here */ 1519c0ba5947SNicolas Ferre 1520c0ba5947SNicolas Ferre vdbg_dump_regs(atchan); 1521c0ba5947SNicolas Ferre } 1522c0ba5947SNicolas Ferre 152333f82d14SDan Williams static int at_dma_resume_noirq(struct device *dev) 1524dc78baa2SNicolas Ferre { 152533f82d14SDan Williams struct platform_device *pdev = to_platform_device(dev); 1526dc78baa2SNicolas Ferre struct at_dma *atdma = platform_get_drvdata(pdev); 1527c0ba5947SNicolas Ferre struct dma_chan *chan, *_chan; 1528dc78baa2SNicolas Ferre 1529c0ba5947SNicolas Ferre /* bring back DMA controller */ 1530dc78baa2SNicolas Ferre clk_enable(atdma->clk); 1531dc78baa2SNicolas Ferre dma_writel(atdma, EN, AT_DMA_ENABLE); 1532c0ba5947SNicolas Ferre 1533c0ba5947SNicolas Ferre /* clear any pending interrupt */ 1534c0ba5947SNicolas Ferre while (dma_readl(atdma, EBCISR)) 1535c0ba5947SNicolas Ferre cpu_relax(); 1536c0ba5947SNicolas Ferre 1537c0ba5947SNicolas Ferre /* restore saved data */ 1538c0ba5947SNicolas Ferre dma_writel(atdma, EBCIER, atdma->save_imr); 1539c0ba5947SNicolas Ferre list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels, 1540c0ba5947SNicolas Ferre device_node) { 1541c0ba5947SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 1542c0ba5947SNicolas Ferre 1543c0ba5947SNicolas Ferre channel_writel(atchan, CFG, atchan->save_cfg); 15443c477482SNicolas Ferre if (atc_chan_is_cyclic(atchan)) 1545c0ba5947SNicolas Ferre atc_resume_cyclic(atchan); 1546c0ba5947SNicolas Ferre } 1547dc78baa2SNicolas Ferre return 0; 1548dc78baa2SNicolas Ferre } 1549dc78baa2SNicolas Ferre 155047145210SAlexey Dobriyan static const struct dev_pm_ops at_dma_dev_pm_ops = { 1551c0ba5947SNicolas Ferre .prepare = at_dma_prepare, 155233f82d14SDan Williams .suspend_noirq = at_dma_suspend_noirq, 155333f82d14SDan Williams .resume_noirq = at_dma_resume_noirq, 155433f82d14SDan Williams }; 155533f82d14SDan Williams 1556dc78baa2SNicolas Ferre static struct platform_driver at_dma_driver = { 1557dc78baa2SNicolas Ferre .remove = __exit_p(at_dma_remove), 1558dc78baa2SNicolas Ferre .shutdown = at_dma_shutdown, 155967348450SNicolas Ferre .id_table = atdma_devtypes, 1560dc78baa2SNicolas Ferre .driver = { 1561dc78baa2SNicolas Ferre .name = "at_hdmac", 156233f82d14SDan Williams .pm = &at_dma_dev_pm_ops, 1563c5115953SNicolas Ferre .of_match_table = of_match_ptr(atmel_dma_dt_ids), 1564dc78baa2SNicolas Ferre }, 1565dc78baa2SNicolas Ferre }; 1566dc78baa2SNicolas Ferre 1567dc78baa2SNicolas Ferre static int __init at_dma_init(void) 1568dc78baa2SNicolas Ferre { 1569dc78baa2SNicolas Ferre return platform_driver_probe(&at_dma_driver, at_dma_probe); 1570dc78baa2SNicolas Ferre } 157193d0bec2SEric Xu subsys_initcall(at_dma_init); 1572dc78baa2SNicolas Ferre 1573dc78baa2SNicolas Ferre static void __exit at_dma_exit(void) 1574dc78baa2SNicolas Ferre { 1575dc78baa2SNicolas Ferre platform_driver_unregister(&at_dma_driver); 1576dc78baa2SNicolas Ferre } 1577dc78baa2SNicolas Ferre module_exit(at_dma_exit); 1578dc78baa2SNicolas Ferre 1579dc78baa2SNicolas Ferre MODULE_DESCRIPTION("Atmel AHB DMA Controller driver"); 1580dc78baa2SNicolas Ferre MODULE_AUTHOR("Nicolas Ferre <nicolas.ferre@atmel.com>"); 1581dc78baa2SNicolas Ferre MODULE_LICENSE("GPL"); 1582dc78baa2SNicolas Ferre MODULE_ALIAS("platform:at_hdmac"); 1583