1dc78baa2SNicolas Ferre /* 2dc78baa2SNicolas Ferre * Driver for the Atmel AHB DMA Controller (aka HDMA or DMAC on AT91 systems) 3dc78baa2SNicolas Ferre * 4dc78baa2SNicolas Ferre * Copyright (C) 2008 Atmel Corporation 5dc78baa2SNicolas Ferre * 6dc78baa2SNicolas Ferre * This program is free software; you can redistribute it and/or modify 7dc78baa2SNicolas Ferre * it under the terms of the GNU General Public License as published by 8dc78baa2SNicolas Ferre * the Free Software Foundation; either version 2 of the License, or 9dc78baa2SNicolas Ferre * (at your option) any later version. 10dc78baa2SNicolas Ferre * 11dc78baa2SNicolas Ferre * 12dc78baa2SNicolas Ferre * This supports the Atmel AHB DMA Controller, 13dc78baa2SNicolas Ferre * 14dc78baa2SNicolas Ferre * The driver has currently been tested with the Atmel AT91SAM9RL 15dc78baa2SNicolas Ferre * and AT91SAM9G45 series. 16dc78baa2SNicolas Ferre */ 17dc78baa2SNicolas Ferre 18dc78baa2SNicolas Ferre #include <linux/clk.h> 19dc78baa2SNicolas Ferre #include <linux/dmaengine.h> 20dc78baa2SNicolas Ferre #include <linux/dma-mapping.h> 21dc78baa2SNicolas Ferre #include <linux/dmapool.h> 22dc78baa2SNicolas Ferre #include <linux/interrupt.h> 23dc78baa2SNicolas Ferre #include <linux/module.h> 24dc78baa2SNicolas Ferre #include <linux/platform_device.h> 255a0e3ad6STejun Heo #include <linux/slab.h> 26c5115953SNicolas Ferre #include <linux/of.h> 27c5115953SNicolas Ferre #include <linux/of_device.h> 28dc78baa2SNicolas Ferre 29dc78baa2SNicolas Ferre #include "at_hdmac_regs.h" 30d2ebfb33SRussell King - ARM Linux #include "dmaengine.h" 31dc78baa2SNicolas Ferre 32dc78baa2SNicolas Ferre /* 33dc78baa2SNicolas Ferre * Glossary 34dc78baa2SNicolas Ferre * -------- 35dc78baa2SNicolas Ferre * 36dc78baa2SNicolas Ferre * at_hdmac : Name of the ATmel AHB DMA Controller 37dc78baa2SNicolas Ferre * at_dma_ / atdma : ATmel DMA controller entity related 38dc78baa2SNicolas Ferre * atc_ / atchan : ATmel DMA Channel entity related 39dc78baa2SNicolas Ferre */ 40dc78baa2SNicolas Ferre 41dc78baa2SNicolas Ferre #define ATC_DEFAULT_CFG (ATC_FIFOCFG_HALFFIFO) 42dc78baa2SNicolas Ferre #define ATC_DEFAULT_CTRLA (0) 43ae14d4b5SNicolas Ferre #define ATC_DEFAULT_CTRLB (ATC_SIF(AT_DMA_MEM_IF) \ 44ae14d4b5SNicolas Ferre |ATC_DIF(AT_DMA_MEM_IF)) 45dc78baa2SNicolas Ferre 46dc78baa2SNicolas Ferre /* 47dc78baa2SNicolas Ferre * Initial number of descriptors to allocate for each channel. This could 48dc78baa2SNicolas Ferre * be increased during dma usage. 49dc78baa2SNicolas Ferre */ 50dc78baa2SNicolas Ferre static unsigned int init_nr_desc_per_channel = 64; 51dc78baa2SNicolas Ferre module_param(init_nr_desc_per_channel, uint, 0644); 52dc78baa2SNicolas Ferre MODULE_PARM_DESC(init_nr_desc_per_channel, 53dc78baa2SNicolas Ferre "initial descriptors per channel (default: 64)"); 54dc78baa2SNicolas Ferre 55dc78baa2SNicolas Ferre 56dc78baa2SNicolas Ferre /* prototypes */ 57dc78baa2SNicolas Ferre static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx); 58dc78baa2SNicolas Ferre 59dc78baa2SNicolas Ferre 60dc78baa2SNicolas Ferre /*----------------------------------------------------------------------*/ 61dc78baa2SNicolas Ferre 62dc78baa2SNicolas Ferre static struct at_desc *atc_first_active(struct at_dma_chan *atchan) 63dc78baa2SNicolas Ferre { 64dc78baa2SNicolas Ferre return list_first_entry(&atchan->active_list, 65dc78baa2SNicolas Ferre struct at_desc, desc_node); 66dc78baa2SNicolas Ferre } 67dc78baa2SNicolas Ferre 68dc78baa2SNicolas Ferre static struct at_desc *atc_first_queued(struct at_dma_chan *atchan) 69dc78baa2SNicolas Ferre { 70dc78baa2SNicolas Ferre return list_first_entry(&atchan->queue, 71dc78baa2SNicolas Ferre struct at_desc, desc_node); 72dc78baa2SNicolas Ferre } 73dc78baa2SNicolas Ferre 74dc78baa2SNicolas Ferre /** 75421f91d2SUwe Kleine-König * atc_alloc_descriptor - allocate and return an initialized descriptor 76dc78baa2SNicolas Ferre * @chan: the channel to allocate descriptors for 77dc78baa2SNicolas Ferre * @gfp_flags: GFP allocation flags 78dc78baa2SNicolas Ferre * 79dc78baa2SNicolas Ferre * Note: The ack-bit is positioned in the descriptor flag at creation time 80dc78baa2SNicolas Ferre * to make initial allocation more convenient. This bit will be cleared 81dc78baa2SNicolas Ferre * and control will be given to client at usage time (during 82dc78baa2SNicolas Ferre * preparation functions). 83dc78baa2SNicolas Ferre */ 84dc78baa2SNicolas Ferre static struct at_desc *atc_alloc_descriptor(struct dma_chan *chan, 85dc78baa2SNicolas Ferre gfp_t gfp_flags) 86dc78baa2SNicolas Ferre { 87dc78baa2SNicolas Ferre struct at_desc *desc = NULL; 88dc78baa2SNicolas Ferre struct at_dma *atdma = to_at_dma(chan->device); 89dc78baa2SNicolas Ferre dma_addr_t phys; 90dc78baa2SNicolas Ferre 91dc78baa2SNicolas Ferre desc = dma_pool_alloc(atdma->dma_desc_pool, gfp_flags, &phys); 92dc78baa2SNicolas Ferre if (desc) { 93dc78baa2SNicolas Ferre memset(desc, 0, sizeof(struct at_desc)); 94285a3c71SDan Williams INIT_LIST_HEAD(&desc->tx_list); 95dc78baa2SNicolas Ferre dma_async_tx_descriptor_init(&desc->txd, chan); 96dc78baa2SNicolas Ferre /* txd.flags will be overwritten in prep functions */ 97dc78baa2SNicolas Ferre desc->txd.flags = DMA_CTRL_ACK; 98dc78baa2SNicolas Ferre desc->txd.tx_submit = atc_tx_submit; 99dc78baa2SNicolas Ferre desc->txd.phys = phys; 100dc78baa2SNicolas Ferre } 101dc78baa2SNicolas Ferre 102dc78baa2SNicolas Ferre return desc; 103dc78baa2SNicolas Ferre } 104dc78baa2SNicolas Ferre 105dc78baa2SNicolas Ferre /** 106af901ca1SAndré Goddard Rosa * atc_desc_get - get an unused descriptor from free_list 107dc78baa2SNicolas Ferre * @atchan: channel we want a new descriptor for 108dc78baa2SNicolas Ferre */ 109dc78baa2SNicolas Ferre static struct at_desc *atc_desc_get(struct at_dma_chan *atchan) 110dc78baa2SNicolas Ferre { 111dc78baa2SNicolas Ferre struct at_desc *desc, *_desc; 112dc78baa2SNicolas Ferre struct at_desc *ret = NULL; 113d8cb04b0SNicolas Ferre unsigned long flags; 114dc78baa2SNicolas Ferre unsigned int i = 0; 115dc78baa2SNicolas Ferre LIST_HEAD(tmp_list); 116dc78baa2SNicolas Ferre 117d8cb04b0SNicolas Ferre spin_lock_irqsave(&atchan->lock, flags); 118dc78baa2SNicolas Ferre list_for_each_entry_safe(desc, _desc, &atchan->free_list, desc_node) { 119dc78baa2SNicolas Ferre i++; 120dc78baa2SNicolas Ferre if (async_tx_test_ack(&desc->txd)) { 121dc78baa2SNicolas Ferre list_del(&desc->desc_node); 122dc78baa2SNicolas Ferre ret = desc; 123dc78baa2SNicolas Ferre break; 124dc78baa2SNicolas Ferre } 125dc78baa2SNicolas Ferre dev_dbg(chan2dev(&atchan->chan_common), 126dc78baa2SNicolas Ferre "desc %p not ACKed\n", desc); 127dc78baa2SNicolas Ferre } 128d8cb04b0SNicolas Ferre spin_unlock_irqrestore(&atchan->lock, flags); 129dc78baa2SNicolas Ferre dev_vdbg(chan2dev(&atchan->chan_common), 130dc78baa2SNicolas Ferre "scanned %u descriptors on freelist\n", i); 131dc78baa2SNicolas Ferre 132dc78baa2SNicolas Ferre /* no more descriptor available in initial pool: create one more */ 133dc78baa2SNicolas Ferre if (!ret) { 134dc78baa2SNicolas Ferre ret = atc_alloc_descriptor(&atchan->chan_common, GFP_ATOMIC); 135dc78baa2SNicolas Ferre if (ret) { 136d8cb04b0SNicolas Ferre spin_lock_irqsave(&atchan->lock, flags); 137dc78baa2SNicolas Ferre atchan->descs_allocated++; 138d8cb04b0SNicolas Ferre spin_unlock_irqrestore(&atchan->lock, flags); 139dc78baa2SNicolas Ferre } else { 140dc78baa2SNicolas Ferre dev_err(chan2dev(&atchan->chan_common), 141dc78baa2SNicolas Ferre "not enough descriptors available\n"); 142dc78baa2SNicolas Ferre } 143dc78baa2SNicolas Ferre } 144dc78baa2SNicolas Ferre 145dc78baa2SNicolas Ferre return ret; 146dc78baa2SNicolas Ferre } 147dc78baa2SNicolas Ferre 148dc78baa2SNicolas Ferre /** 149dc78baa2SNicolas Ferre * atc_desc_put - move a descriptor, including any children, to the free list 150dc78baa2SNicolas Ferre * @atchan: channel we work on 151dc78baa2SNicolas Ferre * @desc: descriptor, at the head of a chain, to move to free list 152dc78baa2SNicolas Ferre */ 153dc78baa2SNicolas Ferre static void atc_desc_put(struct at_dma_chan *atchan, struct at_desc *desc) 154dc78baa2SNicolas Ferre { 155dc78baa2SNicolas Ferre if (desc) { 156dc78baa2SNicolas Ferre struct at_desc *child; 157d8cb04b0SNicolas Ferre unsigned long flags; 158dc78baa2SNicolas Ferre 159d8cb04b0SNicolas Ferre spin_lock_irqsave(&atchan->lock, flags); 160285a3c71SDan Williams list_for_each_entry(child, &desc->tx_list, desc_node) 161dc78baa2SNicolas Ferre dev_vdbg(chan2dev(&atchan->chan_common), 162dc78baa2SNicolas Ferre "moving child desc %p to freelist\n", 163dc78baa2SNicolas Ferre child); 164285a3c71SDan Williams list_splice_init(&desc->tx_list, &atchan->free_list); 165dc78baa2SNicolas Ferre dev_vdbg(chan2dev(&atchan->chan_common), 166dc78baa2SNicolas Ferre "moving desc %p to freelist\n", desc); 167dc78baa2SNicolas Ferre list_add(&desc->desc_node, &atchan->free_list); 168d8cb04b0SNicolas Ferre spin_unlock_irqrestore(&atchan->lock, flags); 169dc78baa2SNicolas Ferre } 170dc78baa2SNicolas Ferre } 171dc78baa2SNicolas Ferre 172dc78baa2SNicolas Ferre /** 17353830cc7SNicolas Ferre * atc_desc_chain - build chain adding a descripor 17453830cc7SNicolas Ferre * @first: address of first descripor of the chain 17553830cc7SNicolas Ferre * @prev: address of previous descripor of the chain 17653830cc7SNicolas Ferre * @desc: descriptor to queue 17753830cc7SNicolas Ferre * 17853830cc7SNicolas Ferre * Called from prep_* functions 17953830cc7SNicolas Ferre */ 18053830cc7SNicolas Ferre static void atc_desc_chain(struct at_desc **first, struct at_desc **prev, 18153830cc7SNicolas Ferre struct at_desc *desc) 18253830cc7SNicolas Ferre { 18353830cc7SNicolas Ferre if (!(*first)) { 18453830cc7SNicolas Ferre *first = desc; 18553830cc7SNicolas Ferre } else { 18653830cc7SNicolas Ferre /* inform the HW lli about chaining */ 18753830cc7SNicolas Ferre (*prev)->lli.dscr = desc->txd.phys; 18853830cc7SNicolas Ferre /* insert the link descriptor to the LD ring */ 18953830cc7SNicolas Ferre list_add_tail(&desc->desc_node, 19053830cc7SNicolas Ferre &(*first)->tx_list); 19153830cc7SNicolas Ferre } 19253830cc7SNicolas Ferre *prev = desc; 19353830cc7SNicolas Ferre } 19453830cc7SNicolas Ferre 19553830cc7SNicolas Ferre /** 196dc78baa2SNicolas Ferre * atc_assign_cookie - compute and assign new cookie 197dc78baa2SNicolas Ferre * @atchan: channel we work on 19825985edcSLucas De Marchi * @desc: descriptor to assign cookie for 199dc78baa2SNicolas Ferre * 200dc78baa2SNicolas Ferre * Called with atchan->lock held and bh disabled 201dc78baa2SNicolas Ferre */ 202dc78baa2SNicolas Ferre static dma_cookie_t 203dc78baa2SNicolas Ferre atc_assign_cookie(struct at_dma_chan *atchan, struct at_desc *desc) 204dc78baa2SNicolas Ferre { 205dc78baa2SNicolas Ferre dma_cookie_t cookie = atchan->chan_common.cookie; 206dc78baa2SNicolas Ferre 207dc78baa2SNicolas Ferre if (++cookie < 0) 208dc78baa2SNicolas Ferre cookie = 1; 209dc78baa2SNicolas Ferre 210dc78baa2SNicolas Ferre atchan->chan_common.cookie = cookie; 211dc78baa2SNicolas Ferre desc->txd.cookie = cookie; 212dc78baa2SNicolas Ferre 213dc78baa2SNicolas Ferre return cookie; 214dc78baa2SNicolas Ferre } 215dc78baa2SNicolas Ferre 216dc78baa2SNicolas Ferre /** 217dc78baa2SNicolas Ferre * atc_dostart - starts the DMA engine for real 218dc78baa2SNicolas Ferre * @atchan: the channel we want to start 219dc78baa2SNicolas Ferre * @first: first descriptor in the list we want to begin with 220dc78baa2SNicolas Ferre * 221dc78baa2SNicolas Ferre * Called with atchan->lock held and bh disabled 222dc78baa2SNicolas Ferre */ 223dc78baa2SNicolas Ferre static void atc_dostart(struct at_dma_chan *atchan, struct at_desc *first) 224dc78baa2SNicolas Ferre { 225dc78baa2SNicolas Ferre struct at_dma *atdma = to_at_dma(atchan->chan_common.device); 226dc78baa2SNicolas Ferre 227dc78baa2SNicolas Ferre /* ASSERT: channel is idle */ 228dc78baa2SNicolas Ferre if (atc_chan_is_enabled(atchan)) { 229dc78baa2SNicolas Ferre dev_err(chan2dev(&atchan->chan_common), 230dc78baa2SNicolas Ferre "BUG: Attempted to start non-idle channel\n"); 231dc78baa2SNicolas Ferre dev_err(chan2dev(&atchan->chan_common), 232dc78baa2SNicolas Ferre " channel: s0x%x d0x%x ctrl0x%x:0x%x l0x%x\n", 233dc78baa2SNicolas Ferre channel_readl(atchan, SADDR), 234dc78baa2SNicolas Ferre channel_readl(atchan, DADDR), 235dc78baa2SNicolas Ferre channel_readl(atchan, CTRLA), 236dc78baa2SNicolas Ferre channel_readl(atchan, CTRLB), 237dc78baa2SNicolas Ferre channel_readl(atchan, DSCR)); 238dc78baa2SNicolas Ferre 239dc78baa2SNicolas Ferre /* The tasklet will hopefully advance the queue... */ 240dc78baa2SNicolas Ferre return; 241dc78baa2SNicolas Ferre } 242dc78baa2SNicolas Ferre 243dc78baa2SNicolas Ferre vdbg_dump_regs(atchan); 244dc78baa2SNicolas Ferre 245dc78baa2SNicolas Ferre /* clear any pending interrupt */ 246dc78baa2SNicolas Ferre while (dma_readl(atdma, EBCISR)) 247dc78baa2SNicolas Ferre cpu_relax(); 248dc78baa2SNicolas Ferre 249dc78baa2SNicolas Ferre channel_writel(atchan, SADDR, 0); 250dc78baa2SNicolas Ferre channel_writel(atchan, DADDR, 0); 251dc78baa2SNicolas Ferre channel_writel(atchan, CTRLA, 0); 252dc78baa2SNicolas Ferre channel_writel(atchan, CTRLB, 0); 253dc78baa2SNicolas Ferre channel_writel(atchan, DSCR, first->txd.phys); 254dc78baa2SNicolas Ferre dma_writel(atdma, CHER, atchan->mask); 255dc78baa2SNicolas Ferre 256dc78baa2SNicolas Ferre vdbg_dump_regs(atchan); 257dc78baa2SNicolas Ferre } 258dc78baa2SNicolas Ferre 259dc78baa2SNicolas Ferre /** 260dc78baa2SNicolas Ferre * atc_chain_complete - finish work for one transaction chain 261dc78baa2SNicolas Ferre * @atchan: channel we work on 262dc78baa2SNicolas Ferre * @desc: descriptor at the head of the chain we want do complete 263dc78baa2SNicolas Ferre * 264dc78baa2SNicolas Ferre * Called with atchan->lock held and bh disabled */ 265dc78baa2SNicolas Ferre static void 266dc78baa2SNicolas Ferre atc_chain_complete(struct at_dma_chan *atchan, struct at_desc *desc) 267dc78baa2SNicolas Ferre { 268dc78baa2SNicolas Ferre struct dma_async_tx_descriptor *txd = &desc->txd; 269dc78baa2SNicolas Ferre 270dc78baa2SNicolas Ferre dev_vdbg(chan2dev(&atchan->chan_common), 271dc78baa2SNicolas Ferre "descriptor %u complete\n", txd->cookie); 272dc78baa2SNicolas Ferre 2734d4e58deSRussell King - ARM Linux atchan->chan_common.completed_cookie = txd->cookie; 274dc78baa2SNicolas Ferre 275dc78baa2SNicolas Ferre /* move children to free_list */ 276285a3c71SDan Williams list_splice_init(&desc->tx_list, &atchan->free_list); 277dc78baa2SNicolas Ferre /* move myself to free_list */ 278dc78baa2SNicolas Ferre list_move(&desc->desc_node, &atchan->free_list); 279dc78baa2SNicolas Ferre 280ebcf9b80SNicolas Ferre /* unmap dma addresses (not on slave channels) */ 281657a77faSAtsushi Nemoto if (!atchan->chan_common.private) { 282657a77faSAtsushi Nemoto struct device *parent = chan2parent(&atchan->chan_common); 283dc78baa2SNicolas Ferre if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) { 284dc78baa2SNicolas Ferre if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE) 285657a77faSAtsushi Nemoto dma_unmap_single(parent, 286dc78baa2SNicolas Ferre desc->lli.daddr, 287dc78baa2SNicolas Ferre desc->len, DMA_FROM_DEVICE); 288dc78baa2SNicolas Ferre else 289657a77faSAtsushi Nemoto dma_unmap_page(parent, 290dc78baa2SNicolas Ferre desc->lli.daddr, 291dc78baa2SNicolas Ferre desc->len, DMA_FROM_DEVICE); 292dc78baa2SNicolas Ferre } 293dc78baa2SNicolas Ferre if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) { 294dc78baa2SNicolas Ferre if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE) 295657a77faSAtsushi Nemoto dma_unmap_single(parent, 296dc78baa2SNicolas Ferre desc->lli.saddr, 297dc78baa2SNicolas Ferre desc->len, DMA_TO_DEVICE); 298dc78baa2SNicolas Ferre else 299657a77faSAtsushi Nemoto dma_unmap_page(parent, 300dc78baa2SNicolas Ferre desc->lli.saddr, 301dc78baa2SNicolas Ferre desc->len, DMA_TO_DEVICE); 302dc78baa2SNicolas Ferre } 303657a77faSAtsushi Nemoto } 304dc78baa2SNicolas Ferre 30553830cc7SNicolas Ferre /* for cyclic transfers, 30653830cc7SNicolas Ferre * no need to replay callback function while stopping */ 3073c477482SNicolas Ferre if (!atc_chan_is_cyclic(atchan)) { 30853830cc7SNicolas Ferre dma_async_tx_callback callback = txd->callback; 30953830cc7SNicolas Ferre void *param = txd->callback_param; 31053830cc7SNicolas Ferre 311dc78baa2SNicolas Ferre /* 312dc78baa2SNicolas Ferre * The API requires that no submissions are done from a 313dc78baa2SNicolas Ferre * callback, so we don't need to drop the lock here 314dc78baa2SNicolas Ferre */ 315dc78baa2SNicolas Ferre if (callback) 316dc78baa2SNicolas Ferre callback(param); 31753830cc7SNicolas Ferre } 318dc78baa2SNicolas Ferre 319dc78baa2SNicolas Ferre dma_run_dependencies(txd); 320dc78baa2SNicolas Ferre } 321dc78baa2SNicolas Ferre 322dc78baa2SNicolas Ferre /** 323dc78baa2SNicolas Ferre * atc_complete_all - finish work for all transactions 324dc78baa2SNicolas Ferre * @atchan: channel to complete transactions for 325dc78baa2SNicolas Ferre * 326dc78baa2SNicolas Ferre * Eventually submit queued descriptors if any 327dc78baa2SNicolas Ferre * 328dc78baa2SNicolas Ferre * Assume channel is idle while calling this function 329dc78baa2SNicolas Ferre * Called with atchan->lock held and bh disabled 330dc78baa2SNicolas Ferre */ 331dc78baa2SNicolas Ferre static void atc_complete_all(struct at_dma_chan *atchan) 332dc78baa2SNicolas Ferre { 333dc78baa2SNicolas Ferre struct at_desc *desc, *_desc; 334dc78baa2SNicolas Ferre LIST_HEAD(list); 335dc78baa2SNicolas Ferre 336dc78baa2SNicolas Ferre dev_vdbg(chan2dev(&atchan->chan_common), "complete all\n"); 337dc78baa2SNicolas Ferre 338dc78baa2SNicolas Ferre BUG_ON(atc_chan_is_enabled(atchan)); 339dc78baa2SNicolas Ferre 340dc78baa2SNicolas Ferre /* 341dc78baa2SNicolas Ferre * Submit queued descriptors ASAP, i.e. before we go through 342dc78baa2SNicolas Ferre * the completed ones. 343dc78baa2SNicolas Ferre */ 344dc78baa2SNicolas Ferre if (!list_empty(&atchan->queue)) 345dc78baa2SNicolas Ferre atc_dostart(atchan, atc_first_queued(atchan)); 346dc78baa2SNicolas Ferre /* empty active_list now it is completed */ 347dc78baa2SNicolas Ferre list_splice_init(&atchan->active_list, &list); 348dc78baa2SNicolas Ferre /* empty queue list by moving descriptors (if any) to active_list */ 349dc78baa2SNicolas Ferre list_splice_init(&atchan->queue, &atchan->active_list); 350dc78baa2SNicolas Ferre 351dc78baa2SNicolas Ferre list_for_each_entry_safe(desc, _desc, &list, desc_node) 352dc78baa2SNicolas Ferre atc_chain_complete(atchan, desc); 353dc78baa2SNicolas Ferre } 354dc78baa2SNicolas Ferre 355dc78baa2SNicolas Ferre /** 356dc78baa2SNicolas Ferre * atc_cleanup_descriptors - cleanup up finished descriptors in active_list 357dc78baa2SNicolas Ferre * @atchan: channel to be cleaned up 358dc78baa2SNicolas Ferre * 359dc78baa2SNicolas Ferre * Called with atchan->lock held and bh disabled 360dc78baa2SNicolas Ferre */ 361dc78baa2SNicolas Ferre static void atc_cleanup_descriptors(struct at_dma_chan *atchan) 362dc78baa2SNicolas Ferre { 363dc78baa2SNicolas Ferre struct at_desc *desc, *_desc; 364dc78baa2SNicolas Ferre struct at_desc *child; 365dc78baa2SNicolas Ferre 366dc78baa2SNicolas Ferre dev_vdbg(chan2dev(&atchan->chan_common), "cleanup descriptors\n"); 367dc78baa2SNicolas Ferre 368dc78baa2SNicolas Ferre list_for_each_entry_safe(desc, _desc, &atchan->active_list, desc_node) { 369dc78baa2SNicolas Ferre if (!(desc->lli.ctrla & ATC_DONE)) 370dc78baa2SNicolas Ferre /* This one is currently in progress */ 371dc78baa2SNicolas Ferre return; 372dc78baa2SNicolas Ferre 373285a3c71SDan Williams list_for_each_entry(child, &desc->tx_list, desc_node) 374dc78baa2SNicolas Ferre if (!(child->lli.ctrla & ATC_DONE)) 375dc78baa2SNicolas Ferre /* Currently in progress */ 376dc78baa2SNicolas Ferre return; 377dc78baa2SNicolas Ferre 378dc78baa2SNicolas Ferre /* 379dc78baa2SNicolas Ferre * No descriptors so far seem to be in progress, i.e. 380dc78baa2SNicolas Ferre * this chain must be done. 381dc78baa2SNicolas Ferre */ 382dc78baa2SNicolas Ferre atc_chain_complete(atchan, desc); 383dc78baa2SNicolas Ferre } 384dc78baa2SNicolas Ferre } 385dc78baa2SNicolas Ferre 386dc78baa2SNicolas Ferre /** 387dc78baa2SNicolas Ferre * atc_advance_work - at the end of a transaction, move forward 388dc78baa2SNicolas Ferre * @atchan: channel where the transaction ended 389dc78baa2SNicolas Ferre * 390dc78baa2SNicolas Ferre * Called with atchan->lock held and bh disabled 391dc78baa2SNicolas Ferre */ 392dc78baa2SNicolas Ferre static void atc_advance_work(struct at_dma_chan *atchan) 393dc78baa2SNicolas Ferre { 394dc78baa2SNicolas Ferre dev_vdbg(chan2dev(&atchan->chan_common), "advance_work\n"); 395dc78baa2SNicolas Ferre 396dc78baa2SNicolas Ferre if (list_empty(&atchan->active_list) || 397dc78baa2SNicolas Ferre list_is_singular(&atchan->active_list)) { 398dc78baa2SNicolas Ferre atc_complete_all(atchan); 399dc78baa2SNicolas Ferre } else { 400dc78baa2SNicolas Ferre atc_chain_complete(atchan, atc_first_active(atchan)); 401dc78baa2SNicolas Ferre /* advance work */ 402dc78baa2SNicolas Ferre atc_dostart(atchan, atc_first_active(atchan)); 403dc78baa2SNicolas Ferre } 404dc78baa2SNicolas Ferre } 405dc78baa2SNicolas Ferre 406dc78baa2SNicolas Ferre 407dc78baa2SNicolas Ferre /** 408dc78baa2SNicolas Ferre * atc_handle_error - handle errors reported by DMA controller 409dc78baa2SNicolas Ferre * @atchan: channel where error occurs 410dc78baa2SNicolas Ferre * 411dc78baa2SNicolas Ferre * Called with atchan->lock held and bh disabled 412dc78baa2SNicolas Ferre */ 413dc78baa2SNicolas Ferre static void atc_handle_error(struct at_dma_chan *atchan) 414dc78baa2SNicolas Ferre { 415dc78baa2SNicolas Ferre struct at_desc *bad_desc; 416dc78baa2SNicolas Ferre struct at_desc *child; 417dc78baa2SNicolas Ferre 418dc78baa2SNicolas Ferre /* 419dc78baa2SNicolas Ferre * The descriptor currently at the head of the active list is 420dc78baa2SNicolas Ferre * broked. Since we don't have any way to report errors, we'll 421dc78baa2SNicolas Ferre * just have to scream loudly and try to carry on. 422dc78baa2SNicolas Ferre */ 423dc78baa2SNicolas Ferre bad_desc = atc_first_active(atchan); 424dc78baa2SNicolas Ferre list_del_init(&bad_desc->desc_node); 425dc78baa2SNicolas Ferre 426dc78baa2SNicolas Ferre /* As we are stopped, take advantage to push queued descriptors 427dc78baa2SNicolas Ferre * in active_list */ 428dc78baa2SNicolas Ferre list_splice_init(&atchan->queue, atchan->active_list.prev); 429dc78baa2SNicolas Ferre 430dc78baa2SNicolas Ferre /* Try to restart the controller */ 431dc78baa2SNicolas Ferre if (!list_empty(&atchan->active_list)) 432dc78baa2SNicolas Ferre atc_dostart(atchan, atc_first_active(atchan)); 433dc78baa2SNicolas Ferre 434dc78baa2SNicolas Ferre /* 435dc78baa2SNicolas Ferre * KERN_CRITICAL may seem harsh, but since this only happens 436dc78baa2SNicolas Ferre * when someone submits a bad physical address in a 437dc78baa2SNicolas Ferre * descriptor, we should consider ourselves lucky that the 438dc78baa2SNicolas Ferre * controller flagged an error instead of scribbling over 439dc78baa2SNicolas Ferre * random memory locations. 440dc78baa2SNicolas Ferre */ 441dc78baa2SNicolas Ferre dev_crit(chan2dev(&atchan->chan_common), 442dc78baa2SNicolas Ferre "Bad descriptor submitted for DMA!\n"); 443dc78baa2SNicolas Ferre dev_crit(chan2dev(&atchan->chan_common), 444dc78baa2SNicolas Ferre " cookie: %d\n", bad_desc->txd.cookie); 445dc78baa2SNicolas Ferre atc_dump_lli(atchan, &bad_desc->lli); 446285a3c71SDan Williams list_for_each_entry(child, &bad_desc->tx_list, desc_node) 447dc78baa2SNicolas Ferre atc_dump_lli(atchan, &child->lli); 448dc78baa2SNicolas Ferre 449dc78baa2SNicolas Ferre /* Pretend the descriptor completed successfully */ 450dc78baa2SNicolas Ferre atc_chain_complete(atchan, bad_desc); 451dc78baa2SNicolas Ferre } 452dc78baa2SNicolas Ferre 45353830cc7SNicolas Ferre /** 45453830cc7SNicolas Ferre * atc_handle_cyclic - at the end of a period, run callback function 45553830cc7SNicolas Ferre * @atchan: channel used for cyclic operations 45653830cc7SNicolas Ferre * 45753830cc7SNicolas Ferre * Called with atchan->lock held and bh disabled 45853830cc7SNicolas Ferre */ 45953830cc7SNicolas Ferre static void atc_handle_cyclic(struct at_dma_chan *atchan) 46053830cc7SNicolas Ferre { 46153830cc7SNicolas Ferre struct at_desc *first = atc_first_active(atchan); 46253830cc7SNicolas Ferre struct dma_async_tx_descriptor *txd = &first->txd; 46353830cc7SNicolas Ferre dma_async_tx_callback callback = txd->callback; 46453830cc7SNicolas Ferre void *param = txd->callback_param; 46553830cc7SNicolas Ferre 46653830cc7SNicolas Ferre dev_vdbg(chan2dev(&atchan->chan_common), 46753830cc7SNicolas Ferre "new cyclic period llp 0x%08x\n", 46853830cc7SNicolas Ferre channel_readl(atchan, DSCR)); 46953830cc7SNicolas Ferre 47053830cc7SNicolas Ferre if (callback) 47153830cc7SNicolas Ferre callback(param); 47253830cc7SNicolas Ferre } 473dc78baa2SNicolas Ferre 474dc78baa2SNicolas Ferre /*-- IRQ & Tasklet ---------------------------------------------------*/ 475dc78baa2SNicolas Ferre 476dc78baa2SNicolas Ferre static void atc_tasklet(unsigned long data) 477dc78baa2SNicolas Ferre { 478dc78baa2SNicolas Ferre struct at_dma_chan *atchan = (struct at_dma_chan *)data; 479d8cb04b0SNicolas Ferre unsigned long flags; 480dc78baa2SNicolas Ferre 481d8cb04b0SNicolas Ferre spin_lock_irqsave(&atchan->lock, flags); 48253830cc7SNicolas Ferre if (test_and_clear_bit(ATC_IS_ERROR, &atchan->status)) 483dc78baa2SNicolas Ferre atc_handle_error(atchan); 4843c477482SNicolas Ferre else if (atc_chan_is_cyclic(atchan)) 48553830cc7SNicolas Ferre atc_handle_cyclic(atchan); 486dc78baa2SNicolas Ferre else 487dc78baa2SNicolas Ferre atc_advance_work(atchan); 488dc78baa2SNicolas Ferre 489d8cb04b0SNicolas Ferre spin_unlock_irqrestore(&atchan->lock, flags); 490dc78baa2SNicolas Ferre } 491dc78baa2SNicolas Ferre 492dc78baa2SNicolas Ferre static irqreturn_t at_dma_interrupt(int irq, void *dev_id) 493dc78baa2SNicolas Ferre { 494dc78baa2SNicolas Ferre struct at_dma *atdma = (struct at_dma *)dev_id; 495dc78baa2SNicolas Ferre struct at_dma_chan *atchan; 496dc78baa2SNicolas Ferre int i; 497dc78baa2SNicolas Ferre u32 status, pending, imr; 498dc78baa2SNicolas Ferre int ret = IRQ_NONE; 499dc78baa2SNicolas Ferre 500dc78baa2SNicolas Ferre do { 501dc78baa2SNicolas Ferre imr = dma_readl(atdma, EBCIMR); 502dc78baa2SNicolas Ferre status = dma_readl(atdma, EBCISR); 503dc78baa2SNicolas Ferre pending = status & imr; 504dc78baa2SNicolas Ferre 505dc78baa2SNicolas Ferre if (!pending) 506dc78baa2SNicolas Ferre break; 507dc78baa2SNicolas Ferre 508dc78baa2SNicolas Ferre dev_vdbg(atdma->dma_common.dev, 509dc78baa2SNicolas Ferre "interrupt: status = 0x%08x, 0x%08x, 0x%08x\n", 510dc78baa2SNicolas Ferre status, imr, pending); 511dc78baa2SNicolas Ferre 512dc78baa2SNicolas Ferre for (i = 0; i < atdma->dma_common.chancnt; i++) { 513dc78baa2SNicolas Ferre atchan = &atdma->chan[i]; 5149b3aa589SNicolas Ferre if (pending & (AT_DMA_BTC(i) | AT_DMA_ERR(i))) { 515dc78baa2SNicolas Ferre if (pending & AT_DMA_ERR(i)) { 516dc78baa2SNicolas Ferre /* Disable channel on AHB error */ 51723b5e3adSNicolas Ferre dma_writel(atdma, CHDR, 51823b5e3adSNicolas Ferre AT_DMA_RES(i) | atchan->mask); 519dc78baa2SNicolas Ferre /* Give information to tasklet */ 52053830cc7SNicolas Ferre set_bit(ATC_IS_ERROR, &atchan->status); 521dc78baa2SNicolas Ferre } 522dc78baa2SNicolas Ferre tasklet_schedule(&atchan->tasklet); 523dc78baa2SNicolas Ferre ret = IRQ_HANDLED; 524dc78baa2SNicolas Ferre } 525dc78baa2SNicolas Ferre } 526dc78baa2SNicolas Ferre 527dc78baa2SNicolas Ferre } while (pending); 528dc78baa2SNicolas Ferre 529dc78baa2SNicolas Ferre return ret; 530dc78baa2SNicolas Ferre } 531dc78baa2SNicolas Ferre 532dc78baa2SNicolas Ferre 533dc78baa2SNicolas Ferre /*-- DMA Engine API --------------------------------------------------*/ 534dc78baa2SNicolas Ferre 535dc78baa2SNicolas Ferre /** 536dc78baa2SNicolas Ferre * atc_tx_submit - set the prepared descriptor(s) to be executed by the engine 537dc78baa2SNicolas Ferre * @desc: descriptor at the head of the transaction chain 538dc78baa2SNicolas Ferre * 539dc78baa2SNicolas Ferre * Queue chain if DMA engine is working already 540dc78baa2SNicolas Ferre * 541dc78baa2SNicolas Ferre * Cookie increment and adding to active_list or queue must be atomic 542dc78baa2SNicolas Ferre */ 543dc78baa2SNicolas Ferre static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx) 544dc78baa2SNicolas Ferre { 545dc78baa2SNicolas Ferre struct at_desc *desc = txd_to_at_desc(tx); 546dc78baa2SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(tx->chan); 547dc78baa2SNicolas Ferre dma_cookie_t cookie; 548d8cb04b0SNicolas Ferre unsigned long flags; 549dc78baa2SNicolas Ferre 550d8cb04b0SNicolas Ferre spin_lock_irqsave(&atchan->lock, flags); 551dc78baa2SNicolas Ferre cookie = atc_assign_cookie(atchan, desc); 552dc78baa2SNicolas Ferre 553dc78baa2SNicolas Ferre if (list_empty(&atchan->active_list)) { 554dc78baa2SNicolas Ferre dev_vdbg(chan2dev(tx->chan), "tx_submit: started %u\n", 555dc78baa2SNicolas Ferre desc->txd.cookie); 556dc78baa2SNicolas Ferre atc_dostart(atchan, desc); 557dc78baa2SNicolas Ferre list_add_tail(&desc->desc_node, &atchan->active_list); 558dc78baa2SNicolas Ferre } else { 559dc78baa2SNicolas Ferre dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u\n", 560dc78baa2SNicolas Ferre desc->txd.cookie); 561dc78baa2SNicolas Ferre list_add_tail(&desc->desc_node, &atchan->queue); 562dc78baa2SNicolas Ferre } 563dc78baa2SNicolas Ferre 564d8cb04b0SNicolas Ferre spin_unlock_irqrestore(&atchan->lock, flags); 565dc78baa2SNicolas Ferre 566dc78baa2SNicolas Ferre return cookie; 567dc78baa2SNicolas Ferre } 568dc78baa2SNicolas Ferre 569dc78baa2SNicolas Ferre /** 570dc78baa2SNicolas Ferre * atc_prep_dma_memcpy - prepare a memcpy operation 571dc78baa2SNicolas Ferre * @chan: the channel to prepare operation on 572dc78baa2SNicolas Ferre * @dest: operation virtual destination address 573dc78baa2SNicolas Ferre * @src: operation virtual source address 574dc78baa2SNicolas Ferre * @len: operation length 575dc78baa2SNicolas Ferre * @flags: tx descriptor status flags 576dc78baa2SNicolas Ferre */ 577dc78baa2SNicolas Ferre static struct dma_async_tx_descriptor * 578dc78baa2SNicolas Ferre atc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, 579dc78baa2SNicolas Ferre size_t len, unsigned long flags) 580dc78baa2SNicolas Ferre { 581dc78baa2SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 582dc78baa2SNicolas Ferre struct at_desc *desc = NULL; 583dc78baa2SNicolas Ferre struct at_desc *first = NULL; 584dc78baa2SNicolas Ferre struct at_desc *prev = NULL; 585dc78baa2SNicolas Ferre size_t xfer_count; 586dc78baa2SNicolas Ferre size_t offset; 587dc78baa2SNicolas Ferre unsigned int src_width; 588dc78baa2SNicolas Ferre unsigned int dst_width; 589dc78baa2SNicolas Ferre u32 ctrla; 590dc78baa2SNicolas Ferre u32 ctrlb; 591dc78baa2SNicolas Ferre 592dc78baa2SNicolas Ferre dev_vdbg(chan2dev(chan), "prep_dma_memcpy: d0x%x s0x%x l0x%zx f0x%lx\n", 593dc78baa2SNicolas Ferre dest, src, len, flags); 594dc78baa2SNicolas Ferre 595dc78baa2SNicolas Ferre if (unlikely(!len)) { 596dc78baa2SNicolas Ferre dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n"); 597dc78baa2SNicolas Ferre return NULL; 598dc78baa2SNicolas Ferre } 599dc78baa2SNicolas Ferre 600dc78baa2SNicolas Ferre ctrla = ATC_DEFAULT_CTRLA; 6019b3aa589SNicolas Ferre ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN 602dc78baa2SNicolas Ferre | ATC_SRC_ADDR_MODE_INCR 603dc78baa2SNicolas Ferre | ATC_DST_ADDR_MODE_INCR 604dc78baa2SNicolas Ferre | ATC_FC_MEM2MEM; 605dc78baa2SNicolas Ferre 606dc78baa2SNicolas Ferre /* 607dc78baa2SNicolas Ferre * We can be a lot more clever here, but this should take care 608dc78baa2SNicolas Ferre * of the most common optimization. 609dc78baa2SNicolas Ferre */ 610dc78baa2SNicolas Ferre if (!((src | dest | len) & 3)) { 611dc78baa2SNicolas Ferre ctrla |= ATC_SRC_WIDTH_WORD | ATC_DST_WIDTH_WORD; 612dc78baa2SNicolas Ferre src_width = dst_width = 2; 613dc78baa2SNicolas Ferre } else if (!((src | dest | len) & 1)) { 614dc78baa2SNicolas Ferre ctrla |= ATC_SRC_WIDTH_HALFWORD | ATC_DST_WIDTH_HALFWORD; 615dc78baa2SNicolas Ferre src_width = dst_width = 1; 616dc78baa2SNicolas Ferre } else { 617dc78baa2SNicolas Ferre ctrla |= ATC_SRC_WIDTH_BYTE | ATC_DST_WIDTH_BYTE; 618dc78baa2SNicolas Ferre src_width = dst_width = 0; 619dc78baa2SNicolas Ferre } 620dc78baa2SNicolas Ferre 621dc78baa2SNicolas Ferre for (offset = 0; offset < len; offset += xfer_count << src_width) { 622dc78baa2SNicolas Ferre xfer_count = min_t(size_t, (len - offset) >> src_width, 623dc78baa2SNicolas Ferre ATC_BTSIZE_MAX); 624dc78baa2SNicolas Ferre 625dc78baa2SNicolas Ferre desc = atc_desc_get(atchan); 626dc78baa2SNicolas Ferre if (!desc) 627dc78baa2SNicolas Ferre goto err_desc_get; 628dc78baa2SNicolas Ferre 629dc78baa2SNicolas Ferre desc->lli.saddr = src + offset; 630dc78baa2SNicolas Ferre desc->lli.daddr = dest + offset; 631dc78baa2SNicolas Ferre desc->lli.ctrla = ctrla | xfer_count; 632dc78baa2SNicolas Ferre desc->lli.ctrlb = ctrlb; 633dc78baa2SNicolas Ferre 634dc78baa2SNicolas Ferre desc->txd.cookie = 0; 635dc78baa2SNicolas Ferre 636e257e156SNicolas Ferre atc_desc_chain(&first, &prev, desc); 637dc78baa2SNicolas Ferre } 638dc78baa2SNicolas Ferre 639dc78baa2SNicolas Ferre /* First descriptor of the chain embedds additional information */ 640dc78baa2SNicolas Ferre first->txd.cookie = -EBUSY; 641dc78baa2SNicolas Ferre first->len = len; 642dc78baa2SNicolas Ferre 643dc78baa2SNicolas Ferre /* set end-of-link to the last link descriptor of list*/ 644dc78baa2SNicolas Ferre set_desc_eol(desc); 645dc78baa2SNicolas Ferre 646568f7f0cSNicolas Ferre first->txd.flags = flags; /* client is in control of this ack */ 647dc78baa2SNicolas Ferre 648dc78baa2SNicolas Ferre return &first->txd; 649dc78baa2SNicolas Ferre 650dc78baa2SNicolas Ferre err_desc_get: 651dc78baa2SNicolas Ferre atc_desc_put(atchan, first); 652dc78baa2SNicolas Ferre return NULL; 653dc78baa2SNicolas Ferre } 654dc78baa2SNicolas Ferre 655808347f6SNicolas Ferre 656808347f6SNicolas Ferre /** 657808347f6SNicolas Ferre * atc_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction 658808347f6SNicolas Ferre * @chan: DMA channel 659808347f6SNicolas Ferre * @sgl: scatterlist to transfer to/from 660808347f6SNicolas Ferre * @sg_len: number of entries in @scatterlist 661808347f6SNicolas Ferre * @direction: DMA direction 662808347f6SNicolas Ferre * @flags: tx descriptor status flags 663808347f6SNicolas Ferre */ 664808347f6SNicolas Ferre static struct dma_async_tx_descriptor * 665808347f6SNicolas Ferre atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, 666db8196dfSVinod Koul unsigned int sg_len, enum dma_transfer_direction direction, 667808347f6SNicolas Ferre unsigned long flags) 668808347f6SNicolas Ferre { 669808347f6SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 670808347f6SNicolas Ferre struct at_dma_slave *atslave = chan->private; 671808347f6SNicolas Ferre struct at_desc *first = NULL; 672808347f6SNicolas Ferre struct at_desc *prev = NULL; 673808347f6SNicolas Ferre u32 ctrla; 674808347f6SNicolas Ferre u32 ctrlb; 675808347f6SNicolas Ferre dma_addr_t reg; 676808347f6SNicolas Ferre unsigned int reg_width; 677808347f6SNicolas Ferre unsigned int mem_width; 678808347f6SNicolas Ferre unsigned int i; 679808347f6SNicolas Ferre struct scatterlist *sg; 680808347f6SNicolas Ferre size_t total_len = 0; 681808347f6SNicolas Ferre 682cc52a10aSNicolas Ferre dev_vdbg(chan2dev(chan), "prep_slave_sg (%d): %s f0x%lx\n", 683cc52a10aSNicolas Ferre sg_len, 684db8196dfSVinod Koul direction == DMA_MEM_TO_DEV ? "TO DEVICE" : "FROM DEVICE", 685808347f6SNicolas Ferre flags); 686808347f6SNicolas Ferre 687808347f6SNicolas Ferre if (unlikely(!atslave || !sg_len)) { 688808347f6SNicolas Ferre dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n"); 689808347f6SNicolas Ferre return NULL; 690808347f6SNicolas Ferre } 691808347f6SNicolas Ferre 692808347f6SNicolas Ferre reg_width = atslave->reg_width; 693808347f6SNicolas Ferre 694808347f6SNicolas Ferre ctrla = ATC_DEFAULT_CTRLA | atslave->ctrla; 695ae14d4b5SNicolas Ferre ctrlb = ATC_IEN; 696808347f6SNicolas Ferre 697808347f6SNicolas Ferre switch (direction) { 698db8196dfSVinod Koul case DMA_MEM_TO_DEV: 699808347f6SNicolas Ferre ctrla |= ATC_DST_WIDTH(reg_width); 700808347f6SNicolas Ferre ctrlb |= ATC_DST_ADDR_MODE_FIXED 701808347f6SNicolas Ferre | ATC_SRC_ADDR_MODE_INCR 702ae14d4b5SNicolas Ferre | ATC_FC_MEM2PER 703ae14d4b5SNicolas Ferre | ATC_SIF(AT_DMA_MEM_IF) | ATC_DIF(AT_DMA_PER_IF); 704808347f6SNicolas Ferre reg = atslave->tx_reg; 705808347f6SNicolas Ferre for_each_sg(sgl, sg, sg_len, i) { 706808347f6SNicolas Ferre struct at_desc *desc; 707808347f6SNicolas Ferre u32 len; 708808347f6SNicolas Ferre u32 mem; 709808347f6SNicolas Ferre 710808347f6SNicolas Ferre desc = atc_desc_get(atchan); 711808347f6SNicolas Ferre if (!desc) 712808347f6SNicolas Ferre goto err_desc_get; 713808347f6SNicolas Ferre 7140f70e8ceSNicolas Ferre mem = sg_dma_address(sg); 715808347f6SNicolas Ferre len = sg_dma_len(sg); 716808347f6SNicolas Ferre mem_width = 2; 717808347f6SNicolas Ferre if (unlikely(mem & 3 || len & 3)) 718808347f6SNicolas Ferre mem_width = 0; 719808347f6SNicolas Ferre 720808347f6SNicolas Ferre desc->lli.saddr = mem; 721808347f6SNicolas Ferre desc->lli.daddr = reg; 722808347f6SNicolas Ferre desc->lli.ctrla = ctrla 723808347f6SNicolas Ferre | ATC_SRC_WIDTH(mem_width) 724808347f6SNicolas Ferre | len >> mem_width; 725808347f6SNicolas Ferre desc->lli.ctrlb = ctrlb; 726808347f6SNicolas Ferre 727e257e156SNicolas Ferre atc_desc_chain(&first, &prev, desc); 728808347f6SNicolas Ferre total_len += len; 729808347f6SNicolas Ferre } 730808347f6SNicolas Ferre break; 731db8196dfSVinod Koul case DMA_DEV_TO_MEM: 732808347f6SNicolas Ferre ctrla |= ATC_SRC_WIDTH(reg_width); 733808347f6SNicolas Ferre ctrlb |= ATC_DST_ADDR_MODE_INCR 734808347f6SNicolas Ferre | ATC_SRC_ADDR_MODE_FIXED 735ae14d4b5SNicolas Ferre | ATC_FC_PER2MEM 736ae14d4b5SNicolas Ferre | ATC_SIF(AT_DMA_PER_IF) | ATC_DIF(AT_DMA_MEM_IF); 737808347f6SNicolas Ferre 738808347f6SNicolas Ferre reg = atslave->rx_reg; 739808347f6SNicolas Ferre for_each_sg(sgl, sg, sg_len, i) { 740808347f6SNicolas Ferre struct at_desc *desc; 741808347f6SNicolas Ferre u32 len; 742808347f6SNicolas Ferre u32 mem; 743808347f6SNicolas Ferre 744808347f6SNicolas Ferre desc = atc_desc_get(atchan); 745808347f6SNicolas Ferre if (!desc) 746808347f6SNicolas Ferre goto err_desc_get; 747808347f6SNicolas Ferre 7480f70e8ceSNicolas Ferre mem = sg_dma_address(sg); 749808347f6SNicolas Ferre len = sg_dma_len(sg); 750808347f6SNicolas Ferre mem_width = 2; 751808347f6SNicolas Ferre if (unlikely(mem & 3 || len & 3)) 752808347f6SNicolas Ferre mem_width = 0; 753808347f6SNicolas Ferre 754808347f6SNicolas Ferre desc->lli.saddr = reg; 755808347f6SNicolas Ferre desc->lli.daddr = mem; 756808347f6SNicolas Ferre desc->lli.ctrla = ctrla 757808347f6SNicolas Ferre | ATC_DST_WIDTH(mem_width) 75859a609d9SNicolas Ferre | len >> reg_width; 759808347f6SNicolas Ferre desc->lli.ctrlb = ctrlb; 760808347f6SNicolas Ferre 761e257e156SNicolas Ferre atc_desc_chain(&first, &prev, desc); 762808347f6SNicolas Ferre total_len += len; 763808347f6SNicolas Ferre } 764808347f6SNicolas Ferre break; 765808347f6SNicolas Ferre default: 766808347f6SNicolas Ferre return NULL; 767808347f6SNicolas Ferre } 768808347f6SNicolas Ferre 769808347f6SNicolas Ferre /* set end-of-link to the last link descriptor of list*/ 770808347f6SNicolas Ferre set_desc_eol(prev); 771808347f6SNicolas Ferre 772808347f6SNicolas Ferre /* First descriptor of the chain embedds additional information */ 773808347f6SNicolas Ferre first->txd.cookie = -EBUSY; 774808347f6SNicolas Ferre first->len = total_len; 775808347f6SNicolas Ferre 776568f7f0cSNicolas Ferre /* first link descriptor of list is responsible of flags */ 777568f7f0cSNicolas Ferre first->txd.flags = flags; /* client is in control of this ack */ 778808347f6SNicolas Ferre 779808347f6SNicolas Ferre return &first->txd; 780808347f6SNicolas Ferre 781808347f6SNicolas Ferre err_desc_get: 782808347f6SNicolas Ferre dev_err(chan2dev(chan), "not enough descriptors available\n"); 783808347f6SNicolas Ferre atc_desc_put(atchan, first); 784808347f6SNicolas Ferre return NULL; 785808347f6SNicolas Ferre } 786808347f6SNicolas Ferre 78753830cc7SNicolas Ferre /** 78853830cc7SNicolas Ferre * atc_dma_cyclic_check_values 78953830cc7SNicolas Ferre * Check for too big/unaligned periods and unaligned DMA buffer 79053830cc7SNicolas Ferre */ 79153830cc7SNicolas Ferre static int 79253830cc7SNicolas Ferre atc_dma_cyclic_check_values(unsigned int reg_width, dma_addr_t buf_addr, 793db8196dfSVinod Koul size_t period_len, enum dma_transfer_direction direction) 79453830cc7SNicolas Ferre { 79553830cc7SNicolas Ferre if (period_len > (ATC_BTSIZE_MAX << reg_width)) 79653830cc7SNicolas Ferre goto err_out; 79753830cc7SNicolas Ferre if (unlikely(period_len & ((1 << reg_width) - 1))) 79853830cc7SNicolas Ferre goto err_out; 79953830cc7SNicolas Ferre if (unlikely(buf_addr & ((1 << reg_width) - 1))) 80053830cc7SNicolas Ferre goto err_out; 801db8196dfSVinod Koul if (unlikely(!(direction & (DMA_DEV_TO_MEM | DMA_MEM_TO_DEV)))) 80253830cc7SNicolas Ferre goto err_out; 80353830cc7SNicolas Ferre 80453830cc7SNicolas Ferre return 0; 80553830cc7SNicolas Ferre 80653830cc7SNicolas Ferre err_out: 80753830cc7SNicolas Ferre return -EINVAL; 80853830cc7SNicolas Ferre } 80953830cc7SNicolas Ferre 81053830cc7SNicolas Ferre /** 81153830cc7SNicolas Ferre * atc_dma_cyclic_fill_desc - Fill one period decriptor 81253830cc7SNicolas Ferre */ 81353830cc7SNicolas Ferre static int 81453830cc7SNicolas Ferre atc_dma_cyclic_fill_desc(struct at_dma_slave *atslave, struct at_desc *desc, 81553830cc7SNicolas Ferre unsigned int period_index, dma_addr_t buf_addr, 816db8196dfSVinod Koul size_t period_len, enum dma_transfer_direction direction) 81753830cc7SNicolas Ferre { 81853830cc7SNicolas Ferre u32 ctrla; 81953830cc7SNicolas Ferre unsigned int reg_width = atslave->reg_width; 82053830cc7SNicolas Ferre 82153830cc7SNicolas Ferre /* prepare common CRTLA value */ 82253830cc7SNicolas Ferre ctrla = ATC_DEFAULT_CTRLA | atslave->ctrla 82353830cc7SNicolas Ferre | ATC_DST_WIDTH(reg_width) 82453830cc7SNicolas Ferre | ATC_SRC_WIDTH(reg_width) 82553830cc7SNicolas Ferre | period_len >> reg_width; 82653830cc7SNicolas Ferre 82753830cc7SNicolas Ferre switch (direction) { 828db8196dfSVinod Koul case DMA_MEM_TO_DEV: 82953830cc7SNicolas Ferre desc->lli.saddr = buf_addr + (period_len * period_index); 83053830cc7SNicolas Ferre desc->lli.daddr = atslave->tx_reg; 83153830cc7SNicolas Ferre desc->lli.ctrla = ctrla; 832ae14d4b5SNicolas Ferre desc->lli.ctrlb = ATC_DST_ADDR_MODE_FIXED 83353830cc7SNicolas Ferre | ATC_SRC_ADDR_MODE_INCR 834ae14d4b5SNicolas Ferre | ATC_FC_MEM2PER 835ae14d4b5SNicolas Ferre | ATC_SIF(AT_DMA_MEM_IF) 836ae14d4b5SNicolas Ferre | ATC_DIF(AT_DMA_PER_IF); 83753830cc7SNicolas Ferre break; 83853830cc7SNicolas Ferre 839db8196dfSVinod Koul case DMA_DEV_TO_MEM: 84053830cc7SNicolas Ferre desc->lli.saddr = atslave->rx_reg; 84153830cc7SNicolas Ferre desc->lli.daddr = buf_addr + (period_len * period_index); 84253830cc7SNicolas Ferre desc->lli.ctrla = ctrla; 843ae14d4b5SNicolas Ferre desc->lli.ctrlb = ATC_DST_ADDR_MODE_INCR 84453830cc7SNicolas Ferre | ATC_SRC_ADDR_MODE_FIXED 845ae14d4b5SNicolas Ferre | ATC_FC_PER2MEM 846ae14d4b5SNicolas Ferre | ATC_SIF(AT_DMA_PER_IF) 847ae14d4b5SNicolas Ferre | ATC_DIF(AT_DMA_MEM_IF); 84853830cc7SNicolas Ferre break; 84953830cc7SNicolas Ferre 85053830cc7SNicolas Ferre default: 85153830cc7SNicolas Ferre return -EINVAL; 85253830cc7SNicolas Ferre } 85353830cc7SNicolas Ferre 85453830cc7SNicolas Ferre return 0; 85553830cc7SNicolas Ferre } 85653830cc7SNicolas Ferre 85753830cc7SNicolas Ferre /** 85853830cc7SNicolas Ferre * atc_prep_dma_cyclic - prepare the cyclic DMA transfer 85953830cc7SNicolas Ferre * @chan: the DMA channel to prepare 86053830cc7SNicolas Ferre * @buf_addr: physical DMA address where the buffer starts 86153830cc7SNicolas Ferre * @buf_len: total number of bytes for the entire buffer 86253830cc7SNicolas Ferre * @period_len: number of bytes for each period 86353830cc7SNicolas Ferre * @direction: transfer direction, to or from device 86453830cc7SNicolas Ferre */ 86553830cc7SNicolas Ferre static struct dma_async_tx_descriptor * 86653830cc7SNicolas Ferre atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, 867db8196dfSVinod Koul size_t period_len, enum dma_transfer_direction direction) 86853830cc7SNicolas Ferre { 86953830cc7SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 87053830cc7SNicolas Ferre struct at_dma_slave *atslave = chan->private; 87153830cc7SNicolas Ferre struct at_desc *first = NULL; 87253830cc7SNicolas Ferre struct at_desc *prev = NULL; 87353830cc7SNicolas Ferre unsigned long was_cyclic; 87453830cc7SNicolas Ferre unsigned int periods = buf_len / period_len; 87553830cc7SNicolas Ferre unsigned int i; 87653830cc7SNicolas Ferre 87753830cc7SNicolas Ferre dev_vdbg(chan2dev(chan), "prep_dma_cyclic: %s buf@0x%08x - %d (%d/%d)\n", 878db8196dfSVinod Koul direction == DMA_MEM_TO_DEV ? "TO DEVICE" : "FROM DEVICE", 87953830cc7SNicolas Ferre buf_addr, 88053830cc7SNicolas Ferre periods, buf_len, period_len); 88153830cc7SNicolas Ferre 88253830cc7SNicolas Ferre if (unlikely(!atslave || !buf_len || !period_len)) { 88353830cc7SNicolas Ferre dev_dbg(chan2dev(chan), "prep_dma_cyclic: length is zero!\n"); 88453830cc7SNicolas Ferre return NULL; 88553830cc7SNicolas Ferre } 88653830cc7SNicolas Ferre 88753830cc7SNicolas Ferre was_cyclic = test_and_set_bit(ATC_IS_CYCLIC, &atchan->status); 88853830cc7SNicolas Ferre if (was_cyclic) { 88953830cc7SNicolas Ferre dev_dbg(chan2dev(chan), "prep_dma_cyclic: channel in use!\n"); 89053830cc7SNicolas Ferre return NULL; 89153830cc7SNicolas Ferre } 89253830cc7SNicolas Ferre 89353830cc7SNicolas Ferre /* Check for too big/unaligned periods and unaligned DMA buffer */ 89453830cc7SNicolas Ferre if (atc_dma_cyclic_check_values(atslave->reg_width, buf_addr, 89553830cc7SNicolas Ferre period_len, direction)) 89653830cc7SNicolas Ferre goto err_out; 89753830cc7SNicolas Ferre 89853830cc7SNicolas Ferre /* build cyclic linked list */ 89953830cc7SNicolas Ferre for (i = 0; i < periods; i++) { 90053830cc7SNicolas Ferre struct at_desc *desc; 90153830cc7SNicolas Ferre 90253830cc7SNicolas Ferre desc = atc_desc_get(atchan); 90353830cc7SNicolas Ferre if (!desc) 90453830cc7SNicolas Ferre goto err_desc_get; 90553830cc7SNicolas Ferre 90653830cc7SNicolas Ferre if (atc_dma_cyclic_fill_desc(atslave, desc, i, buf_addr, 90753830cc7SNicolas Ferre period_len, direction)) 90853830cc7SNicolas Ferre goto err_desc_get; 90953830cc7SNicolas Ferre 91053830cc7SNicolas Ferre atc_desc_chain(&first, &prev, desc); 91153830cc7SNicolas Ferre } 91253830cc7SNicolas Ferre 91353830cc7SNicolas Ferre /* lets make a cyclic list */ 91453830cc7SNicolas Ferre prev->lli.dscr = first->txd.phys; 91553830cc7SNicolas Ferre 91653830cc7SNicolas Ferre /* First descriptor of the chain embedds additional information */ 91753830cc7SNicolas Ferre first->txd.cookie = -EBUSY; 91853830cc7SNicolas Ferre first->len = buf_len; 91953830cc7SNicolas Ferre 92053830cc7SNicolas Ferre return &first->txd; 92153830cc7SNicolas Ferre 92253830cc7SNicolas Ferre err_desc_get: 92353830cc7SNicolas Ferre dev_err(chan2dev(chan), "not enough descriptors available\n"); 92453830cc7SNicolas Ferre atc_desc_put(atchan, first); 92553830cc7SNicolas Ferre err_out: 92653830cc7SNicolas Ferre clear_bit(ATC_IS_CYCLIC, &atchan->status); 92753830cc7SNicolas Ferre return NULL; 92853830cc7SNicolas Ferre } 92953830cc7SNicolas Ferre 93053830cc7SNicolas Ferre 93105827630SLinus Walleij static int atc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, 93205827630SLinus Walleij unsigned long arg) 933808347f6SNicolas Ferre { 934808347f6SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 935808347f6SNicolas Ferre struct at_dma *atdma = to_at_dma(chan->device); 93623b5e3adSNicolas Ferre int chan_id = atchan->chan_common.chan_id; 937d8cb04b0SNicolas Ferre unsigned long flags; 93823b5e3adSNicolas Ferre 939808347f6SNicolas Ferre LIST_HEAD(list); 940808347f6SNicolas Ferre 94123b5e3adSNicolas Ferre dev_vdbg(chan2dev(chan), "atc_control (%d)\n", cmd); 942c3635c78SLinus Walleij 94323b5e3adSNicolas Ferre if (cmd == DMA_PAUSE) { 944d8cb04b0SNicolas Ferre spin_lock_irqsave(&atchan->lock, flags); 94523b5e3adSNicolas Ferre 94623b5e3adSNicolas Ferre dma_writel(atdma, CHER, AT_DMA_SUSP(chan_id)); 94723b5e3adSNicolas Ferre set_bit(ATC_IS_PAUSED, &atchan->status); 94823b5e3adSNicolas Ferre 949d8cb04b0SNicolas Ferre spin_unlock_irqrestore(&atchan->lock, flags); 95023b5e3adSNicolas Ferre } else if (cmd == DMA_RESUME) { 9513c477482SNicolas Ferre if (!atc_chan_is_paused(atchan)) 95223b5e3adSNicolas Ferre return 0; 95323b5e3adSNicolas Ferre 954d8cb04b0SNicolas Ferre spin_lock_irqsave(&atchan->lock, flags); 95523b5e3adSNicolas Ferre 95623b5e3adSNicolas Ferre dma_writel(atdma, CHDR, AT_DMA_RES(chan_id)); 95723b5e3adSNicolas Ferre clear_bit(ATC_IS_PAUSED, &atchan->status); 95823b5e3adSNicolas Ferre 959d8cb04b0SNicolas Ferre spin_unlock_irqrestore(&atchan->lock, flags); 96023b5e3adSNicolas Ferre } else if (cmd == DMA_TERMINATE_ALL) { 96123b5e3adSNicolas Ferre struct at_desc *desc, *_desc; 962808347f6SNicolas Ferre /* 963808347f6SNicolas Ferre * This is only called when something went wrong elsewhere, so 964808347f6SNicolas Ferre * we don't really care about the data. Just disable the 965808347f6SNicolas Ferre * channel. We still have to poll the channel enable bit due 966808347f6SNicolas Ferre * to AHB/HSB limitations. 967808347f6SNicolas Ferre */ 968d8cb04b0SNicolas Ferre spin_lock_irqsave(&atchan->lock, flags); 969808347f6SNicolas Ferre 97023b5e3adSNicolas Ferre /* disabling channel: must also remove suspend state */ 97123b5e3adSNicolas Ferre dma_writel(atdma, CHDR, AT_DMA_RES(chan_id) | atchan->mask); 972808347f6SNicolas Ferre 973808347f6SNicolas Ferre /* confirm that this channel is disabled */ 974808347f6SNicolas Ferre while (dma_readl(atdma, CHSR) & atchan->mask) 975808347f6SNicolas Ferre cpu_relax(); 976808347f6SNicolas Ferre 977808347f6SNicolas Ferre /* active_list entries will end up before queued entries */ 978808347f6SNicolas Ferre list_splice_init(&atchan->queue, &list); 979808347f6SNicolas Ferre list_splice_init(&atchan->active_list, &list); 980808347f6SNicolas Ferre 981808347f6SNicolas Ferre /* Flush all pending and queued descriptors */ 982808347f6SNicolas Ferre list_for_each_entry_safe(desc, _desc, &list, desc_node) 983808347f6SNicolas Ferre atc_chain_complete(atchan, desc); 984c3635c78SLinus Walleij 98523b5e3adSNicolas Ferre clear_bit(ATC_IS_PAUSED, &atchan->status); 98653830cc7SNicolas Ferre /* if channel dedicated to cyclic operations, free it */ 98753830cc7SNicolas Ferre clear_bit(ATC_IS_CYCLIC, &atchan->status); 98853830cc7SNicolas Ferre 989d8cb04b0SNicolas Ferre spin_unlock_irqrestore(&atchan->lock, flags); 99023b5e3adSNicolas Ferre } else { 99123b5e3adSNicolas Ferre return -ENXIO; 99223b5e3adSNicolas Ferre } 993b0ebeb9cSYong Wang 994c3635c78SLinus Walleij return 0; 995808347f6SNicolas Ferre } 996808347f6SNicolas Ferre 997dc78baa2SNicolas Ferre /** 99807934481SLinus Walleij * atc_tx_status - poll for transaction completion 999dc78baa2SNicolas Ferre * @chan: DMA channel 1000dc78baa2SNicolas Ferre * @cookie: transaction identifier to check status of 100107934481SLinus Walleij * @txstate: if not %NULL updated with transaction state 1002dc78baa2SNicolas Ferre * 100307934481SLinus Walleij * If @txstate is passed in, upon return it reflect the driver 1004dc78baa2SNicolas Ferre * internal state and can be used with dma_async_is_complete() to check 1005dc78baa2SNicolas Ferre * the status of multiple cookies without re-checking hardware state. 1006dc78baa2SNicolas Ferre */ 1007dc78baa2SNicolas Ferre static enum dma_status 100807934481SLinus Walleij atc_tx_status(struct dma_chan *chan, 1009dc78baa2SNicolas Ferre dma_cookie_t cookie, 101007934481SLinus Walleij struct dma_tx_state *txstate) 1011dc78baa2SNicolas Ferre { 1012dc78baa2SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 1013dc78baa2SNicolas Ferre dma_cookie_t last_used; 1014dc78baa2SNicolas Ferre dma_cookie_t last_complete; 1015d8cb04b0SNicolas Ferre unsigned long flags; 1016dc78baa2SNicolas Ferre enum dma_status ret; 1017dc78baa2SNicolas Ferre 1018d8cb04b0SNicolas Ferre spin_lock_irqsave(&atchan->lock, flags); 1019dc78baa2SNicolas Ferre 10204d4e58deSRussell King - ARM Linux last_complete = chan->completed_cookie; 1021dc78baa2SNicolas Ferre last_used = chan->cookie; 1022dc78baa2SNicolas Ferre 1023dc78baa2SNicolas Ferre ret = dma_async_is_complete(cookie, last_complete, last_used); 1024dc78baa2SNicolas Ferre if (ret != DMA_SUCCESS) { 1025dc78baa2SNicolas Ferre atc_cleanup_descriptors(atchan); 1026dc78baa2SNicolas Ferre 10274d4e58deSRussell King - ARM Linux last_complete = chan->completed_cookie; 1028dc78baa2SNicolas Ferre last_used = chan->cookie; 1029dc78baa2SNicolas Ferre 1030dc78baa2SNicolas Ferre ret = dma_async_is_complete(cookie, last_complete, last_used); 1031dc78baa2SNicolas Ferre } 1032dc78baa2SNicolas Ferre 1033d8cb04b0SNicolas Ferre spin_unlock_irqrestore(&atchan->lock, flags); 1034dc78baa2SNicolas Ferre 1035543aabc7SNicolas Ferre if (ret != DMA_SUCCESS) 1036543aabc7SNicolas Ferre dma_set_tx_state(txstate, last_complete, last_used, 1037543aabc7SNicolas Ferre atc_first_active(atchan)->len); 1038543aabc7SNicolas Ferre else 1039bca34692SDan Williams dma_set_tx_state(txstate, last_complete, last_used, 0); 1040543aabc7SNicolas Ferre 10413c477482SNicolas Ferre if (atc_chan_is_paused(atchan)) 104223b5e3adSNicolas Ferre ret = DMA_PAUSED; 104323b5e3adSNicolas Ferre 104423b5e3adSNicolas Ferre dev_vdbg(chan2dev(chan), "tx_status %d: cookie = %d (d%d, u%d)\n", 104523b5e3adSNicolas Ferre ret, cookie, last_complete ? last_complete : 0, 104607934481SLinus Walleij last_used ? last_used : 0); 1047dc78baa2SNicolas Ferre 1048dc78baa2SNicolas Ferre return ret; 1049dc78baa2SNicolas Ferre } 1050dc78baa2SNicolas Ferre 1051dc78baa2SNicolas Ferre /** 1052dc78baa2SNicolas Ferre * atc_issue_pending - try to finish work 1053dc78baa2SNicolas Ferre * @chan: target DMA channel 1054dc78baa2SNicolas Ferre */ 1055dc78baa2SNicolas Ferre static void atc_issue_pending(struct dma_chan *chan) 1056dc78baa2SNicolas Ferre { 1057dc78baa2SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 1058d8cb04b0SNicolas Ferre unsigned long flags; 1059dc78baa2SNicolas Ferre 1060dc78baa2SNicolas Ferre dev_vdbg(chan2dev(chan), "issue_pending\n"); 1061dc78baa2SNicolas Ferre 106253830cc7SNicolas Ferre /* Not needed for cyclic transfers */ 10633c477482SNicolas Ferre if (atc_chan_is_cyclic(atchan)) 106453830cc7SNicolas Ferre return; 106553830cc7SNicolas Ferre 1066d8cb04b0SNicolas Ferre spin_lock_irqsave(&atchan->lock, flags); 1067dda36f98SNicolas Ferre if (!atc_chan_is_enabled(atchan)) { 1068dc78baa2SNicolas Ferre atc_advance_work(atchan); 1069dc78baa2SNicolas Ferre } 1070d8cb04b0SNicolas Ferre spin_unlock_irqrestore(&atchan->lock, flags); 1071dc78baa2SNicolas Ferre } 1072dc78baa2SNicolas Ferre 1073dc78baa2SNicolas Ferre /** 1074dc78baa2SNicolas Ferre * atc_alloc_chan_resources - allocate resources for DMA channel 1075dc78baa2SNicolas Ferre * @chan: allocate descriptor resources for this channel 1076dc78baa2SNicolas Ferre * @client: current client requesting the channel be ready for requests 1077dc78baa2SNicolas Ferre * 1078dc78baa2SNicolas Ferre * return - the number of allocated descriptors 1079dc78baa2SNicolas Ferre */ 1080dc78baa2SNicolas Ferre static int atc_alloc_chan_resources(struct dma_chan *chan) 1081dc78baa2SNicolas Ferre { 1082dc78baa2SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 1083dc78baa2SNicolas Ferre struct at_dma *atdma = to_at_dma(chan->device); 1084dc78baa2SNicolas Ferre struct at_desc *desc; 1085808347f6SNicolas Ferre struct at_dma_slave *atslave; 1086d8cb04b0SNicolas Ferre unsigned long flags; 1087dc78baa2SNicolas Ferre int i; 1088808347f6SNicolas Ferre u32 cfg; 1089dc78baa2SNicolas Ferre LIST_HEAD(tmp_list); 1090dc78baa2SNicolas Ferre 1091dc78baa2SNicolas Ferre dev_vdbg(chan2dev(chan), "alloc_chan_resources\n"); 1092dc78baa2SNicolas Ferre 1093dc78baa2SNicolas Ferre /* ASSERT: channel is idle */ 1094dc78baa2SNicolas Ferre if (atc_chan_is_enabled(atchan)) { 1095dc78baa2SNicolas Ferre dev_dbg(chan2dev(chan), "DMA channel not idle ?\n"); 1096dc78baa2SNicolas Ferre return -EIO; 1097dc78baa2SNicolas Ferre } 1098dc78baa2SNicolas Ferre 1099808347f6SNicolas Ferre cfg = ATC_DEFAULT_CFG; 1100808347f6SNicolas Ferre 1101808347f6SNicolas Ferre atslave = chan->private; 1102808347f6SNicolas Ferre if (atslave) { 1103808347f6SNicolas Ferre /* 1104808347f6SNicolas Ferre * We need controller-specific data to set up slave 1105808347f6SNicolas Ferre * transfers. 1106808347f6SNicolas Ferre */ 1107808347f6SNicolas Ferre BUG_ON(!atslave->dma_dev || atslave->dma_dev != atdma->dma_common.dev); 1108808347f6SNicolas Ferre 1109808347f6SNicolas Ferre /* if cfg configuration specified take it instad of default */ 1110808347f6SNicolas Ferre if (atslave->cfg) 1111808347f6SNicolas Ferre cfg = atslave->cfg; 1112808347f6SNicolas Ferre } 1113808347f6SNicolas Ferre 1114808347f6SNicolas Ferre /* have we already been set up? 1115808347f6SNicolas Ferre * reconfigure channel but no need to reallocate descriptors */ 1116dc78baa2SNicolas Ferre if (!list_empty(&atchan->free_list)) 1117dc78baa2SNicolas Ferre return atchan->descs_allocated; 1118dc78baa2SNicolas Ferre 1119dc78baa2SNicolas Ferre /* Allocate initial pool of descriptors */ 1120dc78baa2SNicolas Ferre for (i = 0; i < init_nr_desc_per_channel; i++) { 1121dc78baa2SNicolas Ferre desc = atc_alloc_descriptor(chan, GFP_KERNEL); 1122dc78baa2SNicolas Ferre if (!desc) { 1123dc78baa2SNicolas Ferre dev_err(atdma->dma_common.dev, 1124dc78baa2SNicolas Ferre "Only %d initial descriptors\n", i); 1125dc78baa2SNicolas Ferre break; 1126dc78baa2SNicolas Ferre } 1127dc78baa2SNicolas Ferre list_add_tail(&desc->desc_node, &tmp_list); 1128dc78baa2SNicolas Ferre } 1129dc78baa2SNicolas Ferre 1130d8cb04b0SNicolas Ferre spin_lock_irqsave(&atchan->lock, flags); 1131dc78baa2SNicolas Ferre atchan->descs_allocated = i; 1132dc78baa2SNicolas Ferre list_splice(&tmp_list, &atchan->free_list); 11334d4e58deSRussell King - ARM Linux chan->completed_cookie = chan->cookie = 1; 1134d8cb04b0SNicolas Ferre spin_unlock_irqrestore(&atchan->lock, flags); 1135dc78baa2SNicolas Ferre 1136dc78baa2SNicolas Ferre /* channel parameters */ 1137808347f6SNicolas Ferre channel_writel(atchan, CFG, cfg); 1138dc78baa2SNicolas Ferre 1139dc78baa2SNicolas Ferre dev_dbg(chan2dev(chan), 1140dc78baa2SNicolas Ferre "alloc_chan_resources: allocated %d descriptors\n", 1141dc78baa2SNicolas Ferre atchan->descs_allocated); 1142dc78baa2SNicolas Ferre 1143dc78baa2SNicolas Ferre return atchan->descs_allocated; 1144dc78baa2SNicolas Ferre } 1145dc78baa2SNicolas Ferre 1146dc78baa2SNicolas Ferre /** 1147dc78baa2SNicolas Ferre * atc_free_chan_resources - free all channel resources 1148dc78baa2SNicolas Ferre * @chan: DMA channel 1149dc78baa2SNicolas Ferre */ 1150dc78baa2SNicolas Ferre static void atc_free_chan_resources(struct dma_chan *chan) 1151dc78baa2SNicolas Ferre { 1152dc78baa2SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 1153dc78baa2SNicolas Ferre struct at_dma *atdma = to_at_dma(chan->device); 1154dc78baa2SNicolas Ferre struct at_desc *desc, *_desc; 1155dc78baa2SNicolas Ferre LIST_HEAD(list); 1156dc78baa2SNicolas Ferre 1157dc78baa2SNicolas Ferre dev_dbg(chan2dev(chan), "free_chan_resources: (descs allocated=%u)\n", 1158dc78baa2SNicolas Ferre atchan->descs_allocated); 1159dc78baa2SNicolas Ferre 1160dc78baa2SNicolas Ferre /* ASSERT: channel is idle */ 1161dc78baa2SNicolas Ferre BUG_ON(!list_empty(&atchan->active_list)); 1162dc78baa2SNicolas Ferre BUG_ON(!list_empty(&atchan->queue)); 1163dc78baa2SNicolas Ferre BUG_ON(atc_chan_is_enabled(atchan)); 1164dc78baa2SNicolas Ferre 1165dc78baa2SNicolas Ferre list_for_each_entry_safe(desc, _desc, &atchan->free_list, desc_node) { 1166dc78baa2SNicolas Ferre dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc); 1167dc78baa2SNicolas Ferre list_del(&desc->desc_node); 1168dc78baa2SNicolas Ferre /* free link descriptor */ 1169dc78baa2SNicolas Ferre dma_pool_free(atdma->dma_desc_pool, desc, desc->txd.phys); 1170dc78baa2SNicolas Ferre } 1171dc78baa2SNicolas Ferre list_splice_init(&atchan->free_list, &list); 1172dc78baa2SNicolas Ferre atchan->descs_allocated = 0; 117353830cc7SNicolas Ferre atchan->status = 0; 1174dc78baa2SNicolas Ferre 1175dc78baa2SNicolas Ferre dev_vdbg(chan2dev(chan), "free_chan_resources: done\n"); 1176dc78baa2SNicolas Ferre } 1177dc78baa2SNicolas Ferre 1178dc78baa2SNicolas Ferre 1179dc78baa2SNicolas Ferre /*-- Module Management -----------------------------------------------*/ 1180dc78baa2SNicolas Ferre 118102f88be9SNicolas Ferre /* cap_mask is a multi-u32 bitfield, fill it with proper C code. */ 118202f88be9SNicolas Ferre static struct at_dma_platform_data at91sam9rl_config = { 118302f88be9SNicolas Ferre .nr_channels = 2, 118402f88be9SNicolas Ferre }; 118502f88be9SNicolas Ferre static struct at_dma_platform_data at91sam9g45_config = { 118602f88be9SNicolas Ferre .nr_channels = 8, 118702f88be9SNicolas Ferre }; 118802f88be9SNicolas Ferre 1189c5115953SNicolas Ferre #if defined(CONFIG_OF) 1190c5115953SNicolas Ferre static const struct of_device_id atmel_dma_dt_ids[] = { 1191c5115953SNicolas Ferre { 1192c5115953SNicolas Ferre .compatible = "atmel,at91sam9rl-dma", 119302f88be9SNicolas Ferre .data = &at91sam9rl_config, 1194c5115953SNicolas Ferre }, { 1195c5115953SNicolas Ferre .compatible = "atmel,at91sam9g45-dma", 119602f88be9SNicolas Ferre .data = &at91sam9g45_config, 1197dcc81734SNicolas Ferre }, { 1198dcc81734SNicolas Ferre /* sentinel */ 1199dcc81734SNicolas Ferre } 1200c5115953SNicolas Ferre }; 1201c5115953SNicolas Ferre 1202c5115953SNicolas Ferre MODULE_DEVICE_TABLE(of, atmel_dma_dt_ids); 1203c5115953SNicolas Ferre #endif 1204c5115953SNicolas Ferre 12050ab88a01SNicolas Ferre static const struct platform_device_id atdma_devtypes[] = { 120667348450SNicolas Ferre { 120767348450SNicolas Ferre .name = "at91sam9rl_dma", 120802f88be9SNicolas Ferre .driver_data = (unsigned long) &at91sam9rl_config, 120967348450SNicolas Ferre }, { 121067348450SNicolas Ferre .name = "at91sam9g45_dma", 121102f88be9SNicolas Ferre .driver_data = (unsigned long) &at91sam9g45_config, 121267348450SNicolas Ferre }, { 121367348450SNicolas Ferre /* sentinel */ 121467348450SNicolas Ferre } 121567348450SNicolas Ferre }; 121667348450SNicolas Ferre 121702f88be9SNicolas Ferre static inline struct at_dma_platform_data * __init at_dma_get_driver_data( 1218c5115953SNicolas Ferre struct platform_device *pdev) 1219c5115953SNicolas Ferre { 1220c5115953SNicolas Ferre if (pdev->dev.of_node) { 1221c5115953SNicolas Ferre const struct of_device_id *match; 1222c5115953SNicolas Ferre match = of_match_node(atmel_dma_dt_ids, pdev->dev.of_node); 1223c5115953SNicolas Ferre if (match == NULL) 122402f88be9SNicolas Ferre return NULL; 122502f88be9SNicolas Ferre return match->data; 1226c5115953SNicolas Ferre } 122702f88be9SNicolas Ferre return (struct at_dma_platform_data *) 122802f88be9SNicolas Ferre platform_get_device_id(pdev)->driver_data; 1229c5115953SNicolas Ferre } 1230c5115953SNicolas Ferre 1231dc78baa2SNicolas Ferre /** 1232dc78baa2SNicolas Ferre * at_dma_off - disable DMA controller 1233dc78baa2SNicolas Ferre * @atdma: the Atmel HDAMC device 1234dc78baa2SNicolas Ferre */ 1235dc78baa2SNicolas Ferre static void at_dma_off(struct at_dma *atdma) 1236dc78baa2SNicolas Ferre { 1237dc78baa2SNicolas Ferre dma_writel(atdma, EN, 0); 1238dc78baa2SNicolas Ferre 1239dc78baa2SNicolas Ferre /* disable all interrupts */ 1240dc78baa2SNicolas Ferre dma_writel(atdma, EBCIDR, -1L); 1241dc78baa2SNicolas Ferre 1242dc78baa2SNicolas Ferre /* confirm that all channels are disabled */ 1243dc78baa2SNicolas Ferre while (dma_readl(atdma, CHSR) & atdma->all_chan_mask) 1244dc78baa2SNicolas Ferre cpu_relax(); 1245dc78baa2SNicolas Ferre } 1246dc78baa2SNicolas Ferre 1247dc78baa2SNicolas Ferre static int __init at_dma_probe(struct platform_device *pdev) 1248dc78baa2SNicolas Ferre { 1249dc78baa2SNicolas Ferre struct resource *io; 1250dc78baa2SNicolas Ferre struct at_dma *atdma; 1251dc78baa2SNicolas Ferre size_t size; 1252dc78baa2SNicolas Ferre int irq; 1253dc78baa2SNicolas Ferre int err; 1254dc78baa2SNicolas Ferre int i; 125502f88be9SNicolas Ferre struct at_dma_platform_data *plat_dat; 1256dc78baa2SNicolas Ferre 125702f88be9SNicolas Ferre /* setup platform data for each SoC */ 125802f88be9SNicolas Ferre dma_cap_set(DMA_MEMCPY, at91sam9rl_config.cap_mask); 125902f88be9SNicolas Ferre dma_cap_set(DMA_MEMCPY, at91sam9g45_config.cap_mask); 126002f88be9SNicolas Ferre dma_cap_set(DMA_SLAVE, at91sam9g45_config.cap_mask); 126167348450SNicolas Ferre 126267348450SNicolas Ferre /* get DMA parameters from controller type */ 126302f88be9SNicolas Ferre plat_dat = at_dma_get_driver_data(pdev); 126402f88be9SNicolas Ferre if (!plat_dat) 126502f88be9SNicolas Ferre return -ENODEV; 1266dc78baa2SNicolas Ferre 1267dc78baa2SNicolas Ferre io = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1268dc78baa2SNicolas Ferre if (!io) 1269dc78baa2SNicolas Ferre return -EINVAL; 1270dc78baa2SNicolas Ferre 1271dc78baa2SNicolas Ferre irq = platform_get_irq(pdev, 0); 1272dc78baa2SNicolas Ferre if (irq < 0) 1273dc78baa2SNicolas Ferre return irq; 1274dc78baa2SNicolas Ferre 1275dc78baa2SNicolas Ferre size = sizeof(struct at_dma); 127602f88be9SNicolas Ferre size += plat_dat->nr_channels * sizeof(struct at_dma_chan); 1277dc78baa2SNicolas Ferre atdma = kzalloc(size, GFP_KERNEL); 1278dc78baa2SNicolas Ferre if (!atdma) 1279dc78baa2SNicolas Ferre return -ENOMEM; 1280dc78baa2SNicolas Ferre 128167348450SNicolas Ferre /* discover transaction capabilities */ 128202f88be9SNicolas Ferre atdma->dma_common.cap_mask = plat_dat->cap_mask; 128302f88be9SNicolas Ferre atdma->all_chan_mask = (1 << plat_dat->nr_channels) - 1; 1284dc78baa2SNicolas Ferre 1285114df7d6SH Hartley Sweeten size = resource_size(io); 1286dc78baa2SNicolas Ferre if (!request_mem_region(io->start, size, pdev->dev.driver->name)) { 1287dc78baa2SNicolas Ferre err = -EBUSY; 1288dc78baa2SNicolas Ferre goto err_kfree; 1289dc78baa2SNicolas Ferre } 1290dc78baa2SNicolas Ferre 1291dc78baa2SNicolas Ferre atdma->regs = ioremap(io->start, size); 1292dc78baa2SNicolas Ferre if (!atdma->regs) { 1293dc78baa2SNicolas Ferre err = -ENOMEM; 1294dc78baa2SNicolas Ferre goto err_release_r; 1295dc78baa2SNicolas Ferre } 1296dc78baa2SNicolas Ferre 1297dc78baa2SNicolas Ferre atdma->clk = clk_get(&pdev->dev, "dma_clk"); 1298dc78baa2SNicolas Ferre if (IS_ERR(atdma->clk)) { 1299dc78baa2SNicolas Ferre err = PTR_ERR(atdma->clk); 1300dc78baa2SNicolas Ferre goto err_clk; 1301dc78baa2SNicolas Ferre } 1302dc78baa2SNicolas Ferre clk_enable(atdma->clk); 1303dc78baa2SNicolas Ferre 1304dc78baa2SNicolas Ferre /* force dma off, just in case */ 1305dc78baa2SNicolas Ferre at_dma_off(atdma); 1306dc78baa2SNicolas Ferre 1307dc78baa2SNicolas Ferre err = request_irq(irq, at_dma_interrupt, 0, "at_hdmac", atdma); 1308dc78baa2SNicolas Ferre if (err) 1309dc78baa2SNicolas Ferre goto err_irq; 1310dc78baa2SNicolas Ferre 1311dc78baa2SNicolas Ferre platform_set_drvdata(pdev, atdma); 1312dc78baa2SNicolas Ferre 1313dc78baa2SNicolas Ferre /* create a pool of consistent memory blocks for hardware descriptors */ 1314dc78baa2SNicolas Ferre atdma->dma_desc_pool = dma_pool_create("at_hdmac_desc_pool", 1315dc78baa2SNicolas Ferre &pdev->dev, sizeof(struct at_desc), 1316dc78baa2SNicolas Ferre 4 /* word alignment */, 0); 1317dc78baa2SNicolas Ferre if (!atdma->dma_desc_pool) { 1318dc78baa2SNicolas Ferre dev_err(&pdev->dev, "No memory for descriptors dma pool\n"); 1319dc78baa2SNicolas Ferre err = -ENOMEM; 1320dc78baa2SNicolas Ferre goto err_pool_create; 1321dc78baa2SNicolas Ferre } 1322dc78baa2SNicolas Ferre 1323dc78baa2SNicolas Ferre /* clear any pending interrupt */ 1324dc78baa2SNicolas Ferre while (dma_readl(atdma, EBCISR)) 1325dc78baa2SNicolas Ferre cpu_relax(); 1326dc78baa2SNicolas Ferre 1327dc78baa2SNicolas Ferre /* initialize channels related values */ 1328dc78baa2SNicolas Ferre INIT_LIST_HEAD(&atdma->dma_common.channels); 132902f88be9SNicolas Ferre for (i = 0; i < plat_dat->nr_channels; i++) { 1330dc78baa2SNicolas Ferre struct at_dma_chan *atchan = &atdma->chan[i]; 1331dc78baa2SNicolas Ferre 1332dc78baa2SNicolas Ferre atchan->chan_common.device = &atdma->dma_common; 13334d4e58deSRussell King - ARM Linux atchan->chan_common.cookie = atchan->chan_common.completed_cookie = 1; 1334dc78baa2SNicolas Ferre list_add_tail(&atchan->chan_common.device_node, 1335dc78baa2SNicolas Ferre &atdma->dma_common.channels); 1336dc78baa2SNicolas Ferre 1337dc78baa2SNicolas Ferre atchan->ch_regs = atdma->regs + ch_regs(i); 1338dc78baa2SNicolas Ferre spin_lock_init(&atchan->lock); 1339dc78baa2SNicolas Ferre atchan->mask = 1 << i; 1340dc78baa2SNicolas Ferre 1341dc78baa2SNicolas Ferre INIT_LIST_HEAD(&atchan->active_list); 1342dc78baa2SNicolas Ferre INIT_LIST_HEAD(&atchan->queue); 1343dc78baa2SNicolas Ferre INIT_LIST_HEAD(&atchan->free_list); 1344dc78baa2SNicolas Ferre 1345dc78baa2SNicolas Ferre tasklet_init(&atchan->tasklet, atc_tasklet, 1346dc78baa2SNicolas Ferre (unsigned long)atchan); 1347bda3a47cSNikolaus Voss atc_enable_chan_irq(atdma, i); 1348dc78baa2SNicolas Ferre } 1349dc78baa2SNicolas Ferre 1350dc78baa2SNicolas Ferre /* set base routines */ 1351dc78baa2SNicolas Ferre atdma->dma_common.device_alloc_chan_resources = atc_alloc_chan_resources; 1352dc78baa2SNicolas Ferre atdma->dma_common.device_free_chan_resources = atc_free_chan_resources; 135307934481SLinus Walleij atdma->dma_common.device_tx_status = atc_tx_status; 1354dc78baa2SNicolas Ferre atdma->dma_common.device_issue_pending = atc_issue_pending; 1355dc78baa2SNicolas Ferre atdma->dma_common.dev = &pdev->dev; 1356dc78baa2SNicolas Ferre 1357dc78baa2SNicolas Ferre /* set prep routines based on capability */ 1358dc78baa2SNicolas Ferre if (dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask)) 1359dc78baa2SNicolas Ferre atdma->dma_common.device_prep_dma_memcpy = atc_prep_dma_memcpy; 1360dc78baa2SNicolas Ferre 1361d7db8080SNicolas Ferre if (dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask)) { 1362808347f6SNicolas Ferre atdma->dma_common.device_prep_slave_sg = atc_prep_slave_sg; 1363d7db8080SNicolas Ferre /* controller can do slave DMA: can trigger cyclic transfers */ 1364d7db8080SNicolas Ferre dma_cap_set(DMA_CYCLIC, atdma->dma_common.cap_mask); 136553830cc7SNicolas Ferre atdma->dma_common.device_prep_dma_cyclic = atc_prep_dma_cyclic; 1366c3635c78SLinus Walleij atdma->dma_common.device_control = atc_control; 1367d7db8080SNicolas Ferre } 1368808347f6SNicolas Ferre 1369dc78baa2SNicolas Ferre dma_writel(atdma, EN, AT_DMA_ENABLE); 1370dc78baa2SNicolas Ferre 1371dc78baa2SNicolas Ferre dev_info(&pdev->dev, "Atmel AHB DMA Controller ( %s%s), %d channels\n", 1372dc78baa2SNicolas Ferre dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask) ? "cpy " : "", 1373dc78baa2SNicolas Ferre dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask) ? "slave " : "", 137402f88be9SNicolas Ferre plat_dat->nr_channels); 1375dc78baa2SNicolas Ferre 1376dc78baa2SNicolas Ferre dma_async_device_register(&atdma->dma_common); 1377dc78baa2SNicolas Ferre 1378dc78baa2SNicolas Ferre return 0; 1379dc78baa2SNicolas Ferre 1380dc78baa2SNicolas Ferre err_pool_create: 1381dc78baa2SNicolas Ferre platform_set_drvdata(pdev, NULL); 1382dc78baa2SNicolas Ferre free_irq(platform_get_irq(pdev, 0), atdma); 1383dc78baa2SNicolas Ferre err_irq: 1384dc78baa2SNicolas Ferre clk_disable(atdma->clk); 1385dc78baa2SNicolas Ferre clk_put(atdma->clk); 1386dc78baa2SNicolas Ferre err_clk: 1387dc78baa2SNicolas Ferre iounmap(atdma->regs); 1388dc78baa2SNicolas Ferre atdma->regs = NULL; 1389dc78baa2SNicolas Ferre err_release_r: 1390dc78baa2SNicolas Ferre release_mem_region(io->start, size); 1391dc78baa2SNicolas Ferre err_kfree: 1392dc78baa2SNicolas Ferre kfree(atdma); 1393dc78baa2SNicolas Ferre return err; 1394dc78baa2SNicolas Ferre } 1395dc78baa2SNicolas Ferre 1396dc78baa2SNicolas Ferre static int __exit at_dma_remove(struct platform_device *pdev) 1397dc78baa2SNicolas Ferre { 1398dc78baa2SNicolas Ferre struct at_dma *atdma = platform_get_drvdata(pdev); 1399dc78baa2SNicolas Ferre struct dma_chan *chan, *_chan; 1400dc78baa2SNicolas Ferre struct resource *io; 1401dc78baa2SNicolas Ferre 1402dc78baa2SNicolas Ferre at_dma_off(atdma); 1403dc78baa2SNicolas Ferre dma_async_device_unregister(&atdma->dma_common); 1404dc78baa2SNicolas Ferre 1405dc78baa2SNicolas Ferre dma_pool_destroy(atdma->dma_desc_pool); 1406dc78baa2SNicolas Ferre platform_set_drvdata(pdev, NULL); 1407dc78baa2SNicolas Ferre free_irq(platform_get_irq(pdev, 0), atdma); 1408dc78baa2SNicolas Ferre 1409dc78baa2SNicolas Ferre list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels, 1410dc78baa2SNicolas Ferre device_node) { 1411dc78baa2SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 1412dc78baa2SNicolas Ferre 1413dc78baa2SNicolas Ferre /* Disable interrupts */ 1414bda3a47cSNikolaus Voss atc_disable_chan_irq(atdma, chan->chan_id); 1415dc78baa2SNicolas Ferre tasklet_disable(&atchan->tasklet); 1416dc78baa2SNicolas Ferre 1417dc78baa2SNicolas Ferre tasklet_kill(&atchan->tasklet); 1418dc78baa2SNicolas Ferre list_del(&chan->device_node); 1419dc78baa2SNicolas Ferre } 1420dc78baa2SNicolas Ferre 1421dc78baa2SNicolas Ferre clk_disable(atdma->clk); 1422dc78baa2SNicolas Ferre clk_put(atdma->clk); 1423dc78baa2SNicolas Ferre 1424dc78baa2SNicolas Ferre iounmap(atdma->regs); 1425dc78baa2SNicolas Ferre atdma->regs = NULL; 1426dc78baa2SNicolas Ferre 1427dc78baa2SNicolas Ferre io = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1428114df7d6SH Hartley Sweeten release_mem_region(io->start, resource_size(io)); 1429dc78baa2SNicolas Ferre 1430dc78baa2SNicolas Ferre kfree(atdma); 1431dc78baa2SNicolas Ferre 1432dc78baa2SNicolas Ferre return 0; 1433dc78baa2SNicolas Ferre } 1434dc78baa2SNicolas Ferre 1435dc78baa2SNicolas Ferre static void at_dma_shutdown(struct platform_device *pdev) 1436dc78baa2SNicolas Ferre { 1437dc78baa2SNicolas Ferre struct at_dma *atdma = platform_get_drvdata(pdev); 1438dc78baa2SNicolas Ferre 1439dc78baa2SNicolas Ferre at_dma_off(platform_get_drvdata(pdev)); 1440dc78baa2SNicolas Ferre clk_disable(atdma->clk); 1441dc78baa2SNicolas Ferre } 1442dc78baa2SNicolas Ferre 1443c0ba5947SNicolas Ferre static int at_dma_prepare(struct device *dev) 1444c0ba5947SNicolas Ferre { 1445c0ba5947SNicolas Ferre struct platform_device *pdev = to_platform_device(dev); 1446c0ba5947SNicolas Ferre struct at_dma *atdma = platform_get_drvdata(pdev); 1447c0ba5947SNicolas Ferre struct dma_chan *chan, *_chan; 1448c0ba5947SNicolas Ferre 1449c0ba5947SNicolas Ferre list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels, 1450c0ba5947SNicolas Ferre device_node) { 1451c0ba5947SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 1452c0ba5947SNicolas Ferre /* wait for transaction completion (except in cyclic case) */ 14533c477482SNicolas Ferre if (atc_chan_is_enabled(atchan) && !atc_chan_is_cyclic(atchan)) 1454c0ba5947SNicolas Ferre return -EAGAIN; 1455c0ba5947SNicolas Ferre } 1456c0ba5947SNicolas Ferre return 0; 1457c0ba5947SNicolas Ferre } 1458c0ba5947SNicolas Ferre 1459c0ba5947SNicolas Ferre static void atc_suspend_cyclic(struct at_dma_chan *atchan) 1460c0ba5947SNicolas Ferre { 1461c0ba5947SNicolas Ferre struct dma_chan *chan = &atchan->chan_common; 1462c0ba5947SNicolas Ferre 1463c0ba5947SNicolas Ferre /* Channel should be paused by user 1464c0ba5947SNicolas Ferre * do it anyway even if it is not done already */ 14653c477482SNicolas Ferre if (!atc_chan_is_paused(atchan)) { 1466c0ba5947SNicolas Ferre dev_warn(chan2dev(chan), 1467c0ba5947SNicolas Ferre "cyclic channel not paused, should be done by channel user\n"); 1468c0ba5947SNicolas Ferre atc_control(chan, DMA_PAUSE, 0); 1469c0ba5947SNicolas Ferre } 1470c0ba5947SNicolas Ferre 1471c0ba5947SNicolas Ferre /* now preserve additional data for cyclic operations */ 1472c0ba5947SNicolas Ferre /* next descriptor address in the cyclic list */ 1473c0ba5947SNicolas Ferre atchan->save_dscr = channel_readl(atchan, DSCR); 1474c0ba5947SNicolas Ferre 1475c0ba5947SNicolas Ferre vdbg_dump_regs(atchan); 1476c0ba5947SNicolas Ferre } 1477c0ba5947SNicolas Ferre 147833f82d14SDan Williams static int at_dma_suspend_noirq(struct device *dev) 1479dc78baa2SNicolas Ferre { 148033f82d14SDan Williams struct platform_device *pdev = to_platform_device(dev); 1481dc78baa2SNicolas Ferre struct at_dma *atdma = platform_get_drvdata(pdev); 1482c0ba5947SNicolas Ferre struct dma_chan *chan, *_chan; 1483dc78baa2SNicolas Ferre 1484c0ba5947SNicolas Ferre /* preserve data */ 1485c0ba5947SNicolas Ferre list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels, 1486c0ba5947SNicolas Ferre device_node) { 1487c0ba5947SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 1488c0ba5947SNicolas Ferre 14893c477482SNicolas Ferre if (atc_chan_is_cyclic(atchan)) 1490c0ba5947SNicolas Ferre atc_suspend_cyclic(atchan); 1491c0ba5947SNicolas Ferre atchan->save_cfg = channel_readl(atchan, CFG); 1492c0ba5947SNicolas Ferre } 1493c0ba5947SNicolas Ferre atdma->save_imr = dma_readl(atdma, EBCIMR); 1494c0ba5947SNicolas Ferre 1495c0ba5947SNicolas Ferre /* disable DMA controller */ 1496c0ba5947SNicolas Ferre at_dma_off(atdma); 1497dc78baa2SNicolas Ferre clk_disable(atdma->clk); 1498dc78baa2SNicolas Ferre return 0; 1499dc78baa2SNicolas Ferre } 1500dc78baa2SNicolas Ferre 1501c0ba5947SNicolas Ferre static void atc_resume_cyclic(struct at_dma_chan *atchan) 1502c0ba5947SNicolas Ferre { 1503c0ba5947SNicolas Ferre struct at_dma *atdma = to_at_dma(atchan->chan_common.device); 1504c0ba5947SNicolas Ferre 1505c0ba5947SNicolas Ferre /* restore channel status for cyclic descriptors list: 1506c0ba5947SNicolas Ferre * next descriptor in the cyclic list at the time of suspend */ 1507c0ba5947SNicolas Ferre channel_writel(atchan, SADDR, 0); 1508c0ba5947SNicolas Ferre channel_writel(atchan, DADDR, 0); 1509c0ba5947SNicolas Ferre channel_writel(atchan, CTRLA, 0); 1510c0ba5947SNicolas Ferre channel_writel(atchan, CTRLB, 0); 1511c0ba5947SNicolas Ferre channel_writel(atchan, DSCR, atchan->save_dscr); 1512c0ba5947SNicolas Ferre dma_writel(atdma, CHER, atchan->mask); 1513c0ba5947SNicolas Ferre 1514c0ba5947SNicolas Ferre /* channel pause status should be removed by channel user 1515c0ba5947SNicolas Ferre * We cannot take the initiative to do it here */ 1516c0ba5947SNicolas Ferre 1517c0ba5947SNicolas Ferre vdbg_dump_regs(atchan); 1518c0ba5947SNicolas Ferre } 1519c0ba5947SNicolas Ferre 152033f82d14SDan Williams static int at_dma_resume_noirq(struct device *dev) 1521dc78baa2SNicolas Ferre { 152233f82d14SDan Williams struct platform_device *pdev = to_platform_device(dev); 1523dc78baa2SNicolas Ferre struct at_dma *atdma = platform_get_drvdata(pdev); 1524c0ba5947SNicolas Ferre struct dma_chan *chan, *_chan; 1525dc78baa2SNicolas Ferre 1526c0ba5947SNicolas Ferre /* bring back DMA controller */ 1527dc78baa2SNicolas Ferre clk_enable(atdma->clk); 1528dc78baa2SNicolas Ferre dma_writel(atdma, EN, AT_DMA_ENABLE); 1529c0ba5947SNicolas Ferre 1530c0ba5947SNicolas Ferre /* clear any pending interrupt */ 1531c0ba5947SNicolas Ferre while (dma_readl(atdma, EBCISR)) 1532c0ba5947SNicolas Ferre cpu_relax(); 1533c0ba5947SNicolas Ferre 1534c0ba5947SNicolas Ferre /* restore saved data */ 1535c0ba5947SNicolas Ferre dma_writel(atdma, EBCIER, atdma->save_imr); 1536c0ba5947SNicolas Ferre list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels, 1537c0ba5947SNicolas Ferre device_node) { 1538c0ba5947SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 1539c0ba5947SNicolas Ferre 1540c0ba5947SNicolas Ferre channel_writel(atchan, CFG, atchan->save_cfg); 15413c477482SNicolas Ferre if (atc_chan_is_cyclic(atchan)) 1542c0ba5947SNicolas Ferre atc_resume_cyclic(atchan); 1543c0ba5947SNicolas Ferre } 1544dc78baa2SNicolas Ferre return 0; 1545dc78baa2SNicolas Ferre } 1546dc78baa2SNicolas Ferre 154747145210SAlexey Dobriyan static const struct dev_pm_ops at_dma_dev_pm_ops = { 1548c0ba5947SNicolas Ferre .prepare = at_dma_prepare, 154933f82d14SDan Williams .suspend_noirq = at_dma_suspend_noirq, 155033f82d14SDan Williams .resume_noirq = at_dma_resume_noirq, 155133f82d14SDan Williams }; 155233f82d14SDan Williams 1553dc78baa2SNicolas Ferre static struct platform_driver at_dma_driver = { 1554dc78baa2SNicolas Ferre .remove = __exit_p(at_dma_remove), 1555dc78baa2SNicolas Ferre .shutdown = at_dma_shutdown, 155667348450SNicolas Ferre .id_table = atdma_devtypes, 1557dc78baa2SNicolas Ferre .driver = { 1558dc78baa2SNicolas Ferre .name = "at_hdmac", 155933f82d14SDan Williams .pm = &at_dma_dev_pm_ops, 1560c5115953SNicolas Ferre .of_match_table = of_match_ptr(atmel_dma_dt_ids), 1561dc78baa2SNicolas Ferre }, 1562dc78baa2SNicolas Ferre }; 1563dc78baa2SNicolas Ferre 1564dc78baa2SNicolas Ferre static int __init at_dma_init(void) 1565dc78baa2SNicolas Ferre { 1566dc78baa2SNicolas Ferre return platform_driver_probe(&at_dma_driver, at_dma_probe); 1567dc78baa2SNicolas Ferre } 156893d0bec2SEric Xu subsys_initcall(at_dma_init); 1569dc78baa2SNicolas Ferre 1570dc78baa2SNicolas Ferre static void __exit at_dma_exit(void) 1571dc78baa2SNicolas Ferre { 1572dc78baa2SNicolas Ferre platform_driver_unregister(&at_dma_driver); 1573dc78baa2SNicolas Ferre } 1574dc78baa2SNicolas Ferre module_exit(at_dma_exit); 1575dc78baa2SNicolas Ferre 1576dc78baa2SNicolas Ferre MODULE_DESCRIPTION("Atmel AHB DMA Controller driver"); 1577dc78baa2SNicolas Ferre MODULE_AUTHOR("Nicolas Ferre <nicolas.ferre@atmel.com>"); 1578dc78baa2SNicolas Ferre MODULE_LICENSE("GPL"); 1579dc78baa2SNicolas Ferre MODULE_ALIAS("platform:at_hdmac"); 1580