1dc78baa2SNicolas Ferre /* 2dc78baa2SNicolas Ferre * Driver for the Atmel AHB DMA Controller (aka HDMA or DMAC on AT91 systems) 3dc78baa2SNicolas Ferre * 4dc78baa2SNicolas Ferre * Copyright (C) 2008 Atmel Corporation 5dc78baa2SNicolas Ferre * 6dc78baa2SNicolas Ferre * This program is free software; you can redistribute it and/or modify 7dc78baa2SNicolas Ferre * it under the terms of the GNU General Public License as published by 8dc78baa2SNicolas Ferre * the Free Software Foundation; either version 2 of the License, or 9dc78baa2SNicolas Ferre * (at your option) any later version. 10dc78baa2SNicolas Ferre * 11dc78baa2SNicolas Ferre * 12dc78baa2SNicolas Ferre * This supports the Atmel AHB DMA Controller, 13dc78baa2SNicolas Ferre * 14dc78baa2SNicolas Ferre * The driver has currently been tested with the Atmel AT91SAM9RL 15dc78baa2SNicolas Ferre * and AT91SAM9G45 series. 16dc78baa2SNicolas Ferre */ 17dc78baa2SNicolas Ferre 18dc78baa2SNicolas Ferre #include <linux/clk.h> 19dc78baa2SNicolas Ferre #include <linux/dmaengine.h> 20dc78baa2SNicolas Ferre #include <linux/dma-mapping.h> 21dc78baa2SNicolas Ferre #include <linux/dmapool.h> 22dc78baa2SNicolas Ferre #include <linux/interrupt.h> 23dc78baa2SNicolas Ferre #include <linux/module.h> 24dc78baa2SNicolas Ferre #include <linux/platform_device.h> 255a0e3ad6STejun Heo #include <linux/slab.h> 26c5115953SNicolas Ferre #include <linux/of.h> 27c5115953SNicolas Ferre #include <linux/of_device.h> 28dc78baa2SNicolas Ferre 29dc78baa2SNicolas Ferre #include "at_hdmac_regs.h" 30d2ebfb33SRussell King - ARM Linux #include "dmaengine.h" 31dc78baa2SNicolas Ferre 32dc78baa2SNicolas Ferre /* 33dc78baa2SNicolas Ferre * Glossary 34dc78baa2SNicolas Ferre * -------- 35dc78baa2SNicolas Ferre * 36dc78baa2SNicolas Ferre * at_hdmac : Name of the ATmel AHB DMA Controller 37dc78baa2SNicolas Ferre * at_dma_ / atdma : ATmel DMA controller entity related 38dc78baa2SNicolas Ferre * atc_ / atchan : ATmel DMA Channel entity related 39dc78baa2SNicolas Ferre */ 40dc78baa2SNicolas Ferre 41dc78baa2SNicolas Ferre #define ATC_DEFAULT_CFG (ATC_FIFOCFG_HALFFIFO) 42dc78baa2SNicolas Ferre #define ATC_DEFAULT_CTRLA (0) 43ae14d4b5SNicolas Ferre #define ATC_DEFAULT_CTRLB (ATC_SIF(AT_DMA_MEM_IF) \ 44ae14d4b5SNicolas Ferre |ATC_DIF(AT_DMA_MEM_IF)) 45dc78baa2SNicolas Ferre 46dc78baa2SNicolas Ferre /* 47dc78baa2SNicolas Ferre * Initial number of descriptors to allocate for each channel. This could 48dc78baa2SNicolas Ferre * be increased during dma usage. 49dc78baa2SNicolas Ferre */ 50dc78baa2SNicolas Ferre static unsigned int init_nr_desc_per_channel = 64; 51dc78baa2SNicolas Ferre module_param(init_nr_desc_per_channel, uint, 0644); 52dc78baa2SNicolas Ferre MODULE_PARM_DESC(init_nr_desc_per_channel, 53dc78baa2SNicolas Ferre "initial descriptors per channel (default: 64)"); 54dc78baa2SNicolas Ferre 55dc78baa2SNicolas Ferre 56dc78baa2SNicolas Ferre /* prototypes */ 57dc78baa2SNicolas Ferre static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx); 58dc78baa2SNicolas Ferre 59dc78baa2SNicolas Ferre 60dc78baa2SNicolas Ferre /*----------------------------------------------------------------------*/ 61dc78baa2SNicolas Ferre 62dc78baa2SNicolas Ferre static struct at_desc *atc_first_active(struct at_dma_chan *atchan) 63dc78baa2SNicolas Ferre { 64dc78baa2SNicolas Ferre return list_first_entry(&atchan->active_list, 65dc78baa2SNicolas Ferre struct at_desc, desc_node); 66dc78baa2SNicolas Ferre } 67dc78baa2SNicolas Ferre 68dc78baa2SNicolas Ferre static struct at_desc *atc_first_queued(struct at_dma_chan *atchan) 69dc78baa2SNicolas Ferre { 70dc78baa2SNicolas Ferre return list_first_entry(&atchan->queue, 71dc78baa2SNicolas Ferre struct at_desc, desc_node); 72dc78baa2SNicolas Ferre } 73dc78baa2SNicolas Ferre 74dc78baa2SNicolas Ferre /** 75421f91d2SUwe Kleine-König * atc_alloc_descriptor - allocate and return an initialized descriptor 76dc78baa2SNicolas Ferre * @chan: the channel to allocate descriptors for 77dc78baa2SNicolas Ferre * @gfp_flags: GFP allocation flags 78dc78baa2SNicolas Ferre * 79dc78baa2SNicolas Ferre * Note: The ack-bit is positioned in the descriptor flag at creation time 80dc78baa2SNicolas Ferre * to make initial allocation more convenient. This bit will be cleared 81dc78baa2SNicolas Ferre * and control will be given to client at usage time (during 82dc78baa2SNicolas Ferre * preparation functions). 83dc78baa2SNicolas Ferre */ 84dc78baa2SNicolas Ferre static struct at_desc *atc_alloc_descriptor(struct dma_chan *chan, 85dc78baa2SNicolas Ferre gfp_t gfp_flags) 86dc78baa2SNicolas Ferre { 87dc78baa2SNicolas Ferre struct at_desc *desc = NULL; 88dc78baa2SNicolas Ferre struct at_dma *atdma = to_at_dma(chan->device); 89dc78baa2SNicolas Ferre dma_addr_t phys; 90dc78baa2SNicolas Ferre 91dc78baa2SNicolas Ferre desc = dma_pool_alloc(atdma->dma_desc_pool, gfp_flags, &phys); 92dc78baa2SNicolas Ferre if (desc) { 93dc78baa2SNicolas Ferre memset(desc, 0, sizeof(struct at_desc)); 94285a3c71SDan Williams INIT_LIST_HEAD(&desc->tx_list); 95dc78baa2SNicolas Ferre dma_async_tx_descriptor_init(&desc->txd, chan); 96dc78baa2SNicolas Ferre /* txd.flags will be overwritten in prep functions */ 97dc78baa2SNicolas Ferre desc->txd.flags = DMA_CTRL_ACK; 98dc78baa2SNicolas Ferre desc->txd.tx_submit = atc_tx_submit; 99dc78baa2SNicolas Ferre desc->txd.phys = phys; 100dc78baa2SNicolas Ferre } 101dc78baa2SNicolas Ferre 102dc78baa2SNicolas Ferre return desc; 103dc78baa2SNicolas Ferre } 104dc78baa2SNicolas Ferre 105dc78baa2SNicolas Ferre /** 106af901ca1SAndré Goddard Rosa * atc_desc_get - get an unused descriptor from free_list 107dc78baa2SNicolas Ferre * @atchan: channel we want a new descriptor for 108dc78baa2SNicolas Ferre */ 109dc78baa2SNicolas Ferre static struct at_desc *atc_desc_get(struct at_dma_chan *atchan) 110dc78baa2SNicolas Ferre { 111dc78baa2SNicolas Ferre struct at_desc *desc, *_desc; 112dc78baa2SNicolas Ferre struct at_desc *ret = NULL; 113d8cb04b0SNicolas Ferre unsigned long flags; 114dc78baa2SNicolas Ferre unsigned int i = 0; 115dc78baa2SNicolas Ferre LIST_HEAD(tmp_list); 116dc78baa2SNicolas Ferre 117d8cb04b0SNicolas Ferre spin_lock_irqsave(&atchan->lock, flags); 118dc78baa2SNicolas Ferre list_for_each_entry_safe(desc, _desc, &atchan->free_list, desc_node) { 119dc78baa2SNicolas Ferre i++; 120dc78baa2SNicolas Ferre if (async_tx_test_ack(&desc->txd)) { 121dc78baa2SNicolas Ferre list_del(&desc->desc_node); 122dc78baa2SNicolas Ferre ret = desc; 123dc78baa2SNicolas Ferre break; 124dc78baa2SNicolas Ferre } 125dc78baa2SNicolas Ferre dev_dbg(chan2dev(&atchan->chan_common), 126dc78baa2SNicolas Ferre "desc %p not ACKed\n", desc); 127dc78baa2SNicolas Ferre } 128d8cb04b0SNicolas Ferre spin_unlock_irqrestore(&atchan->lock, flags); 129dc78baa2SNicolas Ferre dev_vdbg(chan2dev(&atchan->chan_common), 130dc78baa2SNicolas Ferre "scanned %u descriptors on freelist\n", i); 131dc78baa2SNicolas Ferre 132dc78baa2SNicolas Ferre /* no more descriptor available in initial pool: create one more */ 133dc78baa2SNicolas Ferre if (!ret) { 134dc78baa2SNicolas Ferre ret = atc_alloc_descriptor(&atchan->chan_common, GFP_ATOMIC); 135dc78baa2SNicolas Ferre if (ret) { 136d8cb04b0SNicolas Ferre spin_lock_irqsave(&atchan->lock, flags); 137dc78baa2SNicolas Ferre atchan->descs_allocated++; 138d8cb04b0SNicolas Ferre spin_unlock_irqrestore(&atchan->lock, flags); 139dc78baa2SNicolas Ferre } else { 140dc78baa2SNicolas Ferre dev_err(chan2dev(&atchan->chan_common), 141dc78baa2SNicolas Ferre "not enough descriptors available\n"); 142dc78baa2SNicolas Ferre } 143dc78baa2SNicolas Ferre } 144dc78baa2SNicolas Ferre 145dc78baa2SNicolas Ferre return ret; 146dc78baa2SNicolas Ferre } 147dc78baa2SNicolas Ferre 148dc78baa2SNicolas Ferre /** 149dc78baa2SNicolas Ferre * atc_desc_put - move a descriptor, including any children, to the free list 150dc78baa2SNicolas Ferre * @atchan: channel we work on 151dc78baa2SNicolas Ferre * @desc: descriptor, at the head of a chain, to move to free list 152dc78baa2SNicolas Ferre */ 153dc78baa2SNicolas Ferre static void atc_desc_put(struct at_dma_chan *atchan, struct at_desc *desc) 154dc78baa2SNicolas Ferre { 155dc78baa2SNicolas Ferre if (desc) { 156dc78baa2SNicolas Ferre struct at_desc *child; 157d8cb04b0SNicolas Ferre unsigned long flags; 158dc78baa2SNicolas Ferre 159d8cb04b0SNicolas Ferre spin_lock_irqsave(&atchan->lock, flags); 160285a3c71SDan Williams list_for_each_entry(child, &desc->tx_list, desc_node) 161dc78baa2SNicolas Ferre dev_vdbg(chan2dev(&atchan->chan_common), 162dc78baa2SNicolas Ferre "moving child desc %p to freelist\n", 163dc78baa2SNicolas Ferre child); 164285a3c71SDan Williams list_splice_init(&desc->tx_list, &atchan->free_list); 165dc78baa2SNicolas Ferre dev_vdbg(chan2dev(&atchan->chan_common), 166dc78baa2SNicolas Ferre "moving desc %p to freelist\n", desc); 167dc78baa2SNicolas Ferre list_add(&desc->desc_node, &atchan->free_list); 168d8cb04b0SNicolas Ferre spin_unlock_irqrestore(&atchan->lock, flags); 169dc78baa2SNicolas Ferre } 170dc78baa2SNicolas Ferre } 171dc78baa2SNicolas Ferre 172dc78baa2SNicolas Ferre /** 17353830cc7SNicolas Ferre * atc_desc_chain - build chain adding a descripor 17453830cc7SNicolas Ferre * @first: address of first descripor of the chain 17553830cc7SNicolas Ferre * @prev: address of previous descripor of the chain 17653830cc7SNicolas Ferre * @desc: descriptor to queue 17753830cc7SNicolas Ferre * 17853830cc7SNicolas Ferre * Called from prep_* functions 17953830cc7SNicolas Ferre */ 18053830cc7SNicolas Ferre static void atc_desc_chain(struct at_desc **first, struct at_desc **prev, 18153830cc7SNicolas Ferre struct at_desc *desc) 18253830cc7SNicolas Ferre { 18353830cc7SNicolas Ferre if (!(*first)) { 18453830cc7SNicolas Ferre *first = desc; 18553830cc7SNicolas Ferre } else { 18653830cc7SNicolas Ferre /* inform the HW lli about chaining */ 18753830cc7SNicolas Ferre (*prev)->lli.dscr = desc->txd.phys; 18853830cc7SNicolas Ferre /* insert the link descriptor to the LD ring */ 18953830cc7SNicolas Ferre list_add_tail(&desc->desc_node, 19053830cc7SNicolas Ferre &(*first)->tx_list); 19153830cc7SNicolas Ferre } 19253830cc7SNicolas Ferre *prev = desc; 19353830cc7SNicolas Ferre } 19453830cc7SNicolas Ferre 19553830cc7SNicolas Ferre /** 196dc78baa2SNicolas Ferre * atc_dostart - starts the DMA engine for real 197dc78baa2SNicolas Ferre * @atchan: the channel we want to start 198dc78baa2SNicolas Ferre * @first: first descriptor in the list we want to begin with 199dc78baa2SNicolas Ferre * 200dc78baa2SNicolas Ferre * Called with atchan->lock held and bh disabled 201dc78baa2SNicolas Ferre */ 202dc78baa2SNicolas Ferre static void atc_dostart(struct at_dma_chan *atchan, struct at_desc *first) 203dc78baa2SNicolas Ferre { 204dc78baa2SNicolas Ferre struct at_dma *atdma = to_at_dma(atchan->chan_common.device); 205dc78baa2SNicolas Ferre 206dc78baa2SNicolas Ferre /* ASSERT: channel is idle */ 207dc78baa2SNicolas Ferre if (atc_chan_is_enabled(atchan)) { 208dc78baa2SNicolas Ferre dev_err(chan2dev(&atchan->chan_common), 209dc78baa2SNicolas Ferre "BUG: Attempted to start non-idle channel\n"); 210dc78baa2SNicolas Ferre dev_err(chan2dev(&atchan->chan_common), 211dc78baa2SNicolas Ferre " channel: s0x%x d0x%x ctrl0x%x:0x%x l0x%x\n", 212dc78baa2SNicolas Ferre channel_readl(atchan, SADDR), 213dc78baa2SNicolas Ferre channel_readl(atchan, DADDR), 214dc78baa2SNicolas Ferre channel_readl(atchan, CTRLA), 215dc78baa2SNicolas Ferre channel_readl(atchan, CTRLB), 216dc78baa2SNicolas Ferre channel_readl(atchan, DSCR)); 217dc78baa2SNicolas Ferre 218dc78baa2SNicolas Ferre /* The tasklet will hopefully advance the queue... */ 219dc78baa2SNicolas Ferre return; 220dc78baa2SNicolas Ferre } 221dc78baa2SNicolas Ferre 222dc78baa2SNicolas Ferre vdbg_dump_regs(atchan); 223dc78baa2SNicolas Ferre 224dc78baa2SNicolas Ferre /* clear any pending interrupt */ 225dc78baa2SNicolas Ferre while (dma_readl(atdma, EBCISR)) 226dc78baa2SNicolas Ferre cpu_relax(); 227dc78baa2SNicolas Ferre 228dc78baa2SNicolas Ferre channel_writel(atchan, SADDR, 0); 229dc78baa2SNicolas Ferre channel_writel(atchan, DADDR, 0); 230dc78baa2SNicolas Ferre channel_writel(atchan, CTRLA, 0); 231dc78baa2SNicolas Ferre channel_writel(atchan, CTRLB, 0); 232dc78baa2SNicolas Ferre channel_writel(atchan, DSCR, first->txd.phys); 233dc78baa2SNicolas Ferre dma_writel(atdma, CHER, atchan->mask); 234dc78baa2SNicolas Ferre 235dc78baa2SNicolas Ferre vdbg_dump_regs(atchan); 236dc78baa2SNicolas Ferre } 237dc78baa2SNicolas Ferre 238dc78baa2SNicolas Ferre /** 239dc78baa2SNicolas Ferre * atc_chain_complete - finish work for one transaction chain 240dc78baa2SNicolas Ferre * @atchan: channel we work on 241dc78baa2SNicolas Ferre * @desc: descriptor at the head of the chain we want do complete 242dc78baa2SNicolas Ferre * 243dc78baa2SNicolas Ferre * Called with atchan->lock held and bh disabled */ 244dc78baa2SNicolas Ferre static void 245dc78baa2SNicolas Ferre atc_chain_complete(struct at_dma_chan *atchan, struct at_desc *desc) 246dc78baa2SNicolas Ferre { 247dc78baa2SNicolas Ferre struct dma_async_tx_descriptor *txd = &desc->txd; 248dc78baa2SNicolas Ferre 249dc78baa2SNicolas Ferre dev_vdbg(chan2dev(&atchan->chan_common), 250dc78baa2SNicolas Ferre "descriptor %u complete\n", txd->cookie); 251dc78baa2SNicolas Ferre 2524d4e58deSRussell King - ARM Linux atchan->chan_common.completed_cookie = txd->cookie; 253dc78baa2SNicolas Ferre 254dc78baa2SNicolas Ferre /* move children to free_list */ 255285a3c71SDan Williams list_splice_init(&desc->tx_list, &atchan->free_list); 256dc78baa2SNicolas Ferre /* move myself to free_list */ 257dc78baa2SNicolas Ferre list_move(&desc->desc_node, &atchan->free_list); 258dc78baa2SNicolas Ferre 259ebcf9b80SNicolas Ferre /* unmap dma addresses (not on slave channels) */ 260657a77faSAtsushi Nemoto if (!atchan->chan_common.private) { 261657a77faSAtsushi Nemoto struct device *parent = chan2parent(&atchan->chan_common); 262dc78baa2SNicolas Ferre if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) { 263dc78baa2SNicolas Ferre if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE) 264657a77faSAtsushi Nemoto dma_unmap_single(parent, 265dc78baa2SNicolas Ferre desc->lli.daddr, 266dc78baa2SNicolas Ferre desc->len, DMA_FROM_DEVICE); 267dc78baa2SNicolas Ferre else 268657a77faSAtsushi Nemoto dma_unmap_page(parent, 269dc78baa2SNicolas Ferre desc->lli.daddr, 270dc78baa2SNicolas Ferre desc->len, DMA_FROM_DEVICE); 271dc78baa2SNicolas Ferre } 272dc78baa2SNicolas Ferre if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) { 273dc78baa2SNicolas Ferre if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE) 274657a77faSAtsushi Nemoto dma_unmap_single(parent, 275dc78baa2SNicolas Ferre desc->lli.saddr, 276dc78baa2SNicolas Ferre desc->len, DMA_TO_DEVICE); 277dc78baa2SNicolas Ferre else 278657a77faSAtsushi Nemoto dma_unmap_page(parent, 279dc78baa2SNicolas Ferre desc->lli.saddr, 280dc78baa2SNicolas Ferre desc->len, DMA_TO_DEVICE); 281dc78baa2SNicolas Ferre } 282657a77faSAtsushi Nemoto } 283dc78baa2SNicolas Ferre 28453830cc7SNicolas Ferre /* for cyclic transfers, 28553830cc7SNicolas Ferre * no need to replay callback function while stopping */ 2863c477482SNicolas Ferre if (!atc_chan_is_cyclic(atchan)) { 28753830cc7SNicolas Ferre dma_async_tx_callback callback = txd->callback; 28853830cc7SNicolas Ferre void *param = txd->callback_param; 28953830cc7SNicolas Ferre 290dc78baa2SNicolas Ferre /* 291dc78baa2SNicolas Ferre * The API requires that no submissions are done from a 292dc78baa2SNicolas Ferre * callback, so we don't need to drop the lock here 293dc78baa2SNicolas Ferre */ 294dc78baa2SNicolas Ferre if (callback) 295dc78baa2SNicolas Ferre callback(param); 29653830cc7SNicolas Ferre } 297dc78baa2SNicolas Ferre 298dc78baa2SNicolas Ferre dma_run_dependencies(txd); 299dc78baa2SNicolas Ferre } 300dc78baa2SNicolas Ferre 301dc78baa2SNicolas Ferre /** 302dc78baa2SNicolas Ferre * atc_complete_all - finish work for all transactions 303dc78baa2SNicolas Ferre * @atchan: channel to complete transactions for 304dc78baa2SNicolas Ferre * 305dc78baa2SNicolas Ferre * Eventually submit queued descriptors if any 306dc78baa2SNicolas Ferre * 307dc78baa2SNicolas Ferre * Assume channel is idle while calling this function 308dc78baa2SNicolas Ferre * Called with atchan->lock held and bh disabled 309dc78baa2SNicolas Ferre */ 310dc78baa2SNicolas Ferre static void atc_complete_all(struct at_dma_chan *atchan) 311dc78baa2SNicolas Ferre { 312dc78baa2SNicolas Ferre struct at_desc *desc, *_desc; 313dc78baa2SNicolas Ferre LIST_HEAD(list); 314dc78baa2SNicolas Ferre 315dc78baa2SNicolas Ferre dev_vdbg(chan2dev(&atchan->chan_common), "complete all\n"); 316dc78baa2SNicolas Ferre 317dc78baa2SNicolas Ferre BUG_ON(atc_chan_is_enabled(atchan)); 318dc78baa2SNicolas Ferre 319dc78baa2SNicolas Ferre /* 320dc78baa2SNicolas Ferre * Submit queued descriptors ASAP, i.e. before we go through 321dc78baa2SNicolas Ferre * the completed ones. 322dc78baa2SNicolas Ferre */ 323dc78baa2SNicolas Ferre if (!list_empty(&atchan->queue)) 324dc78baa2SNicolas Ferre atc_dostart(atchan, atc_first_queued(atchan)); 325dc78baa2SNicolas Ferre /* empty active_list now it is completed */ 326dc78baa2SNicolas Ferre list_splice_init(&atchan->active_list, &list); 327dc78baa2SNicolas Ferre /* empty queue list by moving descriptors (if any) to active_list */ 328dc78baa2SNicolas Ferre list_splice_init(&atchan->queue, &atchan->active_list); 329dc78baa2SNicolas Ferre 330dc78baa2SNicolas Ferre list_for_each_entry_safe(desc, _desc, &list, desc_node) 331dc78baa2SNicolas Ferre atc_chain_complete(atchan, desc); 332dc78baa2SNicolas Ferre } 333dc78baa2SNicolas Ferre 334dc78baa2SNicolas Ferre /** 335dc78baa2SNicolas Ferre * atc_cleanup_descriptors - cleanup up finished descriptors in active_list 336dc78baa2SNicolas Ferre * @atchan: channel to be cleaned up 337dc78baa2SNicolas Ferre * 338dc78baa2SNicolas Ferre * Called with atchan->lock held and bh disabled 339dc78baa2SNicolas Ferre */ 340dc78baa2SNicolas Ferre static void atc_cleanup_descriptors(struct at_dma_chan *atchan) 341dc78baa2SNicolas Ferre { 342dc78baa2SNicolas Ferre struct at_desc *desc, *_desc; 343dc78baa2SNicolas Ferre struct at_desc *child; 344dc78baa2SNicolas Ferre 345dc78baa2SNicolas Ferre dev_vdbg(chan2dev(&atchan->chan_common), "cleanup descriptors\n"); 346dc78baa2SNicolas Ferre 347dc78baa2SNicolas Ferre list_for_each_entry_safe(desc, _desc, &atchan->active_list, desc_node) { 348dc78baa2SNicolas Ferre if (!(desc->lli.ctrla & ATC_DONE)) 349dc78baa2SNicolas Ferre /* This one is currently in progress */ 350dc78baa2SNicolas Ferre return; 351dc78baa2SNicolas Ferre 352285a3c71SDan Williams list_for_each_entry(child, &desc->tx_list, desc_node) 353dc78baa2SNicolas Ferre if (!(child->lli.ctrla & ATC_DONE)) 354dc78baa2SNicolas Ferre /* Currently in progress */ 355dc78baa2SNicolas Ferre return; 356dc78baa2SNicolas Ferre 357dc78baa2SNicolas Ferre /* 358dc78baa2SNicolas Ferre * No descriptors so far seem to be in progress, i.e. 359dc78baa2SNicolas Ferre * this chain must be done. 360dc78baa2SNicolas Ferre */ 361dc78baa2SNicolas Ferre atc_chain_complete(atchan, desc); 362dc78baa2SNicolas Ferre } 363dc78baa2SNicolas Ferre } 364dc78baa2SNicolas Ferre 365dc78baa2SNicolas Ferre /** 366dc78baa2SNicolas Ferre * atc_advance_work - at the end of a transaction, move forward 367dc78baa2SNicolas Ferre * @atchan: channel where the transaction ended 368dc78baa2SNicolas Ferre * 369dc78baa2SNicolas Ferre * Called with atchan->lock held and bh disabled 370dc78baa2SNicolas Ferre */ 371dc78baa2SNicolas Ferre static void atc_advance_work(struct at_dma_chan *atchan) 372dc78baa2SNicolas Ferre { 373dc78baa2SNicolas Ferre dev_vdbg(chan2dev(&atchan->chan_common), "advance_work\n"); 374dc78baa2SNicolas Ferre 375dc78baa2SNicolas Ferre if (list_empty(&atchan->active_list) || 376dc78baa2SNicolas Ferre list_is_singular(&atchan->active_list)) { 377dc78baa2SNicolas Ferre atc_complete_all(atchan); 378dc78baa2SNicolas Ferre } else { 379dc78baa2SNicolas Ferre atc_chain_complete(atchan, atc_first_active(atchan)); 380dc78baa2SNicolas Ferre /* advance work */ 381dc78baa2SNicolas Ferre atc_dostart(atchan, atc_first_active(atchan)); 382dc78baa2SNicolas Ferre } 383dc78baa2SNicolas Ferre } 384dc78baa2SNicolas Ferre 385dc78baa2SNicolas Ferre 386dc78baa2SNicolas Ferre /** 387dc78baa2SNicolas Ferre * atc_handle_error - handle errors reported by DMA controller 388dc78baa2SNicolas Ferre * @atchan: channel where error occurs 389dc78baa2SNicolas Ferre * 390dc78baa2SNicolas Ferre * Called with atchan->lock held and bh disabled 391dc78baa2SNicolas Ferre */ 392dc78baa2SNicolas Ferre static void atc_handle_error(struct at_dma_chan *atchan) 393dc78baa2SNicolas Ferre { 394dc78baa2SNicolas Ferre struct at_desc *bad_desc; 395dc78baa2SNicolas Ferre struct at_desc *child; 396dc78baa2SNicolas Ferre 397dc78baa2SNicolas Ferre /* 398dc78baa2SNicolas Ferre * The descriptor currently at the head of the active list is 399dc78baa2SNicolas Ferre * broked. Since we don't have any way to report errors, we'll 400dc78baa2SNicolas Ferre * just have to scream loudly and try to carry on. 401dc78baa2SNicolas Ferre */ 402dc78baa2SNicolas Ferre bad_desc = atc_first_active(atchan); 403dc78baa2SNicolas Ferre list_del_init(&bad_desc->desc_node); 404dc78baa2SNicolas Ferre 405dc78baa2SNicolas Ferre /* As we are stopped, take advantage to push queued descriptors 406dc78baa2SNicolas Ferre * in active_list */ 407dc78baa2SNicolas Ferre list_splice_init(&atchan->queue, atchan->active_list.prev); 408dc78baa2SNicolas Ferre 409dc78baa2SNicolas Ferre /* Try to restart the controller */ 410dc78baa2SNicolas Ferre if (!list_empty(&atchan->active_list)) 411dc78baa2SNicolas Ferre atc_dostart(atchan, atc_first_active(atchan)); 412dc78baa2SNicolas Ferre 413dc78baa2SNicolas Ferre /* 414dc78baa2SNicolas Ferre * KERN_CRITICAL may seem harsh, but since this only happens 415dc78baa2SNicolas Ferre * when someone submits a bad physical address in a 416dc78baa2SNicolas Ferre * descriptor, we should consider ourselves lucky that the 417dc78baa2SNicolas Ferre * controller flagged an error instead of scribbling over 418dc78baa2SNicolas Ferre * random memory locations. 419dc78baa2SNicolas Ferre */ 420dc78baa2SNicolas Ferre dev_crit(chan2dev(&atchan->chan_common), 421dc78baa2SNicolas Ferre "Bad descriptor submitted for DMA!\n"); 422dc78baa2SNicolas Ferre dev_crit(chan2dev(&atchan->chan_common), 423dc78baa2SNicolas Ferre " cookie: %d\n", bad_desc->txd.cookie); 424dc78baa2SNicolas Ferre atc_dump_lli(atchan, &bad_desc->lli); 425285a3c71SDan Williams list_for_each_entry(child, &bad_desc->tx_list, desc_node) 426dc78baa2SNicolas Ferre atc_dump_lli(atchan, &child->lli); 427dc78baa2SNicolas Ferre 428dc78baa2SNicolas Ferre /* Pretend the descriptor completed successfully */ 429dc78baa2SNicolas Ferre atc_chain_complete(atchan, bad_desc); 430dc78baa2SNicolas Ferre } 431dc78baa2SNicolas Ferre 43253830cc7SNicolas Ferre /** 43353830cc7SNicolas Ferre * atc_handle_cyclic - at the end of a period, run callback function 43453830cc7SNicolas Ferre * @atchan: channel used for cyclic operations 43553830cc7SNicolas Ferre * 43653830cc7SNicolas Ferre * Called with atchan->lock held and bh disabled 43753830cc7SNicolas Ferre */ 43853830cc7SNicolas Ferre static void atc_handle_cyclic(struct at_dma_chan *atchan) 43953830cc7SNicolas Ferre { 44053830cc7SNicolas Ferre struct at_desc *first = atc_first_active(atchan); 44153830cc7SNicolas Ferre struct dma_async_tx_descriptor *txd = &first->txd; 44253830cc7SNicolas Ferre dma_async_tx_callback callback = txd->callback; 44353830cc7SNicolas Ferre void *param = txd->callback_param; 44453830cc7SNicolas Ferre 44553830cc7SNicolas Ferre dev_vdbg(chan2dev(&atchan->chan_common), 44653830cc7SNicolas Ferre "new cyclic period llp 0x%08x\n", 44753830cc7SNicolas Ferre channel_readl(atchan, DSCR)); 44853830cc7SNicolas Ferre 44953830cc7SNicolas Ferre if (callback) 45053830cc7SNicolas Ferre callback(param); 45153830cc7SNicolas Ferre } 452dc78baa2SNicolas Ferre 453dc78baa2SNicolas Ferre /*-- IRQ & Tasklet ---------------------------------------------------*/ 454dc78baa2SNicolas Ferre 455dc78baa2SNicolas Ferre static void atc_tasklet(unsigned long data) 456dc78baa2SNicolas Ferre { 457dc78baa2SNicolas Ferre struct at_dma_chan *atchan = (struct at_dma_chan *)data; 458d8cb04b0SNicolas Ferre unsigned long flags; 459dc78baa2SNicolas Ferre 460d8cb04b0SNicolas Ferre spin_lock_irqsave(&atchan->lock, flags); 46153830cc7SNicolas Ferre if (test_and_clear_bit(ATC_IS_ERROR, &atchan->status)) 462dc78baa2SNicolas Ferre atc_handle_error(atchan); 4633c477482SNicolas Ferre else if (atc_chan_is_cyclic(atchan)) 46453830cc7SNicolas Ferre atc_handle_cyclic(atchan); 465dc78baa2SNicolas Ferre else 466dc78baa2SNicolas Ferre atc_advance_work(atchan); 467dc78baa2SNicolas Ferre 468d8cb04b0SNicolas Ferre spin_unlock_irqrestore(&atchan->lock, flags); 469dc78baa2SNicolas Ferre } 470dc78baa2SNicolas Ferre 471dc78baa2SNicolas Ferre static irqreturn_t at_dma_interrupt(int irq, void *dev_id) 472dc78baa2SNicolas Ferre { 473dc78baa2SNicolas Ferre struct at_dma *atdma = (struct at_dma *)dev_id; 474dc78baa2SNicolas Ferre struct at_dma_chan *atchan; 475dc78baa2SNicolas Ferre int i; 476dc78baa2SNicolas Ferre u32 status, pending, imr; 477dc78baa2SNicolas Ferre int ret = IRQ_NONE; 478dc78baa2SNicolas Ferre 479dc78baa2SNicolas Ferre do { 480dc78baa2SNicolas Ferre imr = dma_readl(atdma, EBCIMR); 481dc78baa2SNicolas Ferre status = dma_readl(atdma, EBCISR); 482dc78baa2SNicolas Ferre pending = status & imr; 483dc78baa2SNicolas Ferre 484dc78baa2SNicolas Ferre if (!pending) 485dc78baa2SNicolas Ferre break; 486dc78baa2SNicolas Ferre 487dc78baa2SNicolas Ferre dev_vdbg(atdma->dma_common.dev, 488dc78baa2SNicolas Ferre "interrupt: status = 0x%08x, 0x%08x, 0x%08x\n", 489dc78baa2SNicolas Ferre status, imr, pending); 490dc78baa2SNicolas Ferre 491dc78baa2SNicolas Ferre for (i = 0; i < atdma->dma_common.chancnt; i++) { 492dc78baa2SNicolas Ferre atchan = &atdma->chan[i]; 4939b3aa589SNicolas Ferre if (pending & (AT_DMA_BTC(i) | AT_DMA_ERR(i))) { 494dc78baa2SNicolas Ferre if (pending & AT_DMA_ERR(i)) { 495dc78baa2SNicolas Ferre /* Disable channel on AHB error */ 49623b5e3adSNicolas Ferre dma_writel(atdma, CHDR, 49723b5e3adSNicolas Ferre AT_DMA_RES(i) | atchan->mask); 498dc78baa2SNicolas Ferre /* Give information to tasklet */ 49953830cc7SNicolas Ferre set_bit(ATC_IS_ERROR, &atchan->status); 500dc78baa2SNicolas Ferre } 501dc78baa2SNicolas Ferre tasklet_schedule(&atchan->tasklet); 502dc78baa2SNicolas Ferre ret = IRQ_HANDLED; 503dc78baa2SNicolas Ferre } 504dc78baa2SNicolas Ferre } 505dc78baa2SNicolas Ferre 506dc78baa2SNicolas Ferre } while (pending); 507dc78baa2SNicolas Ferre 508dc78baa2SNicolas Ferre return ret; 509dc78baa2SNicolas Ferre } 510dc78baa2SNicolas Ferre 511dc78baa2SNicolas Ferre 512dc78baa2SNicolas Ferre /*-- DMA Engine API --------------------------------------------------*/ 513dc78baa2SNicolas Ferre 514dc78baa2SNicolas Ferre /** 515dc78baa2SNicolas Ferre * atc_tx_submit - set the prepared descriptor(s) to be executed by the engine 516dc78baa2SNicolas Ferre * @desc: descriptor at the head of the transaction chain 517dc78baa2SNicolas Ferre * 518dc78baa2SNicolas Ferre * Queue chain if DMA engine is working already 519dc78baa2SNicolas Ferre * 520dc78baa2SNicolas Ferre * Cookie increment and adding to active_list or queue must be atomic 521dc78baa2SNicolas Ferre */ 522dc78baa2SNicolas Ferre static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx) 523dc78baa2SNicolas Ferre { 524dc78baa2SNicolas Ferre struct at_desc *desc = txd_to_at_desc(tx); 525dc78baa2SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(tx->chan); 526dc78baa2SNicolas Ferre dma_cookie_t cookie; 527d8cb04b0SNicolas Ferre unsigned long flags; 528dc78baa2SNicolas Ferre 529d8cb04b0SNicolas Ferre spin_lock_irqsave(&atchan->lock, flags); 530884485e1SRussell King - ARM Linux cookie = dma_cookie_assign(tx); 531dc78baa2SNicolas Ferre 532dc78baa2SNicolas Ferre if (list_empty(&atchan->active_list)) { 533dc78baa2SNicolas Ferre dev_vdbg(chan2dev(tx->chan), "tx_submit: started %u\n", 534dc78baa2SNicolas Ferre desc->txd.cookie); 535dc78baa2SNicolas Ferre atc_dostart(atchan, desc); 536dc78baa2SNicolas Ferre list_add_tail(&desc->desc_node, &atchan->active_list); 537dc78baa2SNicolas Ferre } else { 538dc78baa2SNicolas Ferre dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u\n", 539dc78baa2SNicolas Ferre desc->txd.cookie); 540dc78baa2SNicolas Ferre list_add_tail(&desc->desc_node, &atchan->queue); 541dc78baa2SNicolas Ferre } 542dc78baa2SNicolas Ferre 543d8cb04b0SNicolas Ferre spin_unlock_irqrestore(&atchan->lock, flags); 544dc78baa2SNicolas Ferre 545dc78baa2SNicolas Ferre return cookie; 546dc78baa2SNicolas Ferre } 547dc78baa2SNicolas Ferre 548dc78baa2SNicolas Ferre /** 549dc78baa2SNicolas Ferre * atc_prep_dma_memcpy - prepare a memcpy operation 550dc78baa2SNicolas Ferre * @chan: the channel to prepare operation on 551dc78baa2SNicolas Ferre * @dest: operation virtual destination address 552dc78baa2SNicolas Ferre * @src: operation virtual source address 553dc78baa2SNicolas Ferre * @len: operation length 554dc78baa2SNicolas Ferre * @flags: tx descriptor status flags 555dc78baa2SNicolas Ferre */ 556dc78baa2SNicolas Ferre static struct dma_async_tx_descriptor * 557dc78baa2SNicolas Ferre atc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, 558dc78baa2SNicolas Ferre size_t len, unsigned long flags) 559dc78baa2SNicolas Ferre { 560dc78baa2SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 561dc78baa2SNicolas Ferre struct at_desc *desc = NULL; 562dc78baa2SNicolas Ferre struct at_desc *first = NULL; 563dc78baa2SNicolas Ferre struct at_desc *prev = NULL; 564dc78baa2SNicolas Ferre size_t xfer_count; 565dc78baa2SNicolas Ferre size_t offset; 566dc78baa2SNicolas Ferre unsigned int src_width; 567dc78baa2SNicolas Ferre unsigned int dst_width; 568dc78baa2SNicolas Ferre u32 ctrla; 569dc78baa2SNicolas Ferre u32 ctrlb; 570dc78baa2SNicolas Ferre 571dc78baa2SNicolas Ferre dev_vdbg(chan2dev(chan), "prep_dma_memcpy: d0x%x s0x%x l0x%zx f0x%lx\n", 572dc78baa2SNicolas Ferre dest, src, len, flags); 573dc78baa2SNicolas Ferre 574dc78baa2SNicolas Ferre if (unlikely(!len)) { 575dc78baa2SNicolas Ferre dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n"); 576dc78baa2SNicolas Ferre return NULL; 577dc78baa2SNicolas Ferre } 578dc78baa2SNicolas Ferre 579dc78baa2SNicolas Ferre ctrla = ATC_DEFAULT_CTRLA; 5809b3aa589SNicolas Ferre ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN 581dc78baa2SNicolas Ferre | ATC_SRC_ADDR_MODE_INCR 582dc78baa2SNicolas Ferre | ATC_DST_ADDR_MODE_INCR 583dc78baa2SNicolas Ferre | ATC_FC_MEM2MEM; 584dc78baa2SNicolas Ferre 585dc78baa2SNicolas Ferre /* 586dc78baa2SNicolas Ferre * We can be a lot more clever here, but this should take care 587dc78baa2SNicolas Ferre * of the most common optimization. 588dc78baa2SNicolas Ferre */ 589dc78baa2SNicolas Ferre if (!((src | dest | len) & 3)) { 590dc78baa2SNicolas Ferre ctrla |= ATC_SRC_WIDTH_WORD | ATC_DST_WIDTH_WORD; 591dc78baa2SNicolas Ferre src_width = dst_width = 2; 592dc78baa2SNicolas Ferre } else if (!((src | dest | len) & 1)) { 593dc78baa2SNicolas Ferre ctrla |= ATC_SRC_WIDTH_HALFWORD | ATC_DST_WIDTH_HALFWORD; 594dc78baa2SNicolas Ferre src_width = dst_width = 1; 595dc78baa2SNicolas Ferre } else { 596dc78baa2SNicolas Ferre ctrla |= ATC_SRC_WIDTH_BYTE | ATC_DST_WIDTH_BYTE; 597dc78baa2SNicolas Ferre src_width = dst_width = 0; 598dc78baa2SNicolas Ferre } 599dc78baa2SNicolas Ferre 600dc78baa2SNicolas Ferre for (offset = 0; offset < len; offset += xfer_count << src_width) { 601dc78baa2SNicolas Ferre xfer_count = min_t(size_t, (len - offset) >> src_width, 602dc78baa2SNicolas Ferre ATC_BTSIZE_MAX); 603dc78baa2SNicolas Ferre 604dc78baa2SNicolas Ferre desc = atc_desc_get(atchan); 605dc78baa2SNicolas Ferre if (!desc) 606dc78baa2SNicolas Ferre goto err_desc_get; 607dc78baa2SNicolas Ferre 608dc78baa2SNicolas Ferre desc->lli.saddr = src + offset; 609dc78baa2SNicolas Ferre desc->lli.daddr = dest + offset; 610dc78baa2SNicolas Ferre desc->lli.ctrla = ctrla | xfer_count; 611dc78baa2SNicolas Ferre desc->lli.ctrlb = ctrlb; 612dc78baa2SNicolas Ferre 613dc78baa2SNicolas Ferre desc->txd.cookie = 0; 614dc78baa2SNicolas Ferre 615e257e156SNicolas Ferre atc_desc_chain(&first, &prev, desc); 616dc78baa2SNicolas Ferre } 617dc78baa2SNicolas Ferre 618dc78baa2SNicolas Ferre /* First descriptor of the chain embedds additional information */ 619dc78baa2SNicolas Ferre first->txd.cookie = -EBUSY; 620dc78baa2SNicolas Ferre first->len = len; 621dc78baa2SNicolas Ferre 622dc78baa2SNicolas Ferre /* set end-of-link to the last link descriptor of list*/ 623dc78baa2SNicolas Ferre set_desc_eol(desc); 624dc78baa2SNicolas Ferre 625568f7f0cSNicolas Ferre first->txd.flags = flags; /* client is in control of this ack */ 626dc78baa2SNicolas Ferre 627dc78baa2SNicolas Ferre return &first->txd; 628dc78baa2SNicolas Ferre 629dc78baa2SNicolas Ferre err_desc_get: 630dc78baa2SNicolas Ferre atc_desc_put(atchan, first); 631dc78baa2SNicolas Ferre return NULL; 632dc78baa2SNicolas Ferre } 633dc78baa2SNicolas Ferre 634808347f6SNicolas Ferre 635808347f6SNicolas Ferre /** 636808347f6SNicolas Ferre * atc_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction 637808347f6SNicolas Ferre * @chan: DMA channel 638808347f6SNicolas Ferre * @sgl: scatterlist to transfer to/from 639808347f6SNicolas Ferre * @sg_len: number of entries in @scatterlist 640808347f6SNicolas Ferre * @direction: DMA direction 641808347f6SNicolas Ferre * @flags: tx descriptor status flags 642808347f6SNicolas Ferre */ 643808347f6SNicolas Ferre static struct dma_async_tx_descriptor * 644808347f6SNicolas Ferre atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, 645db8196dfSVinod Koul unsigned int sg_len, enum dma_transfer_direction direction, 646808347f6SNicolas Ferre unsigned long flags) 647808347f6SNicolas Ferre { 648808347f6SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 649808347f6SNicolas Ferre struct at_dma_slave *atslave = chan->private; 650808347f6SNicolas Ferre struct at_desc *first = NULL; 651808347f6SNicolas Ferre struct at_desc *prev = NULL; 652808347f6SNicolas Ferre u32 ctrla; 653808347f6SNicolas Ferre u32 ctrlb; 654808347f6SNicolas Ferre dma_addr_t reg; 655808347f6SNicolas Ferre unsigned int reg_width; 656808347f6SNicolas Ferre unsigned int mem_width; 657808347f6SNicolas Ferre unsigned int i; 658808347f6SNicolas Ferre struct scatterlist *sg; 659808347f6SNicolas Ferre size_t total_len = 0; 660808347f6SNicolas Ferre 661cc52a10aSNicolas Ferre dev_vdbg(chan2dev(chan), "prep_slave_sg (%d): %s f0x%lx\n", 662cc52a10aSNicolas Ferre sg_len, 663db8196dfSVinod Koul direction == DMA_MEM_TO_DEV ? "TO DEVICE" : "FROM DEVICE", 664808347f6SNicolas Ferre flags); 665808347f6SNicolas Ferre 666808347f6SNicolas Ferre if (unlikely(!atslave || !sg_len)) { 667808347f6SNicolas Ferre dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n"); 668808347f6SNicolas Ferre return NULL; 669808347f6SNicolas Ferre } 670808347f6SNicolas Ferre 671808347f6SNicolas Ferre reg_width = atslave->reg_width; 672808347f6SNicolas Ferre 673808347f6SNicolas Ferre ctrla = ATC_DEFAULT_CTRLA | atslave->ctrla; 674ae14d4b5SNicolas Ferre ctrlb = ATC_IEN; 675808347f6SNicolas Ferre 676808347f6SNicolas Ferre switch (direction) { 677db8196dfSVinod Koul case DMA_MEM_TO_DEV: 678808347f6SNicolas Ferre ctrla |= ATC_DST_WIDTH(reg_width); 679808347f6SNicolas Ferre ctrlb |= ATC_DST_ADDR_MODE_FIXED 680808347f6SNicolas Ferre | ATC_SRC_ADDR_MODE_INCR 681ae14d4b5SNicolas Ferre | ATC_FC_MEM2PER 682ae14d4b5SNicolas Ferre | ATC_SIF(AT_DMA_MEM_IF) | ATC_DIF(AT_DMA_PER_IF); 683808347f6SNicolas Ferre reg = atslave->tx_reg; 684808347f6SNicolas Ferre for_each_sg(sgl, sg, sg_len, i) { 685808347f6SNicolas Ferre struct at_desc *desc; 686808347f6SNicolas Ferre u32 len; 687808347f6SNicolas Ferre u32 mem; 688808347f6SNicolas Ferre 689808347f6SNicolas Ferre desc = atc_desc_get(atchan); 690808347f6SNicolas Ferre if (!desc) 691808347f6SNicolas Ferre goto err_desc_get; 692808347f6SNicolas Ferre 6930f70e8ceSNicolas Ferre mem = sg_dma_address(sg); 694808347f6SNicolas Ferre len = sg_dma_len(sg); 695808347f6SNicolas Ferre mem_width = 2; 696808347f6SNicolas Ferre if (unlikely(mem & 3 || len & 3)) 697808347f6SNicolas Ferre mem_width = 0; 698808347f6SNicolas Ferre 699808347f6SNicolas Ferre desc->lli.saddr = mem; 700808347f6SNicolas Ferre desc->lli.daddr = reg; 701808347f6SNicolas Ferre desc->lli.ctrla = ctrla 702808347f6SNicolas Ferre | ATC_SRC_WIDTH(mem_width) 703808347f6SNicolas Ferre | len >> mem_width; 704808347f6SNicolas Ferre desc->lli.ctrlb = ctrlb; 705808347f6SNicolas Ferre 706e257e156SNicolas Ferre atc_desc_chain(&first, &prev, desc); 707808347f6SNicolas Ferre total_len += len; 708808347f6SNicolas Ferre } 709808347f6SNicolas Ferre break; 710db8196dfSVinod Koul case DMA_DEV_TO_MEM: 711808347f6SNicolas Ferre ctrla |= ATC_SRC_WIDTH(reg_width); 712808347f6SNicolas Ferre ctrlb |= ATC_DST_ADDR_MODE_INCR 713808347f6SNicolas Ferre | ATC_SRC_ADDR_MODE_FIXED 714ae14d4b5SNicolas Ferre | ATC_FC_PER2MEM 715ae14d4b5SNicolas Ferre | ATC_SIF(AT_DMA_PER_IF) | ATC_DIF(AT_DMA_MEM_IF); 716808347f6SNicolas Ferre 717808347f6SNicolas Ferre reg = atslave->rx_reg; 718808347f6SNicolas Ferre for_each_sg(sgl, sg, sg_len, i) { 719808347f6SNicolas Ferre struct at_desc *desc; 720808347f6SNicolas Ferre u32 len; 721808347f6SNicolas Ferre u32 mem; 722808347f6SNicolas Ferre 723808347f6SNicolas Ferre desc = atc_desc_get(atchan); 724808347f6SNicolas Ferre if (!desc) 725808347f6SNicolas Ferre goto err_desc_get; 726808347f6SNicolas Ferre 7270f70e8ceSNicolas Ferre mem = sg_dma_address(sg); 728808347f6SNicolas Ferre len = sg_dma_len(sg); 729808347f6SNicolas Ferre mem_width = 2; 730808347f6SNicolas Ferre if (unlikely(mem & 3 || len & 3)) 731808347f6SNicolas Ferre mem_width = 0; 732808347f6SNicolas Ferre 733808347f6SNicolas Ferre desc->lli.saddr = reg; 734808347f6SNicolas Ferre desc->lli.daddr = mem; 735808347f6SNicolas Ferre desc->lli.ctrla = ctrla 736808347f6SNicolas Ferre | ATC_DST_WIDTH(mem_width) 73759a609d9SNicolas Ferre | len >> reg_width; 738808347f6SNicolas Ferre desc->lli.ctrlb = ctrlb; 739808347f6SNicolas Ferre 740e257e156SNicolas Ferre atc_desc_chain(&first, &prev, desc); 741808347f6SNicolas Ferre total_len += len; 742808347f6SNicolas Ferre } 743808347f6SNicolas Ferre break; 744808347f6SNicolas Ferre default: 745808347f6SNicolas Ferre return NULL; 746808347f6SNicolas Ferre } 747808347f6SNicolas Ferre 748808347f6SNicolas Ferre /* set end-of-link to the last link descriptor of list*/ 749808347f6SNicolas Ferre set_desc_eol(prev); 750808347f6SNicolas Ferre 751808347f6SNicolas Ferre /* First descriptor of the chain embedds additional information */ 752808347f6SNicolas Ferre first->txd.cookie = -EBUSY; 753808347f6SNicolas Ferre first->len = total_len; 754808347f6SNicolas Ferre 755568f7f0cSNicolas Ferre /* first link descriptor of list is responsible of flags */ 756568f7f0cSNicolas Ferre first->txd.flags = flags; /* client is in control of this ack */ 757808347f6SNicolas Ferre 758808347f6SNicolas Ferre return &first->txd; 759808347f6SNicolas Ferre 760808347f6SNicolas Ferre err_desc_get: 761808347f6SNicolas Ferre dev_err(chan2dev(chan), "not enough descriptors available\n"); 762808347f6SNicolas Ferre atc_desc_put(atchan, first); 763808347f6SNicolas Ferre return NULL; 764808347f6SNicolas Ferre } 765808347f6SNicolas Ferre 76653830cc7SNicolas Ferre /** 76753830cc7SNicolas Ferre * atc_dma_cyclic_check_values 76853830cc7SNicolas Ferre * Check for too big/unaligned periods and unaligned DMA buffer 76953830cc7SNicolas Ferre */ 77053830cc7SNicolas Ferre static int 77153830cc7SNicolas Ferre atc_dma_cyclic_check_values(unsigned int reg_width, dma_addr_t buf_addr, 772db8196dfSVinod Koul size_t period_len, enum dma_transfer_direction direction) 77353830cc7SNicolas Ferre { 77453830cc7SNicolas Ferre if (period_len > (ATC_BTSIZE_MAX << reg_width)) 77553830cc7SNicolas Ferre goto err_out; 77653830cc7SNicolas Ferre if (unlikely(period_len & ((1 << reg_width) - 1))) 77753830cc7SNicolas Ferre goto err_out; 77853830cc7SNicolas Ferre if (unlikely(buf_addr & ((1 << reg_width) - 1))) 77953830cc7SNicolas Ferre goto err_out; 780db8196dfSVinod Koul if (unlikely(!(direction & (DMA_DEV_TO_MEM | DMA_MEM_TO_DEV)))) 78153830cc7SNicolas Ferre goto err_out; 78253830cc7SNicolas Ferre 78353830cc7SNicolas Ferre return 0; 78453830cc7SNicolas Ferre 78553830cc7SNicolas Ferre err_out: 78653830cc7SNicolas Ferre return -EINVAL; 78753830cc7SNicolas Ferre } 78853830cc7SNicolas Ferre 78953830cc7SNicolas Ferre /** 79053830cc7SNicolas Ferre * atc_dma_cyclic_fill_desc - Fill one period decriptor 79153830cc7SNicolas Ferre */ 79253830cc7SNicolas Ferre static int 79353830cc7SNicolas Ferre atc_dma_cyclic_fill_desc(struct at_dma_slave *atslave, struct at_desc *desc, 79453830cc7SNicolas Ferre unsigned int period_index, dma_addr_t buf_addr, 795db8196dfSVinod Koul size_t period_len, enum dma_transfer_direction direction) 79653830cc7SNicolas Ferre { 79753830cc7SNicolas Ferre u32 ctrla; 79853830cc7SNicolas Ferre unsigned int reg_width = atslave->reg_width; 79953830cc7SNicolas Ferre 80053830cc7SNicolas Ferre /* prepare common CRTLA value */ 80153830cc7SNicolas Ferre ctrla = ATC_DEFAULT_CTRLA | atslave->ctrla 80253830cc7SNicolas Ferre | ATC_DST_WIDTH(reg_width) 80353830cc7SNicolas Ferre | ATC_SRC_WIDTH(reg_width) 80453830cc7SNicolas Ferre | period_len >> reg_width; 80553830cc7SNicolas Ferre 80653830cc7SNicolas Ferre switch (direction) { 807db8196dfSVinod Koul case DMA_MEM_TO_DEV: 80853830cc7SNicolas Ferre desc->lli.saddr = buf_addr + (period_len * period_index); 80953830cc7SNicolas Ferre desc->lli.daddr = atslave->tx_reg; 81053830cc7SNicolas Ferre desc->lli.ctrla = ctrla; 811ae14d4b5SNicolas Ferre desc->lli.ctrlb = ATC_DST_ADDR_MODE_FIXED 81253830cc7SNicolas Ferre | ATC_SRC_ADDR_MODE_INCR 813ae14d4b5SNicolas Ferre | ATC_FC_MEM2PER 814ae14d4b5SNicolas Ferre | ATC_SIF(AT_DMA_MEM_IF) 815ae14d4b5SNicolas Ferre | ATC_DIF(AT_DMA_PER_IF); 81653830cc7SNicolas Ferre break; 81753830cc7SNicolas Ferre 818db8196dfSVinod Koul case DMA_DEV_TO_MEM: 81953830cc7SNicolas Ferre desc->lli.saddr = atslave->rx_reg; 82053830cc7SNicolas Ferre desc->lli.daddr = buf_addr + (period_len * period_index); 82153830cc7SNicolas Ferre desc->lli.ctrla = ctrla; 822ae14d4b5SNicolas Ferre desc->lli.ctrlb = ATC_DST_ADDR_MODE_INCR 82353830cc7SNicolas Ferre | ATC_SRC_ADDR_MODE_FIXED 824ae14d4b5SNicolas Ferre | ATC_FC_PER2MEM 825ae14d4b5SNicolas Ferre | ATC_SIF(AT_DMA_PER_IF) 826ae14d4b5SNicolas Ferre | ATC_DIF(AT_DMA_MEM_IF); 82753830cc7SNicolas Ferre break; 82853830cc7SNicolas Ferre 82953830cc7SNicolas Ferre default: 83053830cc7SNicolas Ferre return -EINVAL; 83153830cc7SNicolas Ferre } 83253830cc7SNicolas Ferre 83353830cc7SNicolas Ferre return 0; 83453830cc7SNicolas Ferre } 83553830cc7SNicolas Ferre 83653830cc7SNicolas Ferre /** 83753830cc7SNicolas Ferre * atc_prep_dma_cyclic - prepare the cyclic DMA transfer 83853830cc7SNicolas Ferre * @chan: the DMA channel to prepare 83953830cc7SNicolas Ferre * @buf_addr: physical DMA address where the buffer starts 84053830cc7SNicolas Ferre * @buf_len: total number of bytes for the entire buffer 84153830cc7SNicolas Ferre * @period_len: number of bytes for each period 84253830cc7SNicolas Ferre * @direction: transfer direction, to or from device 84353830cc7SNicolas Ferre */ 84453830cc7SNicolas Ferre static struct dma_async_tx_descriptor * 84553830cc7SNicolas Ferre atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, 846db8196dfSVinod Koul size_t period_len, enum dma_transfer_direction direction) 84753830cc7SNicolas Ferre { 84853830cc7SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 84953830cc7SNicolas Ferre struct at_dma_slave *atslave = chan->private; 85053830cc7SNicolas Ferre struct at_desc *first = NULL; 85153830cc7SNicolas Ferre struct at_desc *prev = NULL; 85253830cc7SNicolas Ferre unsigned long was_cyclic; 85353830cc7SNicolas Ferre unsigned int periods = buf_len / period_len; 85453830cc7SNicolas Ferre unsigned int i; 85553830cc7SNicolas Ferre 85653830cc7SNicolas Ferre dev_vdbg(chan2dev(chan), "prep_dma_cyclic: %s buf@0x%08x - %d (%d/%d)\n", 857db8196dfSVinod Koul direction == DMA_MEM_TO_DEV ? "TO DEVICE" : "FROM DEVICE", 85853830cc7SNicolas Ferre buf_addr, 85953830cc7SNicolas Ferre periods, buf_len, period_len); 86053830cc7SNicolas Ferre 86153830cc7SNicolas Ferre if (unlikely(!atslave || !buf_len || !period_len)) { 86253830cc7SNicolas Ferre dev_dbg(chan2dev(chan), "prep_dma_cyclic: length is zero!\n"); 86353830cc7SNicolas Ferre return NULL; 86453830cc7SNicolas Ferre } 86553830cc7SNicolas Ferre 86653830cc7SNicolas Ferre was_cyclic = test_and_set_bit(ATC_IS_CYCLIC, &atchan->status); 86753830cc7SNicolas Ferre if (was_cyclic) { 86853830cc7SNicolas Ferre dev_dbg(chan2dev(chan), "prep_dma_cyclic: channel in use!\n"); 86953830cc7SNicolas Ferre return NULL; 87053830cc7SNicolas Ferre } 87153830cc7SNicolas Ferre 87253830cc7SNicolas Ferre /* Check for too big/unaligned periods and unaligned DMA buffer */ 87353830cc7SNicolas Ferre if (atc_dma_cyclic_check_values(atslave->reg_width, buf_addr, 87453830cc7SNicolas Ferre period_len, direction)) 87553830cc7SNicolas Ferre goto err_out; 87653830cc7SNicolas Ferre 87753830cc7SNicolas Ferre /* build cyclic linked list */ 87853830cc7SNicolas Ferre for (i = 0; i < periods; i++) { 87953830cc7SNicolas Ferre struct at_desc *desc; 88053830cc7SNicolas Ferre 88153830cc7SNicolas Ferre desc = atc_desc_get(atchan); 88253830cc7SNicolas Ferre if (!desc) 88353830cc7SNicolas Ferre goto err_desc_get; 88453830cc7SNicolas Ferre 88553830cc7SNicolas Ferre if (atc_dma_cyclic_fill_desc(atslave, desc, i, buf_addr, 88653830cc7SNicolas Ferre period_len, direction)) 88753830cc7SNicolas Ferre goto err_desc_get; 88853830cc7SNicolas Ferre 88953830cc7SNicolas Ferre atc_desc_chain(&first, &prev, desc); 89053830cc7SNicolas Ferre } 89153830cc7SNicolas Ferre 89253830cc7SNicolas Ferre /* lets make a cyclic list */ 89353830cc7SNicolas Ferre prev->lli.dscr = first->txd.phys; 89453830cc7SNicolas Ferre 89553830cc7SNicolas Ferre /* First descriptor of the chain embedds additional information */ 89653830cc7SNicolas Ferre first->txd.cookie = -EBUSY; 89753830cc7SNicolas Ferre first->len = buf_len; 89853830cc7SNicolas Ferre 89953830cc7SNicolas Ferre return &first->txd; 90053830cc7SNicolas Ferre 90153830cc7SNicolas Ferre err_desc_get: 90253830cc7SNicolas Ferre dev_err(chan2dev(chan), "not enough descriptors available\n"); 90353830cc7SNicolas Ferre atc_desc_put(atchan, first); 90453830cc7SNicolas Ferre err_out: 90553830cc7SNicolas Ferre clear_bit(ATC_IS_CYCLIC, &atchan->status); 90653830cc7SNicolas Ferre return NULL; 90753830cc7SNicolas Ferre } 90853830cc7SNicolas Ferre 90953830cc7SNicolas Ferre 91005827630SLinus Walleij static int atc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, 91105827630SLinus Walleij unsigned long arg) 912808347f6SNicolas Ferre { 913808347f6SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 914808347f6SNicolas Ferre struct at_dma *atdma = to_at_dma(chan->device); 91523b5e3adSNicolas Ferre int chan_id = atchan->chan_common.chan_id; 916d8cb04b0SNicolas Ferre unsigned long flags; 91723b5e3adSNicolas Ferre 918808347f6SNicolas Ferre LIST_HEAD(list); 919808347f6SNicolas Ferre 92023b5e3adSNicolas Ferre dev_vdbg(chan2dev(chan), "atc_control (%d)\n", cmd); 921c3635c78SLinus Walleij 92223b5e3adSNicolas Ferre if (cmd == DMA_PAUSE) { 923d8cb04b0SNicolas Ferre spin_lock_irqsave(&atchan->lock, flags); 92423b5e3adSNicolas Ferre 92523b5e3adSNicolas Ferre dma_writel(atdma, CHER, AT_DMA_SUSP(chan_id)); 92623b5e3adSNicolas Ferre set_bit(ATC_IS_PAUSED, &atchan->status); 92723b5e3adSNicolas Ferre 928d8cb04b0SNicolas Ferre spin_unlock_irqrestore(&atchan->lock, flags); 92923b5e3adSNicolas Ferre } else if (cmd == DMA_RESUME) { 9303c477482SNicolas Ferre if (!atc_chan_is_paused(atchan)) 93123b5e3adSNicolas Ferre return 0; 93223b5e3adSNicolas Ferre 933d8cb04b0SNicolas Ferre spin_lock_irqsave(&atchan->lock, flags); 93423b5e3adSNicolas Ferre 93523b5e3adSNicolas Ferre dma_writel(atdma, CHDR, AT_DMA_RES(chan_id)); 93623b5e3adSNicolas Ferre clear_bit(ATC_IS_PAUSED, &atchan->status); 93723b5e3adSNicolas Ferre 938d8cb04b0SNicolas Ferre spin_unlock_irqrestore(&atchan->lock, flags); 93923b5e3adSNicolas Ferre } else if (cmd == DMA_TERMINATE_ALL) { 94023b5e3adSNicolas Ferre struct at_desc *desc, *_desc; 941808347f6SNicolas Ferre /* 942808347f6SNicolas Ferre * This is only called when something went wrong elsewhere, so 943808347f6SNicolas Ferre * we don't really care about the data. Just disable the 944808347f6SNicolas Ferre * channel. We still have to poll the channel enable bit due 945808347f6SNicolas Ferre * to AHB/HSB limitations. 946808347f6SNicolas Ferre */ 947d8cb04b0SNicolas Ferre spin_lock_irqsave(&atchan->lock, flags); 948808347f6SNicolas Ferre 94923b5e3adSNicolas Ferre /* disabling channel: must also remove suspend state */ 95023b5e3adSNicolas Ferre dma_writel(atdma, CHDR, AT_DMA_RES(chan_id) | atchan->mask); 951808347f6SNicolas Ferre 952808347f6SNicolas Ferre /* confirm that this channel is disabled */ 953808347f6SNicolas Ferre while (dma_readl(atdma, CHSR) & atchan->mask) 954808347f6SNicolas Ferre cpu_relax(); 955808347f6SNicolas Ferre 956808347f6SNicolas Ferre /* active_list entries will end up before queued entries */ 957808347f6SNicolas Ferre list_splice_init(&atchan->queue, &list); 958808347f6SNicolas Ferre list_splice_init(&atchan->active_list, &list); 959808347f6SNicolas Ferre 960808347f6SNicolas Ferre /* Flush all pending and queued descriptors */ 961808347f6SNicolas Ferre list_for_each_entry_safe(desc, _desc, &list, desc_node) 962808347f6SNicolas Ferre atc_chain_complete(atchan, desc); 963c3635c78SLinus Walleij 96423b5e3adSNicolas Ferre clear_bit(ATC_IS_PAUSED, &atchan->status); 96553830cc7SNicolas Ferre /* if channel dedicated to cyclic operations, free it */ 96653830cc7SNicolas Ferre clear_bit(ATC_IS_CYCLIC, &atchan->status); 96753830cc7SNicolas Ferre 968d8cb04b0SNicolas Ferre spin_unlock_irqrestore(&atchan->lock, flags); 96923b5e3adSNicolas Ferre } else { 97023b5e3adSNicolas Ferre return -ENXIO; 97123b5e3adSNicolas Ferre } 972b0ebeb9cSYong Wang 973c3635c78SLinus Walleij return 0; 974808347f6SNicolas Ferre } 975808347f6SNicolas Ferre 976dc78baa2SNicolas Ferre /** 97707934481SLinus Walleij * atc_tx_status - poll for transaction completion 978dc78baa2SNicolas Ferre * @chan: DMA channel 979dc78baa2SNicolas Ferre * @cookie: transaction identifier to check status of 98007934481SLinus Walleij * @txstate: if not %NULL updated with transaction state 981dc78baa2SNicolas Ferre * 98207934481SLinus Walleij * If @txstate is passed in, upon return it reflect the driver 983dc78baa2SNicolas Ferre * internal state and can be used with dma_async_is_complete() to check 984dc78baa2SNicolas Ferre * the status of multiple cookies without re-checking hardware state. 985dc78baa2SNicolas Ferre */ 986dc78baa2SNicolas Ferre static enum dma_status 98707934481SLinus Walleij atc_tx_status(struct dma_chan *chan, 988dc78baa2SNicolas Ferre dma_cookie_t cookie, 98907934481SLinus Walleij struct dma_tx_state *txstate) 990dc78baa2SNicolas Ferre { 991dc78baa2SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 992dc78baa2SNicolas Ferre dma_cookie_t last_used; 993dc78baa2SNicolas Ferre dma_cookie_t last_complete; 994d8cb04b0SNicolas Ferre unsigned long flags; 995dc78baa2SNicolas Ferre enum dma_status ret; 996dc78baa2SNicolas Ferre 997d8cb04b0SNicolas Ferre spin_lock_irqsave(&atchan->lock, flags); 998dc78baa2SNicolas Ferre 9994d4e58deSRussell King - ARM Linux last_complete = chan->completed_cookie; 1000dc78baa2SNicolas Ferre last_used = chan->cookie; 1001dc78baa2SNicolas Ferre 1002dc78baa2SNicolas Ferre ret = dma_async_is_complete(cookie, last_complete, last_used); 1003dc78baa2SNicolas Ferre if (ret != DMA_SUCCESS) { 1004dc78baa2SNicolas Ferre atc_cleanup_descriptors(atchan); 1005dc78baa2SNicolas Ferre 10064d4e58deSRussell King - ARM Linux last_complete = chan->completed_cookie; 1007dc78baa2SNicolas Ferre last_used = chan->cookie; 1008dc78baa2SNicolas Ferre 1009dc78baa2SNicolas Ferre ret = dma_async_is_complete(cookie, last_complete, last_used); 1010dc78baa2SNicolas Ferre } 1011dc78baa2SNicolas Ferre 1012d8cb04b0SNicolas Ferre spin_unlock_irqrestore(&atchan->lock, flags); 1013dc78baa2SNicolas Ferre 1014543aabc7SNicolas Ferre if (ret != DMA_SUCCESS) 1015543aabc7SNicolas Ferre dma_set_tx_state(txstate, last_complete, last_used, 1016543aabc7SNicolas Ferre atc_first_active(atchan)->len); 1017543aabc7SNicolas Ferre else 1018bca34692SDan Williams dma_set_tx_state(txstate, last_complete, last_used, 0); 1019543aabc7SNicolas Ferre 10203c477482SNicolas Ferre if (atc_chan_is_paused(atchan)) 102123b5e3adSNicolas Ferre ret = DMA_PAUSED; 102223b5e3adSNicolas Ferre 102323b5e3adSNicolas Ferre dev_vdbg(chan2dev(chan), "tx_status %d: cookie = %d (d%d, u%d)\n", 102423b5e3adSNicolas Ferre ret, cookie, last_complete ? last_complete : 0, 102507934481SLinus Walleij last_used ? last_used : 0); 1026dc78baa2SNicolas Ferre 1027dc78baa2SNicolas Ferre return ret; 1028dc78baa2SNicolas Ferre } 1029dc78baa2SNicolas Ferre 1030dc78baa2SNicolas Ferre /** 1031dc78baa2SNicolas Ferre * atc_issue_pending - try to finish work 1032dc78baa2SNicolas Ferre * @chan: target DMA channel 1033dc78baa2SNicolas Ferre */ 1034dc78baa2SNicolas Ferre static void atc_issue_pending(struct dma_chan *chan) 1035dc78baa2SNicolas Ferre { 1036dc78baa2SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 1037d8cb04b0SNicolas Ferre unsigned long flags; 1038dc78baa2SNicolas Ferre 1039dc78baa2SNicolas Ferre dev_vdbg(chan2dev(chan), "issue_pending\n"); 1040dc78baa2SNicolas Ferre 104153830cc7SNicolas Ferre /* Not needed for cyclic transfers */ 10423c477482SNicolas Ferre if (atc_chan_is_cyclic(atchan)) 104353830cc7SNicolas Ferre return; 104453830cc7SNicolas Ferre 1045d8cb04b0SNicolas Ferre spin_lock_irqsave(&atchan->lock, flags); 1046dda36f98SNicolas Ferre if (!atc_chan_is_enabled(atchan)) { 1047dc78baa2SNicolas Ferre atc_advance_work(atchan); 1048dc78baa2SNicolas Ferre } 1049d8cb04b0SNicolas Ferre spin_unlock_irqrestore(&atchan->lock, flags); 1050dc78baa2SNicolas Ferre } 1051dc78baa2SNicolas Ferre 1052dc78baa2SNicolas Ferre /** 1053dc78baa2SNicolas Ferre * atc_alloc_chan_resources - allocate resources for DMA channel 1054dc78baa2SNicolas Ferre * @chan: allocate descriptor resources for this channel 1055dc78baa2SNicolas Ferre * @client: current client requesting the channel be ready for requests 1056dc78baa2SNicolas Ferre * 1057dc78baa2SNicolas Ferre * return - the number of allocated descriptors 1058dc78baa2SNicolas Ferre */ 1059dc78baa2SNicolas Ferre static int atc_alloc_chan_resources(struct dma_chan *chan) 1060dc78baa2SNicolas Ferre { 1061dc78baa2SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 1062dc78baa2SNicolas Ferre struct at_dma *atdma = to_at_dma(chan->device); 1063dc78baa2SNicolas Ferre struct at_desc *desc; 1064808347f6SNicolas Ferre struct at_dma_slave *atslave; 1065d8cb04b0SNicolas Ferre unsigned long flags; 1066dc78baa2SNicolas Ferre int i; 1067808347f6SNicolas Ferre u32 cfg; 1068dc78baa2SNicolas Ferre LIST_HEAD(tmp_list); 1069dc78baa2SNicolas Ferre 1070dc78baa2SNicolas Ferre dev_vdbg(chan2dev(chan), "alloc_chan_resources\n"); 1071dc78baa2SNicolas Ferre 1072dc78baa2SNicolas Ferre /* ASSERT: channel is idle */ 1073dc78baa2SNicolas Ferre if (atc_chan_is_enabled(atchan)) { 1074dc78baa2SNicolas Ferre dev_dbg(chan2dev(chan), "DMA channel not idle ?\n"); 1075dc78baa2SNicolas Ferre return -EIO; 1076dc78baa2SNicolas Ferre } 1077dc78baa2SNicolas Ferre 1078808347f6SNicolas Ferre cfg = ATC_DEFAULT_CFG; 1079808347f6SNicolas Ferre 1080808347f6SNicolas Ferre atslave = chan->private; 1081808347f6SNicolas Ferre if (atslave) { 1082808347f6SNicolas Ferre /* 1083808347f6SNicolas Ferre * We need controller-specific data to set up slave 1084808347f6SNicolas Ferre * transfers. 1085808347f6SNicolas Ferre */ 1086808347f6SNicolas Ferre BUG_ON(!atslave->dma_dev || atslave->dma_dev != atdma->dma_common.dev); 1087808347f6SNicolas Ferre 1088808347f6SNicolas Ferre /* if cfg configuration specified take it instad of default */ 1089808347f6SNicolas Ferre if (atslave->cfg) 1090808347f6SNicolas Ferre cfg = atslave->cfg; 1091808347f6SNicolas Ferre } 1092808347f6SNicolas Ferre 1093808347f6SNicolas Ferre /* have we already been set up? 1094808347f6SNicolas Ferre * reconfigure channel but no need to reallocate descriptors */ 1095dc78baa2SNicolas Ferre if (!list_empty(&atchan->free_list)) 1096dc78baa2SNicolas Ferre return atchan->descs_allocated; 1097dc78baa2SNicolas Ferre 1098dc78baa2SNicolas Ferre /* Allocate initial pool of descriptors */ 1099dc78baa2SNicolas Ferre for (i = 0; i < init_nr_desc_per_channel; i++) { 1100dc78baa2SNicolas Ferre desc = atc_alloc_descriptor(chan, GFP_KERNEL); 1101dc78baa2SNicolas Ferre if (!desc) { 1102dc78baa2SNicolas Ferre dev_err(atdma->dma_common.dev, 1103dc78baa2SNicolas Ferre "Only %d initial descriptors\n", i); 1104dc78baa2SNicolas Ferre break; 1105dc78baa2SNicolas Ferre } 1106dc78baa2SNicolas Ferre list_add_tail(&desc->desc_node, &tmp_list); 1107dc78baa2SNicolas Ferre } 1108dc78baa2SNicolas Ferre 1109d8cb04b0SNicolas Ferre spin_lock_irqsave(&atchan->lock, flags); 1110dc78baa2SNicolas Ferre atchan->descs_allocated = i; 1111dc78baa2SNicolas Ferre list_splice(&tmp_list, &atchan->free_list); 11124d4e58deSRussell King - ARM Linux chan->completed_cookie = chan->cookie = 1; 1113d8cb04b0SNicolas Ferre spin_unlock_irqrestore(&atchan->lock, flags); 1114dc78baa2SNicolas Ferre 1115dc78baa2SNicolas Ferre /* channel parameters */ 1116808347f6SNicolas Ferre channel_writel(atchan, CFG, cfg); 1117dc78baa2SNicolas Ferre 1118dc78baa2SNicolas Ferre dev_dbg(chan2dev(chan), 1119dc78baa2SNicolas Ferre "alloc_chan_resources: allocated %d descriptors\n", 1120dc78baa2SNicolas Ferre atchan->descs_allocated); 1121dc78baa2SNicolas Ferre 1122dc78baa2SNicolas Ferre return atchan->descs_allocated; 1123dc78baa2SNicolas Ferre } 1124dc78baa2SNicolas Ferre 1125dc78baa2SNicolas Ferre /** 1126dc78baa2SNicolas Ferre * atc_free_chan_resources - free all channel resources 1127dc78baa2SNicolas Ferre * @chan: DMA channel 1128dc78baa2SNicolas Ferre */ 1129dc78baa2SNicolas Ferre static void atc_free_chan_resources(struct dma_chan *chan) 1130dc78baa2SNicolas Ferre { 1131dc78baa2SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 1132dc78baa2SNicolas Ferre struct at_dma *atdma = to_at_dma(chan->device); 1133dc78baa2SNicolas Ferre struct at_desc *desc, *_desc; 1134dc78baa2SNicolas Ferre LIST_HEAD(list); 1135dc78baa2SNicolas Ferre 1136dc78baa2SNicolas Ferre dev_dbg(chan2dev(chan), "free_chan_resources: (descs allocated=%u)\n", 1137dc78baa2SNicolas Ferre atchan->descs_allocated); 1138dc78baa2SNicolas Ferre 1139dc78baa2SNicolas Ferre /* ASSERT: channel is idle */ 1140dc78baa2SNicolas Ferre BUG_ON(!list_empty(&atchan->active_list)); 1141dc78baa2SNicolas Ferre BUG_ON(!list_empty(&atchan->queue)); 1142dc78baa2SNicolas Ferre BUG_ON(atc_chan_is_enabled(atchan)); 1143dc78baa2SNicolas Ferre 1144dc78baa2SNicolas Ferre list_for_each_entry_safe(desc, _desc, &atchan->free_list, desc_node) { 1145dc78baa2SNicolas Ferre dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc); 1146dc78baa2SNicolas Ferre list_del(&desc->desc_node); 1147dc78baa2SNicolas Ferre /* free link descriptor */ 1148dc78baa2SNicolas Ferre dma_pool_free(atdma->dma_desc_pool, desc, desc->txd.phys); 1149dc78baa2SNicolas Ferre } 1150dc78baa2SNicolas Ferre list_splice_init(&atchan->free_list, &list); 1151dc78baa2SNicolas Ferre atchan->descs_allocated = 0; 115253830cc7SNicolas Ferre atchan->status = 0; 1153dc78baa2SNicolas Ferre 1154dc78baa2SNicolas Ferre dev_vdbg(chan2dev(chan), "free_chan_resources: done\n"); 1155dc78baa2SNicolas Ferre } 1156dc78baa2SNicolas Ferre 1157dc78baa2SNicolas Ferre 1158dc78baa2SNicolas Ferre /*-- Module Management -----------------------------------------------*/ 1159dc78baa2SNicolas Ferre 116002f88be9SNicolas Ferre /* cap_mask is a multi-u32 bitfield, fill it with proper C code. */ 116102f88be9SNicolas Ferre static struct at_dma_platform_data at91sam9rl_config = { 116202f88be9SNicolas Ferre .nr_channels = 2, 116302f88be9SNicolas Ferre }; 116402f88be9SNicolas Ferre static struct at_dma_platform_data at91sam9g45_config = { 116502f88be9SNicolas Ferre .nr_channels = 8, 116602f88be9SNicolas Ferre }; 116702f88be9SNicolas Ferre 1168c5115953SNicolas Ferre #if defined(CONFIG_OF) 1169c5115953SNicolas Ferre static const struct of_device_id atmel_dma_dt_ids[] = { 1170c5115953SNicolas Ferre { 1171c5115953SNicolas Ferre .compatible = "atmel,at91sam9rl-dma", 117202f88be9SNicolas Ferre .data = &at91sam9rl_config, 1173c5115953SNicolas Ferre }, { 1174c5115953SNicolas Ferre .compatible = "atmel,at91sam9g45-dma", 117502f88be9SNicolas Ferre .data = &at91sam9g45_config, 1176dcc81734SNicolas Ferre }, { 1177dcc81734SNicolas Ferre /* sentinel */ 1178dcc81734SNicolas Ferre } 1179c5115953SNicolas Ferre }; 1180c5115953SNicolas Ferre 1181c5115953SNicolas Ferre MODULE_DEVICE_TABLE(of, atmel_dma_dt_ids); 1182c5115953SNicolas Ferre #endif 1183c5115953SNicolas Ferre 11840ab88a01SNicolas Ferre static const struct platform_device_id atdma_devtypes[] = { 118567348450SNicolas Ferre { 118667348450SNicolas Ferre .name = "at91sam9rl_dma", 118702f88be9SNicolas Ferre .driver_data = (unsigned long) &at91sam9rl_config, 118867348450SNicolas Ferre }, { 118967348450SNicolas Ferre .name = "at91sam9g45_dma", 119002f88be9SNicolas Ferre .driver_data = (unsigned long) &at91sam9g45_config, 119167348450SNicolas Ferre }, { 119267348450SNicolas Ferre /* sentinel */ 119367348450SNicolas Ferre } 119467348450SNicolas Ferre }; 119567348450SNicolas Ferre 119602f88be9SNicolas Ferre static inline struct at_dma_platform_data * __init at_dma_get_driver_data( 1197c5115953SNicolas Ferre struct platform_device *pdev) 1198c5115953SNicolas Ferre { 1199c5115953SNicolas Ferre if (pdev->dev.of_node) { 1200c5115953SNicolas Ferre const struct of_device_id *match; 1201c5115953SNicolas Ferre match = of_match_node(atmel_dma_dt_ids, pdev->dev.of_node); 1202c5115953SNicolas Ferre if (match == NULL) 120302f88be9SNicolas Ferre return NULL; 120402f88be9SNicolas Ferre return match->data; 1205c5115953SNicolas Ferre } 120602f88be9SNicolas Ferre return (struct at_dma_platform_data *) 120702f88be9SNicolas Ferre platform_get_device_id(pdev)->driver_data; 1208c5115953SNicolas Ferre } 1209c5115953SNicolas Ferre 1210dc78baa2SNicolas Ferre /** 1211dc78baa2SNicolas Ferre * at_dma_off - disable DMA controller 1212dc78baa2SNicolas Ferre * @atdma: the Atmel HDAMC device 1213dc78baa2SNicolas Ferre */ 1214dc78baa2SNicolas Ferre static void at_dma_off(struct at_dma *atdma) 1215dc78baa2SNicolas Ferre { 1216dc78baa2SNicolas Ferre dma_writel(atdma, EN, 0); 1217dc78baa2SNicolas Ferre 1218dc78baa2SNicolas Ferre /* disable all interrupts */ 1219dc78baa2SNicolas Ferre dma_writel(atdma, EBCIDR, -1L); 1220dc78baa2SNicolas Ferre 1221dc78baa2SNicolas Ferre /* confirm that all channels are disabled */ 1222dc78baa2SNicolas Ferre while (dma_readl(atdma, CHSR) & atdma->all_chan_mask) 1223dc78baa2SNicolas Ferre cpu_relax(); 1224dc78baa2SNicolas Ferre } 1225dc78baa2SNicolas Ferre 1226dc78baa2SNicolas Ferre static int __init at_dma_probe(struct platform_device *pdev) 1227dc78baa2SNicolas Ferre { 1228dc78baa2SNicolas Ferre struct resource *io; 1229dc78baa2SNicolas Ferre struct at_dma *atdma; 1230dc78baa2SNicolas Ferre size_t size; 1231dc78baa2SNicolas Ferre int irq; 1232dc78baa2SNicolas Ferre int err; 1233dc78baa2SNicolas Ferre int i; 123402f88be9SNicolas Ferre struct at_dma_platform_data *plat_dat; 1235dc78baa2SNicolas Ferre 123602f88be9SNicolas Ferre /* setup platform data for each SoC */ 123702f88be9SNicolas Ferre dma_cap_set(DMA_MEMCPY, at91sam9rl_config.cap_mask); 123802f88be9SNicolas Ferre dma_cap_set(DMA_MEMCPY, at91sam9g45_config.cap_mask); 123902f88be9SNicolas Ferre dma_cap_set(DMA_SLAVE, at91sam9g45_config.cap_mask); 124067348450SNicolas Ferre 124167348450SNicolas Ferre /* get DMA parameters from controller type */ 124202f88be9SNicolas Ferre plat_dat = at_dma_get_driver_data(pdev); 124302f88be9SNicolas Ferre if (!plat_dat) 124402f88be9SNicolas Ferre return -ENODEV; 1245dc78baa2SNicolas Ferre 1246dc78baa2SNicolas Ferre io = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1247dc78baa2SNicolas Ferre if (!io) 1248dc78baa2SNicolas Ferre return -EINVAL; 1249dc78baa2SNicolas Ferre 1250dc78baa2SNicolas Ferre irq = platform_get_irq(pdev, 0); 1251dc78baa2SNicolas Ferre if (irq < 0) 1252dc78baa2SNicolas Ferre return irq; 1253dc78baa2SNicolas Ferre 1254dc78baa2SNicolas Ferre size = sizeof(struct at_dma); 125502f88be9SNicolas Ferre size += plat_dat->nr_channels * sizeof(struct at_dma_chan); 1256dc78baa2SNicolas Ferre atdma = kzalloc(size, GFP_KERNEL); 1257dc78baa2SNicolas Ferre if (!atdma) 1258dc78baa2SNicolas Ferre return -ENOMEM; 1259dc78baa2SNicolas Ferre 126067348450SNicolas Ferre /* discover transaction capabilities */ 126102f88be9SNicolas Ferre atdma->dma_common.cap_mask = plat_dat->cap_mask; 126202f88be9SNicolas Ferre atdma->all_chan_mask = (1 << plat_dat->nr_channels) - 1; 1263dc78baa2SNicolas Ferre 1264114df7d6SH Hartley Sweeten size = resource_size(io); 1265dc78baa2SNicolas Ferre if (!request_mem_region(io->start, size, pdev->dev.driver->name)) { 1266dc78baa2SNicolas Ferre err = -EBUSY; 1267dc78baa2SNicolas Ferre goto err_kfree; 1268dc78baa2SNicolas Ferre } 1269dc78baa2SNicolas Ferre 1270dc78baa2SNicolas Ferre atdma->regs = ioremap(io->start, size); 1271dc78baa2SNicolas Ferre if (!atdma->regs) { 1272dc78baa2SNicolas Ferre err = -ENOMEM; 1273dc78baa2SNicolas Ferre goto err_release_r; 1274dc78baa2SNicolas Ferre } 1275dc78baa2SNicolas Ferre 1276dc78baa2SNicolas Ferre atdma->clk = clk_get(&pdev->dev, "dma_clk"); 1277dc78baa2SNicolas Ferre if (IS_ERR(atdma->clk)) { 1278dc78baa2SNicolas Ferre err = PTR_ERR(atdma->clk); 1279dc78baa2SNicolas Ferre goto err_clk; 1280dc78baa2SNicolas Ferre } 1281dc78baa2SNicolas Ferre clk_enable(atdma->clk); 1282dc78baa2SNicolas Ferre 1283dc78baa2SNicolas Ferre /* force dma off, just in case */ 1284dc78baa2SNicolas Ferre at_dma_off(atdma); 1285dc78baa2SNicolas Ferre 1286dc78baa2SNicolas Ferre err = request_irq(irq, at_dma_interrupt, 0, "at_hdmac", atdma); 1287dc78baa2SNicolas Ferre if (err) 1288dc78baa2SNicolas Ferre goto err_irq; 1289dc78baa2SNicolas Ferre 1290dc78baa2SNicolas Ferre platform_set_drvdata(pdev, atdma); 1291dc78baa2SNicolas Ferre 1292dc78baa2SNicolas Ferre /* create a pool of consistent memory blocks for hardware descriptors */ 1293dc78baa2SNicolas Ferre atdma->dma_desc_pool = dma_pool_create("at_hdmac_desc_pool", 1294dc78baa2SNicolas Ferre &pdev->dev, sizeof(struct at_desc), 1295dc78baa2SNicolas Ferre 4 /* word alignment */, 0); 1296dc78baa2SNicolas Ferre if (!atdma->dma_desc_pool) { 1297dc78baa2SNicolas Ferre dev_err(&pdev->dev, "No memory for descriptors dma pool\n"); 1298dc78baa2SNicolas Ferre err = -ENOMEM; 1299dc78baa2SNicolas Ferre goto err_pool_create; 1300dc78baa2SNicolas Ferre } 1301dc78baa2SNicolas Ferre 1302dc78baa2SNicolas Ferre /* clear any pending interrupt */ 1303dc78baa2SNicolas Ferre while (dma_readl(atdma, EBCISR)) 1304dc78baa2SNicolas Ferre cpu_relax(); 1305dc78baa2SNicolas Ferre 1306dc78baa2SNicolas Ferre /* initialize channels related values */ 1307dc78baa2SNicolas Ferre INIT_LIST_HEAD(&atdma->dma_common.channels); 130802f88be9SNicolas Ferre for (i = 0; i < plat_dat->nr_channels; i++) { 1309dc78baa2SNicolas Ferre struct at_dma_chan *atchan = &atdma->chan[i]; 1310dc78baa2SNicolas Ferre 1311dc78baa2SNicolas Ferre atchan->chan_common.device = &atdma->dma_common; 13124d4e58deSRussell King - ARM Linux atchan->chan_common.cookie = atchan->chan_common.completed_cookie = 1; 1313dc78baa2SNicolas Ferre list_add_tail(&atchan->chan_common.device_node, 1314dc78baa2SNicolas Ferre &atdma->dma_common.channels); 1315dc78baa2SNicolas Ferre 1316dc78baa2SNicolas Ferre atchan->ch_regs = atdma->regs + ch_regs(i); 1317dc78baa2SNicolas Ferre spin_lock_init(&atchan->lock); 1318dc78baa2SNicolas Ferre atchan->mask = 1 << i; 1319dc78baa2SNicolas Ferre 1320dc78baa2SNicolas Ferre INIT_LIST_HEAD(&atchan->active_list); 1321dc78baa2SNicolas Ferre INIT_LIST_HEAD(&atchan->queue); 1322dc78baa2SNicolas Ferre INIT_LIST_HEAD(&atchan->free_list); 1323dc78baa2SNicolas Ferre 1324dc78baa2SNicolas Ferre tasklet_init(&atchan->tasklet, atc_tasklet, 1325dc78baa2SNicolas Ferre (unsigned long)atchan); 1326bda3a47cSNikolaus Voss atc_enable_chan_irq(atdma, i); 1327dc78baa2SNicolas Ferre } 1328dc78baa2SNicolas Ferre 1329dc78baa2SNicolas Ferre /* set base routines */ 1330dc78baa2SNicolas Ferre atdma->dma_common.device_alloc_chan_resources = atc_alloc_chan_resources; 1331dc78baa2SNicolas Ferre atdma->dma_common.device_free_chan_resources = atc_free_chan_resources; 133207934481SLinus Walleij atdma->dma_common.device_tx_status = atc_tx_status; 1333dc78baa2SNicolas Ferre atdma->dma_common.device_issue_pending = atc_issue_pending; 1334dc78baa2SNicolas Ferre atdma->dma_common.dev = &pdev->dev; 1335dc78baa2SNicolas Ferre 1336dc78baa2SNicolas Ferre /* set prep routines based on capability */ 1337dc78baa2SNicolas Ferre if (dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask)) 1338dc78baa2SNicolas Ferre atdma->dma_common.device_prep_dma_memcpy = atc_prep_dma_memcpy; 1339dc78baa2SNicolas Ferre 1340d7db8080SNicolas Ferre if (dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask)) { 1341808347f6SNicolas Ferre atdma->dma_common.device_prep_slave_sg = atc_prep_slave_sg; 1342d7db8080SNicolas Ferre /* controller can do slave DMA: can trigger cyclic transfers */ 1343d7db8080SNicolas Ferre dma_cap_set(DMA_CYCLIC, atdma->dma_common.cap_mask); 134453830cc7SNicolas Ferre atdma->dma_common.device_prep_dma_cyclic = atc_prep_dma_cyclic; 1345c3635c78SLinus Walleij atdma->dma_common.device_control = atc_control; 1346d7db8080SNicolas Ferre } 1347808347f6SNicolas Ferre 1348dc78baa2SNicolas Ferre dma_writel(atdma, EN, AT_DMA_ENABLE); 1349dc78baa2SNicolas Ferre 1350dc78baa2SNicolas Ferre dev_info(&pdev->dev, "Atmel AHB DMA Controller ( %s%s), %d channels\n", 1351dc78baa2SNicolas Ferre dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask) ? "cpy " : "", 1352dc78baa2SNicolas Ferre dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask) ? "slave " : "", 135302f88be9SNicolas Ferre plat_dat->nr_channels); 1354dc78baa2SNicolas Ferre 1355dc78baa2SNicolas Ferre dma_async_device_register(&atdma->dma_common); 1356dc78baa2SNicolas Ferre 1357dc78baa2SNicolas Ferre return 0; 1358dc78baa2SNicolas Ferre 1359dc78baa2SNicolas Ferre err_pool_create: 1360dc78baa2SNicolas Ferre platform_set_drvdata(pdev, NULL); 1361dc78baa2SNicolas Ferre free_irq(platform_get_irq(pdev, 0), atdma); 1362dc78baa2SNicolas Ferre err_irq: 1363dc78baa2SNicolas Ferre clk_disable(atdma->clk); 1364dc78baa2SNicolas Ferre clk_put(atdma->clk); 1365dc78baa2SNicolas Ferre err_clk: 1366dc78baa2SNicolas Ferre iounmap(atdma->regs); 1367dc78baa2SNicolas Ferre atdma->regs = NULL; 1368dc78baa2SNicolas Ferre err_release_r: 1369dc78baa2SNicolas Ferre release_mem_region(io->start, size); 1370dc78baa2SNicolas Ferre err_kfree: 1371dc78baa2SNicolas Ferre kfree(atdma); 1372dc78baa2SNicolas Ferre return err; 1373dc78baa2SNicolas Ferre } 1374dc78baa2SNicolas Ferre 1375dc78baa2SNicolas Ferre static int __exit at_dma_remove(struct platform_device *pdev) 1376dc78baa2SNicolas Ferre { 1377dc78baa2SNicolas Ferre struct at_dma *atdma = platform_get_drvdata(pdev); 1378dc78baa2SNicolas Ferre struct dma_chan *chan, *_chan; 1379dc78baa2SNicolas Ferre struct resource *io; 1380dc78baa2SNicolas Ferre 1381dc78baa2SNicolas Ferre at_dma_off(atdma); 1382dc78baa2SNicolas Ferre dma_async_device_unregister(&atdma->dma_common); 1383dc78baa2SNicolas Ferre 1384dc78baa2SNicolas Ferre dma_pool_destroy(atdma->dma_desc_pool); 1385dc78baa2SNicolas Ferre platform_set_drvdata(pdev, NULL); 1386dc78baa2SNicolas Ferre free_irq(platform_get_irq(pdev, 0), atdma); 1387dc78baa2SNicolas Ferre 1388dc78baa2SNicolas Ferre list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels, 1389dc78baa2SNicolas Ferre device_node) { 1390dc78baa2SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 1391dc78baa2SNicolas Ferre 1392dc78baa2SNicolas Ferre /* Disable interrupts */ 1393bda3a47cSNikolaus Voss atc_disable_chan_irq(atdma, chan->chan_id); 1394dc78baa2SNicolas Ferre tasklet_disable(&atchan->tasklet); 1395dc78baa2SNicolas Ferre 1396dc78baa2SNicolas Ferre tasklet_kill(&atchan->tasklet); 1397dc78baa2SNicolas Ferre list_del(&chan->device_node); 1398dc78baa2SNicolas Ferre } 1399dc78baa2SNicolas Ferre 1400dc78baa2SNicolas Ferre clk_disable(atdma->clk); 1401dc78baa2SNicolas Ferre clk_put(atdma->clk); 1402dc78baa2SNicolas Ferre 1403dc78baa2SNicolas Ferre iounmap(atdma->regs); 1404dc78baa2SNicolas Ferre atdma->regs = NULL; 1405dc78baa2SNicolas Ferre 1406dc78baa2SNicolas Ferre io = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1407114df7d6SH Hartley Sweeten release_mem_region(io->start, resource_size(io)); 1408dc78baa2SNicolas Ferre 1409dc78baa2SNicolas Ferre kfree(atdma); 1410dc78baa2SNicolas Ferre 1411dc78baa2SNicolas Ferre return 0; 1412dc78baa2SNicolas Ferre } 1413dc78baa2SNicolas Ferre 1414dc78baa2SNicolas Ferre static void at_dma_shutdown(struct platform_device *pdev) 1415dc78baa2SNicolas Ferre { 1416dc78baa2SNicolas Ferre struct at_dma *atdma = platform_get_drvdata(pdev); 1417dc78baa2SNicolas Ferre 1418dc78baa2SNicolas Ferre at_dma_off(platform_get_drvdata(pdev)); 1419dc78baa2SNicolas Ferre clk_disable(atdma->clk); 1420dc78baa2SNicolas Ferre } 1421dc78baa2SNicolas Ferre 1422c0ba5947SNicolas Ferre static int at_dma_prepare(struct device *dev) 1423c0ba5947SNicolas Ferre { 1424c0ba5947SNicolas Ferre struct platform_device *pdev = to_platform_device(dev); 1425c0ba5947SNicolas Ferre struct at_dma *atdma = platform_get_drvdata(pdev); 1426c0ba5947SNicolas Ferre struct dma_chan *chan, *_chan; 1427c0ba5947SNicolas Ferre 1428c0ba5947SNicolas Ferre list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels, 1429c0ba5947SNicolas Ferre device_node) { 1430c0ba5947SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 1431c0ba5947SNicolas Ferre /* wait for transaction completion (except in cyclic case) */ 14323c477482SNicolas Ferre if (atc_chan_is_enabled(atchan) && !atc_chan_is_cyclic(atchan)) 1433c0ba5947SNicolas Ferre return -EAGAIN; 1434c0ba5947SNicolas Ferre } 1435c0ba5947SNicolas Ferre return 0; 1436c0ba5947SNicolas Ferre } 1437c0ba5947SNicolas Ferre 1438c0ba5947SNicolas Ferre static void atc_suspend_cyclic(struct at_dma_chan *atchan) 1439c0ba5947SNicolas Ferre { 1440c0ba5947SNicolas Ferre struct dma_chan *chan = &atchan->chan_common; 1441c0ba5947SNicolas Ferre 1442c0ba5947SNicolas Ferre /* Channel should be paused by user 1443c0ba5947SNicolas Ferre * do it anyway even if it is not done already */ 14443c477482SNicolas Ferre if (!atc_chan_is_paused(atchan)) { 1445c0ba5947SNicolas Ferre dev_warn(chan2dev(chan), 1446c0ba5947SNicolas Ferre "cyclic channel not paused, should be done by channel user\n"); 1447c0ba5947SNicolas Ferre atc_control(chan, DMA_PAUSE, 0); 1448c0ba5947SNicolas Ferre } 1449c0ba5947SNicolas Ferre 1450c0ba5947SNicolas Ferre /* now preserve additional data for cyclic operations */ 1451c0ba5947SNicolas Ferre /* next descriptor address in the cyclic list */ 1452c0ba5947SNicolas Ferre atchan->save_dscr = channel_readl(atchan, DSCR); 1453c0ba5947SNicolas Ferre 1454c0ba5947SNicolas Ferre vdbg_dump_regs(atchan); 1455c0ba5947SNicolas Ferre } 1456c0ba5947SNicolas Ferre 145733f82d14SDan Williams static int at_dma_suspend_noirq(struct device *dev) 1458dc78baa2SNicolas Ferre { 145933f82d14SDan Williams struct platform_device *pdev = to_platform_device(dev); 1460dc78baa2SNicolas Ferre struct at_dma *atdma = platform_get_drvdata(pdev); 1461c0ba5947SNicolas Ferre struct dma_chan *chan, *_chan; 1462dc78baa2SNicolas Ferre 1463c0ba5947SNicolas Ferre /* preserve data */ 1464c0ba5947SNicolas Ferre list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels, 1465c0ba5947SNicolas Ferre device_node) { 1466c0ba5947SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 1467c0ba5947SNicolas Ferre 14683c477482SNicolas Ferre if (atc_chan_is_cyclic(atchan)) 1469c0ba5947SNicolas Ferre atc_suspend_cyclic(atchan); 1470c0ba5947SNicolas Ferre atchan->save_cfg = channel_readl(atchan, CFG); 1471c0ba5947SNicolas Ferre } 1472c0ba5947SNicolas Ferre atdma->save_imr = dma_readl(atdma, EBCIMR); 1473c0ba5947SNicolas Ferre 1474c0ba5947SNicolas Ferre /* disable DMA controller */ 1475c0ba5947SNicolas Ferre at_dma_off(atdma); 1476dc78baa2SNicolas Ferre clk_disable(atdma->clk); 1477dc78baa2SNicolas Ferre return 0; 1478dc78baa2SNicolas Ferre } 1479dc78baa2SNicolas Ferre 1480c0ba5947SNicolas Ferre static void atc_resume_cyclic(struct at_dma_chan *atchan) 1481c0ba5947SNicolas Ferre { 1482c0ba5947SNicolas Ferre struct at_dma *atdma = to_at_dma(atchan->chan_common.device); 1483c0ba5947SNicolas Ferre 1484c0ba5947SNicolas Ferre /* restore channel status for cyclic descriptors list: 1485c0ba5947SNicolas Ferre * next descriptor in the cyclic list at the time of suspend */ 1486c0ba5947SNicolas Ferre channel_writel(atchan, SADDR, 0); 1487c0ba5947SNicolas Ferre channel_writel(atchan, DADDR, 0); 1488c0ba5947SNicolas Ferre channel_writel(atchan, CTRLA, 0); 1489c0ba5947SNicolas Ferre channel_writel(atchan, CTRLB, 0); 1490c0ba5947SNicolas Ferre channel_writel(atchan, DSCR, atchan->save_dscr); 1491c0ba5947SNicolas Ferre dma_writel(atdma, CHER, atchan->mask); 1492c0ba5947SNicolas Ferre 1493c0ba5947SNicolas Ferre /* channel pause status should be removed by channel user 1494c0ba5947SNicolas Ferre * We cannot take the initiative to do it here */ 1495c0ba5947SNicolas Ferre 1496c0ba5947SNicolas Ferre vdbg_dump_regs(atchan); 1497c0ba5947SNicolas Ferre } 1498c0ba5947SNicolas Ferre 149933f82d14SDan Williams static int at_dma_resume_noirq(struct device *dev) 1500dc78baa2SNicolas Ferre { 150133f82d14SDan Williams struct platform_device *pdev = to_platform_device(dev); 1502dc78baa2SNicolas Ferre struct at_dma *atdma = platform_get_drvdata(pdev); 1503c0ba5947SNicolas Ferre struct dma_chan *chan, *_chan; 1504dc78baa2SNicolas Ferre 1505c0ba5947SNicolas Ferre /* bring back DMA controller */ 1506dc78baa2SNicolas Ferre clk_enable(atdma->clk); 1507dc78baa2SNicolas Ferre dma_writel(atdma, EN, AT_DMA_ENABLE); 1508c0ba5947SNicolas Ferre 1509c0ba5947SNicolas Ferre /* clear any pending interrupt */ 1510c0ba5947SNicolas Ferre while (dma_readl(atdma, EBCISR)) 1511c0ba5947SNicolas Ferre cpu_relax(); 1512c0ba5947SNicolas Ferre 1513c0ba5947SNicolas Ferre /* restore saved data */ 1514c0ba5947SNicolas Ferre dma_writel(atdma, EBCIER, atdma->save_imr); 1515c0ba5947SNicolas Ferre list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels, 1516c0ba5947SNicolas Ferre device_node) { 1517c0ba5947SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 1518c0ba5947SNicolas Ferre 1519c0ba5947SNicolas Ferre channel_writel(atchan, CFG, atchan->save_cfg); 15203c477482SNicolas Ferre if (atc_chan_is_cyclic(atchan)) 1521c0ba5947SNicolas Ferre atc_resume_cyclic(atchan); 1522c0ba5947SNicolas Ferre } 1523dc78baa2SNicolas Ferre return 0; 1524dc78baa2SNicolas Ferre } 1525dc78baa2SNicolas Ferre 152647145210SAlexey Dobriyan static const struct dev_pm_ops at_dma_dev_pm_ops = { 1527c0ba5947SNicolas Ferre .prepare = at_dma_prepare, 152833f82d14SDan Williams .suspend_noirq = at_dma_suspend_noirq, 152933f82d14SDan Williams .resume_noirq = at_dma_resume_noirq, 153033f82d14SDan Williams }; 153133f82d14SDan Williams 1532dc78baa2SNicolas Ferre static struct platform_driver at_dma_driver = { 1533dc78baa2SNicolas Ferre .remove = __exit_p(at_dma_remove), 1534dc78baa2SNicolas Ferre .shutdown = at_dma_shutdown, 153567348450SNicolas Ferre .id_table = atdma_devtypes, 1536dc78baa2SNicolas Ferre .driver = { 1537dc78baa2SNicolas Ferre .name = "at_hdmac", 153833f82d14SDan Williams .pm = &at_dma_dev_pm_ops, 1539c5115953SNicolas Ferre .of_match_table = of_match_ptr(atmel_dma_dt_ids), 1540dc78baa2SNicolas Ferre }, 1541dc78baa2SNicolas Ferre }; 1542dc78baa2SNicolas Ferre 1543dc78baa2SNicolas Ferre static int __init at_dma_init(void) 1544dc78baa2SNicolas Ferre { 1545dc78baa2SNicolas Ferre return platform_driver_probe(&at_dma_driver, at_dma_probe); 1546dc78baa2SNicolas Ferre } 154793d0bec2SEric Xu subsys_initcall(at_dma_init); 1548dc78baa2SNicolas Ferre 1549dc78baa2SNicolas Ferre static void __exit at_dma_exit(void) 1550dc78baa2SNicolas Ferre { 1551dc78baa2SNicolas Ferre platform_driver_unregister(&at_dma_driver); 1552dc78baa2SNicolas Ferre } 1553dc78baa2SNicolas Ferre module_exit(at_dma_exit); 1554dc78baa2SNicolas Ferre 1555dc78baa2SNicolas Ferre MODULE_DESCRIPTION("Atmel AHB DMA Controller driver"); 1556dc78baa2SNicolas Ferre MODULE_AUTHOR("Nicolas Ferre <nicolas.ferre@atmel.com>"); 1557dc78baa2SNicolas Ferre MODULE_LICENSE("GPL"); 1558dc78baa2SNicolas Ferre MODULE_ALIAS("platform:at_hdmac"); 1559