1dc78baa2SNicolas Ferre /* 2dc78baa2SNicolas Ferre * Driver for the Atmel AHB DMA Controller (aka HDMA or DMAC on AT91 systems) 3dc78baa2SNicolas Ferre * 4dc78baa2SNicolas Ferre * Copyright (C) 2008 Atmel Corporation 5dc78baa2SNicolas Ferre * 6dc78baa2SNicolas Ferre * This program is free software; you can redistribute it and/or modify 7dc78baa2SNicolas Ferre * it under the terms of the GNU General Public License as published by 8dc78baa2SNicolas Ferre * the Free Software Foundation; either version 2 of the License, or 9dc78baa2SNicolas Ferre * (at your option) any later version. 10dc78baa2SNicolas Ferre * 11dc78baa2SNicolas Ferre * 12dc78baa2SNicolas Ferre * This supports the Atmel AHB DMA Controller, 13dc78baa2SNicolas Ferre * 14dc78baa2SNicolas Ferre * The driver has currently been tested with the Atmel AT91SAM9RL 15dc78baa2SNicolas Ferre * and AT91SAM9G45 series. 16dc78baa2SNicolas Ferre */ 17dc78baa2SNicolas Ferre 18dc78baa2SNicolas Ferre #include <linux/clk.h> 19dc78baa2SNicolas Ferre #include <linux/dmaengine.h> 20dc78baa2SNicolas Ferre #include <linux/dma-mapping.h> 21dc78baa2SNicolas Ferre #include <linux/dmapool.h> 22dc78baa2SNicolas Ferre #include <linux/interrupt.h> 23dc78baa2SNicolas Ferre #include <linux/module.h> 24dc78baa2SNicolas Ferre #include <linux/platform_device.h> 255a0e3ad6STejun Heo #include <linux/slab.h> 26dc78baa2SNicolas Ferre 27dc78baa2SNicolas Ferre #include "at_hdmac_regs.h" 28dc78baa2SNicolas Ferre 29dc78baa2SNicolas Ferre /* 30dc78baa2SNicolas Ferre * Glossary 31dc78baa2SNicolas Ferre * -------- 32dc78baa2SNicolas Ferre * 33dc78baa2SNicolas Ferre * at_hdmac : Name of the ATmel AHB DMA Controller 34dc78baa2SNicolas Ferre * at_dma_ / atdma : ATmel DMA controller entity related 35dc78baa2SNicolas Ferre * atc_ / atchan : ATmel DMA Channel entity related 36dc78baa2SNicolas Ferre */ 37dc78baa2SNicolas Ferre 38dc78baa2SNicolas Ferre #define ATC_DEFAULT_CFG (ATC_FIFOCFG_HALFFIFO) 39dc78baa2SNicolas Ferre #define ATC_DEFAULT_CTRLA (0) 40ae14d4b5SNicolas Ferre #define ATC_DEFAULT_CTRLB (ATC_SIF(AT_DMA_MEM_IF) \ 41ae14d4b5SNicolas Ferre |ATC_DIF(AT_DMA_MEM_IF)) 42dc78baa2SNicolas Ferre 43dc78baa2SNicolas Ferre /* 44dc78baa2SNicolas Ferre * Initial number of descriptors to allocate for each channel. This could 45dc78baa2SNicolas Ferre * be increased during dma usage. 46dc78baa2SNicolas Ferre */ 47dc78baa2SNicolas Ferre static unsigned int init_nr_desc_per_channel = 64; 48dc78baa2SNicolas Ferre module_param(init_nr_desc_per_channel, uint, 0644); 49dc78baa2SNicolas Ferre MODULE_PARM_DESC(init_nr_desc_per_channel, 50dc78baa2SNicolas Ferre "initial descriptors per channel (default: 64)"); 51dc78baa2SNicolas Ferre 52dc78baa2SNicolas Ferre 53dc78baa2SNicolas Ferre /* prototypes */ 54dc78baa2SNicolas Ferre static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx); 55dc78baa2SNicolas Ferre 56dc78baa2SNicolas Ferre 57dc78baa2SNicolas Ferre /*----------------------------------------------------------------------*/ 58dc78baa2SNicolas Ferre 59dc78baa2SNicolas Ferre static struct at_desc *atc_first_active(struct at_dma_chan *atchan) 60dc78baa2SNicolas Ferre { 61dc78baa2SNicolas Ferre return list_first_entry(&atchan->active_list, 62dc78baa2SNicolas Ferre struct at_desc, desc_node); 63dc78baa2SNicolas Ferre } 64dc78baa2SNicolas Ferre 65dc78baa2SNicolas Ferre static struct at_desc *atc_first_queued(struct at_dma_chan *atchan) 66dc78baa2SNicolas Ferre { 67dc78baa2SNicolas Ferre return list_first_entry(&atchan->queue, 68dc78baa2SNicolas Ferre struct at_desc, desc_node); 69dc78baa2SNicolas Ferre } 70dc78baa2SNicolas Ferre 71dc78baa2SNicolas Ferre /** 72421f91d2SUwe Kleine-König * atc_alloc_descriptor - allocate and return an initialized descriptor 73dc78baa2SNicolas Ferre * @chan: the channel to allocate descriptors for 74dc78baa2SNicolas Ferre * @gfp_flags: GFP allocation flags 75dc78baa2SNicolas Ferre * 76dc78baa2SNicolas Ferre * Note: The ack-bit is positioned in the descriptor flag at creation time 77dc78baa2SNicolas Ferre * to make initial allocation more convenient. This bit will be cleared 78dc78baa2SNicolas Ferre * and control will be given to client at usage time (during 79dc78baa2SNicolas Ferre * preparation functions). 80dc78baa2SNicolas Ferre */ 81dc78baa2SNicolas Ferre static struct at_desc *atc_alloc_descriptor(struct dma_chan *chan, 82dc78baa2SNicolas Ferre gfp_t gfp_flags) 83dc78baa2SNicolas Ferre { 84dc78baa2SNicolas Ferre struct at_desc *desc = NULL; 85dc78baa2SNicolas Ferre struct at_dma *atdma = to_at_dma(chan->device); 86dc78baa2SNicolas Ferre dma_addr_t phys; 87dc78baa2SNicolas Ferre 88dc78baa2SNicolas Ferre desc = dma_pool_alloc(atdma->dma_desc_pool, gfp_flags, &phys); 89dc78baa2SNicolas Ferre if (desc) { 90dc78baa2SNicolas Ferre memset(desc, 0, sizeof(struct at_desc)); 91285a3c71SDan Williams INIT_LIST_HEAD(&desc->tx_list); 92dc78baa2SNicolas Ferre dma_async_tx_descriptor_init(&desc->txd, chan); 93dc78baa2SNicolas Ferre /* txd.flags will be overwritten in prep functions */ 94dc78baa2SNicolas Ferre desc->txd.flags = DMA_CTRL_ACK; 95dc78baa2SNicolas Ferre desc->txd.tx_submit = atc_tx_submit; 96dc78baa2SNicolas Ferre desc->txd.phys = phys; 97dc78baa2SNicolas Ferre } 98dc78baa2SNicolas Ferre 99dc78baa2SNicolas Ferre return desc; 100dc78baa2SNicolas Ferre } 101dc78baa2SNicolas Ferre 102dc78baa2SNicolas Ferre /** 103af901ca1SAndré Goddard Rosa * atc_desc_get - get an unused descriptor from free_list 104dc78baa2SNicolas Ferre * @atchan: channel we want a new descriptor for 105dc78baa2SNicolas Ferre */ 106dc78baa2SNicolas Ferre static struct at_desc *atc_desc_get(struct at_dma_chan *atchan) 107dc78baa2SNicolas Ferre { 108dc78baa2SNicolas Ferre struct at_desc *desc, *_desc; 109dc78baa2SNicolas Ferre struct at_desc *ret = NULL; 110d8cb04b0SNicolas Ferre unsigned long flags; 111dc78baa2SNicolas Ferre unsigned int i = 0; 112dc78baa2SNicolas Ferre LIST_HEAD(tmp_list); 113dc78baa2SNicolas Ferre 114d8cb04b0SNicolas Ferre spin_lock_irqsave(&atchan->lock, flags); 115dc78baa2SNicolas Ferre list_for_each_entry_safe(desc, _desc, &atchan->free_list, desc_node) { 116dc78baa2SNicolas Ferre i++; 117dc78baa2SNicolas Ferre if (async_tx_test_ack(&desc->txd)) { 118dc78baa2SNicolas Ferre list_del(&desc->desc_node); 119dc78baa2SNicolas Ferre ret = desc; 120dc78baa2SNicolas Ferre break; 121dc78baa2SNicolas Ferre } 122dc78baa2SNicolas Ferre dev_dbg(chan2dev(&atchan->chan_common), 123dc78baa2SNicolas Ferre "desc %p not ACKed\n", desc); 124dc78baa2SNicolas Ferre } 125d8cb04b0SNicolas Ferre spin_unlock_irqrestore(&atchan->lock, flags); 126dc78baa2SNicolas Ferre dev_vdbg(chan2dev(&atchan->chan_common), 127dc78baa2SNicolas Ferre "scanned %u descriptors on freelist\n", i); 128dc78baa2SNicolas Ferre 129dc78baa2SNicolas Ferre /* no more descriptor available in initial pool: create one more */ 130dc78baa2SNicolas Ferre if (!ret) { 131dc78baa2SNicolas Ferre ret = atc_alloc_descriptor(&atchan->chan_common, GFP_ATOMIC); 132dc78baa2SNicolas Ferre if (ret) { 133d8cb04b0SNicolas Ferre spin_lock_irqsave(&atchan->lock, flags); 134dc78baa2SNicolas Ferre atchan->descs_allocated++; 135d8cb04b0SNicolas Ferre spin_unlock_irqrestore(&atchan->lock, flags); 136dc78baa2SNicolas Ferre } else { 137dc78baa2SNicolas Ferre dev_err(chan2dev(&atchan->chan_common), 138dc78baa2SNicolas Ferre "not enough descriptors available\n"); 139dc78baa2SNicolas Ferre } 140dc78baa2SNicolas Ferre } 141dc78baa2SNicolas Ferre 142dc78baa2SNicolas Ferre return ret; 143dc78baa2SNicolas Ferre } 144dc78baa2SNicolas Ferre 145dc78baa2SNicolas Ferre /** 146dc78baa2SNicolas Ferre * atc_desc_put - move a descriptor, including any children, to the free list 147dc78baa2SNicolas Ferre * @atchan: channel we work on 148dc78baa2SNicolas Ferre * @desc: descriptor, at the head of a chain, to move to free list 149dc78baa2SNicolas Ferre */ 150dc78baa2SNicolas Ferre static void atc_desc_put(struct at_dma_chan *atchan, struct at_desc *desc) 151dc78baa2SNicolas Ferre { 152dc78baa2SNicolas Ferre if (desc) { 153dc78baa2SNicolas Ferre struct at_desc *child; 154d8cb04b0SNicolas Ferre unsigned long flags; 155dc78baa2SNicolas Ferre 156d8cb04b0SNicolas Ferre spin_lock_irqsave(&atchan->lock, flags); 157285a3c71SDan Williams list_for_each_entry(child, &desc->tx_list, desc_node) 158dc78baa2SNicolas Ferre dev_vdbg(chan2dev(&atchan->chan_common), 159dc78baa2SNicolas Ferre "moving child desc %p to freelist\n", 160dc78baa2SNicolas Ferre child); 161285a3c71SDan Williams list_splice_init(&desc->tx_list, &atchan->free_list); 162dc78baa2SNicolas Ferre dev_vdbg(chan2dev(&atchan->chan_common), 163dc78baa2SNicolas Ferre "moving desc %p to freelist\n", desc); 164dc78baa2SNicolas Ferre list_add(&desc->desc_node, &atchan->free_list); 165d8cb04b0SNicolas Ferre spin_unlock_irqrestore(&atchan->lock, flags); 166dc78baa2SNicolas Ferre } 167dc78baa2SNicolas Ferre } 168dc78baa2SNicolas Ferre 169dc78baa2SNicolas Ferre /** 17053830cc7SNicolas Ferre * atc_desc_chain - build chain adding a descripor 17153830cc7SNicolas Ferre * @first: address of first descripor of the chain 17253830cc7SNicolas Ferre * @prev: address of previous descripor of the chain 17353830cc7SNicolas Ferre * @desc: descriptor to queue 17453830cc7SNicolas Ferre * 17553830cc7SNicolas Ferre * Called from prep_* functions 17653830cc7SNicolas Ferre */ 17753830cc7SNicolas Ferre static void atc_desc_chain(struct at_desc **first, struct at_desc **prev, 17853830cc7SNicolas Ferre struct at_desc *desc) 17953830cc7SNicolas Ferre { 18053830cc7SNicolas Ferre if (!(*first)) { 18153830cc7SNicolas Ferre *first = desc; 18253830cc7SNicolas Ferre } else { 18353830cc7SNicolas Ferre /* inform the HW lli about chaining */ 18453830cc7SNicolas Ferre (*prev)->lli.dscr = desc->txd.phys; 18553830cc7SNicolas Ferre /* insert the link descriptor to the LD ring */ 18653830cc7SNicolas Ferre list_add_tail(&desc->desc_node, 18753830cc7SNicolas Ferre &(*first)->tx_list); 18853830cc7SNicolas Ferre } 18953830cc7SNicolas Ferre *prev = desc; 19053830cc7SNicolas Ferre } 19153830cc7SNicolas Ferre 19253830cc7SNicolas Ferre /** 193dc78baa2SNicolas Ferre * atc_assign_cookie - compute and assign new cookie 194dc78baa2SNicolas Ferre * @atchan: channel we work on 19525985edcSLucas De Marchi * @desc: descriptor to assign cookie for 196dc78baa2SNicolas Ferre * 197dc78baa2SNicolas Ferre * Called with atchan->lock held and bh disabled 198dc78baa2SNicolas Ferre */ 199dc78baa2SNicolas Ferre static dma_cookie_t 200dc78baa2SNicolas Ferre atc_assign_cookie(struct at_dma_chan *atchan, struct at_desc *desc) 201dc78baa2SNicolas Ferre { 202dc78baa2SNicolas Ferre dma_cookie_t cookie = atchan->chan_common.cookie; 203dc78baa2SNicolas Ferre 204dc78baa2SNicolas Ferre if (++cookie < 0) 205dc78baa2SNicolas Ferre cookie = 1; 206dc78baa2SNicolas Ferre 207dc78baa2SNicolas Ferre atchan->chan_common.cookie = cookie; 208dc78baa2SNicolas Ferre desc->txd.cookie = cookie; 209dc78baa2SNicolas Ferre 210dc78baa2SNicolas Ferre return cookie; 211dc78baa2SNicolas Ferre } 212dc78baa2SNicolas Ferre 213dc78baa2SNicolas Ferre /** 214dc78baa2SNicolas Ferre * atc_dostart - starts the DMA engine for real 215dc78baa2SNicolas Ferre * @atchan: the channel we want to start 216dc78baa2SNicolas Ferre * @first: first descriptor in the list we want to begin with 217dc78baa2SNicolas Ferre * 218dc78baa2SNicolas Ferre * Called with atchan->lock held and bh disabled 219dc78baa2SNicolas Ferre */ 220dc78baa2SNicolas Ferre static void atc_dostart(struct at_dma_chan *atchan, struct at_desc *first) 221dc78baa2SNicolas Ferre { 222dc78baa2SNicolas Ferre struct at_dma *atdma = to_at_dma(atchan->chan_common.device); 223dc78baa2SNicolas Ferre 224dc78baa2SNicolas Ferre /* ASSERT: channel is idle */ 225dc78baa2SNicolas Ferre if (atc_chan_is_enabled(atchan)) { 226dc78baa2SNicolas Ferre dev_err(chan2dev(&atchan->chan_common), 227dc78baa2SNicolas Ferre "BUG: Attempted to start non-idle channel\n"); 228dc78baa2SNicolas Ferre dev_err(chan2dev(&atchan->chan_common), 229dc78baa2SNicolas Ferre " channel: s0x%x d0x%x ctrl0x%x:0x%x l0x%x\n", 230dc78baa2SNicolas Ferre channel_readl(atchan, SADDR), 231dc78baa2SNicolas Ferre channel_readl(atchan, DADDR), 232dc78baa2SNicolas Ferre channel_readl(atchan, CTRLA), 233dc78baa2SNicolas Ferre channel_readl(atchan, CTRLB), 234dc78baa2SNicolas Ferre channel_readl(atchan, DSCR)); 235dc78baa2SNicolas Ferre 236dc78baa2SNicolas Ferre /* The tasklet will hopefully advance the queue... */ 237dc78baa2SNicolas Ferre return; 238dc78baa2SNicolas Ferre } 239dc78baa2SNicolas Ferre 240dc78baa2SNicolas Ferre vdbg_dump_regs(atchan); 241dc78baa2SNicolas Ferre 242dc78baa2SNicolas Ferre /* clear any pending interrupt */ 243dc78baa2SNicolas Ferre while (dma_readl(atdma, EBCISR)) 244dc78baa2SNicolas Ferre cpu_relax(); 245dc78baa2SNicolas Ferre 246dc78baa2SNicolas Ferre channel_writel(atchan, SADDR, 0); 247dc78baa2SNicolas Ferre channel_writel(atchan, DADDR, 0); 248dc78baa2SNicolas Ferre channel_writel(atchan, CTRLA, 0); 249dc78baa2SNicolas Ferre channel_writel(atchan, CTRLB, 0); 250dc78baa2SNicolas Ferre channel_writel(atchan, DSCR, first->txd.phys); 251dc78baa2SNicolas Ferre dma_writel(atdma, CHER, atchan->mask); 252dc78baa2SNicolas Ferre 253dc78baa2SNicolas Ferre vdbg_dump_regs(atchan); 254dc78baa2SNicolas Ferre } 255dc78baa2SNicolas Ferre 256dc78baa2SNicolas Ferre /** 257dc78baa2SNicolas Ferre * atc_chain_complete - finish work for one transaction chain 258dc78baa2SNicolas Ferre * @atchan: channel we work on 259dc78baa2SNicolas Ferre * @desc: descriptor at the head of the chain we want do complete 260dc78baa2SNicolas Ferre * 261dc78baa2SNicolas Ferre * Called with atchan->lock held and bh disabled */ 262dc78baa2SNicolas Ferre static void 263dc78baa2SNicolas Ferre atc_chain_complete(struct at_dma_chan *atchan, struct at_desc *desc) 264dc78baa2SNicolas Ferre { 265dc78baa2SNicolas Ferre struct dma_async_tx_descriptor *txd = &desc->txd; 266dc78baa2SNicolas Ferre 267dc78baa2SNicolas Ferre dev_vdbg(chan2dev(&atchan->chan_common), 268dc78baa2SNicolas Ferre "descriptor %u complete\n", txd->cookie); 269dc78baa2SNicolas Ferre 270dc78baa2SNicolas Ferre atchan->completed_cookie = txd->cookie; 271dc78baa2SNicolas Ferre 272dc78baa2SNicolas Ferre /* move children to free_list */ 273285a3c71SDan Williams list_splice_init(&desc->tx_list, &atchan->free_list); 274dc78baa2SNicolas Ferre /* move myself to free_list */ 275dc78baa2SNicolas Ferre list_move(&desc->desc_node, &atchan->free_list); 276dc78baa2SNicolas Ferre 277ebcf9b80SNicolas Ferre /* unmap dma addresses (not on slave channels) */ 278657a77faSAtsushi Nemoto if (!atchan->chan_common.private) { 279657a77faSAtsushi Nemoto struct device *parent = chan2parent(&atchan->chan_common); 280dc78baa2SNicolas Ferre if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) { 281dc78baa2SNicolas Ferre if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE) 282657a77faSAtsushi Nemoto dma_unmap_single(parent, 283dc78baa2SNicolas Ferre desc->lli.daddr, 284dc78baa2SNicolas Ferre desc->len, DMA_FROM_DEVICE); 285dc78baa2SNicolas Ferre else 286657a77faSAtsushi Nemoto dma_unmap_page(parent, 287dc78baa2SNicolas Ferre desc->lli.daddr, 288dc78baa2SNicolas Ferre desc->len, DMA_FROM_DEVICE); 289dc78baa2SNicolas Ferre } 290dc78baa2SNicolas Ferre if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) { 291dc78baa2SNicolas Ferre if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE) 292657a77faSAtsushi Nemoto dma_unmap_single(parent, 293dc78baa2SNicolas Ferre desc->lli.saddr, 294dc78baa2SNicolas Ferre desc->len, DMA_TO_DEVICE); 295dc78baa2SNicolas Ferre else 296657a77faSAtsushi Nemoto dma_unmap_page(parent, 297dc78baa2SNicolas Ferre desc->lli.saddr, 298dc78baa2SNicolas Ferre desc->len, DMA_TO_DEVICE); 299dc78baa2SNicolas Ferre } 300657a77faSAtsushi Nemoto } 301dc78baa2SNicolas Ferre 30253830cc7SNicolas Ferre /* for cyclic transfers, 30353830cc7SNicolas Ferre * no need to replay callback function while stopping */ 3043c477482SNicolas Ferre if (!atc_chan_is_cyclic(atchan)) { 30553830cc7SNicolas Ferre dma_async_tx_callback callback = txd->callback; 30653830cc7SNicolas Ferre void *param = txd->callback_param; 30753830cc7SNicolas Ferre 308dc78baa2SNicolas Ferre /* 309dc78baa2SNicolas Ferre * The API requires that no submissions are done from a 310dc78baa2SNicolas Ferre * callback, so we don't need to drop the lock here 311dc78baa2SNicolas Ferre */ 312dc78baa2SNicolas Ferre if (callback) 313dc78baa2SNicolas Ferre callback(param); 31453830cc7SNicolas Ferre } 315dc78baa2SNicolas Ferre 316dc78baa2SNicolas Ferre dma_run_dependencies(txd); 317dc78baa2SNicolas Ferre } 318dc78baa2SNicolas Ferre 319dc78baa2SNicolas Ferre /** 320dc78baa2SNicolas Ferre * atc_complete_all - finish work for all transactions 321dc78baa2SNicolas Ferre * @atchan: channel to complete transactions for 322dc78baa2SNicolas Ferre * 323dc78baa2SNicolas Ferre * Eventually submit queued descriptors if any 324dc78baa2SNicolas Ferre * 325dc78baa2SNicolas Ferre * Assume channel is idle while calling this function 326dc78baa2SNicolas Ferre * Called with atchan->lock held and bh disabled 327dc78baa2SNicolas Ferre */ 328dc78baa2SNicolas Ferre static void atc_complete_all(struct at_dma_chan *atchan) 329dc78baa2SNicolas Ferre { 330dc78baa2SNicolas Ferre struct at_desc *desc, *_desc; 331dc78baa2SNicolas Ferre LIST_HEAD(list); 332dc78baa2SNicolas Ferre 333dc78baa2SNicolas Ferre dev_vdbg(chan2dev(&atchan->chan_common), "complete all\n"); 334dc78baa2SNicolas Ferre 335dc78baa2SNicolas Ferre BUG_ON(atc_chan_is_enabled(atchan)); 336dc78baa2SNicolas Ferre 337dc78baa2SNicolas Ferre /* 338dc78baa2SNicolas Ferre * Submit queued descriptors ASAP, i.e. before we go through 339dc78baa2SNicolas Ferre * the completed ones. 340dc78baa2SNicolas Ferre */ 341dc78baa2SNicolas Ferre if (!list_empty(&atchan->queue)) 342dc78baa2SNicolas Ferre atc_dostart(atchan, atc_first_queued(atchan)); 343dc78baa2SNicolas Ferre /* empty active_list now it is completed */ 344dc78baa2SNicolas Ferre list_splice_init(&atchan->active_list, &list); 345dc78baa2SNicolas Ferre /* empty queue list by moving descriptors (if any) to active_list */ 346dc78baa2SNicolas Ferre list_splice_init(&atchan->queue, &atchan->active_list); 347dc78baa2SNicolas Ferre 348dc78baa2SNicolas Ferre list_for_each_entry_safe(desc, _desc, &list, desc_node) 349dc78baa2SNicolas Ferre atc_chain_complete(atchan, desc); 350dc78baa2SNicolas Ferre } 351dc78baa2SNicolas Ferre 352dc78baa2SNicolas Ferre /** 353dc78baa2SNicolas Ferre * atc_cleanup_descriptors - cleanup up finished descriptors in active_list 354dc78baa2SNicolas Ferre * @atchan: channel to be cleaned up 355dc78baa2SNicolas Ferre * 356dc78baa2SNicolas Ferre * Called with atchan->lock held and bh disabled 357dc78baa2SNicolas Ferre */ 358dc78baa2SNicolas Ferre static void atc_cleanup_descriptors(struct at_dma_chan *atchan) 359dc78baa2SNicolas Ferre { 360dc78baa2SNicolas Ferre struct at_desc *desc, *_desc; 361dc78baa2SNicolas Ferre struct at_desc *child; 362dc78baa2SNicolas Ferre 363dc78baa2SNicolas Ferre dev_vdbg(chan2dev(&atchan->chan_common), "cleanup descriptors\n"); 364dc78baa2SNicolas Ferre 365dc78baa2SNicolas Ferre list_for_each_entry_safe(desc, _desc, &atchan->active_list, desc_node) { 366dc78baa2SNicolas Ferre if (!(desc->lli.ctrla & ATC_DONE)) 367dc78baa2SNicolas Ferre /* This one is currently in progress */ 368dc78baa2SNicolas Ferre return; 369dc78baa2SNicolas Ferre 370285a3c71SDan Williams list_for_each_entry(child, &desc->tx_list, desc_node) 371dc78baa2SNicolas Ferre if (!(child->lli.ctrla & ATC_DONE)) 372dc78baa2SNicolas Ferre /* Currently in progress */ 373dc78baa2SNicolas Ferre return; 374dc78baa2SNicolas Ferre 375dc78baa2SNicolas Ferre /* 376dc78baa2SNicolas Ferre * No descriptors so far seem to be in progress, i.e. 377dc78baa2SNicolas Ferre * this chain must be done. 378dc78baa2SNicolas Ferre */ 379dc78baa2SNicolas Ferre atc_chain_complete(atchan, desc); 380dc78baa2SNicolas Ferre } 381dc78baa2SNicolas Ferre } 382dc78baa2SNicolas Ferre 383dc78baa2SNicolas Ferre /** 384dc78baa2SNicolas Ferre * atc_advance_work - at the end of a transaction, move forward 385dc78baa2SNicolas Ferre * @atchan: channel where the transaction ended 386dc78baa2SNicolas Ferre * 387dc78baa2SNicolas Ferre * Called with atchan->lock held and bh disabled 388dc78baa2SNicolas Ferre */ 389dc78baa2SNicolas Ferre static void atc_advance_work(struct at_dma_chan *atchan) 390dc78baa2SNicolas Ferre { 391dc78baa2SNicolas Ferre dev_vdbg(chan2dev(&atchan->chan_common), "advance_work\n"); 392dc78baa2SNicolas Ferre 393dc78baa2SNicolas Ferre if (list_empty(&atchan->active_list) || 394dc78baa2SNicolas Ferre list_is_singular(&atchan->active_list)) { 395dc78baa2SNicolas Ferre atc_complete_all(atchan); 396dc78baa2SNicolas Ferre } else { 397dc78baa2SNicolas Ferre atc_chain_complete(atchan, atc_first_active(atchan)); 398dc78baa2SNicolas Ferre /* advance work */ 399dc78baa2SNicolas Ferre atc_dostart(atchan, atc_first_active(atchan)); 400dc78baa2SNicolas Ferre } 401dc78baa2SNicolas Ferre } 402dc78baa2SNicolas Ferre 403dc78baa2SNicolas Ferre 404dc78baa2SNicolas Ferre /** 405dc78baa2SNicolas Ferre * atc_handle_error - handle errors reported by DMA controller 406dc78baa2SNicolas Ferre * @atchan: channel where error occurs 407dc78baa2SNicolas Ferre * 408dc78baa2SNicolas Ferre * Called with atchan->lock held and bh disabled 409dc78baa2SNicolas Ferre */ 410dc78baa2SNicolas Ferre static void atc_handle_error(struct at_dma_chan *atchan) 411dc78baa2SNicolas Ferre { 412dc78baa2SNicolas Ferre struct at_desc *bad_desc; 413dc78baa2SNicolas Ferre struct at_desc *child; 414dc78baa2SNicolas Ferre 415dc78baa2SNicolas Ferre /* 416dc78baa2SNicolas Ferre * The descriptor currently at the head of the active list is 417dc78baa2SNicolas Ferre * broked. Since we don't have any way to report errors, we'll 418dc78baa2SNicolas Ferre * just have to scream loudly and try to carry on. 419dc78baa2SNicolas Ferre */ 420dc78baa2SNicolas Ferre bad_desc = atc_first_active(atchan); 421dc78baa2SNicolas Ferre list_del_init(&bad_desc->desc_node); 422dc78baa2SNicolas Ferre 423dc78baa2SNicolas Ferre /* As we are stopped, take advantage to push queued descriptors 424dc78baa2SNicolas Ferre * in active_list */ 425dc78baa2SNicolas Ferre list_splice_init(&atchan->queue, atchan->active_list.prev); 426dc78baa2SNicolas Ferre 427dc78baa2SNicolas Ferre /* Try to restart the controller */ 428dc78baa2SNicolas Ferre if (!list_empty(&atchan->active_list)) 429dc78baa2SNicolas Ferre atc_dostart(atchan, atc_first_active(atchan)); 430dc78baa2SNicolas Ferre 431dc78baa2SNicolas Ferre /* 432dc78baa2SNicolas Ferre * KERN_CRITICAL may seem harsh, but since this only happens 433dc78baa2SNicolas Ferre * when someone submits a bad physical address in a 434dc78baa2SNicolas Ferre * descriptor, we should consider ourselves lucky that the 435dc78baa2SNicolas Ferre * controller flagged an error instead of scribbling over 436dc78baa2SNicolas Ferre * random memory locations. 437dc78baa2SNicolas Ferre */ 438dc78baa2SNicolas Ferre dev_crit(chan2dev(&atchan->chan_common), 439dc78baa2SNicolas Ferre "Bad descriptor submitted for DMA!\n"); 440dc78baa2SNicolas Ferre dev_crit(chan2dev(&atchan->chan_common), 441dc78baa2SNicolas Ferre " cookie: %d\n", bad_desc->txd.cookie); 442dc78baa2SNicolas Ferre atc_dump_lli(atchan, &bad_desc->lli); 443285a3c71SDan Williams list_for_each_entry(child, &bad_desc->tx_list, desc_node) 444dc78baa2SNicolas Ferre atc_dump_lli(atchan, &child->lli); 445dc78baa2SNicolas Ferre 446dc78baa2SNicolas Ferre /* Pretend the descriptor completed successfully */ 447dc78baa2SNicolas Ferre atc_chain_complete(atchan, bad_desc); 448dc78baa2SNicolas Ferre } 449dc78baa2SNicolas Ferre 45053830cc7SNicolas Ferre /** 45153830cc7SNicolas Ferre * atc_handle_cyclic - at the end of a period, run callback function 45253830cc7SNicolas Ferre * @atchan: channel used for cyclic operations 45353830cc7SNicolas Ferre * 45453830cc7SNicolas Ferre * Called with atchan->lock held and bh disabled 45553830cc7SNicolas Ferre */ 45653830cc7SNicolas Ferre static void atc_handle_cyclic(struct at_dma_chan *atchan) 45753830cc7SNicolas Ferre { 45853830cc7SNicolas Ferre struct at_desc *first = atc_first_active(atchan); 45953830cc7SNicolas Ferre struct dma_async_tx_descriptor *txd = &first->txd; 46053830cc7SNicolas Ferre dma_async_tx_callback callback = txd->callback; 46153830cc7SNicolas Ferre void *param = txd->callback_param; 46253830cc7SNicolas Ferre 46353830cc7SNicolas Ferre dev_vdbg(chan2dev(&atchan->chan_common), 46453830cc7SNicolas Ferre "new cyclic period llp 0x%08x\n", 46553830cc7SNicolas Ferre channel_readl(atchan, DSCR)); 46653830cc7SNicolas Ferre 46753830cc7SNicolas Ferre if (callback) 46853830cc7SNicolas Ferre callback(param); 46953830cc7SNicolas Ferre } 470dc78baa2SNicolas Ferre 471dc78baa2SNicolas Ferre /*-- IRQ & Tasklet ---------------------------------------------------*/ 472dc78baa2SNicolas Ferre 473dc78baa2SNicolas Ferre static void atc_tasklet(unsigned long data) 474dc78baa2SNicolas Ferre { 475dc78baa2SNicolas Ferre struct at_dma_chan *atchan = (struct at_dma_chan *)data; 476d8cb04b0SNicolas Ferre unsigned long flags; 477dc78baa2SNicolas Ferre 478d8cb04b0SNicolas Ferre spin_lock_irqsave(&atchan->lock, flags); 47953830cc7SNicolas Ferre if (test_and_clear_bit(ATC_IS_ERROR, &atchan->status)) 480dc78baa2SNicolas Ferre atc_handle_error(atchan); 4813c477482SNicolas Ferre else if (atc_chan_is_cyclic(atchan)) 48253830cc7SNicolas Ferre atc_handle_cyclic(atchan); 483dc78baa2SNicolas Ferre else 484dc78baa2SNicolas Ferre atc_advance_work(atchan); 485dc78baa2SNicolas Ferre 486d8cb04b0SNicolas Ferre spin_unlock_irqrestore(&atchan->lock, flags); 487dc78baa2SNicolas Ferre } 488dc78baa2SNicolas Ferre 489dc78baa2SNicolas Ferre static irqreturn_t at_dma_interrupt(int irq, void *dev_id) 490dc78baa2SNicolas Ferre { 491dc78baa2SNicolas Ferre struct at_dma *atdma = (struct at_dma *)dev_id; 492dc78baa2SNicolas Ferre struct at_dma_chan *atchan; 493dc78baa2SNicolas Ferre int i; 494dc78baa2SNicolas Ferre u32 status, pending, imr; 495dc78baa2SNicolas Ferre int ret = IRQ_NONE; 496dc78baa2SNicolas Ferre 497dc78baa2SNicolas Ferre do { 498dc78baa2SNicolas Ferre imr = dma_readl(atdma, EBCIMR); 499dc78baa2SNicolas Ferre status = dma_readl(atdma, EBCISR); 500dc78baa2SNicolas Ferre pending = status & imr; 501dc78baa2SNicolas Ferre 502dc78baa2SNicolas Ferre if (!pending) 503dc78baa2SNicolas Ferre break; 504dc78baa2SNicolas Ferre 505dc78baa2SNicolas Ferre dev_vdbg(atdma->dma_common.dev, 506dc78baa2SNicolas Ferre "interrupt: status = 0x%08x, 0x%08x, 0x%08x\n", 507dc78baa2SNicolas Ferre status, imr, pending); 508dc78baa2SNicolas Ferre 509dc78baa2SNicolas Ferre for (i = 0; i < atdma->dma_common.chancnt; i++) { 510dc78baa2SNicolas Ferre atchan = &atdma->chan[i]; 5119b3aa589SNicolas Ferre if (pending & (AT_DMA_BTC(i) | AT_DMA_ERR(i))) { 512dc78baa2SNicolas Ferre if (pending & AT_DMA_ERR(i)) { 513dc78baa2SNicolas Ferre /* Disable channel on AHB error */ 51423b5e3adSNicolas Ferre dma_writel(atdma, CHDR, 51523b5e3adSNicolas Ferre AT_DMA_RES(i) | atchan->mask); 516dc78baa2SNicolas Ferre /* Give information to tasklet */ 51753830cc7SNicolas Ferre set_bit(ATC_IS_ERROR, &atchan->status); 518dc78baa2SNicolas Ferre } 519dc78baa2SNicolas Ferre tasklet_schedule(&atchan->tasklet); 520dc78baa2SNicolas Ferre ret = IRQ_HANDLED; 521dc78baa2SNicolas Ferre } 522dc78baa2SNicolas Ferre } 523dc78baa2SNicolas Ferre 524dc78baa2SNicolas Ferre } while (pending); 525dc78baa2SNicolas Ferre 526dc78baa2SNicolas Ferre return ret; 527dc78baa2SNicolas Ferre } 528dc78baa2SNicolas Ferre 529dc78baa2SNicolas Ferre 530dc78baa2SNicolas Ferre /*-- DMA Engine API --------------------------------------------------*/ 531dc78baa2SNicolas Ferre 532dc78baa2SNicolas Ferre /** 533dc78baa2SNicolas Ferre * atc_tx_submit - set the prepared descriptor(s) to be executed by the engine 534dc78baa2SNicolas Ferre * @desc: descriptor at the head of the transaction chain 535dc78baa2SNicolas Ferre * 536dc78baa2SNicolas Ferre * Queue chain if DMA engine is working already 537dc78baa2SNicolas Ferre * 538dc78baa2SNicolas Ferre * Cookie increment and adding to active_list or queue must be atomic 539dc78baa2SNicolas Ferre */ 540dc78baa2SNicolas Ferre static dma_cookie_t atc_tx_submit(struct dma_async_tx_descriptor *tx) 541dc78baa2SNicolas Ferre { 542dc78baa2SNicolas Ferre struct at_desc *desc = txd_to_at_desc(tx); 543dc78baa2SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(tx->chan); 544dc78baa2SNicolas Ferre dma_cookie_t cookie; 545d8cb04b0SNicolas Ferre unsigned long flags; 546dc78baa2SNicolas Ferre 547d8cb04b0SNicolas Ferre spin_lock_irqsave(&atchan->lock, flags); 548dc78baa2SNicolas Ferre cookie = atc_assign_cookie(atchan, desc); 549dc78baa2SNicolas Ferre 550dc78baa2SNicolas Ferre if (list_empty(&atchan->active_list)) { 551dc78baa2SNicolas Ferre dev_vdbg(chan2dev(tx->chan), "tx_submit: started %u\n", 552dc78baa2SNicolas Ferre desc->txd.cookie); 553dc78baa2SNicolas Ferre atc_dostart(atchan, desc); 554dc78baa2SNicolas Ferre list_add_tail(&desc->desc_node, &atchan->active_list); 555dc78baa2SNicolas Ferre } else { 556dc78baa2SNicolas Ferre dev_vdbg(chan2dev(tx->chan), "tx_submit: queued %u\n", 557dc78baa2SNicolas Ferre desc->txd.cookie); 558dc78baa2SNicolas Ferre list_add_tail(&desc->desc_node, &atchan->queue); 559dc78baa2SNicolas Ferre } 560dc78baa2SNicolas Ferre 561d8cb04b0SNicolas Ferre spin_unlock_irqrestore(&atchan->lock, flags); 562dc78baa2SNicolas Ferre 563dc78baa2SNicolas Ferre return cookie; 564dc78baa2SNicolas Ferre } 565dc78baa2SNicolas Ferre 566dc78baa2SNicolas Ferre /** 567dc78baa2SNicolas Ferre * atc_prep_dma_memcpy - prepare a memcpy operation 568dc78baa2SNicolas Ferre * @chan: the channel to prepare operation on 569dc78baa2SNicolas Ferre * @dest: operation virtual destination address 570dc78baa2SNicolas Ferre * @src: operation virtual source address 571dc78baa2SNicolas Ferre * @len: operation length 572dc78baa2SNicolas Ferre * @flags: tx descriptor status flags 573dc78baa2SNicolas Ferre */ 574dc78baa2SNicolas Ferre static struct dma_async_tx_descriptor * 575dc78baa2SNicolas Ferre atc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, 576dc78baa2SNicolas Ferre size_t len, unsigned long flags) 577dc78baa2SNicolas Ferre { 578dc78baa2SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 579dc78baa2SNicolas Ferre struct at_desc *desc = NULL; 580dc78baa2SNicolas Ferre struct at_desc *first = NULL; 581dc78baa2SNicolas Ferre struct at_desc *prev = NULL; 582dc78baa2SNicolas Ferre size_t xfer_count; 583dc78baa2SNicolas Ferre size_t offset; 584dc78baa2SNicolas Ferre unsigned int src_width; 585dc78baa2SNicolas Ferre unsigned int dst_width; 586dc78baa2SNicolas Ferre u32 ctrla; 587dc78baa2SNicolas Ferre u32 ctrlb; 588dc78baa2SNicolas Ferre 589dc78baa2SNicolas Ferre dev_vdbg(chan2dev(chan), "prep_dma_memcpy: d0x%x s0x%x l0x%zx f0x%lx\n", 590dc78baa2SNicolas Ferre dest, src, len, flags); 591dc78baa2SNicolas Ferre 592dc78baa2SNicolas Ferre if (unlikely(!len)) { 593dc78baa2SNicolas Ferre dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n"); 594dc78baa2SNicolas Ferre return NULL; 595dc78baa2SNicolas Ferre } 596dc78baa2SNicolas Ferre 597dc78baa2SNicolas Ferre ctrla = ATC_DEFAULT_CTRLA; 5989b3aa589SNicolas Ferre ctrlb = ATC_DEFAULT_CTRLB | ATC_IEN 599dc78baa2SNicolas Ferre | ATC_SRC_ADDR_MODE_INCR 600dc78baa2SNicolas Ferre | ATC_DST_ADDR_MODE_INCR 601dc78baa2SNicolas Ferre | ATC_FC_MEM2MEM; 602dc78baa2SNicolas Ferre 603dc78baa2SNicolas Ferre /* 604dc78baa2SNicolas Ferre * We can be a lot more clever here, but this should take care 605dc78baa2SNicolas Ferre * of the most common optimization. 606dc78baa2SNicolas Ferre */ 607dc78baa2SNicolas Ferre if (!((src | dest | len) & 3)) { 608dc78baa2SNicolas Ferre ctrla |= ATC_SRC_WIDTH_WORD | ATC_DST_WIDTH_WORD; 609dc78baa2SNicolas Ferre src_width = dst_width = 2; 610dc78baa2SNicolas Ferre } else if (!((src | dest | len) & 1)) { 611dc78baa2SNicolas Ferre ctrla |= ATC_SRC_WIDTH_HALFWORD | ATC_DST_WIDTH_HALFWORD; 612dc78baa2SNicolas Ferre src_width = dst_width = 1; 613dc78baa2SNicolas Ferre } else { 614dc78baa2SNicolas Ferre ctrla |= ATC_SRC_WIDTH_BYTE | ATC_DST_WIDTH_BYTE; 615dc78baa2SNicolas Ferre src_width = dst_width = 0; 616dc78baa2SNicolas Ferre } 617dc78baa2SNicolas Ferre 618dc78baa2SNicolas Ferre for (offset = 0; offset < len; offset += xfer_count << src_width) { 619dc78baa2SNicolas Ferre xfer_count = min_t(size_t, (len - offset) >> src_width, 620dc78baa2SNicolas Ferre ATC_BTSIZE_MAX); 621dc78baa2SNicolas Ferre 622dc78baa2SNicolas Ferre desc = atc_desc_get(atchan); 623dc78baa2SNicolas Ferre if (!desc) 624dc78baa2SNicolas Ferre goto err_desc_get; 625dc78baa2SNicolas Ferre 626dc78baa2SNicolas Ferre desc->lli.saddr = src + offset; 627dc78baa2SNicolas Ferre desc->lli.daddr = dest + offset; 628dc78baa2SNicolas Ferre desc->lli.ctrla = ctrla | xfer_count; 629dc78baa2SNicolas Ferre desc->lli.ctrlb = ctrlb; 630dc78baa2SNicolas Ferre 631dc78baa2SNicolas Ferre desc->txd.cookie = 0; 632dc78baa2SNicolas Ferre 633e257e156SNicolas Ferre atc_desc_chain(&first, &prev, desc); 634dc78baa2SNicolas Ferre } 635dc78baa2SNicolas Ferre 636dc78baa2SNicolas Ferre /* First descriptor of the chain embedds additional information */ 637dc78baa2SNicolas Ferre first->txd.cookie = -EBUSY; 638dc78baa2SNicolas Ferre first->len = len; 639dc78baa2SNicolas Ferre 640dc78baa2SNicolas Ferre /* set end-of-link to the last link descriptor of list*/ 641dc78baa2SNicolas Ferre set_desc_eol(desc); 642dc78baa2SNicolas Ferre 643568f7f0cSNicolas Ferre first->txd.flags = flags; /* client is in control of this ack */ 644dc78baa2SNicolas Ferre 645dc78baa2SNicolas Ferre return &first->txd; 646dc78baa2SNicolas Ferre 647dc78baa2SNicolas Ferre err_desc_get: 648dc78baa2SNicolas Ferre atc_desc_put(atchan, first); 649dc78baa2SNicolas Ferre return NULL; 650dc78baa2SNicolas Ferre } 651dc78baa2SNicolas Ferre 652808347f6SNicolas Ferre 653808347f6SNicolas Ferre /** 654808347f6SNicolas Ferre * atc_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction 655808347f6SNicolas Ferre * @chan: DMA channel 656808347f6SNicolas Ferre * @sgl: scatterlist to transfer to/from 657808347f6SNicolas Ferre * @sg_len: number of entries in @scatterlist 658808347f6SNicolas Ferre * @direction: DMA direction 659808347f6SNicolas Ferre * @flags: tx descriptor status flags 660808347f6SNicolas Ferre */ 661808347f6SNicolas Ferre static struct dma_async_tx_descriptor * 662808347f6SNicolas Ferre atc_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, 663808347f6SNicolas Ferre unsigned int sg_len, enum dma_data_direction direction, 664808347f6SNicolas Ferre unsigned long flags) 665808347f6SNicolas Ferre { 666808347f6SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 667808347f6SNicolas Ferre struct at_dma_slave *atslave = chan->private; 668808347f6SNicolas Ferre struct at_desc *first = NULL; 669808347f6SNicolas Ferre struct at_desc *prev = NULL; 670808347f6SNicolas Ferre u32 ctrla; 671808347f6SNicolas Ferre u32 ctrlb; 672808347f6SNicolas Ferre dma_addr_t reg; 673808347f6SNicolas Ferre unsigned int reg_width; 674808347f6SNicolas Ferre unsigned int mem_width; 675808347f6SNicolas Ferre unsigned int i; 676808347f6SNicolas Ferre struct scatterlist *sg; 677808347f6SNicolas Ferre size_t total_len = 0; 678808347f6SNicolas Ferre 679cc52a10aSNicolas Ferre dev_vdbg(chan2dev(chan), "prep_slave_sg (%d): %s f0x%lx\n", 680cc52a10aSNicolas Ferre sg_len, 681808347f6SNicolas Ferre direction == DMA_TO_DEVICE ? "TO DEVICE" : "FROM DEVICE", 682808347f6SNicolas Ferre flags); 683808347f6SNicolas Ferre 684808347f6SNicolas Ferre if (unlikely(!atslave || !sg_len)) { 685808347f6SNicolas Ferre dev_dbg(chan2dev(chan), "prep_dma_memcpy: length is zero!\n"); 686808347f6SNicolas Ferre return NULL; 687808347f6SNicolas Ferre } 688808347f6SNicolas Ferre 689808347f6SNicolas Ferre reg_width = atslave->reg_width; 690808347f6SNicolas Ferre 691808347f6SNicolas Ferre ctrla = ATC_DEFAULT_CTRLA | atslave->ctrla; 692ae14d4b5SNicolas Ferre ctrlb = ATC_IEN; 693808347f6SNicolas Ferre 694808347f6SNicolas Ferre switch (direction) { 695808347f6SNicolas Ferre case DMA_TO_DEVICE: 696808347f6SNicolas Ferre ctrla |= ATC_DST_WIDTH(reg_width); 697808347f6SNicolas Ferre ctrlb |= ATC_DST_ADDR_MODE_FIXED 698808347f6SNicolas Ferre | ATC_SRC_ADDR_MODE_INCR 699ae14d4b5SNicolas Ferre | ATC_FC_MEM2PER 700ae14d4b5SNicolas Ferre | ATC_SIF(AT_DMA_MEM_IF) | ATC_DIF(AT_DMA_PER_IF); 701808347f6SNicolas Ferre reg = atslave->tx_reg; 702808347f6SNicolas Ferre for_each_sg(sgl, sg, sg_len, i) { 703808347f6SNicolas Ferre struct at_desc *desc; 704808347f6SNicolas Ferre u32 len; 705808347f6SNicolas Ferre u32 mem; 706808347f6SNicolas Ferre 707808347f6SNicolas Ferre desc = atc_desc_get(atchan); 708808347f6SNicolas Ferre if (!desc) 709808347f6SNicolas Ferre goto err_desc_get; 710808347f6SNicolas Ferre 7110f70e8ceSNicolas Ferre mem = sg_dma_address(sg); 712808347f6SNicolas Ferre len = sg_dma_len(sg); 713808347f6SNicolas Ferre mem_width = 2; 714808347f6SNicolas Ferre if (unlikely(mem & 3 || len & 3)) 715808347f6SNicolas Ferre mem_width = 0; 716808347f6SNicolas Ferre 717808347f6SNicolas Ferre desc->lli.saddr = mem; 718808347f6SNicolas Ferre desc->lli.daddr = reg; 719808347f6SNicolas Ferre desc->lli.ctrla = ctrla 720808347f6SNicolas Ferre | ATC_SRC_WIDTH(mem_width) 721808347f6SNicolas Ferre | len >> mem_width; 722808347f6SNicolas Ferre desc->lli.ctrlb = ctrlb; 723808347f6SNicolas Ferre 724e257e156SNicolas Ferre atc_desc_chain(&first, &prev, desc); 725808347f6SNicolas Ferre total_len += len; 726808347f6SNicolas Ferre } 727808347f6SNicolas Ferre break; 728808347f6SNicolas Ferre case DMA_FROM_DEVICE: 729808347f6SNicolas Ferre ctrla |= ATC_SRC_WIDTH(reg_width); 730808347f6SNicolas Ferre ctrlb |= ATC_DST_ADDR_MODE_INCR 731808347f6SNicolas Ferre | ATC_SRC_ADDR_MODE_FIXED 732ae14d4b5SNicolas Ferre | ATC_FC_PER2MEM 733ae14d4b5SNicolas Ferre | ATC_SIF(AT_DMA_PER_IF) | ATC_DIF(AT_DMA_MEM_IF); 734808347f6SNicolas Ferre 735808347f6SNicolas Ferre reg = atslave->rx_reg; 736808347f6SNicolas Ferre for_each_sg(sgl, sg, sg_len, i) { 737808347f6SNicolas Ferre struct at_desc *desc; 738808347f6SNicolas Ferre u32 len; 739808347f6SNicolas Ferre u32 mem; 740808347f6SNicolas Ferre 741808347f6SNicolas Ferre desc = atc_desc_get(atchan); 742808347f6SNicolas Ferre if (!desc) 743808347f6SNicolas Ferre goto err_desc_get; 744808347f6SNicolas Ferre 7450f70e8ceSNicolas Ferre mem = sg_dma_address(sg); 746808347f6SNicolas Ferre len = sg_dma_len(sg); 747808347f6SNicolas Ferre mem_width = 2; 748808347f6SNicolas Ferre if (unlikely(mem & 3 || len & 3)) 749808347f6SNicolas Ferre mem_width = 0; 750808347f6SNicolas Ferre 751808347f6SNicolas Ferre desc->lli.saddr = reg; 752808347f6SNicolas Ferre desc->lli.daddr = mem; 753808347f6SNicolas Ferre desc->lli.ctrla = ctrla 754808347f6SNicolas Ferre | ATC_DST_WIDTH(mem_width) 75559a609d9SNicolas Ferre | len >> reg_width; 756808347f6SNicolas Ferre desc->lli.ctrlb = ctrlb; 757808347f6SNicolas Ferre 758e257e156SNicolas Ferre atc_desc_chain(&first, &prev, desc); 759808347f6SNicolas Ferre total_len += len; 760808347f6SNicolas Ferre } 761808347f6SNicolas Ferre break; 762808347f6SNicolas Ferre default: 763808347f6SNicolas Ferre return NULL; 764808347f6SNicolas Ferre } 765808347f6SNicolas Ferre 766808347f6SNicolas Ferre /* set end-of-link to the last link descriptor of list*/ 767808347f6SNicolas Ferre set_desc_eol(prev); 768808347f6SNicolas Ferre 769808347f6SNicolas Ferre /* First descriptor of the chain embedds additional information */ 770808347f6SNicolas Ferre first->txd.cookie = -EBUSY; 771808347f6SNicolas Ferre first->len = total_len; 772808347f6SNicolas Ferre 773568f7f0cSNicolas Ferre /* first link descriptor of list is responsible of flags */ 774568f7f0cSNicolas Ferre first->txd.flags = flags; /* client is in control of this ack */ 775808347f6SNicolas Ferre 776808347f6SNicolas Ferre return &first->txd; 777808347f6SNicolas Ferre 778808347f6SNicolas Ferre err_desc_get: 779808347f6SNicolas Ferre dev_err(chan2dev(chan), "not enough descriptors available\n"); 780808347f6SNicolas Ferre atc_desc_put(atchan, first); 781808347f6SNicolas Ferre return NULL; 782808347f6SNicolas Ferre } 783808347f6SNicolas Ferre 78453830cc7SNicolas Ferre /** 78553830cc7SNicolas Ferre * atc_dma_cyclic_check_values 78653830cc7SNicolas Ferre * Check for too big/unaligned periods and unaligned DMA buffer 78753830cc7SNicolas Ferre */ 78853830cc7SNicolas Ferre static int 78953830cc7SNicolas Ferre atc_dma_cyclic_check_values(unsigned int reg_width, dma_addr_t buf_addr, 79053830cc7SNicolas Ferre size_t period_len, enum dma_data_direction direction) 79153830cc7SNicolas Ferre { 79253830cc7SNicolas Ferre if (period_len > (ATC_BTSIZE_MAX << reg_width)) 79353830cc7SNicolas Ferre goto err_out; 79453830cc7SNicolas Ferre if (unlikely(period_len & ((1 << reg_width) - 1))) 79553830cc7SNicolas Ferre goto err_out; 79653830cc7SNicolas Ferre if (unlikely(buf_addr & ((1 << reg_width) - 1))) 79753830cc7SNicolas Ferre goto err_out; 79853830cc7SNicolas Ferre if (unlikely(!(direction & (DMA_TO_DEVICE | DMA_FROM_DEVICE)))) 79953830cc7SNicolas Ferre goto err_out; 80053830cc7SNicolas Ferre 80153830cc7SNicolas Ferre return 0; 80253830cc7SNicolas Ferre 80353830cc7SNicolas Ferre err_out: 80453830cc7SNicolas Ferre return -EINVAL; 80553830cc7SNicolas Ferre } 80653830cc7SNicolas Ferre 80753830cc7SNicolas Ferre /** 80853830cc7SNicolas Ferre * atc_dma_cyclic_fill_desc - Fill one period decriptor 80953830cc7SNicolas Ferre */ 81053830cc7SNicolas Ferre static int 81153830cc7SNicolas Ferre atc_dma_cyclic_fill_desc(struct at_dma_slave *atslave, struct at_desc *desc, 81253830cc7SNicolas Ferre unsigned int period_index, dma_addr_t buf_addr, 81353830cc7SNicolas Ferre size_t period_len, enum dma_data_direction direction) 81453830cc7SNicolas Ferre { 81553830cc7SNicolas Ferre u32 ctrla; 81653830cc7SNicolas Ferre unsigned int reg_width = atslave->reg_width; 81753830cc7SNicolas Ferre 81853830cc7SNicolas Ferre /* prepare common CRTLA value */ 81953830cc7SNicolas Ferre ctrla = ATC_DEFAULT_CTRLA | atslave->ctrla 82053830cc7SNicolas Ferre | ATC_DST_WIDTH(reg_width) 82153830cc7SNicolas Ferre | ATC_SRC_WIDTH(reg_width) 82253830cc7SNicolas Ferre | period_len >> reg_width; 82353830cc7SNicolas Ferre 82453830cc7SNicolas Ferre switch (direction) { 82553830cc7SNicolas Ferre case DMA_TO_DEVICE: 82653830cc7SNicolas Ferre desc->lli.saddr = buf_addr + (period_len * period_index); 82753830cc7SNicolas Ferre desc->lli.daddr = atslave->tx_reg; 82853830cc7SNicolas Ferre desc->lli.ctrla = ctrla; 829ae14d4b5SNicolas Ferre desc->lli.ctrlb = ATC_DST_ADDR_MODE_FIXED 83053830cc7SNicolas Ferre | ATC_SRC_ADDR_MODE_INCR 831ae14d4b5SNicolas Ferre | ATC_FC_MEM2PER 832ae14d4b5SNicolas Ferre | ATC_SIF(AT_DMA_MEM_IF) 833ae14d4b5SNicolas Ferre | ATC_DIF(AT_DMA_PER_IF); 83453830cc7SNicolas Ferre break; 83553830cc7SNicolas Ferre 83653830cc7SNicolas Ferre case DMA_FROM_DEVICE: 83753830cc7SNicolas Ferre desc->lli.saddr = atslave->rx_reg; 83853830cc7SNicolas Ferre desc->lli.daddr = buf_addr + (period_len * period_index); 83953830cc7SNicolas Ferre desc->lli.ctrla = ctrla; 840ae14d4b5SNicolas Ferre desc->lli.ctrlb = ATC_DST_ADDR_MODE_INCR 84153830cc7SNicolas Ferre | ATC_SRC_ADDR_MODE_FIXED 842ae14d4b5SNicolas Ferre | ATC_FC_PER2MEM 843ae14d4b5SNicolas Ferre | ATC_SIF(AT_DMA_PER_IF) 844ae14d4b5SNicolas Ferre | ATC_DIF(AT_DMA_MEM_IF); 84553830cc7SNicolas Ferre break; 84653830cc7SNicolas Ferre 84753830cc7SNicolas Ferre default: 84853830cc7SNicolas Ferre return -EINVAL; 84953830cc7SNicolas Ferre } 85053830cc7SNicolas Ferre 85153830cc7SNicolas Ferre return 0; 85253830cc7SNicolas Ferre } 85353830cc7SNicolas Ferre 85453830cc7SNicolas Ferre /** 85553830cc7SNicolas Ferre * atc_prep_dma_cyclic - prepare the cyclic DMA transfer 85653830cc7SNicolas Ferre * @chan: the DMA channel to prepare 85753830cc7SNicolas Ferre * @buf_addr: physical DMA address where the buffer starts 85853830cc7SNicolas Ferre * @buf_len: total number of bytes for the entire buffer 85953830cc7SNicolas Ferre * @period_len: number of bytes for each period 86053830cc7SNicolas Ferre * @direction: transfer direction, to or from device 86153830cc7SNicolas Ferre */ 86253830cc7SNicolas Ferre static struct dma_async_tx_descriptor * 86353830cc7SNicolas Ferre atc_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len, 86453830cc7SNicolas Ferre size_t period_len, enum dma_data_direction direction) 86553830cc7SNicolas Ferre { 86653830cc7SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 86753830cc7SNicolas Ferre struct at_dma_slave *atslave = chan->private; 86853830cc7SNicolas Ferre struct at_desc *first = NULL; 86953830cc7SNicolas Ferre struct at_desc *prev = NULL; 87053830cc7SNicolas Ferre unsigned long was_cyclic; 87153830cc7SNicolas Ferre unsigned int periods = buf_len / period_len; 87253830cc7SNicolas Ferre unsigned int i; 87353830cc7SNicolas Ferre 87453830cc7SNicolas Ferre dev_vdbg(chan2dev(chan), "prep_dma_cyclic: %s buf@0x%08x - %d (%d/%d)\n", 87553830cc7SNicolas Ferre direction == DMA_TO_DEVICE ? "TO DEVICE" : "FROM DEVICE", 87653830cc7SNicolas Ferre buf_addr, 87753830cc7SNicolas Ferre periods, buf_len, period_len); 87853830cc7SNicolas Ferre 87953830cc7SNicolas Ferre if (unlikely(!atslave || !buf_len || !period_len)) { 88053830cc7SNicolas Ferre dev_dbg(chan2dev(chan), "prep_dma_cyclic: length is zero!\n"); 88153830cc7SNicolas Ferre return NULL; 88253830cc7SNicolas Ferre } 88353830cc7SNicolas Ferre 88453830cc7SNicolas Ferre was_cyclic = test_and_set_bit(ATC_IS_CYCLIC, &atchan->status); 88553830cc7SNicolas Ferre if (was_cyclic) { 88653830cc7SNicolas Ferre dev_dbg(chan2dev(chan), "prep_dma_cyclic: channel in use!\n"); 88753830cc7SNicolas Ferre return NULL; 88853830cc7SNicolas Ferre } 88953830cc7SNicolas Ferre 89053830cc7SNicolas Ferre /* Check for too big/unaligned periods and unaligned DMA buffer */ 89153830cc7SNicolas Ferre if (atc_dma_cyclic_check_values(atslave->reg_width, buf_addr, 89253830cc7SNicolas Ferre period_len, direction)) 89353830cc7SNicolas Ferre goto err_out; 89453830cc7SNicolas Ferre 89553830cc7SNicolas Ferre /* build cyclic linked list */ 89653830cc7SNicolas Ferre for (i = 0; i < periods; i++) { 89753830cc7SNicolas Ferre struct at_desc *desc; 89853830cc7SNicolas Ferre 89953830cc7SNicolas Ferre desc = atc_desc_get(atchan); 90053830cc7SNicolas Ferre if (!desc) 90153830cc7SNicolas Ferre goto err_desc_get; 90253830cc7SNicolas Ferre 90353830cc7SNicolas Ferre if (atc_dma_cyclic_fill_desc(atslave, desc, i, buf_addr, 90453830cc7SNicolas Ferre period_len, direction)) 90553830cc7SNicolas Ferre goto err_desc_get; 90653830cc7SNicolas Ferre 90753830cc7SNicolas Ferre atc_desc_chain(&first, &prev, desc); 90853830cc7SNicolas Ferre } 90953830cc7SNicolas Ferre 91053830cc7SNicolas Ferre /* lets make a cyclic list */ 91153830cc7SNicolas Ferre prev->lli.dscr = first->txd.phys; 91253830cc7SNicolas Ferre 91353830cc7SNicolas Ferre /* First descriptor of the chain embedds additional information */ 91453830cc7SNicolas Ferre first->txd.cookie = -EBUSY; 91553830cc7SNicolas Ferre first->len = buf_len; 91653830cc7SNicolas Ferre 91753830cc7SNicolas Ferre return &first->txd; 91853830cc7SNicolas Ferre 91953830cc7SNicolas Ferre err_desc_get: 92053830cc7SNicolas Ferre dev_err(chan2dev(chan), "not enough descriptors available\n"); 92153830cc7SNicolas Ferre atc_desc_put(atchan, first); 92253830cc7SNicolas Ferre err_out: 92353830cc7SNicolas Ferre clear_bit(ATC_IS_CYCLIC, &atchan->status); 92453830cc7SNicolas Ferre return NULL; 92553830cc7SNicolas Ferre } 92653830cc7SNicolas Ferre 92753830cc7SNicolas Ferre 92805827630SLinus Walleij static int atc_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd, 92905827630SLinus Walleij unsigned long arg) 930808347f6SNicolas Ferre { 931808347f6SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 932808347f6SNicolas Ferre struct at_dma *atdma = to_at_dma(chan->device); 93323b5e3adSNicolas Ferre int chan_id = atchan->chan_common.chan_id; 934d8cb04b0SNicolas Ferre unsigned long flags; 93523b5e3adSNicolas Ferre 936808347f6SNicolas Ferre LIST_HEAD(list); 937808347f6SNicolas Ferre 93823b5e3adSNicolas Ferre dev_vdbg(chan2dev(chan), "atc_control (%d)\n", cmd); 939c3635c78SLinus Walleij 94023b5e3adSNicolas Ferre if (cmd == DMA_PAUSE) { 941d8cb04b0SNicolas Ferre spin_lock_irqsave(&atchan->lock, flags); 94223b5e3adSNicolas Ferre 94323b5e3adSNicolas Ferre dma_writel(atdma, CHER, AT_DMA_SUSP(chan_id)); 94423b5e3adSNicolas Ferre set_bit(ATC_IS_PAUSED, &atchan->status); 94523b5e3adSNicolas Ferre 946d8cb04b0SNicolas Ferre spin_unlock_irqrestore(&atchan->lock, flags); 94723b5e3adSNicolas Ferre } else if (cmd == DMA_RESUME) { 9483c477482SNicolas Ferre if (!atc_chan_is_paused(atchan)) 94923b5e3adSNicolas Ferre return 0; 95023b5e3adSNicolas Ferre 951d8cb04b0SNicolas Ferre spin_lock_irqsave(&atchan->lock, flags); 95223b5e3adSNicolas Ferre 95323b5e3adSNicolas Ferre dma_writel(atdma, CHDR, AT_DMA_RES(chan_id)); 95423b5e3adSNicolas Ferre clear_bit(ATC_IS_PAUSED, &atchan->status); 95523b5e3adSNicolas Ferre 956d8cb04b0SNicolas Ferre spin_unlock_irqrestore(&atchan->lock, flags); 95723b5e3adSNicolas Ferre } else if (cmd == DMA_TERMINATE_ALL) { 95823b5e3adSNicolas Ferre struct at_desc *desc, *_desc; 959808347f6SNicolas Ferre /* 960808347f6SNicolas Ferre * This is only called when something went wrong elsewhere, so 961808347f6SNicolas Ferre * we don't really care about the data. Just disable the 962808347f6SNicolas Ferre * channel. We still have to poll the channel enable bit due 963808347f6SNicolas Ferre * to AHB/HSB limitations. 964808347f6SNicolas Ferre */ 965d8cb04b0SNicolas Ferre spin_lock_irqsave(&atchan->lock, flags); 966808347f6SNicolas Ferre 96723b5e3adSNicolas Ferre /* disabling channel: must also remove suspend state */ 96823b5e3adSNicolas Ferre dma_writel(atdma, CHDR, AT_DMA_RES(chan_id) | atchan->mask); 969808347f6SNicolas Ferre 970808347f6SNicolas Ferre /* confirm that this channel is disabled */ 971808347f6SNicolas Ferre while (dma_readl(atdma, CHSR) & atchan->mask) 972808347f6SNicolas Ferre cpu_relax(); 973808347f6SNicolas Ferre 974808347f6SNicolas Ferre /* active_list entries will end up before queued entries */ 975808347f6SNicolas Ferre list_splice_init(&atchan->queue, &list); 976808347f6SNicolas Ferre list_splice_init(&atchan->active_list, &list); 977808347f6SNicolas Ferre 978808347f6SNicolas Ferre /* Flush all pending and queued descriptors */ 979808347f6SNicolas Ferre list_for_each_entry_safe(desc, _desc, &list, desc_node) 980808347f6SNicolas Ferre atc_chain_complete(atchan, desc); 981c3635c78SLinus Walleij 98223b5e3adSNicolas Ferre clear_bit(ATC_IS_PAUSED, &atchan->status); 98353830cc7SNicolas Ferre /* if channel dedicated to cyclic operations, free it */ 98453830cc7SNicolas Ferre clear_bit(ATC_IS_CYCLIC, &atchan->status); 98553830cc7SNicolas Ferre 986d8cb04b0SNicolas Ferre spin_unlock_irqrestore(&atchan->lock, flags); 98723b5e3adSNicolas Ferre } else { 98823b5e3adSNicolas Ferre return -ENXIO; 98923b5e3adSNicolas Ferre } 990b0ebeb9cSYong Wang 991c3635c78SLinus Walleij return 0; 992808347f6SNicolas Ferre } 993808347f6SNicolas Ferre 994dc78baa2SNicolas Ferre /** 99507934481SLinus Walleij * atc_tx_status - poll for transaction completion 996dc78baa2SNicolas Ferre * @chan: DMA channel 997dc78baa2SNicolas Ferre * @cookie: transaction identifier to check status of 99807934481SLinus Walleij * @txstate: if not %NULL updated with transaction state 999dc78baa2SNicolas Ferre * 100007934481SLinus Walleij * If @txstate is passed in, upon return it reflect the driver 1001dc78baa2SNicolas Ferre * internal state and can be used with dma_async_is_complete() to check 1002dc78baa2SNicolas Ferre * the status of multiple cookies without re-checking hardware state. 1003dc78baa2SNicolas Ferre */ 1004dc78baa2SNicolas Ferre static enum dma_status 100507934481SLinus Walleij atc_tx_status(struct dma_chan *chan, 1006dc78baa2SNicolas Ferre dma_cookie_t cookie, 100707934481SLinus Walleij struct dma_tx_state *txstate) 1008dc78baa2SNicolas Ferre { 1009dc78baa2SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 1010dc78baa2SNicolas Ferre dma_cookie_t last_used; 1011dc78baa2SNicolas Ferre dma_cookie_t last_complete; 1012d8cb04b0SNicolas Ferre unsigned long flags; 1013dc78baa2SNicolas Ferre enum dma_status ret; 1014dc78baa2SNicolas Ferre 1015d8cb04b0SNicolas Ferre spin_lock_irqsave(&atchan->lock, flags); 1016dc78baa2SNicolas Ferre 1017dc78baa2SNicolas Ferre last_complete = atchan->completed_cookie; 1018dc78baa2SNicolas Ferre last_used = chan->cookie; 1019dc78baa2SNicolas Ferre 1020dc78baa2SNicolas Ferre ret = dma_async_is_complete(cookie, last_complete, last_used); 1021dc78baa2SNicolas Ferre if (ret != DMA_SUCCESS) { 1022dc78baa2SNicolas Ferre atc_cleanup_descriptors(atchan); 1023dc78baa2SNicolas Ferre 1024dc78baa2SNicolas Ferre last_complete = atchan->completed_cookie; 1025dc78baa2SNicolas Ferre last_used = chan->cookie; 1026dc78baa2SNicolas Ferre 1027dc78baa2SNicolas Ferre ret = dma_async_is_complete(cookie, last_complete, last_used); 1028dc78baa2SNicolas Ferre } 1029dc78baa2SNicolas Ferre 1030d8cb04b0SNicolas Ferre spin_unlock_irqrestore(&atchan->lock, flags); 1031dc78baa2SNicolas Ferre 1032543aabc7SNicolas Ferre if (ret != DMA_SUCCESS) 1033543aabc7SNicolas Ferre dma_set_tx_state(txstate, last_complete, last_used, 1034543aabc7SNicolas Ferre atc_first_active(atchan)->len); 1035543aabc7SNicolas Ferre else 1036bca34692SDan Williams dma_set_tx_state(txstate, last_complete, last_used, 0); 1037543aabc7SNicolas Ferre 10383c477482SNicolas Ferre if (atc_chan_is_paused(atchan)) 103923b5e3adSNicolas Ferre ret = DMA_PAUSED; 104023b5e3adSNicolas Ferre 104123b5e3adSNicolas Ferre dev_vdbg(chan2dev(chan), "tx_status %d: cookie = %d (d%d, u%d)\n", 104223b5e3adSNicolas Ferre ret, cookie, last_complete ? last_complete : 0, 104307934481SLinus Walleij last_used ? last_used : 0); 1044dc78baa2SNicolas Ferre 1045dc78baa2SNicolas Ferre return ret; 1046dc78baa2SNicolas Ferre } 1047dc78baa2SNicolas Ferre 1048dc78baa2SNicolas Ferre /** 1049dc78baa2SNicolas Ferre * atc_issue_pending - try to finish work 1050dc78baa2SNicolas Ferre * @chan: target DMA channel 1051dc78baa2SNicolas Ferre */ 1052dc78baa2SNicolas Ferre static void atc_issue_pending(struct dma_chan *chan) 1053dc78baa2SNicolas Ferre { 1054dc78baa2SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 1055d8cb04b0SNicolas Ferre unsigned long flags; 1056dc78baa2SNicolas Ferre 1057dc78baa2SNicolas Ferre dev_vdbg(chan2dev(chan), "issue_pending\n"); 1058dc78baa2SNicolas Ferre 105953830cc7SNicolas Ferre /* Not needed for cyclic transfers */ 10603c477482SNicolas Ferre if (atc_chan_is_cyclic(atchan)) 106153830cc7SNicolas Ferre return; 106253830cc7SNicolas Ferre 1063d8cb04b0SNicolas Ferre spin_lock_irqsave(&atchan->lock, flags); 1064dda36f98SNicolas Ferre if (!atc_chan_is_enabled(atchan)) { 1065dc78baa2SNicolas Ferre atc_advance_work(atchan); 1066dc78baa2SNicolas Ferre } 1067d8cb04b0SNicolas Ferre spin_unlock_irqrestore(&atchan->lock, flags); 1068dc78baa2SNicolas Ferre } 1069dc78baa2SNicolas Ferre 1070dc78baa2SNicolas Ferre /** 1071dc78baa2SNicolas Ferre * atc_alloc_chan_resources - allocate resources for DMA channel 1072dc78baa2SNicolas Ferre * @chan: allocate descriptor resources for this channel 1073dc78baa2SNicolas Ferre * @client: current client requesting the channel be ready for requests 1074dc78baa2SNicolas Ferre * 1075dc78baa2SNicolas Ferre * return - the number of allocated descriptors 1076dc78baa2SNicolas Ferre */ 1077dc78baa2SNicolas Ferre static int atc_alloc_chan_resources(struct dma_chan *chan) 1078dc78baa2SNicolas Ferre { 1079dc78baa2SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 1080dc78baa2SNicolas Ferre struct at_dma *atdma = to_at_dma(chan->device); 1081dc78baa2SNicolas Ferre struct at_desc *desc; 1082808347f6SNicolas Ferre struct at_dma_slave *atslave; 1083d8cb04b0SNicolas Ferre unsigned long flags; 1084dc78baa2SNicolas Ferre int i; 1085808347f6SNicolas Ferre u32 cfg; 1086dc78baa2SNicolas Ferre LIST_HEAD(tmp_list); 1087dc78baa2SNicolas Ferre 1088dc78baa2SNicolas Ferre dev_vdbg(chan2dev(chan), "alloc_chan_resources\n"); 1089dc78baa2SNicolas Ferre 1090dc78baa2SNicolas Ferre /* ASSERT: channel is idle */ 1091dc78baa2SNicolas Ferre if (atc_chan_is_enabled(atchan)) { 1092dc78baa2SNicolas Ferre dev_dbg(chan2dev(chan), "DMA channel not idle ?\n"); 1093dc78baa2SNicolas Ferre return -EIO; 1094dc78baa2SNicolas Ferre } 1095dc78baa2SNicolas Ferre 1096808347f6SNicolas Ferre cfg = ATC_DEFAULT_CFG; 1097808347f6SNicolas Ferre 1098808347f6SNicolas Ferre atslave = chan->private; 1099808347f6SNicolas Ferre if (atslave) { 1100808347f6SNicolas Ferre /* 1101808347f6SNicolas Ferre * We need controller-specific data to set up slave 1102808347f6SNicolas Ferre * transfers. 1103808347f6SNicolas Ferre */ 1104808347f6SNicolas Ferre BUG_ON(!atslave->dma_dev || atslave->dma_dev != atdma->dma_common.dev); 1105808347f6SNicolas Ferre 1106808347f6SNicolas Ferre /* if cfg configuration specified take it instad of default */ 1107808347f6SNicolas Ferre if (atslave->cfg) 1108808347f6SNicolas Ferre cfg = atslave->cfg; 1109808347f6SNicolas Ferre } 1110808347f6SNicolas Ferre 1111808347f6SNicolas Ferre /* have we already been set up? 1112808347f6SNicolas Ferre * reconfigure channel but no need to reallocate descriptors */ 1113dc78baa2SNicolas Ferre if (!list_empty(&atchan->free_list)) 1114dc78baa2SNicolas Ferre return atchan->descs_allocated; 1115dc78baa2SNicolas Ferre 1116dc78baa2SNicolas Ferre /* Allocate initial pool of descriptors */ 1117dc78baa2SNicolas Ferre for (i = 0; i < init_nr_desc_per_channel; i++) { 1118dc78baa2SNicolas Ferre desc = atc_alloc_descriptor(chan, GFP_KERNEL); 1119dc78baa2SNicolas Ferre if (!desc) { 1120dc78baa2SNicolas Ferre dev_err(atdma->dma_common.dev, 1121dc78baa2SNicolas Ferre "Only %d initial descriptors\n", i); 1122dc78baa2SNicolas Ferre break; 1123dc78baa2SNicolas Ferre } 1124dc78baa2SNicolas Ferre list_add_tail(&desc->desc_node, &tmp_list); 1125dc78baa2SNicolas Ferre } 1126dc78baa2SNicolas Ferre 1127d8cb04b0SNicolas Ferre spin_lock_irqsave(&atchan->lock, flags); 1128dc78baa2SNicolas Ferre atchan->descs_allocated = i; 1129dc78baa2SNicolas Ferre list_splice(&tmp_list, &atchan->free_list); 1130dc78baa2SNicolas Ferre atchan->completed_cookie = chan->cookie = 1; 1131d8cb04b0SNicolas Ferre spin_unlock_irqrestore(&atchan->lock, flags); 1132dc78baa2SNicolas Ferre 1133dc78baa2SNicolas Ferre /* channel parameters */ 1134808347f6SNicolas Ferre channel_writel(atchan, CFG, cfg); 1135dc78baa2SNicolas Ferre 1136dc78baa2SNicolas Ferre dev_dbg(chan2dev(chan), 1137dc78baa2SNicolas Ferre "alloc_chan_resources: allocated %d descriptors\n", 1138dc78baa2SNicolas Ferre atchan->descs_allocated); 1139dc78baa2SNicolas Ferre 1140dc78baa2SNicolas Ferre return atchan->descs_allocated; 1141dc78baa2SNicolas Ferre } 1142dc78baa2SNicolas Ferre 1143dc78baa2SNicolas Ferre /** 1144dc78baa2SNicolas Ferre * atc_free_chan_resources - free all channel resources 1145dc78baa2SNicolas Ferre * @chan: DMA channel 1146dc78baa2SNicolas Ferre */ 1147dc78baa2SNicolas Ferre static void atc_free_chan_resources(struct dma_chan *chan) 1148dc78baa2SNicolas Ferre { 1149dc78baa2SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 1150dc78baa2SNicolas Ferre struct at_dma *atdma = to_at_dma(chan->device); 1151dc78baa2SNicolas Ferre struct at_desc *desc, *_desc; 1152dc78baa2SNicolas Ferre LIST_HEAD(list); 1153dc78baa2SNicolas Ferre 1154dc78baa2SNicolas Ferre dev_dbg(chan2dev(chan), "free_chan_resources: (descs allocated=%u)\n", 1155dc78baa2SNicolas Ferre atchan->descs_allocated); 1156dc78baa2SNicolas Ferre 1157dc78baa2SNicolas Ferre /* ASSERT: channel is idle */ 1158dc78baa2SNicolas Ferre BUG_ON(!list_empty(&atchan->active_list)); 1159dc78baa2SNicolas Ferre BUG_ON(!list_empty(&atchan->queue)); 1160dc78baa2SNicolas Ferre BUG_ON(atc_chan_is_enabled(atchan)); 1161dc78baa2SNicolas Ferre 1162dc78baa2SNicolas Ferre list_for_each_entry_safe(desc, _desc, &atchan->free_list, desc_node) { 1163dc78baa2SNicolas Ferre dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc); 1164dc78baa2SNicolas Ferre list_del(&desc->desc_node); 1165dc78baa2SNicolas Ferre /* free link descriptor */ 1166dc78baa2SNicolas Ferre dma_pool_free(atdma->dma_desc_pool, desc, desc->txd.phys); 1167dc78baa2SNicolas Ferre } 1168dc78baa2SNicolas Ferre list_splice_init(&atchan->free_list, &list); 1169dc78baa2SNicolas Ferre atchan->descs_allocated = 0; 117053830cc7SNicolas Ferre atchan->status = 0; 1171dc78baa2SNicolas Ferre 1172dc78baa2SNicolas Ferre dev_vdbg(chan2dev(chan), "free_chan_resources: done\n"); 1173dc78baa2SNicolas Ferre } 1174dc78baa2SNicolas Ferre 1175dc78baa2SNicolas Ferre 1176dc78baa2SNicolas Ferre /*-- Module Management -----------------------------------------------*/ 1177dc78baa2SNicolas Ferre 1178dc78baa2SNicolas Ferre /** 1179dc78baa2SNicolas Ferre * at_dma_off - disable DMA controller 1180dc78baa2SNicolas Ferre * @atdma: the Atmel HDAMC device 1181dc78baa2SNicolas Ferre */ 1182dc78baa2SNicolas Ferre static void at_dma_off(struct at_dma *atdma) 1183dc78baa2SNicolas Ferre { 1184dc78baa2SNicolas Ferre dma_writel(atdma, EN, 0); 1185dc78baa2SNicolas Ferre 1186dc78baa2SNicolas Ferre /* disable all interrupts */ 1187dc78baa2SNicolas Ferre dma_writel(atdma, EBCIDR, -1L); 1188dc78baa2SNicolas Ferre 1189dc78baa2SNicolas Ferre /* confirm that all channels are disabled */ 1190dc78baa2SNicolas Ferre while (dma_readl(atdma, CHSR) & atdma->all_chan_mask) 1191dc78baa2SNicolas Ferre cpu_relax(); 1192dc78baa2SNicolas Ferre } 1193dc78baa2SNicolas Ferre 1194dc78baa2SNicolas Ferre static int __init at_dma_probe(struct platform_device *pdev) 1195dc78baa2SNicolas Ferre { 1196dc78baa2SNicolas Ferre struct at_dma_platform_data *pdata; 1197dc78baa2SNicolas Ferre struct resource *io; 1198dc78baa2SNicolas Ferre struct at_dma *atdma; 1199dc78baa2SNicolas Ferre size_t size; 1200dc78baa2SNicolas Ferre int irq; 1201dc78baa2SNicolas Ferre int err; 1202dc78baa2SNicolas Ferre int i; 1203dc78baa2SNicolas Ferre 1204dc78baa2SNicolas Ferre /* get DMA Controller parameters from platform */ 1205dc78baa2SNicolas Ferre pdata = pdev->dev.platform_data; 1206dc78baa2SNicolas Ferre if (!pdata || pdata->nr_channels > AT_DMA_MAX_NR_CHANNELS) 1207dc78baa2SNicolas Ferre return -EINVAL; 1208dc78baa2SNicolas Ferre 1209dc78baa2SNicolas Ferre io = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1210dc78baa2SNicolas Ferre if (!io) 1211dc78baa2SNicolas Ferre return -EINVAL; 1212dc78baa2SNicolas Ferre 1213dc78baa2SNicolas Ferre irq = platform_get_irq(pdev, 0); 1214dc78baa2SNicolas Ferre if (irq < 0) 1215dc78baa2SNicolas Ferre return irq; 1216dc78baa2SNicolas Ferre 1217dc78baa2SNicolas Ferre size = sizeof(struct at_dma); 1218dc78baa2SNicolas Ferre size += pdata->nr_channels * sizeof(struct at_dma_chan); 1219dc78baa2SNicolas Ferre atdma = kzalloc(size, GFP_KERNEL); 1220dc78baa2SNicolas Ferre if (!atdma) 1221dc78baa2SNicolas Ferre return -ENOMEM; 1222dc78baa2SNicolas Ferre 1223dc78baa2SNicolas Ferre /* discover transaction capabilites from the platform data */ 1224dc78baa2SNicolas Ferre atdma->dma_common.cap_mask = pdata->cap_mask; 1225dc78baa2SNicolas Ferre atdma->all_chan_mask = (1 << pdata->nr_channels) - 1; 1226dc78baa2SNicolas Ferre 1227114df7d6SH Hartley Sweeten size = resource_size(io); 1228dc78baa2SNicolas Ferre if (!request_mem_region(io->start, size, pdev->dev.driver->name)) { 1229dc78baa2SNicolas Ferre err = -EBUSY; 1230dc78baa2SNicolas Ferre goto err_kfree; 1231dc78baa2SNicolas Ferre } 1232dc78baa2SNicolas Ferre 1233dc78baa2SNicolas Ferre atdma->regs = ioremap(io->start, size); 1234dc78baa2SNicolas Ferre if (!atdma->regs) { 1235dc78baa2SNicolas Ferre err = -ENOMEM; 1236dc78baa2SNicolas Ferre goto err_release_r; 1237dc78baa2SNicolas Ferre } 1238dc78baa2SNicolas Ferre 1239dc78baa2SNicolas Ferre atdma->clk = clk_get(&pdev->dev, "dma_clk"); 1240dc78baa2SNicolas Ferre if (IS_ERR(atdma->clk)) { 1241dc78baa2SNicolas Ferre err = PTR_ERR(atdma->clk); 1242dc78baa2SNicolas Ferre goto err_clk; 1243dc78baa2SNicolas Ferre } 1244dc78baa2SNicolas Ferre clk_enable(atdma->clk); 1245dc78baa2SNicolas Ferre 1246dc78baa2SNicolas Ferre /* force dma off, just in case */ 1247dc78baa2SNicolas Ferre at_dma_off(atdma); 1248dc78baa2SNicolas Ferre 1249dc78baa2SNicolas Ferre err = request_irq(irq, at_dma_interrupt, 0, "at_hdmac", atdma); 1250dc78baa2SNicolas Ferre if (err) 1251dc78baa2SNicolas Ferre goto err_irq; 1252dc78baa2SNicolas Ferre 1253dc78baa2SNicolas Ferre platform_set_drvdata(pdev, atdma); 1254dc78baa2SNicolas Ferre 1255dc78baa2SNicolas Ferre /* create a pool of consistent memory blocks for hardware descriptors */ 1256dc78baa2SNicolas Ferre atdma->dma_desc_pool = dma_pool_create("at_hdmac_desc_pool", 1257dc78baa2SNicolas Ferre &pdev->dev, sizeof(struct at_desc), 1258dc78baa2SNicolas Ferre 4 /* word alignment */, 0); 1259dc78baa2SNicolas Ferre if (!atdma->dma_desc_pool) { 1260dc78baa2SNicolas Ferre dev_err(&pdev->dev, "No memory for descriptors dma pool\n"); 1261dc78baa2SNicolas Ferre err = -ENOMEM; 1262dc78baa2SNicolas Ferre goto err_pool_create; 1263dc78baa2SNicolas Ferre } 1264dc78baa2SNicolas Ferre 1265dc78baa2SNicolas Ferre /* clear any pending interrupt */ 1266dc78baa2SNicolas Ferre while (dma_readl(atdma, EBCISR)) 1267dc78baa2SNicolas Ferre cpu_relax(); 1268dc78baa2SNicolas Ferre 1269dc78baa2SNicolas Ferre /* initialize channels related values */ 1270dc78baa2SNicolas Ferre INIT_LIST_HEAD(&atdma->dma_common.channels); 1271dc78baa2SNicolas Ferre for (i = 0; i < pdata->nr_channels; i++, atdma->dma_common.chancnt++) { 1272dc78baa2SNicolas Ferre struct at_dma_chan *atchan = &atdma->chan[i]; 1273dc78baa2SNicolas Ferre 1274dc78baa2SNicolas Ferre atchan->chan_common.device = &atdma->dma_common; 1275dc78baa2SNicolas Ferre atchan->chan_common.cookie = atchan->completed_cookie = 1; 1276dc78baa2SNicolas Ferre atchan->chan_common.chan_id = i; 1277dc78baa2SNicolas Ferre list_add_tail(&atchan->chan_common.device_node, 1278dc78baa2SNicolas Ferre &atdma->dma_common.channels); 1279dc78baa2SNicolas Ferre 1280dc78baa2SNicolas Ferre atchan->ch_regs = atdma->regs + ch_regs(i); 1281dc78baa2SNicolas Ferre spin_lock_init(&atchan->lock); 1282dc78baa2SNicolas Ferre atchan->mask = 1 << i; 1283dc78baa2SNicolas Ferre 1284dc78baa2SNicolas Ferre INIT_LIST_HEAD(&atchan->active_list); 1285dc78baa2SNicolas Ferre INIT_LIST_HEAD(&atchan->queue); 1286dc78baa2SNicolas Ferre INIT_LIST_HEAD(&atchan->free_list); 1287dc78baa2SNicolas Ferre 1288dc78baa2SNicolas Ferre tasklet_init(&atchan->tasklet, atc_tasklet, 1289dc78baa2SNicolas Ferre (unsigned long)atchan); 1290dc78baa2SNicolas Ferre atc_enable_irq(atchan); 1291dc78baa2SNicolas Ferre } 1292dc78baa2SNicolas Ferre 1293dc78baa2SNicolas Ferre /* set base routines */ 1294dc78baa2SNicolas Ferre atdma->dma_common.device_alloc_chan_resources = atc_alloc_chan_resources; 1295dc78baa2SNicolas Ferre atdma->dma_common.device_free_chan_resources = atc_free_chan_resources; 129607934481SLinus Walleij atdma->dma_common.device_tx_status = atc_tx_status; 1297dc78baa2SNicolas Ferre atdma->dma_common.device_issue_pending = atc_issue_pending; 1298dc78baa2SNicolas Ferre atdma->dma_common.dev = &pdev->dev; 1299dc78baa2SNicolas Ferre 1300dc78baa2SNicolas Ferre /* set prep routines based on capability */ 1301dc78baa2SNicolas Ferre if (dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask)) 1302dc78baa2SNicolas Ferre atdma->dma_common.device_prep_dma_memcpy = atc_prep_dma_memcpy; 1303dc78baa2SNicolas Ferre 130453830cc7SNicolas Ferre if (dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask)) 1305808347f6SNicolas Ferre atdma->dma_common.device_prep_slave_sg = atc_prep_slave_sg; 130653830cc7SNicolas Ferre 130753830cc7SNicolas Ferre if (dma_has_cap(DMA_CYCLIC, atdma->dma_common.cap_mask)) 130853830cc7SNicolas Ferre atdma->dma_common.device_prep_dma_cyclic = atc_prep_dma_cyclic; 130953830cc7SNicolas Ferre 131053830cc7SNicolas Ferre if (dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask) || 131153830cc7SNicolas Ferre dma_has_cap(DMA_CYCLIC, atdma->dma_common.cap_mask)) 1312c3635c78SLinus Walleij atdma->dma_common.device_control = atc_control; 1313808347f6SNicolas Ferre 1314dc78baa2SNicolas Ferre dma_writel(atdma, EN, AT_DMA_ENABLE); 1315dc78baa2SNicolas Ferre 1316dc78baa2SNicolas Ferre dev_info(&pdev->dev, "Atmel AHB DMA Controller ( %s%s), %d channels\n", 1317dc78baa2SNicolas Ferre dma_has_cap(DMA_MEMCPY, atdma->dma_common.cap_mask) ? "cpy " : "", 1318dc78baa2SNicolas Ferre dma_has_cap(DMA_SLAVE, atdma->dma_common.cap_mask) ? "slave " : "", 1319dc78baa2SNicolas Ferre atdma->dma_common.chancnt); 1320dc78baa2SNicolas Ferre 1321dc78baa2SNicolas Ferre dma_async_device_register(&atdma->dma_common); 1322dc78baa2SNicolas Ferre 1323dc78baa2SNicolas Ferre return 0; 1324dc78baa2SNicolas Ferre 1325dc78baa2SNicolas Ferre err_pool_create: 1326dc78baa2SNicolas Ferre platform_set_drvdata(pdev, NULL); 1327dc78baa2SNicolas Ferre free_irq(platform_get_irq(pdev, 0), atdma); 1328dc78baa2SNicolas Ferre err_irq: 1329dc78baa2SNicolas Ferre clk_disable(atdma->clk); 1330dc78baa2SNicolas Ferre clk_put(atdma->clk); 1331dc78baa2SNicolas Ferre err_clk: 1332dc78baa2SNicolas Ferre iounmap(atdma->regs); 1333dc78baa2SNicolas Ferre atdma->regs = NULL; 1334dc78baa2SNicolas Ferre err_release_r: 1335dc78baa2SNicolas Ferre release_mem_region(io->start, size); 1336dc78baa2SNicolas Ferre err_kfree: 1337dc78baa2SNicolas Ferre kfree(atdma); 1338dc78baa2SNicolas Ferre return err; 1339dc78baa2SNicolas Ferre } 1340dc78baa2SNicolas Ferre 1341dc78baa2SNicolas Ferre static int __exit at_dma_remove(struct platform_device *pdev) 1342dc78baa2SNicolas Ferre { 1343dc78baa2SNicolas Ferre struct at_dma *atdma = platform_get_drvdata(pdev); 1344dc78baa2SNicolas Ferre struct dma_chan *chan, *_chan; 1345dc78baa2SNicolas Ferre struct resource *io; 1346dc78baa2SNicolas Ferre 1347dc78baa2SNicolas Ferre at_dma_off(atdma); 1348dc78baa2SNicolas Ferre dma_async_device_unregister(&atdma->dma_common); 1349dc78baa2SNicolas Ferre 1350dc78baa2SNicolas Ferre dma_pool_destroy(atdma->dma_desc_pool); 1351dc78baa2SNicolas Ferre platform_set_drvdata(pdev, NULL); 1352dc78baa2SNicolas Ferre free_irq(platform_get_irq(pdev, 0), atdma); 1353dc78baa2SNicolas Ferre 1354dc78baa2SNicolas Ferre list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels, 1355dc78baa2SNicolas Ferre device_node) { 1356dc78baa2SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 1357dc78baa2SNicolas Ferre 1358dc78baa2SNicolas Ferre /* Disable interrupts */ 1359dc78baa2SNicolas Ferre atc_disable_irq(atchan); 1360dc78baa2SNicolas Ferre tasklet_disable(&atchan->tasklet); 1361dc78baa2SNicolas Ferre 1362dc78baa2SNicolas Ferre tasklet_kill(&atchan->tasklet); 1363dc78baa2SNicolas Ferre list_del(&chan->device_node); 1364dc78baa2SNicolas Ferre } 1365dc78baa2SNicolas Ferre 1366dc78baa2SNicolas Ferre clk_disable(atdma->clk); 1367dc78baa2SNicolas Ferre clk_put(atdma->clk); 1368dc78baa2SNicolas Ferre 1369dc78baa2SNicolas Ferre iounmap(atdma->regs); 1370dc78baa2SNicolas Ferre atdma->regs = NULL; 1371dc78baa2SNicolas Ferre 1372dc78baa2SNicolas Ferre io = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1373114df7d6SH Hartley Sweeten release_mem_region(io->start, resource_size(io)); 1374dc78baa2SNicolas Ferre 1375dc78baa2SNicolas Ferre kfree(atdma); 1376dc78baa2SNicolas Ferre 1377dc78baa2SNicolas Ferre return 0; 1378dc78baa2SNicolas Ferre } 1379dc78baa2SNicolas Ferre 1380dc78baa2SNicolas Ferre static void at_dma_shutdown(struct platform_device *pdev) 1381dc78baa2SNicolas Ferre { 1382dc78baa2SNicolas Ferre struct at_dma *atdma = platform_get_drvdata(pdev); 1383dc78baa2SNicolas Ferre 1384dc78baa2SNicolas Ferre at_dma_off(platform_get_drvdata(pdev)); 1385dc78baa2SNicolas Ferre clk_disable(atdma->clk); 1386dc78baa2SNicolas Ferre } 1387dc78baa2SNicolas Ferre 1388c0ba5947SNicolas Ferre static int at_dma_prepare(struct device *dev) 1389c0ba5947SNicolas Ferre { 1390c0ba5947SNicolas Ferre struct platform_device *pdev = to_platform_device(dev); 1391c0ba5947SNicolas Ferre struct at_dma *atdma = platform_get_drvdata(pdev); 1392c0ba5947SNicolas Ferre struct dma_chan *chan, *_chan; 1393c0ba5947SNicolas Ferre 1394c0ba5947SNicolas Ferre list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels, 1395c0ba5947SNicolas Ferre device_node) { 1396c0ba5947SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 1397c0ba5947SNicolas Ferre /* wait for transaction completion (except in cyclic case) */ 13983c477482SNicolas Ferre if (atc_chan_is_enabled(atchan) && !atc_chan_is_cyclic(atchan)) 1399c0ba5947SNicolas Ferre return -EAGAIN; 1400c0ba5947SNicolas Ferre } 1401c0ba5947SNicolas Ferre return 0; 1402c0ba5947SNicolas Ferre } 1403c0ba5947SNicolas Ferre 1404c0ba5947SNicolas Ferre static void atc_suspend_cyclic(struct at_dma_chan *atchan) 1405c0ba5947SNicolas Ferre { 1406c0ba5947SNicolas Ferre struct dma_chan *chan = &atchan->chan_common; 1407c0ba5947SNicolas Ferre 1408c0ba5947SNicolas Ferre /* Channel should be paused by user 1409c0ba5947SNicolas Ferre * do it anyway even if it is not done already */ 14103c477482SNicolas Ferre if (!atc_chan_is_paused(atchan)) { 1411c0ba5947SNicolas Ferre dev_warn(chan2dev(chan), 1412c0ba5947SNicolas Ferre "cyclic channel not paused, should be done by channel user\n"); 1413c0ba5947SNicolas Ferre atc_control(chan, DMA_PAUSE, 0); 1414c0ba5947SNicolas Ferre } 1415c0ba5947SNicolas Ferre 1416c0ba5947SNicolas Ferre /* now preserve additional data for cyclic operations */ 1417c0ba5947SNicolas Ferre /* next descriptor address in the cyclic list */ 1418c0ba5947SNicolas Ferre atchan->save_dscr = channel_readl(atchan, DSCR); 1419c0ba5947SNicolas Ferre 1420c0ba5947SNicolas Ferre vdbg_dump_regs(atchan); 1421c0ba5947SNicolas Ferre } 1422c0ba5947SNicolas Ferre 142333f82d14SDan Williams static int at_dma_suspend_noirq(struct device *dev) 1424dc78baa2SNicolas Ferre { 142533f82d14SDan Williams struct platform_device *pdev = to_platform_device(dev); 1426dc78baa2SNicolas Ferre struct at_dma *atdma = platform_get_drvdata(pdev); 1427c0ba5947SNicolas Ferre struct dma_chan *chan, *_chan; 1428dc78baa2SNicolas Ferre 1429c0ba5947SNicolas Ferre /* preserve data */ 1430c0ba5947SNicolas Ferre list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels, 1431c0ba5947SNicolas Ferre device_node) { 1432c0ba5947SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 1433c0ba5947SNicolas Ferre 14343c477482SNicolas Ferre if (atc_chan_is_cyclic(atchan)) 1435c0ba5947SNicolas Ferre atc_suspend_cyclic(atchan); 1436c0ba5947SNicolas Ferre atchan->save_cfg = channel_readl(atchan, CFG); 1437c0ba5947SNicolas Ferre } 1438c0ba5947SNicolas Ferre atdma->save_imr = dma_readl(atdma, EBCIMR); 1439c0ba5947SNicolas Ferre 1440c0ba5947SNicolas Ferre /* disable DMA controller */ 1441c0ba5947SNicolas Ferre at_dma_off(atdma); 1442dc78baa2SNicolas Ferre clk_disable(atdma->clk); 1443dc78baa2SNicolas Ferre return 0; 1444dc78baa2SNicolas Ferre } 1445dc78baa2SNicolas Ferre 1446c0ba5947SNicolas Ferre static void atc_resume_cyclic(struct at_dma_chan *atchan) 1447c0ba5947SNicolas Ferre { 1448c0ba5947SNicolas Ferre struct at_dma *atdma = to_at_dma(atchan->chan_common.device); 1449c0ba5947SNicolas Ferre 1450c0ba5947SNicolas Ferre /* restore channel status for cyclic descriptors list: 1451c0ba5947SNicolas Ferre * next descriptor in the cyclic list at the time of suspend */ 1452c0ba5947SNicolas Ferre channel_writel(atchan, SADDR, 0); 1453c0ba5947SNicolas Ferre channel_writel(atchan, DADDR, 0); 1454c0ba5947SNicolas Ferre channel_writel(atchan, CTRLA, 0); 1455c0ba5947SNicolas Ferre channel_writel(atchan, CTRLB, 0); 1456c0ba5947SNicolas Ferre channel_writel(atchan, DSCR, atchan->save_dscr); 1457c0ba5947SNicolas Ferre dma_writel(atdma, CHER, atchan->mask); 1458c0ba5947SNicolas Ferre 1459c0ba5947SNicolas Ferre /* channel pause status should be removed by channel user 1460c0ba5947SNicolas Ferre * We cannot take the initiative to do it here */ 1461c0ba5947SNicolas Ferre 1462c0ba5947SNicolas Ferre vdbg_dump_regs(atchan); 1463c0ba5947SNicolas Ferre } 1464c0ba5947SNicolas Ferre 146533f82d14SDan Williams static int at_dma_resume_noirq(struct device *dev) 1466dc78baa2SNicolas Ferre { 146733f82d14SDan Williams struct platform_device *pdev = to_platform_device(dev); 1468dc78baa2SNicolas Ferre struct at_dma *atdma = platform_get_drvdata(pdev); 1469c0ba5947SNicolas Ferre struct dma_chan *chan, *_chan; 1470dc78baa2SNicolas Ferre 1471c0ba5947SNicolas Ferre /* bring back DMA controller */ 1472dc78baa2SNicolas Ferre clk_enable(atdma->clk); 1473dc78baa2SNicolas Ferre dma_writel(atdma, EN, AT_DMA_ENABLE); 1474c0ba5947SNicolas Ferre 1475c0ba5947SNicolas Ferre /* clear any pending interrupt */ 1476c0ba5947SNicolas Ferre while (dma_readl(atdma, EBCISR)) 1477c0ba5947SNicolas Ferre cpu_relax(); 1478c0ba5947SNicolas Ferre 1479c0ba5947SNicolas Ferre /* restore saved data */ 1480c0ba5947SNicolas Ferre dma_writel(atdma, EBCIER, atdma->save_imr); 1481c0ba5947SNicolas Ferre list_for_each_entry_safe(chan, _chan, &atdma->dma_common.channels, 1482c0ba5947SNicolas Ferre device_node) { 1483c0ba5947SNicolas Ferre struct at_dma_chan *atchan = to_at_dma_chan(chan); 1484c0ba5947SNicolas Ferre 1485c0ba5947SNicolas Ferre channel_writel(atchan, CFG, atchan->save_cfg); 14863c477482SNicolas Ferre if (atc_chan_is_cyclic(atchan)) 1487c0ba5947SNicolas Ferre atc_resume_cyclic(atchan); 1488c0ba5947SNicolas Ferre } 1489dc78baa2SNicolas Ferre return 0; 1490dc78baa2SNicolas Ferre } 1491dc78baa2SNicolas Ferre 149247145210SAlexey Dobriyan static const struct dev_pm_ops at_dma_dev_pm_ops = { 1493c0ba5947SNicolas Ferre .prepare = at_dma_prepare, 149433f82d14SDan Williams .suspend_noirq = at_dma_suspend_noirq, 149533f82d14SDan Williams .resume_noirq = at_dma_resume_noirq, 149633f82d14SDan Williams }; 149733f82d14SDan Williams 1498dc78baa2SNicolas Ferre static struct platform_driver at_dma_driver = { 1499dc78baa2SNicolas Ferre .remove = __exit_p(at_dma_remove), 1500dc78baa2SNicolas Ferre .shutdown = at_dma_shutdown, 1501dc78baa2SNicolas Ferre .driver = { 1502dc78baa2SNicolas Ferre .name = "at_hdmac", 150333f82d14SDan Williams .pm = &at_dma_dev_pm_ops, 1504dc78baa2SNicolas Ferre }, 1505dc78baa2SNicolas Ferre }; 1506dc78baa2SNicolas Ferre 1507dc78baa2SNicolas Ferre static int __init at_dma_init(void) 1508dc78baa2SNicolas Ferre { 1509dc78baa2SNicolas Ferre return platform_driver_probe(&at_dma_driver, at_dma_probe); 1510dc78baa2SNicolas Ferre } 151193d0bec2SEric Xu subsys_initcall(at_dma_init); 1512dc78baa2SNicolas Ferre 1513dc78baa2SNicolas Ferre static void __exit at_dma_exit(void) 1514dc78baa2SNicolas Ferre { 1515dc78baa2SNicolas Ferre platform_driver_unregister(&at_dma_driver); 1516dc78baa2SNicolas Ferre } 1517dc78baa2SNicolas Ferre module_exit(at_dma_exit); 1518dc78baa2SNicolas Ferre 1519dc78baa2SNicolas Ferre MODULE_DESCRIPTION("Atmel AHB DMA Controller driver"); 1520dc78baa2SNicolas Ferre MODULE_AUTHOR("Nicolas Ferre <nicolas.ferre@atmel.com>"); 1521dc78baa2SNicolas Ferre MODULE_LICENSE("GPL"); 1522dc78baa2SNicolas Ferre MODULE_ALIAS("platform:at_hdmac"); 1523