1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd. 4 * Author: Lin Huang <hl@rock-chips.com> 5 */ 6 7 #include <linux/arm-smccc.h> 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/devfreq.h> 11 #include <linux/devfreq-event.h> 12 #include <linux/interrupt.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_opp.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/rwsem.h> 21 #include <linux/suspend.h> 22 23 #include <soc/rockchip/rk3399_grf.h> 24 #include <soc/rockchip/rockchip_sip.h> 25 26 struct dram_timing { 27 unsigned int ddr3_speed_bin; 28 unsigned int pd_idle; 29 unsigned int sr_idle; 30 unsigned int sr_mc_gate_idle; 31 unsigned int srpd_lite_idle; 32 unsigned int standby_idle; 33 unsigned int auto_pd_dis_freq; 34 unsigned int dram_dll_dis_freq; 35 unsigned int phy_dll_dis_freq; 36 unsigned int ddr3_odt_dis_freq; 37 unsigned int ddr3_drv; 38 unsigned int ddr3_odt; 39 unsigned int phy_ddr3_ca_drv; 40 unsigned int phy_ddr3_dq_drv; 41 unsigned int phy_ddr3_odt; 42 unsigned int lpddr3_odt_dis_freq; 43 unsigned int lpddr3_drv; 44 unsigned int lpddr3_odt; 45 unsigned int phy_lpddr3_ca_drv; 46 unsigned int phy_lpddr3_dq_drv; 47 unsigned int phy_lpddr3_odt; 48 unsigned int lpddr4_odt_dis_freq; 49 unsigned int lpddr4_drv; 50 unsigned int lpddr4_dq_odt; 51 unsigned int lpddr4_ca_odt; 52 unsigned int phy_lpddr4_ca_drv; 53 unsigned int phy_lpddr4_ck_cs_drv; 54 unsigned int phy_lpddr4_dq_drv; 55 unsigned int phy_lpddr4_odt; 56 }; 57 58 struct rk3399_dmcfreq { 59 struct device *dev; 60 struct devfreq *devfreq; 61 struct devfreq_simple_ondemand_data ondemand_data; 62 struct clk *dmc_clk; 63 struct devfreq_event_dev *edev; 64 struct mutex lock; 65 struct dram_timing timing; 66 struct regulator *vdd_center; 67 struct regmap *regmap_pmu; 68 unsigned long rate, target_rate; 69 unsigned long volt, target_volt; 70 unsigned int odt_dis_freq; 71 int odt_pd_arg0, odt_pd_arg1; 72 }; 73 74 static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq, 75 u32 flags) 76 { 77 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev); 78 struct dev_pm_opp *opp; 79 unsigned long old_clk_rate = dmcfreq->rate; 80 unsigned long target_volt, target_rate; 81 struct arm_smccc_res res; 82 bool odt_enable = false; 83 int err; 84 85 opp = devfreq_recommended_opp(dev, freq, flags); 86 if (IS_ERR(opp)) 87 return PTR_ERR(opp); 88 89 target_rate = dev_pm_opp_get_freq(opp); 90 target_volt = dev_pm_opp_get_voltage(opp); 91 dev_pm_opp_put(opp); 92 93 if (dmcfreq->rate == target_rate) 94 return 0; 95 96 mutex_lock(&dmcfreq->lock); 97 98 if (dmcfreq->regmap_pmu) { 99 if (target_rate >= dmcfreq->odt_dis_freq) 100 odt_enable = true; 101 102 /* 103 * This makes a SMC call to the TF-A to set the DDR PD 104 * (power-down) timings and to enable or disable the 105 * ODT (on-die termination) resistors. 106 */ 107 arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, dmcfreq->odt_pd_arg0, 108 dmcfreq->odt_pd_arg1, 109 ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD, 110 odt_enable, 0, 0, 0, &res); 111 } 112 113 /* 114 * If frequency scaling from low to high, adjust voltage first. 115 * If frequency scaling from high to low, adjust frequency first. 116 */ 117 if (old_clk_rate < target_rate) { 118 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt, 119 target_volt); 120 if (err) { 121 dev_err(dev, "Cannot set voltage %lu uV\n", 122 target_volt); 123 goto out; 124 } 125 } 126 127 err = clk_set_rate(dmcfreq->dmc_clk, target_rate); 128 if (err) { 129 dev_err(dev, "Cannot set frequency %lu (%d)\n", target_rate, 130 err); 131 regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt, 132 dmcfreq->volt); 133 goto out; 134 } 135 136 /* 137 * Check the dpll rate, 138 * There only two result we will get, 139 * 1. Ddr frequency scaling fail, we still get the old rate. 140 * 2. Ddr frequency scaling sucessful, we get the rate we set. 141 */ 142 dmcfreq->rate = clk_get_rate(dmcfreq->dmc_clk); 143 144 /* If get the incorrect rate, set voltage to old value. */ 145 if (dmcfreq->rate != target_rate) { 146 dev_err(dev, "Got wrong frequency, Request %lu, Current %lu\n", 147 target_rate, dmcfreq->rate); 148 regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt, 149 dmcfreq->volt); 150 goto out; 151 } else if (old_clk_rate > target_rate) 152 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt, 153 target_volt); 154 if (err) 155 dev_err(dev, "Cannot set voltage %lu uV\n", target_volt); 156 157 dmcfreq->rate = target_rate; 158 dmcfreq->volt = target_volt; 159 160 out: 161 mutex_unlock(&dmcfreq->lock); 162 return err; 163 } 164 165 static int rk3399_dmcfreq_get_dev_status(struct device *dev, 166 struct devfreq_dev_status *stat) 167 { 168 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev); 169 struct devfreq_event_data edata; 170 int ret = 0; 171 172 ret = devfreq_event_get_event(dmcfreq->edev, &edata); 173 if (ret < 0) 174 return ret; 175 176 stat->current_frequency = dmcfreq->rate; 177 stat->busy_time = edata.load_count; 178 stat->total_time = edata.total_count; 179 180 return ret; 181 } 182 183 static int rk3399_dmcfreq_get_cur_freq(struct device *dev, unsigned long *freq) 184 { 185 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev); 186 187 *freq = dmcfreq->rate; 188 189 return 0; 190 } 191 192 static struct devfreq_dev_profile rk3399_devfreq_dmc_profile = { 193 .polling_ms = 200, 194 .target = rk3399_dmcfreq_target, 195 .get_dev_status = rk3399_dmcfreq_get_dev_status, 196 .get_cur_freq = rk3399_dmcfreq_get_cur_freq, 197 }; 198 199 static __maybe_unused int rk3399_dmcfreq_suspend(struct device *dev) 200 { 201 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev); 202 int ret = 0; 203 204 ret = devfreq_event_disable_edev(dmcfreq->edev); 205 if (ret < 0) { 206 dev_err(dev, "failed to disable the devfreq-event devices\n"); 207 return ret; 208 } 209 210 ret = devfreq_suspend_device(dmcfreq->devfreq); 211 if (ret < 0) { 212 dev_err(dev, "failed to suspend the devfreq devices\n"); 213 return ret; 214 } 215 216 return 0; 217 } 218 219 static __maybe_unused int rk3399_dmcfreq_resume(struct device *dev) 220 { 221 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev); 222 int ret = 0; 223 224 ret = devfreq_event_enable_edev(dmcfreq->edev); 225 if (ret < 0) { 226 dev_err(dev, "failed to enable the devfreq-event devices\n"); 227 return ret; 228 } 229 230 ret = devfreq_resume_device(dmcfreq->devfreq); 231 if (ret < 0) { 232 dev_err(dev, "failed to resume the devfreq devices\n"); 233 return ret; 234 } 235 return ret; 236 } 237 238 static SIMPLE_DEV_PM_OPS(rk3399_dmcfreq_pm, rk3399_dmcfreq_suspend, 239 rk3399_dmcfreq_resume); 240 241 static int of_get_ddr_timings(struct dram_timing *timing, 242 struct device_node *np) 243 { 244 int ret = 0; 245 246 ret = of_property_read_u32(np, "rockchip,ddr3_speed_bin", 247 &timing->ddr3_speed_bin); 248 ret |= of_property_read_u32(np, "rockchip,pd_idle", 249 &timing->pd_idle); 250 ret |= of_property_read_u32(np, "rockchip,sr_idle", 251 &timing->sr_idle); 252 ret |= of_property_read_u32(np, "rockchip,sr_mc_gate_idle", 253 &timing->sr_mc_gate_idle); 254 ret |= of_property_read_u32(np, "rockchip,srpd_lite_idle", 255 &timing->srpd_lite_idle); 256 ret |= of_property_read_u32(np, "rockchip,standby_idle", 257 &timing->standby_idle); 258 ret |= of_property_read_u32(np, "rockchip,auto_pd_dis_freq", 259 &timing->auto_pd_dis_freq); 260 ret |= of_property_read_u32(np, "rockchip,dram_dll_dis_freq", 261 &timing->dram_dll_dis_freq); 262 ret |= of_property_read_u32(np, "rockchip,phy_dll_dis_freq", 263 &timing->phy_dll_dis_freq); 264 ret |= of_property_read_u32(np, "rockchip,ddr3_odt_dis_freq", 265 &timing->ddr3_odt_dis_freq); 266 ret |= of_property_read_u32(np, "rockchip,ddr3_drv", 267 &timing->ddr3_drv); 268 ret |= of_property_read_u32(np, "rockchip,ddr3_odt", 269 &timing->ddr3_odt); 270 ret |= of_property_read_u32(np, "rockchip,phy_ddr3_ca_drv", 271 &timing->phy_ddr3_ca_drv); 272 ret |= of_property_read_u32(np, "rockchip,phy_ddr3_dq_drv", 273 &timing->phy_ddr3_dq_drv); 274 ret |= of_property_read_u32(np, "rockchip,phy_ddr3_odt", 275 &timing->phy_ddr3_odt); 276 ret |= of_property_read_u32(np, "rockchip,lpddr3_odt_dis_freq", 277 &timing->lpddr3_odt_dis_freq); 278 ret |= of_property_read_u32(np, "rockchip,lpddr3_drv", 279 &timing->lpddr3_drv); 280 ret |= of_property_read_u32(np, "rockchip,lpddr3_odt", 281 &timing->lpddr3_odt); 282 ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_ca_drv", 283 &timing->phy_lpddr3_ca_drv); 284 ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_dq_drv", 285 &timing->phy_lpddr3_dq_drv); 286 ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_odt", 287 &timing->phy_lpddr3_odt); 288 ret |= of_property_read_u32(np, "rockchip,lpddr4_odt_dis_freq", 289 &timing->lpddr4_odt_dis_freq); 290 ret |= of_property_read_u32(np, "rockchip,lpddr4_drv", 291 &timing->lpddr4_drv); 292 ret |= of_property_read_u32(np, "rockchip,lpddr4_dq_odt", 293 &timing->lpddr4_dq_odt); 294 ret |= of_property_read_u32(np, "rockchip,lpddr4_ca_odt", 295 &timing->lpddr4_ca_odt); 296 ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_ca_drv", 297 &timing->phy_lpddr4_ca_drv); 298 ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_ck_cs_drv", 299 &timing->phy_lpddr4_ck_cs_drv); 300 ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_dq_drv", 301 &timing->phy_lpddr4_dq_drv); 302 ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_odt", 303 &timing->phy_lpddr4_odt); 304 305 return ret; 306 } 307 308 static int rk3399_dmcfreq_probe(struct platform_device *pdev) 309 { 310 struct arm_smccc_res res; 311 struct device *dev = &pdev->dev; 312 struct device_node *np = pdev->dev.of_node, *node; 313 struct rk3399_dmcfreq *data; 314 int ret, index, size; 315 uint32_t *timing; 316 struct dev_pm_opp *opp; 317 u32 ddr_type; 318 u32 val; 319 320 data = devm_kzalloc(dev, sizeof(struct rk3399_dmcfreq), GFP_KERNEL); 321 if (!data) 322 return -ENOMEM; 323 324 mutex_init(&data->lock); 325 326 data->vdd_center = devm_regulator_get(dev, "center"); 327 if (IS_ERR(data->vdd_center)) { 328 if (PTR_ERR(data->vdd_center) == -EPROBE_DEFER) 329 return -EPROBE_DEFER; 330 331 dev_err(dev, "Cannot get the regulator \"center\"\n"); 332 return PTR_ERR(data->vdd_center); 333 } 334 335 data->dmc_clk = devm_clk_get(dev, "dmc_clk"); 336 if (IS_ERR(data->dmc_clk)) { 337 if (PTR_ERR(data->dmc_clk) == -EPROBE_DEFER) 338 return -EPROBE_DEFER; 339 340 dev_err(dev, "Cannot get the clk dmc_clk\n"); 341 return PTR_ERR(data->dmc_clk); 342 } 343 344 data->edev = devfreq_event_get_edev_by_phandle(dev, "devfreq-events", 0); 345 if (IS_ERR(data->edev)) 346 return -EPROBE_DEFER; 347 348 ret = devfreq_event_enable_edev(data->edev); 349 if (ret < 0) { 350 dev_err(dev, "failed to enable devfreq-event devices\n"); 351 return ret; 352 } 353 354 /* 355 * Get dram timing and pass it to arm trust firmware, 356 * the dram driver in arm trust firmware will get these 357 * timing and to do dram initial. 358 */ 359 if (!of_get_ddr_timings(&data->timing, np)) { 360 timing = &data->timing.ddr3_speed_bin; 361 size = sizeof(struct dram_timing) / 4; 362 for (index = 0; index < size; index++) { 363 arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, *timing++, index, 364 ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM, 365 0, 0, 0, 0, &res); 366 if (res.a0) { 367 dev_err(dev, "Failed to set dram param: %ld\n", 368 res.a0); 369 ret = -EINVAL; 370 goto err_edev; 371 } 372 } 373 } 374 375 node = of_parse_phandle(np, "rockchip,pmu", 0); 376 if (!node) 377 goto no_pmu; 378 379 data->regmap_pmu = syscon_node_to_regmap(node); 380 of_node_put(node); 381 if (IS_ERR(data->regmap_pmu)) { 382 ret = PTR_ERR(data->regmap_pmu); 383 goto err_edev; 384 } 385 386 regmap_read(data->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val); 387 ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) & 388 RK3399_PMUGRF_DDRTYPE_MASK; 389 390 switch (ddr_type) { 391 case RK3399_PMUGRF_DDRTYPE_DDR3: 392 data->odt_dis_freq = data->timing.ddr3_odt_dis_freq; 393 break; 394 case RK3399_PMUGRF_DDRTYPE_LPDDR3: 395 data->odt_dis_freq = data->timing.lpddr3_odt_dis_freq; 396 break; 397 case RK3399_PMUGRF_DDRTYPE_LPDDR4: 398 data->odt_dis_freq = data->timing.lpddr4_odt_dis_freq; 399 break; 400 default: 401 ret = -EINVAL; 402 goto err_edev; 403 } 404 405 no_pmu: 406 arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0, 407 ROCKCHIP_SIP_CONFIG_DRAM_INIT, 408 0, 0, 0, 0, &res); 409 410 /* 411 * In TF-A there is a platform SIP call to set the PD (power-down) 412 * timings and to enable or disable the ODT (on-die termination). 413 * This call needs three arguments as follows: 414 * 415 * arg0: 416 * bit[0-7] : sr_idle 417 * bit[8-15] : sr_mc_gate_idle 418 * bit[16-31] : standby idle 419 * arg1: 420 * bit[0-11] : pd_idle 421 * bit[16-27] : srpd_lite_idle 422 * arg2: 423 * bit[0] : odt enable 424 */ 425 data->odt_pd_arg0 = (data->timing.sr_idle & 0xff) | 426 ((data->timing.sr_mc_gate_idle & 0xff) << 8) | 427 ((data->timing.standby_idle & 0xffff) << 16); 428 data->odt_pd_arg1 = (data->timing.pd_idle & 0xfff) | 429 ((data->timing.srpd_lite_idle & 0xfff) << 16); 430 431 /* 432 * We add a devfreq driver to our parent since it has a device tree node 433 * with operating points. 434 */ 435 if (dev_pm_opp_of_add_table(dev)) { 436 dev_err(dev, "Invalid operating-points in device tree.\n"); 437 ret = -EINVAL; 438 goto err_edev; 439 } 440 441 of_property_read_u32(np, "upthreshold", 442 &data->ondemand_data.upthreshold); 443 of_property_read_u32(np, "downdifferential", 444 &data->ondemand_data.downdifferential); 445 446 data->rate = clk_get_rate(data->dmc_clk); 447 448 opp = devfreq_recommended_opp(dev, &data->rate, 0); 449 if (IS_ERR(opp)) { 450 ret = PTR_ERR(opp); 451 goto err_free_opp; 452 } 453 454 data->rate = dev_pm_opp_get_freq(opp); 455 data->volt = dev_pm_opp_get_voltage(opp); 456 dev_pm_opp_put(opp); 457 458 rk3399_devfreq_dmc_profile.initial_freq = data->rate; 459 460 data->devfreq = devm_devfreq_add_device(dev, 461 &rk3399_devfreq_dmc_profile, 462 DEVFREQ_GOV_SIMPLE_ONDEMAND, 463 &data->ondemand_data); 464 if (IS_ERR(data->devfreq)) { 465 ret = PTR_ERR(data->devfreq); 466 goto err_free_opp; 467 } 468 469 devm_devfreq_register_opp_notifier(dev, data->devfreq); 470 471 data->dev = dev; 472 platform_set_drvdata(pdev, data); 473 474 return 0; 475 476 err_free_opp: 477 dev_pm_opp_of_remove_table(&pdev->dev); 478 err_edev: 479 devfreq_event_disable_edev(data->edev); 480 481 return ret; 482 } 483 484 static int rk3399_dmcfreq_remove(struct platform_device *pdev) 485 { 486 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(&pdev->dev); 487 488 /* 489 * Before remove the opp table we need to unregister the opp notifier. 490 */ 491 devm_devfreq_unregister_opp_notifier(dmcfreq->dev, dmcfreq->devfreq); 492 dev_pm_opp_of_remove_table(dmcfreq->dev); 493 494 return 0; 495 } 496 497 static const struct of_device_id rk3399dmc_devfreq_of_match[] = { 498 { .compatible = "rockchip,rk3399-dmc" }, 499 { }, 500 }; 501 MODULE_DEVICE_TABLE(of, rk3399dmc_devfreq_of_match); 502 503 static struct platform_driver rk3399_dmcfreq_driver = { 504 .probe = rk3399_dmcfreq_probe, 505 .remove = rk3399_dmcfreq_remove, 506 .driver = { 507 .name = "rk3399-dmc-freq", 508 .pm = &rk3399_dmcfreq_pm, 509 .of_match_table = rk3399dmc_devfreq_of_match, 510 }, 511 }; 512 module_platform_driver(rk3399_dmcfreq_driver); 513 514 MODULE_LICENSE("GPL v2"); 515 MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>"); 516 MODULE_DESCRIPTION("RK3399 dmcfreq driver with devfreq framework"); 517