1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd. 4 * Author: Lin Huang <hl@rock-chips.com> 5 */ 6 7 #include <linux/arm-smccc.h> 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/devfreq.h> 11 #include <linux/devfreq-event.h> 12 #include <linux/interrupt.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/platform_device.h> 17 #include <linux/pm_opp.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/rwsem.h> 21 #include <linux/suspend.h> 22 23 #include <soc/rockchip/rk3399_grf.h> 24 #include <soc/rockchip/rockchip_sip.h> 25 26 struct dram_timing { 27 unsigned int ddr3_speed_bin; 28 unsigned int pd_idle; 29 unsigned int sr_idle; 30 unsigned int sr_mc_gate_idle; 31 unsigned int srpd_lite_idle; 32 unsigned int standby_idle; 33 unsigned int auto_pd_dis_freq; 34 unsigned int dram_dll_dis_freq; 35 unsigned int phy_dll_dis_freq; 36 unsigned int ddr3_odt_dis_freq; 37 unsigned int ddr3_drv; 38 unsigned int ddr3_odt; 39 unsigned int phy_ddr3_ca_drv; 40 unsigned int phy_ddr3_dq_drv; 41 unsigned int phy_ddr3_odt; 42 unsigned int lpddr3_odt_dis_freq; 43 unsigned int lpddr3_drv; 44 unsigned int lpddr3_odt; 45 unsigned int phy_lpddr3_ca_drv; 46 unsigned int phy_lpddr3_dq_drv; 47 unsigned int phy_lpddr3_odt; 48 unsigned int lpddr4_odt_dis_freq; 49 unsigned int lpddr4_drv; 50 unsigned int lpddr4_dq_odt; 51 unsigned int lpddr4_ca_odt; 52 unsigned int phy_lpddr4_ca_drv; 53 unsigned int phy_lpddr4_ck_cs_drv; 54 unsigned int phy_lpddr4_dq_drv; 55 unsigned int phy_lpddr4_odt; 56 }; 57 58 struct rk3399_dmcfreq { 59 struct device *dev; 60 struct devfreq *devfreq; 61 struct devfreq_simple_ondemand_data ondemand_data; 62 struct clk *dmc_clk; 63 struct devfreq_event_dev *edev; 64 struct mutex lock; 65 struct dram_timing timing; 66 struct regulator *vdd_center; 67 struct regmap *regmap_pmu; 68 unsigned long rate, target_rate; 69 unsigned long volt, target_volt; 70 unsigned int odt_dis_freq; 71 int odt_pd_arg0, odt_pd_arg1; 72 }; 73 74 static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq, 75 u32 flags) 76 { 77 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev); 78 struct dev_pm_opp *opp; 79 unsigned long old_clk_rate = dmcfreq->rate; 80 unsigned long target_volt, target_rate; 81 struct arm_smccc_res res; 82 bool odt_enable = false; 83 int err; 84 85 opp = devfreq_recommended_opp(dev, freq, flags); 86 if (IS_ERR(opp)) 87 return PTR_ERR(opp); 88 89 target_rate = dev_pm_opp_get_freq(opp); 90 target_volt = dev_pm_opp_get_voltage(opp); 91 dev_pm_opp_put(opp); 92 93 if (dmcfreq->rate == target_rate) 94 return 0; 95 96 mutex_lock(&dmcfreq->lock); 97 98 if (target_rate >= dmcfreq->odt_dis_freq) 99 odt_enable = true; 100 101 /* 102 * This makes a SMC call to the TF-A to set the DDR PD (power-down) 103 * timings and to enable or disable the ODT (on-die termination) 104 * resistors. 105 */ 106 arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, dmcfreq->odt_pd_arg0, 107 dmcfreq->odt_pd_arg1, 108 ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD, 109 odt_enable, 0, 0, 0, &res); 110 111 /* 112 * If frequency scaling from low to high, adjust voltage first. 113 * If frequency scaling from high to low, adjust frequency first. 114 */ 115 if (old_clk_rate < target_rate) { 116 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt, 117 target_volt); 118 if (err) { 119 dev_err(dev, "Cannot set voltage %lu uV\n", 120 target_volt); 121 goto out; 122 } 123 } 124 125 err = clk_set_rate(dmcfreq->dmc_clk, target_rate); 126 if (err) { 127 dev_err(dev, "Cannot set frequency %lu (%d)\n", target_rate, 128 err); 129 regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt, 130 dmcfreq->volt); 131 goto out; 132 } 133 134 /* 135 * Check the dpll rate, 136 * There only two result we will get, 137 * 1. Ddr frequency scaling fail, we still get the old rate. 138 * 2. Ddr frequency scaling sucessful, we get the rate we set. 139 */ 140 dmcfreq->rate = clk_get_rate(dmcfreq->dmc_clk); 141 142 /* If get the incorrect rate, set voltage to old value. */ 143 if (dmcfreq->rate != target_rate) { 144 dev_err(dev, "Got wrong frequency, Request %lu, Current %lu\n", 145 target_rate, dmcfreq->rate); 146 regulator_set_voltage(dmcfreq->vdd_center, dmcfreq->volt, 147 dmcfreq->volt); 148 goto out; 149 } else if (old_clk_rate > target_rate) 150 err = regulator_set_voltage(dmcfreq->vdd_center, target_volt, 151 target_volt); 152 if (err) 153 dev_err(dev, "Cannot set voltage %lu uV\n", target_volt); 154 155 dmcfreq->rate = target_rate; 156 dmcfreq->volt = target_volt; 157 158 out: 159 mutex_unlock(&dmcfreq->lock); 160 return err; 161 } 162 163 static int rk3399_dmcfreq_get_dev_status(struct device *dev, 164 struct devfreq_dev_status *stat) 165 { 166 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev); 167 struct devfreq_event_data edata; 168 int ret = 0; 169 170 ret = devfreq_event_get_event(dmcfreq->edev, &edata); 171 if (ret < 0) 172 return ret; 173 174 stat->current_frequency = dmcfreq->rate; 175 stat->busy_time = edata.load_count; 176 stat->total_time = edata.total_count; 177 178 return ret; 179 } 180 181 static int rk3399_dmcfreq_get_cur_freq(struct device *dev, unsigned long *freq) 182 { 183 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev); 184 185 *freq = dmcfreq->rate; 186 187 return 0; 188 } 189 190 static struct devfreq_dev_profile rk3399_devfreq_dmc_profile = { 191 .polling_ms = 200, 192 .target = rk3399_dmcfreq_target, 193 .get_dev_status = rk3399_dmcfreq_get_dev_status, 194 .get_cur_freq = rk3399_dmcfreq_get_cur_freq, 195 }; 196 197 static __maybe_unused int rk3399_dmcfreq_suspend(struct device *dev) 198 { 199 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev); 200 int ret = 0; 201 202 ret = devfreq_event_disable_edev(dmcfreq->edev); 203 if (ret < 0) { 204 dev_err(dev, "failed to disable the devfreq-event devices\n"); 205 return ret; 206 } 207 208 ret = devfreq_suspend_device(dmcfreq->devfreq); 209 if (ret < 0) { 210 dev_err(dev, "failed to suspend the devfreq devices\n"); 211 return ret; 212 } 213 214 return 0; 215 } 216 217 static __maybe_unused int rk3399_dmcfreq_resume(struct device *dev) 218 { 219 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(dev); 220 int ret = 0; 221 222 ret = devfreq_event_enable_edev(dmcfreq->edev); 223 if (ret < 0) { 224 dev_err(dev, "failed to enable the devfreq-event devices\n"); 225 return ret; 226 } 227 228 ret = devfreq_resume_device(dmcfreq->devfreq); 229 if (ret < 0) { 230 dev_err(dev, "failed to resume the devfreq devices\n"); 231 return ret; 232 } 233 return ret; 234 } 235 236 static SIMPLE_DEV_PM_OPS(rk3399_dmcfreq_pm, rk3399_dmcfreq_suspend, 237 rk3399_dmcfreq_resume); 238 239 static int of_get_ddr_timings(struct dram_timing *timing, 240 struct device_node *np) 241 { 242 int ret = 0; 243 244 ret = of_property_read_u32(np, "rockchip,ddr3_speed_bin", 245 &timing->ddr3_speed_bin); 246 ret |= of_property_read_u32(np, "rockchip,pd_idle", 247 &timing->pd_idle); 248 ret |= of_property_read_u32(np, "rockchip,sr_idle", 249 &timing->sr_idle); 250 ret |= of_property_read_u32(np, "rockchip,sr_mc_gate_idle", 251 &timing->sr_mc_gate_idle); 252 ret |= of_property_read_u32(np, "rockchip,srpd_lite_idle", 253 &timing->srpd_lite_idle); 254 ret |= of_property_read_u32(np, "rockchip,standby_idle", 255 &timing->standby_idle); 256 ret |= of_property_read_u32(np, "rockchip,auto_pd_dis_freq", 257 &timing->auto_pd_dis_freq); 258 ret |= of_property_read_u32(np, "rockchip,dram_dll_dis_freq", 259 &timing->dram_dll_dis_freq); 260 ret |= of_property_read_u32(np, "rockchip,phy_dll_dis_freq", 261 &timing->phy_dll_dis_freq); 262 ret |= of_property_read_u32(np, "rockchip,ddr3_odt_dis_freq", 263 &timing->ddr3_odt_dis_freq); 264 ret |= of_property_read_u32(np, "rockchip,ddr3_drv", 265 &timing->ddr3_drv); 266 ret |= of_property_read_u32(np, "rockchip,ddr3_odt", 267 &timing->ddr3_odt); 268 ret |= of_property_read_u32(np, "rockchip,phy_ddr3_ca_drv", 269 &timing->phy_ddr3_ca_drv); 270 ret |= of_property_read_u32(np, "rockchip,phy_ddr3_dq_drv", 271 &timing->phy_ddr3_dq_drv); 272 ret |= of_property_read_u32(np, "rockchip,phy_ddr3_odt", 273 &timing->phy_ddr3_odt); 274 ret |= of_property_read_u32(np, "rockchip,lpddr3_odt_dis_freq", 275 &timing->lpddr3_odt_dis_freq); 276 ret |= of_property_read_u32(np, "rockchip,lpddr3_drv", 277 &timing->lpddr3_drv); 278 ret |= of_property_read_u32(np, "rockchip,lpddr3_odt", 279 &timing->lpddr3_odt); 280 ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_ca_drv", 281 &timing->phy_lpddr3_ca_drv); 282 ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_dq_drv", 283 &timing->phy_lpddr3_dq_drv); 284 ret |= of_property_read_u32(np, "rockchip,phy_lpddr3_odt", 285 &timing->phy_lpddr3_odt); 286 ret |= of_property_read_u32(np, "rockchip,lpddr4_odt_dis_freq", 287 &timing->lpddr4_odt_dis_freq); 288 ret |= of_property_read_u32(np, "rockchip,lpddr4_drv", 289 &timing->lpddr4_drv); 290 ret |= of_property_read_u32(np, "rockchip,lpddr4_dq_odt", 291 &timing->lpddr4_dq_odt); 292 ret |= of_property_read_u32(np, "rockchip,lpddr4_ca_odt", 293 &timing->lpddr4_ca_odt); 294 ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_ca_drv", 295 &timing->phy_lpddr4_ca_drv); 296 ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_ck_cs_drv", 297 &timing->phy_lpddr4_ck_cs_drv); 298 ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_dq_drv", 299 &timing->phy_lpddr4_dq_drv); 300 ret |= of_property_read_u32(np, "rockchip,phy_lpddr4_odt", 301 &timing->phy_lpddr4_odt); 302 303 return ret; 304 } 305 306 static int rk3399_dmcfreq_probe(struct platform_device *pdev) 307 { 308 struct arm_smccc_res res; 309 struct device *dev = &pdev->dev; 310 struct device_node *np = pdev->dev.of_node, *node; 311 struct rk3399_dmcfreq *data; 312 int ret, index, size; 313 uint32_t *timing; 314 struct dev_pm_opp *opp; 315 u32 ddr_type; 316 u32 val; 317 318 data = devm_kzalloc(dev, sizeof(struct rk3399_dmcfreq), GFP_KERNEL); 319 if (!data) 320 return -ENOMEM; 321 322 mutex_init(&data->lock); 323 324 data->vdd_center = devm_regulator_get(dev, "center"); 325 if (IS_ERR(data->vdd_center)) { 326 if (PTR_ERR(data->vdd_center) == -EPROBE_DEFER) 327 return -EPROBE_DEFER; 328 329 dev_err(dev, "Cannot get the regulator \"center\"\n"); 330 return PTR_ERR(data->vdd_center); 331 } 332 333 data->dmc_clk = devm_clk_get(dev, "dmc_clk"); 334 if (IS_ERR(data->dmc_clk)) { 335 if (PTR_ERR(data->dmc_clk) == -EPROBE_DEFER) 336 return -EPROBE_DEFER; 337 338 dev_err(dev, "Cannot get the clk dmc_clk\n"); 339 return PTR_ERR(data->dmc_clk); 340 } 341 342 data->edev = devfreq_event_get_edev_by_phandle(dev, 0); 343 if (IS_ERR(data->edev)) 344 return -EPROBE_DEFER; 345 346 ret = devfreq_event_enable_edev(data->edev); 347 if (ret < 0) { 348 dev_err(dev, "failed to enable devfreq-event devices\n"); 349 return ret; 350 } 351 352 /* 353 * Get dram timing and pass it to arm trust firmware, 354 * the dram drvier in arm trust firmware will get these 355 * timing and to do dram initial. 356 */ 357 if (!of_get_ddr_timings(&data->timing, np)) { 358 timing = &data->timing.ddr3_speed_bin; 359 size = sizeof(struct dram_timing) / 4; 360 for (index = 0; index < size; index++) { 361 arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, *timing++, index, 362 ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM, 363 0, 0, 0, 0, &res); 364 if (res.a0) { 365 dev_err(dev, "Failed to set dram param: %ld\n", 366 res.a0); 367 return -EINVAL; 368 } 369 } 370 } 371 372 node = of_parse_phandle(np, "rockchip,pmu", 0); 373 if (node) { 374 data->regmap_pmu = syscon_node_to_regmap(node); 375 if (IS_ERR(data->regmap_pmu)) 376 return PTR_ERR(data->regmap_pmu); 377 } 378 379 regmap_read(data->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val); 380 ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) & 381 RK3399_PMUGRF_DDRTYPE_MASK; 382 383 switch (ddr_type) { 384 case RK3399_PMUGRF_DDRTYPE_DDR3: 385 data->odt_dis_freq = data->timing.ddr3_odt_dis_freq; 386 break; 387 case RK3399_PMUGRF_DDRTYPE_LPDDR3: 388 data->odt_dis_freq = data->timing.lpddr3_odt_dis_freq; 389 break; 390 case RK3399_PMUGRF_DDRTYPE_LPDDR4: 391 data->odt_dis_freq = data->timing.lpddr4_odt_dis_freq; 392 break; 393 default: 394 return -EINVAL; 395 }; 396 397 arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, 0, 0, 398 ROCKCHIP_SIP_CONFIG_DRAM_INIT, 399 0, 0, 0, 0, &res); 400 401 /* 402 * In TF-A there is a platform SIP call to set the PD (power-down) 403 * timings and to enable or disable the ODT (on-die termination). 404 * This call needs three arguments as follows: 405 * 406 * arg0: 407 * bit[0-7] : sr_idle 408 * bit[8-15] : sr_mc_gate_idle 409 * bit[16-31] : standby idle 410 * arg1: 411 * bit[0-11] : pd_idle 412 * bit[16-27] : srpd_lite_idle 413 * arg2: 414 * bit[0] : odt enable 415 */ 416 data->odt_pd_arg0 = (data->timing.sr_idle & 0xff) | 417 ((data->timing.sr_mc_gate_idle & 0xff) << 8) | 418 ((data->timing.standby_idle & 0xffff) << 16); 419 data->odt_pd_arg1 = (data->timing.pd_idle & 0xfff) | 420 ((data->timing.srpd_lite_idle & 0xfff) << 16); 421 422 /* 423 * We add a devfreq driver to our parent since it has a device tree node 424 * with operating points. 425 */ 426 if (dev_pm_opp_of_add_table(dev)) { 427 dev_err(dev, "Invalid operating-points in device tree.\n"); 428 return -EINVAL; 429 } 430 431 of_property_read_u32(np, "upthreshold", 432 &data->ondemand_data.upthreshold); 433 of_property_read_u32(np, "downdifferential", 434 &data->ondemand_data.downdifferential); 435 436 data->rate = clk_get_rate(data->dmc_clk); 437 438 opp = devfreq_recommended_opp(dev, &data->rate, 0); 439 if (IS_ERR(opp)) { 440 ret = PTR_ERR(opp); 441 goto err_free_opp; 442 } 443 444 data->rate = dev_pm_opp_get_freq(opp); 445 data->volt = dev_pm_opp_get_voltage(opp); 446 dev_pm_opp_put(opp); 447 448 rk3399_devfreq_dmc_profile.initial_freq = data->rate; 449 450 data->devfreq = devm_devfreq_add_device(dev, 451 &rk3399_devfreq_dmc_profile, 452 DEVFREQ_GOV_SIMPLE_ONDEMAND, 453 &data->ondemand_data); 454 if (IS_ERR(data->devfreq)) { 455 ret = PTR_ERR(data->devfreq); 456 goto err_free_opp; 457 } 458 459 devm_devfreq_register_opp_notifier(dev, data->devfreq); 460 461 data->dev = dev; 462 platform_set_drvdata(pdev, data); 463 464 return 0; 465 466 err_free_opp: 467 dev_pm_opp_of_remove_table(&pdev->dev); 468 return ret; 469 } 470 471 static int rk3399_dmcfreq_remove(struct platform_device *pdev) 472 { 473 struct rk3399_dmcfreq *dmcfreq = dev_get_drvdata(&pdev->dev); 474 475 /* 476 * Before remove the opp table we need to unregister the opp notifier. 477 */ 478 devm_devfreq_unregister_opp_notifier(dmcfreq->dev, dmcfreq->devfreq); 479 dev_pm_opp_of_remove_table(dmcfreq->dev); 480 481 return 0; 482 } 483 484 static const struct of_device_id rk3399dmc_devfreq_of_match[] = { 485 { .compatible = "rockchip,rk3399-dmc" }, 486 { }, 487 }; 488 MODULE_DEVICE_TABLE(of, rk3399dmc_devfreq_of_match); 489 490 static struct platform_driver rk3399_dmcfreq_driver = { 491 .probe = rk3399_dmcfreq_probe, 492 .remove = rk3399_dmcfreq_remove, 493 .driver = { 494 .name = "rk3399-dmc-freq", 495 .pm = &rk3399_dmcfreq_pm, 496 .of_match_table = rk3399dmc_devfreq_of_match, 497 }, 498 }; 499 module_platform_driver(rk3399_dmcfreq_driver); 500 501 MODULE_LICENSE("GPL v2"); 502 MODULE_AUTHOR("Lin Huang <hl@rock-chips.com>"); 503 MODULE_DESCRIPTION("RK3399 dmcfreq driver with devfreq framework"); 504